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ELETRNICA IV

Apostila de Aulas Prticas

Autor: Fernando Antnio Pinto Barqui


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Sumrio

1. INTRODUO..............................................................................................................................3

2. AMPLIFICADOR PUSH-PULL COM SADA COMPLEMENTAR.................................. 4

3. AMPLIFICADOR SINTONIZADO ............................................................................................ 7

4. MODULADOR DE AMPLITUDE.............................................................................................10

5. MULTIPLICADORES ANALGICOS....................................................................................12

6. MODULADOR DE FREQNCIA .......................................................................................... 14

7. FONTES CHAVEADAS .............................................................................................................16

DATASHEETS................................................................................................................................. 20


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1. INTRODUOO contedo desta apostila consiste das aulas experimentais do curso de Eletrnica IV, ministrado no

Departamento de Eletrnica da Escola de Engenharia. Cada captulo corresponde a um experimento a ser

montado e estudado em laboratrio. Esses experimentos foram, ao longo dos anos, sendo aprimorados

didaticamente, de forma a apresentar ao aluno a constatao experimental dos conceitos bsicos, e essenciais,

estudados na disciplina terica. Tambm so fornecidos todos os manuais dos componentes usados nos

experimentos, disponibilizando ao aluno todas as informaes necessrias realizao dos projetos.


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2. AMPLIFICADOR PUSH-PULL COM SADA COMPLEMENTAR

ASSUNTOProjeto de um amplificador de potncia, classe AB, com transistores de sada em simetria com-plementar.

OBJETIVOFamiliarizar o aluno com as condies de operao e caractersticas particulares do circuito.

PROJETO

Fase 1- Projete o circuito da Figura 2.1 obedecendo as seguintes especificaes:

1 - Potncia C.A. de sada de 1W.

2 - Carga de 8.

3 - Eficincia superior a 40%.

4 - Freqncia de corte inferior menor que 50Hz.

5 - Ganho de tenso o maior possvel.

6 - Considerar nos clculos os transistores: TIP29C, TIP30C, BC547 e BC557.

Consideraes:

1 - Calcule os ganhos de tenso e potncia.

2 - Mostre que a eficincia mxima real do estgio de sada dada por:

=V

V

op

cc4onde Vop a tenso de pico de sada.

3 - Explique a funo dos seguintes componentes do circuito: R1, R2, D1, D2, D3, D4, C2 e C5.

4 - Considere R1=R2=0.5.

5 - Ajuste P1 at obter a tenso DC no ponto A igual a zero.

Medidas:

1 - Medir a polarizao aps os ajustes necessrios.

2 - Medir os ganhos de tenso e de potncia.

3 - Medir e traar o grfico de resposta em freqncia.

6 - Medir a eficincia do circuito para a mxima tenso de sada, sem saturao.


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7 - Curto-circuitar os pontos B e C, e observar as alteraes na forma de onda de sada. Explicar estas

alteraes.

Fase 2- Projete o circuito da Figura 2.2 obedecendo as seguintes recomendaes:

1 - Conservar os valores dos componentes calculados para o circuito da Figura 2.1, exceto o capacitor

C1.

2 - Identificar o tipo de realimentao empregada.

3 - Calcular R6 para se obter um ganho de tenso realimentado de 4. Este ganho necessrio para que

um sinal de entrada com 1V de amplitude produza potncia mxima na sada do amplificador. Esta

uma especificao comum aos amplificadores de potncia comerciais.

4 - Recalcular C1 para manter a freqncia de corte inferior menor que 50Hz.

Medidas:

1 -Medir a tenso DC no ponto A e comparar com a da Fase 1.

2 - Medir o ganho de tenso.

3 - Medir e traar o grfico de resposta em freqncia.

6 - Curto-circuitar os pontos B e C, e observar as alteraes na forma de onda de sada. Comparar com o

observado na Fase 1.

Fase 3- Projete o circuito da Figura 2.4 obedecendo as seguintes recomendaes:

1 - Monte o circuito da Figura 2.3 (a) utilizando um microfone de eletreto e um resistor R10=10k.

2 - Fale ao microfone e observe a amplitude mxima do sinal AC em VMic.

3 - Com a tenso VMic, projete o pr-amplificador da Figura 2.3 (b) de tal forma a se obter uma tenso

mxima Vpr=1V e freqncia de corte inferior menor que 50Hz. Conecte o pr-amplificador ao

amplificador da Fase 2, conforme a Figura 2.4, substitua a carga RL por um alto-falante de 8, faleao microfone e relate suas impresses.

Figura 2.1: Amplificador Push-Pull.


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Figura 2.2: Amplificador Push-Pull com realimentao.

Figura 2.3: Microfone de eletreto. a) Polarizao. b) Microfone mais amplificador.

Figura 2.4: Amplificador Push-Pull mais microfone de eletreto.


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3. AMPLIFICADOR SINTONIZADO

OBJETIVOEstudo de um amplificador sintonizado e sua aplicao como amplificador seletivo, multiplicador de

freqncias e conversor.

ESPECIFICAESProjetar um amplificador sintonizado, tomando por base, a Figura 3.1, com as seguintes

caractersticas:

1 - Vcc = 12V.

2 - Freqncia da portadora ( ( )ec kHz i c = 400 ).

3 - Ganho de tenso( )( )

Aec

ecV

o c

i c

=

20 .

4 - Seletividade igual a 10.

PROCEDIMENTOS

1 - Medida das relaes de espiras das bobinas.

2 - Medidas dos fatores de Qualidade e de LX, segundo o esquema abaixo.

onde:

Cv uma dcada capacitiva;

Cp a capacitncia parasita, que inclui a capacitncia do osciloscpio, da fiao, residual da dcada e da

prpria bobina;

( )o

v pC C=

+

1

Lx

Fazer as medidas de Lx em dois valores, o1 e o2, em torno de c, de

modo que seja anulada a capacitncia Cp.

- Medida de Qb.


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V = VZ( )

R + Z( )o i

s o

o

Z( ) = LQo b o (Qb >> 1)

Dados Vi e Rs medir Vo mximo com o osciloscpio (ponta atenuadora) e calcular ( )Z o .

3 - Calcule os componentes para atender as especificaes dadas;

4 - Calcule a seletividade do circuito;

5 - Responda:

Qual o sinal observado na sada quando a entrada:

- for um sinal senoidal de 400kHz;



- for um sinal senoidal de 800 kHz;- for um sinal quadrado de 200kHz;

- for um sinal quadrado de 133kHz;

- for um sinal quadrado de 10kHz;

6 - Monte o circuito e compare os valores previstos e calculados com os medidos.

Medidas:

- o ganho mximo em c;

- a curva de resposta, assinalando os pontos de meia potncia;

- a seletividade;

- os sinais de sada de acordo com as entradas especificadas no item 5;

- explique os resultados;

- faa as observaes que julgue necessrias;

7 - No circuito j montado, aplique base outro gerador de sinais, conforme a Figura 3.2.

- atravs do gerador G1 um sinal de 800kHz;

- atravs do gerador G2 um sinal de 1200kHz;

8 - Qual o sinal que ser observado na sada (sobre RL)?

9 - Comente e apresente as explicaes tericas para o observado.


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Figura 3.1: Amplificador sintonizado.

Figura 3.2: Amplificador sintonizado como mixer.


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4. MODULADOR DE AMPLITUDE

OBJETIVOEstudo de um circuito Modulador de Amplitude (AM).

ESPECIFICAESProjetar um circuito Modulador de Amplitude, tomando por base, o circuito da Figura 4.1, de forma

a atender as especificaes abaixo:

1 - Freqncia da portadora igual a 400kHz.

2 - Freqncia de corte inferior, para o sinal modulador, de 50Hz.

3 - Freqncia de corte superior, para o sinal modulador, de 5kHz.

PROCEDIMENTOS

1 - Mea a indutncia L da bobina, sua relao de espiras e seu fator de qualidade Qb.

2 - Calcule os capacitores C1 e C2 para que o circuito oscile na freqncia de 300kHz.

3 - Calcule R1, R2, P, C3, C5 de forma a atender os itens 2 e 3 das especificaes.

4 - Mostre que para se obter simetria nos ciclos positivo e negativo do sinal modulado Vo(t),

necessrio que a resistncia equivalente no coletor de Q2 seja R VI

eqcc

cq

=2

. Calcule Ro para se obter

Req.

5 - Calcule C4 de tal forma que: na freqncia da portadora o capacitor seja um curto-circuito; nas fre-

qncias moduladoras o capacitor seja um circuito aberto.

MEDIDAS

1 - Mea a freqncia da portadora.

2 - Com um sinal de entrada de 1kHz, ajuste sua amplitude para um ndice de modulao de 50% e

esboce o sinal de sada Vo(t) para as formas de onda quadrada, senoidal e triangular.

3 - Mea o maior ndice de modulao que pode ser obtido sem que haja distoro no sinal de sada.


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Figura 4.1: Modulador de amplitude.


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5. MULTIPLICADORES ANALGICOSOBJETIVO

Familiarizar o aluno quanto s tcnicas de multiplicao de sinais analgicos variantes no tempo e

sua aplicao como moduladores em amplitude com e sem portadora, detectores sncronos, detectores defase, dobradores de freqncia, extratores de raiz quadrada, etc.

INTRODUODurante muito tempo a multiplicao analgica foi conseguida atravs de vrias tcnicas como:

- mtodo do quadrado da soma usando dispositivos no lineares que apresentem caractersticas

quadrticas, predominantes ou no, como FETs, diodos ou transistores de juno, seguidos de

filtros passa-faixa.

- mtodo do quadrado da soma balanceada, usando os mesmos dispositivos anteriores, mas em cir-cuitos onde a portadora suprimida (mais de 40dB) ou reduzida (mais de 20dB). Em baixas fre-

qncias pode-se simular um dispositivo com caractersticas quadrticas com operacionais e redes

de realimentao providas de resistores e diodos em srie. Para cada tenso de entrada o ganho

ser diferente e aproximao por partes poder ser quadrtica.

- mtodo da modulao por largura de pulsos.

- mtodo dos amplificadores logartmicos.

- mtodo dos amplificadores de transcondutncia varivel [1].

Todas estas tcnicas sero analisadas nas aulas tericas.

A presente prtica ser sobre os moduladores balanceados de transcondutncia varivel e com os co-

letores dos diferenciais cruzados, conhecidos como clulas de Gilbert[1]. Estas clulas so comuns a vrios

integrados como multiplicadores de quatro quadrantes, moduladores, etc.

TRABALHO PREPARATRIO

1 - Estudar as caractersticas tcnicas do modulador balanceado MC1496.

2 - Estudar os circuitos apresentados com as funes:

- Modulador AM DSB

- Modulador AM DSB SC

3 - Usando a identidade

( ) ( ) ( ) ( ) sen a sen b sen a b sen a b= + + 1

2

1

2

sendo a tc= + e b tc= idealizar um circuito que possa fornecer uma tenso de sada proporcional ao desvio de fase entre os

sinais a e b, sendo < 4 , onde ( )sen .


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PRTICA

1 - Montar um circuito modulador em amplitude da Figura 5.1 que possa funcionar como AM DSB eAM DSB SC numa freqncia de portadora c rad s= 2 100 10

3e freqncia da moduladora

m mf= 2 , fm variando de 100Hz a 3kHz.

2 - Mea as polarizaes e observe no osciloscpio as formas de onda do item 1, medindo os ndices demodulao em amplitude para AM DSB.

3 - Observe no analisador de espectro as formas de onda do item 1, anotando os resultados. Varie o poten-cimetro que reduz a portadora, medindo o melhor resultado.

4 - Montar o circuito projetado como detector de fase. Caso necessite de um defasador de 2 utilize re-des RC.

Figura 5.1: Modulador balanceado.

Responda:

- Em que se baseia a modulao sncrona? Onde usada?

- Como se poderia obter um oitavador musical?

- Como se poderia obter um extrator de raiz quadrada?

Referncias

[1] Manual da Motorola em anexo.

[2] Design of Analog Integrated Circuits. P. Gray, M. Meyer. John Wiley, Mp.


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6. MODULADOR DE FREQNCIA

OBJETIVOEstudo de um circuito Modulador de Freqncia (FM).

ESPECIFICAESProjetar um circuito Modulador de Freqncia, tomando por base o circuito da Figura 6.1, de forma

a atender as especificaes abaixo:

1 - Freqncia da portadora igual a 40MHz.

2 - Freqncia de corte inferior, para o sinal modulador, de 50Hz.

3 - Freqncia de corte superior, para o sinal modulador, de 50kHz.

PROCEDIMENTOS1 - Determine R4 e C4 de forma a atender as especificaes de freqncias de corte inferior e superior

para o sinal modulador. Considere a capacitncia do diodo varactorem torno de 15pF.

2 - Calcule C1, C2 e L para que o circuito oscile na freqncia de 40MHz. Para isto, reflita todas as ca-

pacitncias e resistncias para o coletor do transistorBF494. A freqncia pode ser determinada pela

frmula abaixo:

fLCeq

= 12

.

3 - A bobina deve ser confeccionada com fio rgido esmaltado (fio de enrolar motor), com uma nica ca-

mada de espiras e com forma cilndrica. Para o clculo do nmero de espiras e das dimenses da bo-

bina, deve ser usada a frmula abaixo:

Lr N

r h=

+

0 394

9 10

2 2.

onde

L - a indutncia em H.r - o raio da bobina em cm.

N - o nmero de espiras.

h - o comprimento da bobina em cm.

MEDIDAS

1 - Sem aplicar o gerador de sinais, varie o potencimetro P entre o mnimo e o mximo. Faa um

grfico da freqncia de oscilao pela tenso no ponto A (que a tenso que polariza o diodo

varactor), e calcule a constante ko do oscilador.

2 - Conecte o gerador de sinais ao modulador, e com o auxlio do Analisador de Espectro, observe e

anote a forma do sinal Vo(t) no domnio da freqncia. Fixe a freqncia do gerador de sinais em


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30kHz, e aumente a amplitude do sinais at que se observe o primeiro apagamento da portadora, que

ocorre quando mf 2 4. , sendo mff

fm=

o ndice de modulao, f k V o B= o desvio de freqncia

e fm a freqncia de modulao. Anote o valor da amplitude do sinal modulador.

3 - Retire os capacitores C1 e C2, de forma que o circuito pare de oscilar. Mea a atenuao

( ) ( ) ( )H j V j V jB A = na freqncia de 30kHz. Com a amplitude anotada no item 4, calcule

( )k

f

H j V o

m

m A

=2 4.

maxe compare com o valor obtido no item 1.

Figura 6.1: Circuito modulador de freqncia.

OBS: Na modulao FM temos:

( ) ( )f t f f f ti c m= + cos

( ) ( ) i it 2 f t dt=

( ) ( )

i c

m

mt 2 f tf

f2 f t= + sen


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7. FONTES CHAVEADAS

OBJETIVO

Projetar e verificar o funcionamento dos conversores BOOST, FLYBACK e BUCK.

PRTICA

a) Conversor BOOST

O circuito da Figura 7.1 um conversor BOOST operando no modo descontnuo. Dimensione RL e CLde forma a se obter VL=20V com =0.5 e uma variao mxima de 0.1V. A tenso VCC deve ser ajustada em5V, e Vp conforme a Figura 7.2. Assuma uma freqncia de chaveamento de 10kHZ.

- equaes de projeto:

Tempo de carregamento do indutor L, TC=T, 00.5

Tempo de descarregamento do indutor L, TD=1T, 01(1-)

Tenso de sada ( ) CCDTCCL VVVVV +=1

, onde VT e VD so as tenses de conduo do transistor e

diodo D1 respectivamente.

A corrente no indutor na fronteira do modo contnuo para o descontnuo

( ) ( )L

TVVI TCCfronteiraL

2

1_

=

Indutor( )

L

TCC

I

TVVL

2

1

2

= , onde IL a corrente DC na carga RL, e To perodo de chaveamento.

Corrente mxima acumulada no indutor L,( )

IV V T

L

CC T

max =

Capacitor em funo da mxima variao de tenso na sada, CI T

V

L

L

=

- medidas:

1) Simule o circuito.2) Mea a tenso de sada (ripple).

3) Mea a variao de tenso na sada.

4) Registre a tenso no ponto B.

5) Verifique a corrente de carga e descarga do indutor, observando a tenso no ponto A. V V I A CC = 100 .

6) Varie de 0.1 a 0.5, e plote um grfico de VL em funo de .7) Compare os resultados prticos com os calculados e os obtidos previamente por simulao. Justifique as

discrepncias.


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Figura 7.1: Conversor BOOST.

Figura 7.2: Fonte de excitao dos conversores BOOST e FLYBACK.

b) Conversor FLYBACK

O circuito da Figura 7.3 um conversor FLYBACK operando no modo descontnuo. Dimensione RL e

CL de forma a se obter VL=-20V com =0.5 e uma variao mxima de 0.1V. A tenso VCC deve ser ajustadaem 5V, e Vp conforme a Figura 7.2. Assuma uma freqncia de chaveamento de 10kHZ.



Tempo de descarregamento do indutor L, TD=1T, 01(1-)

Tenso de sada ( ) DTCCL VVVV =1

, onde VT e VD so as tenses de conduo do transistor e diodo

D respectivamente.

Indutor( )( )

LV V T

V V I

CC T

D L L

=

2 2

2, onde IL a corrente DC na carga RL, e To perodo de chaveamento.

Corrente mxima acumulada no indutor L,( )

IV V T

L

CC T

max =

Capacitor em funo da mxima variao de tenso na sada, CI T

V

L

L

=


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- medidas:

1) Simule o circuito.

2) Mea a tenso de sada (ripple).


4) Registre a tenso no ponto A.

5) Verifique a corrente de carga e descarga do indutor, observando a tenso no ponto B. V IB = 100 .

6) Varie de 0.1 a 0.5, e plote um grfico de VL em funo de .7) Compare os resultados prticos com os calculados e os obtidos previamente por simulao. Justifique as

discrepncias.

Figura 7.3: Conversor FLYBACK.

c) Conversor BUCK

O circuito da Figura 7.4 um conversor BUCK. Dimensione RL e CL de forma a se obter VL=5V com

=0.5 e uma atenuao mnima, do filtro LC, de 0.01 na freqncia de chaveamento. A tenso VCC deve serajustada em 10V, e Vp conforme a Figura 7.5. Assuma uma freqncia de chaveamento de 10kHZ. Considere

tambm a possibilidade poder variar de um valor mnimo de 0.2 a um mximo de 1.



Tenso de sada ( ) ( )V V V V L CC T D= 1 , onde VT e VD so as tenses de conduo do transistor e

diodo D respectivamente.

Capacitor( ) AL

TC

2

2

2= , onde A a atenuao do filtro LC na freqncia de chaveamento, T o

perodo de chaveamento.

A corrente mnima na carga ILmin que garante a corrente I no indutor maior que zero, com mnimo ( )

( )TDCCL VVVL

TI +

=

2

1 minminmin_

.

O resistor mximo admissvel min_

min_

max_

L

L

LI

VR =


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- medidas:

1) Simule o circuito (ripple).

2) Mea a tenso de sada.


4) Registre a tenso no ponto A.

5) Varie de 0.2 a 1, e plote um grfico de VL em funo de .6) Compare os resultados prticos com os calculados e os obtidos previamente por simulao. Justifique as

discrepncias.

Figura 7.4: Conversor BUCK.

Figura 7.5: Fonte de excitao do conversor BUCK.


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DATASHEETS


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Philips Semiconductors Product specification

High-speed diodes 1N4148; 1N4448

FEATURES

Hermetically sealed leaded glass

SOD27 (DO-35) package

High switching speed: max. 4 ns

General application

Continuous reverse voltage:

max. 75 V

Repetitive peak reverse voltage:

max. 75 V

Repetitive peak forward current:

max. 450 mA.

APPLICATIONS

High-speed switching.

DESCRIPTION

The 1N4148 and 1N4448 are high-speed switching diodes fabricated in planar

technology, and encapsulated in hermetically sealed leaded glass SOD27

(DO-35) packages.

Fig.1 Simplified outline (SOD27; DO-35) and symbol.

The diodes are type branded.

handbook, halfpage

MAM246

k a

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. Device mounted on an FR4 printed circuit-board; lead length 10 mm.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VRRM repetitive peak reverse voltage 75 V

VR continuous reverse voltage 75 V

IF continuous forward current see Fig.2; note 1 200 mA

IFRM repetitive peak forward current 450 mA

IFSM non-repetitive peak forward current square wave; Tj = 25 C prior to

surge; see Fig.4

t = 1 s 4 A

t = 1 ms 1 A

t = 1 s 0.5 A

Ptot total power dissipation Tamb = 25 C; note 1 500 mW

Tstg storage temperature 65 +200 C

Tj junction temperature 200 C


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ELECTRICAL CHARACTERISTICS

Tj = 25 C unless otherwise specified.

THERMAL CHARACTERISTICS

Note

1. Device mounted on a printed circuit-board without metallization pad.


VF forward voltage see Fig.3

1N4148 IF = 10 mA 1 V

1N4448 IF = 5 mA 0.62 0.72 V

IF = 100 mA 1 V

IR reverse current VR = 20 V; see Fig.5 25 nA

VR = 20 V; Tj = 150 C; see Fig.5 50 A

IR reverse current; 1N4448 VR = 20 V; Tj = 100 C; see Fig.5 3 A

Cd diode capacitance f = 1 MHz; VR = 0; see Fig.6 4 pFtrr reverse recovery time when switched from IF = 10 mA to

IR = 60 mA; RL = 100 ;

measured at IR = 1 mA; see Fig.7

4 ns

Vfr forward recovery voltage when switched from IF = 50 mA;

tr = 20 ns; see Fig.8

2.5 V

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth j-tp thermal resistance from junction to tie-point lead length 10 mm 240 K/W

Rth j-a thermal resistance from junction to ambient lead length 10 mm; note 1 350 K/W


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GRAPHICAL DATA

Fig.2 Maximum permissible continuous forward

current as a function of ambient

temperature.

handbook, halfpage

0 100 200

300

200

0

100

MBG451

Tamb (oC)

IF(mA)

Device mounted on an FR4 printed-circuit board; lead length 10 mm.

Fig.3 Forward current as a function of forward

voltage.

handbook, halfpage

0 1 2

600

0

200

400

MBG464

VF (V)

IF(mA)

(1) (2) (3)

(1) Tj = 175 C; typical values.

(2) Tj = 25 C; typical values.

(3) Tj = 25 C; maximum values.

Fig.4 Maximum permissible non-repetitive peak forward current as a function of pulse duration.

Based on square wave currents.

Tj = 25 C prior to surge.

handbook, full pagewidth

MBG704

10 tp (s)1

IFSM(A)

102

101

104102 103

10

1


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Fig.5 Reverse current as a function of junction

temperature.

(1) VR = 75 V; typical values.

(2) VR = 20 V; typical values.

handbook, halfpage

0 100Tj (

oC)200

103

102

101

102

10(1)

1

IR(A)

MGD290

(2)

Fig.6 Diode capacitance as a function of reverse

voltage; typical values.

f = 1 MHz; Tj = 25 C.

handbook, halfpage

0 10 20

1.2

1.0

0.6

0.4

0.8

MGD004

VR (V)

Cd(pF)


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Fig.7 Reverse recovery voltage test circuit and waveforms.


t rr

(1)

IFt

output signal

t rt

t p

10%

90%VR

input signal

V = V I x RR F S

R = 50S

IF

D.U.T.

R = 50i

SAMPLINGOSCILLOSCOPE

MGA881

(1) IR = 1 mA.

Fig.8 Forward recovery voltage test circuit and waveforms.

t r

tt p

10%

90%I

inputsignal

R = 50S

I

R = 50i

OSCILLOSCOPE

1 k 450

D.U.T.

MGA882

Vfr

t

outputsignal

V


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NPN general purpose transistors BC546; BC547


Note

1. Transistor mounted on an FR4 printed-circuit board.

CHARACTERISTICS


Notes

1. VBEsat decreases by about 1.7 mV/K with increasing temperature.

2. VBE decreases by about 2 mV/K with increasing temperature.


Rth j-a thermal resistance from junction to ambient note 1 0.25 K/mW

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

ICBO

collector cut-off current IE

= 0; VCB

= 3 0 V 15 nA

IE = 0; VCB = 30 V; Tj = 150 C 5 A

IEBO emitter cut-off current IC = 0; VEB = 5 V 100 nA

hFE DC current gain IC = 10 A; VCE = 5 V;

see Figs 2, 3 and 4BC546A 90

BC546B; BC547B 150

BC547C 270

DC current gain IC = 2 mA; VCE = 5 V;

see Figs 2, 3 and 4BC546A 110 180 220

BC546B; BC547B 200 290 450

BC547C 420 520 800

BC547 110 800

BC546 110 450

VCEsat collector-emitter saturation

voltage

IC = 10 mA; IB = 0.5 mA 90 250 mV

IC = 100 mA; IB = 5 m A 200 600 mV

VBEsat base-emitter saturation voltage IC = 10 mA; IB = 0.5 mA; note 1 700 mV

IC = 100 mA; IB = 5 mA; note 1 900 mV

VBE base-emitter voltage IC = 2 mA; VCE = 5 V; note 2 580 660 700 mV

IC = 10 mA; VCE = 5 V 770 mV

Cc collector capacitance IE = ie = 0; VCB = 10 V; f = 1 MHz 1.5 pF

Ce emitter capacitance IC = ic = 0; VEB = 0.5 V; f = 1 MHz 11 pF

fT transition frequency IC = 10mA; VCE = 5 V; f = 100 MHz 100 MHz

F noise figure IC = 200 A; VCE = 5 V;

RS = 2 k; f = 1 kHz; B = 200 Hz

2 10 dB


28/67



Fig.2 DC current gain; typical values.


0

250

50

100

150

200

MBH723

102 101

hFE

1 IC (mA)10 103102

VCE = 5 V

BC546A.



0

300

100

200

MBH724

102 101

hFE

1 IC (mA)10 103102

VCE = 5 V

BC546B; BC547B.


29/67





0

600

200

400

MBH725

102 101

hFE

1 IC (mA)10 103102

VCE = 5 V

BC547C.


30/67


PNP general purpose transistors BC556; BC557

FEATURES

Low current (max. 100 mA)

Low voltage (max. 65 V).

APPLICATIONS

General purpose switching and amplification.

DESCRIPTION

PNP transistor in a TO-92; SOT54 plastic package.

NPN complements: BC546 and BC547.

PINNING

PIN DESCRIPTION

1 emitter

2 base

3 collector

Fig.1 Simplified outline (TO-92; SOT54)

and symbol.

handbook, halfpage1

3

2

MAM281

3

2

1

LIMITING VALUES



VCBO collector-base voltage open emitter

BC556 80 V

BC557 50 V

VCEO collector-emitter voltage open base

BC556 65 V

BC557 45 V

VEBO emitter-base voltage open collector 5 V

IC collector current (DC) 100 mA

ICM peak collector current 200 mA

IBM peak base current 200 mA

Ptot total power dissipation Tamb 25 C 500 mW


Tj junction temperature 150 C

Tamb operating ambient temperature 65 +150 C


31/67




Note


CHARACTERISTICS


Notes

1. VBEsat decreases by about 1.7 mV/K with increasing temperature.

2. VBE decreases by about 2 mV/K with increasing temperature.


Rth j-a thermal resistance from junction to ambient note 1 250 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

ICBO

collector cut-off current IE

= 0; VCB

= 30 V 1 15 nA

IE = 0; VCB = 30 V; Tj = 150 C 4 A


hFE DC current gain IC = 2 mA; VCE = 5 V;

see Figs 2, 3 and 4BC556 125 475

BC557 125 800

BC556A 125 250

BC556B; BC557B 220 475

BC557C 420 800

VCEsat collector-emitter saturation

voltage

IC = 10 mA; IB = 0.5 mA 60 300 mV

IC = 100 mA; IB = 5 mA 180 650 mV

VBEsat base-emitter saturation voltage IC = 10 mA; IB = 0.5 mA; note 1 750 mV

IC = 100 mA; IB = 5 mA; note 1 930 mV

VBE base-emitter voltage IC = 2 mA; VCE = 5 V; note 2 600 650 750 mV

IC = 10 mA; VCE = 5 V; note 2 820 mV

Cc collector capacitance IE = ie = 0; VCB = 10 V; f = 1 MHz 3 pF

Ce emitter capacitance IC = ic = 0; VEB = 0.5 V; f = 1 MHz 10 pF

fT transition frequency IC = 10 mA; VCE = 5 V; f = 100 MHz 100 MHz

F noise figure IC = 200 A; VCE = 5 V; RS = 2 k;

f = 1 kHz; B = 200 Hz

2 10 dB


32/67





0

300

100

200

MBH726

101

hFE

1 IC (mA)10 103102

VCE = 5 V

BC556A.



0

300

200

100

400MBH727

102 101

hFE

1 IC (mA)10 103102

VCE = 5 V

BC556B; BC557B.


33/67





0

300

200

100

600

500

400

MBH728

102 101

hFE

1 IC (mA)10 103102

VCE = 5 V

BC557C.


34/67


NPN medium frequency transistors BF494; BF495

FEATURES

Low current (max. 30 mA)

Low voltage (max. 20 V).

APPLICATIONS

HF applications in radio and television receivers

FM tuners

Low noise AM mixer-oscillators

IF amplifiers in AM/FM receivers.

DESCRIPTION

NPN medium frequency transistor in a TO-92; SOT54

plastic package.

PINNING

PIN DESCRIPTION

1 base

2 emitter

3 collector

Fig.1 Simplified outline (TO-92; SOT54)

and symbol.

handbook, halfpage1

3

2

MAM258

3

1

2

QUICK REFERENCE DATA


VCBO collector-base voltage open emitter 30 V

VCEO collector-emitter voltage open base 20 V

ICM peak collector current 30 mAPtot total power dissipation Tamb 25 C 300 mW

hFE DC current gain IC = 1 mA; VCE = 10 V

BF494 67 220

BF495 35 125



35/67


NPN medium frequency transistors BF494; BF495

LIMITING VALUES


Note



Note


CHARACTERISTICS

Tamb = 25 C unless otherwise specified.


VCBO collector-base voltage open emitter 30 V

VCEO collector-emitter voltage open base 20 V

VEBO emitter-base voltage open collector 5 V

IC collector current (DC) 30 mA

ICM peak collector current 30 mA

Ptot total power dissipation Tamb 25 C; note 1 300 mW


Tj junction temperature 150 CTamb operating ambient temperature 65 +150 C


Rth j-a thermal resistance from junction to ambient note 1 420 K/W


ICBO collector cut-off current IE = 0; VCB = 2 0 V 100 nA

IE = 0; VCB = 20 V; Tamb = 150 C 4 A


hFE DC current gain IC = 1 mA; VCE = 1 0 V

BF494 67 220

BF494B 100 220

BF495 35 125

BF495B 100 125

VBE base-emitter voltage IC = 1 mA; VCE = 10 V 650 740 mV

Cre feedback capacitance IC = 0; VCB = 10 V; f = 1 MHz 1 pF



36/67

TIP29, TIP29A, TIP29B, TIP29CNPN SILICON POWER TRANSISTORS

P R O D U C T I N F O R M A T I O N

JULY 1968 - REVISED MARCH 1997Copyright 1997, Power Innovations Limited, UK

q Designed for Complementary Use with the

TIP30 Series

q 30 W at 25C Case Temperature

q 1 A Continuous Collector Current

q 3 A Peak Collector Current

q Customer-Specified Selections Available

B

C

E

TO-220 PACKAGE(TOP VIEW)

Pin 2 is in electrical contact with the mounting base.MDTRACA

1

2

3

absolute maximum ratings at 25C case temperature (unless otherwise noted)

NOTES: 1. This value applies for tp 0.3 ms, duty cycle 10%.

2. Derate linearly to 150C case temperature at the rate of 0.24 W/C.

3. Derate linearly to 150C free air temperature at the rate of 16 mW/C.

4. This rating is based on the capability of the transistor to operate safely in a circuit of: L = 20 mH, IB(on) = 0.4 A, RBE = 100 ,

VBE(off) = 0, RS = 0.1 , VCC = 20 V.

RATING SYMBOL VALUE UNIT

Collector-base voltage (IE = 0)

TIP29

TIP29A

TIP29B

TIP29C

VCBO

80

100

120

140

V

Collector-emitter voltage (IB = 0)

TIP29

TIP29A

TIP29B

TIP29C

VCEO

40

60

80

100

V

Emitter-base voltage VEBO 5 V

Continuous collector current IC 1 A

Peak collector current (see Note 1) ICM 3 A

Continuous base current IB 0.4 A

Continuous device dissipation at (or below) 25C case temperature (see Note 2) Ptot 30 WContinuous device dissipation at (or below) 25C free air temperature (see Note 3) Ptot 2 W

Unclamped inductive load energy (see Note 4) LIC2 32 mJ

Operating junction temperature range Tj -65 to +150 C

Storage temperature range Tstg -65 to +150 C

Lead temperature 3.2 mm from case for 10 seconds TL 250 C


37/67


JULY 1968 - REVISED MARCH 1997


NOTES: 5. These parameters must be measured using pulse techniques, tp = 300 s, duty cycle 2%.

6. These parameters must be measured using voltage-sensing contacts, separate from the current carrying contacts.

Voltage and current values shown are nominal; exact values vary slightly with transistor parameters.

electrical characteristics at 25C case temperature

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V(BR)CEOCollector-emitter

breakdown voltage IC = 30 mA

(see Note 5)

IB = 0

TIP29

TIP29A

TIP29B

TIP29C

40

60

80

100

V

ICESCollector-emitter

cut-off current

VCE = 80 V

VCE = 100 V

VCE = 120 V

VCE = 140 V

VBE = 0

VBE = 0

VBE = 0

VBE = 0

TIP29

TIP29A

TIP29B

TIP29C

0.2

0.2

0.2

0.2

mA

ICEOCollector cut-off

current

VCE = 30 V

VCE = 60 V

IB = 0

IB = 0

TIP29/29A

TIP29B/29C

0.3

0.3mA

IEBOEmitter cut-off

currentVEB = 5 V IC = 0 1 mA

hFEForward current

transfer ratio

VCE = 4 V

VCE = 4 V

IC = 0.2 A

IC = 1 A(see Notes 5 and 6)

40

15 75

VCE(sat)Collector-emitter

saturation voltageIB = 125 mA IC = 1 A (see Notes 5 and 6) 0.7 V

VBEBase-emitter

voltageVCE = 4 V IC = 1 A (see Notes 5 and 6) 1.3 V

hfeSmall signal forward

current transfer ratioVCE = 10 V IC = 0.2 A f = 1 kHz 20

|hfe|Small signal forward

current transfer ratioVCE = 10 V IC = 0.2 A f = 1 MHz 3

thermal characteristics

PARAMETER MIN TYP MAX UNIT

RJC Junction to case thermal resistance 4.17 C/W

RJA Junction to free air thermal resistance 62.5 C/W

resistive-load-switching characteristics at 25C case temperature


ton Turn-on time IC = 1 A

VBE(off) = -4.3 V

IB(on) = 0.1 A

RL = 30

IB(off) = -0.1 A

tp = 20 s, dc 2%

0.5 s

toff Turn-off time 2 s


38/67




TYPICAL CHARACTERISTICS

Figure 1. Figure 2.

Figure 3.

TYPICAL DC CURRENT GAIN

vsCOLLECTOR CURRENT

IC

- Collector Current - A

0001 001 01 10

hFE

-DCCurrentGain

1

10

100

1000TCS631AD

VCE = 4 V

TC

= 25C

tp = 300 s, duty cycle < 2%

COLLECTOR-EMITTER SATURATION VOLTAGE

vsBASE CURRENT

IB

- Base Current - mA

01 10 10 100 1000

VCE(sat)-Collecto

r-EmitterSaturationVoltage-V

001

01

10

10TCS631AE

IC = 100 mA

IC

= 300 mA

IC

= 1 A

BASE-EMITTER VOLTAGEvs

COLLECTOR CURRENT

IC - Collector Current - A

001 01 10

VBE-Base-Em

itterVoltage-V

05

06

07

08

09

10TCS631AF

VCE = 4 V

TC = 25C


39/67




MAXIMUM SAFE OPERATING REGIONS

Figure 4.

THERMAL INFORMATION

Figure 5.

MAXIMUM FORWARD-BIASSAFE OPERATING AREA

VCE

- Collector-Emitter Voltage - V

10 10 100 1000

IC-C

ollectorCurrent-A

001

01

10

10

100SAS631AC

TIP29TIP29ATIP29BTIP29C

tp

= 300 s, d = 0.1 = 10%

tp = 1 ms, d = 0.1 = 10%

tp

= 10 ms, d = 0.1 = 10%

DC Operation

MAXIMUM POWER DISSIPATIONvs

CASE TEMPERATURE

TC

- Case Temperature - C

0 25 50 75 100 125 150

Ptot-MaximumP

owerDissipation-W

0

10

20

30

40TIS631AB


40/67

TIP30, TIP30A,TIP30B, TIP30CPNP SILICON POWER TRANSISTORS


JULY 1968 - REVISED MARCH 1997Copyright 1997, Power Innovations Limited, UK

q Designed for Complementary Use with the

TIP29 Series

q 30 W at 25C Case Temperature

q 1 A Continuous Collector Current

q 3 A Peak Collector Current

q Customer-Specified Selections Available

B

C

E

TO-220 PACKAGE(TOP VIEW)

Pin 2 is in electrical contact with the mounting base.MDTRACA

1

2

3

absolute maximum ratings at 25C case temperature (unless otherwise noted)

NOTES: 1. This value applies for tp 0.3 ms, duty cycle 10%.

2. Derate linearly to 150C case temperature at the rate of 0.24 W/C.

3. Derate linearly to 150C free air temperature at the rate of 16 mW/C.

4. This rating is based on the capability of the transistor to operate safely in a circuit of: L = 20 mH, IB(on) = -0.4 A, RBE = 100 ,

VBE(off) = 0, RS = 0.1 , VCC = -20 V.

RATING SYMBOL VALUE UNIT

Collector-base voltage (IE = 0)

TIP30

TIP30A

TIP30B

TIP30C

VCBO

-80

-100

-120

-140

V

Collector-emitter voltage (IB = 0)

TIP30

TIP30A

TIP30B

TIP30C

VCEO

-40

-60

-80

-100

V

Emitter-base voltage VEBO -5 V

Continuous collector current IC -1 A

Peak collector current (see Note 1) ICM -3 A

Continuous base current IB -0.4 A

Continuous device dissipation at (or below) 25C case temperature (see Note 2) Ptot 30 WContinuous device dissipation at (or below) 25C free air temperature (see Note 3) Ptot 2 W

Unclamped inductive load energy (see Note 4) LIC2 32 mJ

Operating junction temperature range Tj -65 to +150 C

Storage temperature range Tstg -65 to +150 C

Lead temperature 3.2 mm from case for 10 seconds TL 250 C


41/67




NOTES: 5. These parameters must be measured using pulse techniques, tp = 300 s, duty cycle 2%.

6. These parameters must be measured using voltage-sensing contacts, separate from the current carrying contacts.

Voltage and current values shown are nominal; exact values vary slightly with transistor parameters.

electrical characteristics at 25C case temperature


V(BR)CEOCollector-emitter

breakdown voltage IC = -30 mA

(see Note 5)

IB = 0

TIP30

TIP30A

TIP30B

TIP30C

-40

-60

-80

-100

V

ICESCollector-emitter

cut-off current

VCE = -80 V

VCE = -100 V

VCE = -120 V

VCE = -140 V

VBE = 0

VBE = 0

VBE = 0

VBE = 0

TIP30

TIP30A

TIP30B

TIP30C

-0.2

-0.2

-0.2

-0.2

mA

ICEOCollector cut-off

current

VCE = -30 V

VCE = -60 V

IB = 0

IB = 0

TIP30/30A

TIP30B/30C

-0.3

-0.3mA

IEBOEmitter cut-off

currentVEB = -5 V IC = 0 -1 mA

hFEForward current

transfer ratio

VCE = -4 V

VCE = -4 V

IC = -0.2 A

IC = -1 A(see Notes 5 and 6)

40

15 75

VCE(sat)Collector-emitter

saturation voltageIB = -125 mA IC = -1 A (see Notes 5 and 6) -0.7 V

VBEBase-emitter

voltageVCE = -4 V IC = -1 A (see Notes 5 and 6) -1.3 V

hfeSmall signal forward

current transfer ratioVCE = -10 V IC = -0.2 A f = 1 kHz 20

|hfe|Small signal forward

current transfer ratioVCE = -10 V IC = -0.2 A f = 1 MHz 3

thermal characteristics

PARAMETER MIN TYP MAX UNIT

RJC Junction to case thermal resistance 4.17 C/W

RJA Junction to free air thermal resistance 62.5 C/W

resistive-load-switching characteristics at 25C case temperature


ton Turn-on time IC = -1 A

VBE(off) = 4.3 V

IB(on) = -0.1 A

RL = 30

IB(off) = 0.1 A

tp = 20 s, dc 2%

0.3 s

toff Turn-off time 1 s


42/67





Figure 1. Figure 2.

Figure 3.

TYPICAL DC CURRENT GAIN

vsCOLLECTOR CURRENT

IC

- Collector Current - A

-0001 -001 -01 -10

hFE

-DCCurrentGain

1

10

100

1000TCS632AD

VCE = -4 V

TC = 25C

tp

= 300 s, duty cycle < 2%

COLLECTOR-EMITTER SATURATION VOLTAGE

vsBASE CURRENT

IB

- Base Current - mA

-01 -10 -10 -100 -1000

VCE(sat)-Collecto

r-EmitterSaturationVoltage-V

-001

-01

-10

-10TCS632AE

IC = -100 mA

IC

= -300 mA

IC

= -1 A

BASE-EMITTER VOLTAGEvs

COLLECTOR CURRENT

IC - Collector Current - A

-001 -01 -10

VBE-Base-Em

itterVoltage-V

-05

-06

-07

-08

-09

-10TCS632AF

VCE = -4 V

TC = 25C


43/67




MAXIMUM SAFE OPERATING REGIONS

Figure 4.

THERMAL INFORMATION

Figure 5.

MAXIMUM FORWARD-BIASSAFE OPERATING AREA

VCE

- Collector-Emitter Voltage - V

-10 -10 -100 -1000

IC-C

ollectorCurrent-A

-001

-01

-10

-10

-100SAS632AB

TIP30TIP30ATIP30BTIP30C

tp

= 300 s, d = 0.1 = 10%

tp = 1 ms, d = 0.1 = 10%

tp

= 10 ms, d = 0.1 = 10%

DC Operation

MAXIMUM POWER DISSIPATIONvs

CASE TEMPERATURE

TC

- Case Temperature - C

0 25 50 75 100 125 150

Ptot-MaximumP

owerDissipation-W

0

10

20

30

40TIS631AB


44/67

TL071, TL071A, TL071B, TL072TL072A, TL072B, TL074, TL074A, TL074B

LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS

SLOS080D SEPTEMBER 1978 REVISED AUGUST 1996

1POST OFFICE BOX 655303 DALLAS, TEXAS 75265

D Low Power Consumption

D Wide Common-Mode and DifferentialVoltage Ranges

D Low Input Bias and Offset Currents

DOutput Short-Circuit Protection

D Low Total Harmonic Distortion0.003% Typ

D Low NoiseVn = 18 nV/Hz Typ at f = 1 kHz

DHigh Input Impedance . . . JFET Input Stage

D Internal Frequency Compensation

DLatch-Up-Free Operation

D High Slew Rate . . . 13 V/s TypD Common-Mode Input Voltage Range

Includes VCC+

description

The JFET-input operational amplifiers in the TL07_ series are designed as low-noise versions of the TL08_series amplifiers with low input bias and offset currents and fast slew rate. The low harmonic distortion and lownoise make the TL07_ series ideally suited for high-fidelity and audio preamplifier applications. Each amplifier

features JFET inputs (for high input impedance) coupled with bipolar output stages integrated on a singlemonolithic chip.

The C-suffix devices are characterized for operation from 0C to 70C. The I-suffix devices are characterized

for operation from 40C to 85

C. The M-suffix devices are characterized for operation over the full militarytemperature range of 55C to 125C.

AVAILABLE OPTIONS

PACKAGE

TAVIOmax

AT 25CSMALL

OUTLINE

(D)

CHIP

CARRIER

(FK)

CERAMIC

DIP

(J)

CERAMIC

DIP

(JG)

PLASTIC

DIP

(N)

PLASTIC

DIP

(P)

TSSOP

PACKAGE

(PW)

FLAT

PACKAGE

(W)

10 mV TL071CD TL071CP TL071CPWLE

6 mV TL071ACD TL071ACP

3 mV TL071BCD TL071BCP

10 mV TL072CD TL072CP TL072CPWLEo

6 mV TL072ACD TL072ACP

3 mV TL072BCD TL072BCP

10 mV TL074CD TL074CN TL074CPWLE

6 mV TL074ACD TL074ACN

3 mV TL074BCD TL074BCN

TL071ID TL071IP o

6 mV TL072ID TL072IP

TL074ID TL074IN

6 mV TL071MFK TL071MJG

o

6 mV TL072MFK TL072MJG TL072MP

9 mV TL074MFK TL074MJ TL074MN TL074MW

The D package is available taped and reeled. Add the suffix R to the device type (e.g., TL071CDR). The PW package is only available left-ended

taped and reeled (e.g., TL072CPWLE).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright 1996, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.


45/67

TL071, TL071A, TL071B, TL072TL072A, TL072B, TL074, TL074A, TL074BLOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS


2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

NC

2OUT

NC

2IN

NC

1IN+

NC

VCC+NC

2IN+

NC

VCC+NC

OUT

NC

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

NC

1IN

NC

1IN+

NC

(TOP VIEW)

NC

1OUT

NC

NC

NC

NC

NC

2IN+

CC

V

CC

+

V

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1OUT

1IN

1IN+

VCC +2IN+

2IN

2OUT

4OUT

4IN

4IN+

VCC 3IN+

3IN

3OUT

TL074, TL074A, TL074B

D, J, N, OR PW PACKAGE

TL074 . . . W PACKAGE

(TOP VIEW)

NC No internal connection

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

NC

IN

NC

IN+

NC

TL071FK PACKAGE

(TOP VIEW)

N

C

O

FFSETN1

N

C

NC

N

C

NC

NC

OFFSETN2

N

C

CC

V

TL072FK PACKAGE

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

4IN+

NC

VCC NC

3IN+

TL074FK PACKAGE

(TOP VIEW)

1IN

1OUT

NC

3IN

4IN

2IN

NC

3OUT

4OUT

2OUT

1

2

3

4

8

7

6

5

OFFSET N1

IN

IN+

VCC

NC

VCC+

OUT

OFFSETN2

TL071, TL071A, TL071B

D, JG, P, OR PW PACKAGE

(TOP VIEW)

1

2

3

4

8

7

6

5

1OUT

1IN

1IN+

VCC

VCC +2OUT

2IN

2IN+

TL072, TL072A, TL072B

D, JG, P, OR PW PACKAGE

(TOP VIEW)

symbols

+

+

IN +

IN

OUT

IN +

IN

OUT

TL072 (each amplifier)TL074 (each amplifier)

TL071

OFFSET N1

OFFSET N2


46/67





schematic (each amplifier)

C1

VCC+

IN +

VCC

1080

1080

IN

TL071 Only

64 128

64

All component values shown are nominal.

OFFSETNULL(N1)

OFFSETNULL(N2)

OUT

18 pF

COMPONENT COUNT

COMPONENT

TYPETL071 TL072 TL074

Resistors 11 22 44

Transistors 14 28 56

JFET 2 4 6

Diodes 1 2 4

Capacitors 1 2 4

epi-FET 1 2 4

Includes bias and trim circuitry


47/67




absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC+ (see Note 1) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Supply voltage, VCC(see Note 1) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Differential input voltage, VID (see Note 2) 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Input voltage, VI (see Notes 1 and 3) 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Duration of output short circuit (see Note 4) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Operating free-air temperature range, TA: C suffix 0C to 70C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I suffix 40C to 85C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .M suffix 55C to 125C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range 65C to 150C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Case temperature for 60 seconds: FK package 260C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: J, JG, or W package 300C. . . . . . . . . . . .Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, P, or PW package 260C. . . . . . . . .

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC.

2. Differential voltages are at IN+ with respect to IN.3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.

4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the

dissipation rating is not exceeded.

DISSIPATION RATING TABLE

PACKAGETA 25C

POWER RATING

DERATING

FACTOR

DERATE

ABOVE TA

TA = 70C

POWER RATING

TA = 85C

POWER RATING

TA = 125C

POWER RATING

D (8 pin) 680 mW 5.8 mW/ C 33C 465 mW 378 mW N/A

D (14 pin) 680 mW 7.6 mW/ C 60C 604 mW 490 mW N/A

FK 680 mW 11.0 mW/ C 88C 680 mW 680 mW 273 mW

J 680 mW 11.0 mW/ C 88C 680 mW 680 mW 273 mW

JG 680 mW 8.4 mW/ C 69C 672 mW 546 mW 210 mW

N 680 mW 9.2 mW/ C 76C 680 mW 597 mW N/A

P 680 mW 8.0 mW/ C 65C 640 mW 520 mW N/A

PW (8 pin) 525 mW 4.2 mW/ C 70C 525 mW N/A N/A

PW (14 pin) 700 mW 5.6 mW/ C 70C 700 mW N/A N/A

W 680 mW 8.0 mW/ C 65C 640 mW 520 mW 200 mW


48/67

POSTOFFICEBOX6

55303

DALLAS,TEXAS

75265

5

electrical characteristics, VCC = 15 V (unless otherwise noted)

TL071C TL071AC TL071BC

TL072C TL072AC TL072BCPARAMETER TEST CONDITIONS TA TL074C TL074AC TL074BC

MIN TYP MAX MIN TYP MAX MIN TYP

p25C 3 10 3 6 2

IO npu o se vo age O = , S =

Full range 13 7.5

VIO

Temperature

coefficient of input

offset voltage

VO = 0, RS = 50 Full range 18 18 18

25C 5 100 5 100 5IO npu o se curren O =

Full range 10 2

p25C 65 200 65 200 65

IB npu as curren O =Full range 7 7

12 12 12VICR

Common-mode

p25C 11 to 11 to 11 to

n u vo age range15 15 15

Maximum peak RL = 10 k 25C 12 13.5 12 13.5 12 13.5

VOM

output voltage RL 10 k 12 12 12

swing RL 2 ku range 10 10 10

Large-signal 25C 25 200 50 200 50 200

VD eren a vo age

amplificationO = , L

Full range 15 25 25

B1Unity-gain

bandwidth25C 3 3 3

ri Input resistance 25C 1012 1012 1012

Common-mode VIC = VICRmin,

rejection ratio VO = 0, RS = 50

Supply-voltageVCC = 9 V to 15 V,

SVR

(VCC/VIO)VO = 0, RS = 50

Supply current CC (each amplifier) O= , o oa . . . . .

VO1/VO2Crosstalk

attenuationAVD = 100 25C 120 120 120

All characteristics are measured under open-loop conditions with zero common-mode voltage unless otherwise specified. Full range is TA = 0C to 70C for TL07_C,TL07_AC, TL07_BC and is TA = 40C to 85C for TL07_I. Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive as shown in F

that maintain the junction temperature as close to the ambient temperature as possible.


49/67


50/67





operating characteristics, VCC =15 V, TA= 25C

TL07xM ALL OTHERS

MIN TYP MAX MIN TYP MAX

SR Slew rate at unity gainVI = 10 V,

CL = 100 pF,

RL = 2 k,

See Figure 15 13 8 13 V/ s

Rise time overshoot VI = 20 mV, RL = 2 k, 0.1 0.1 sr factor CL = 100 pF, See Figure 1 20% 20%

Equivalent input noise f = 1 kHz 18 18 nV/Hzn voltage S

=f = 10 Hz to 10 kHz 4 4 V

InEquivalent input noise

currentRS = 20 , f = 1 kHz 0.01 0.01 pA/Hz

THDTotal harmonic

distortion

VIrms = 6 V,

RL 2 k,

f = 1 kHz

AVD = 1,

RS 1 k , 0.003% 0.003%

PARAMETER MEASUREMENT INFORMATION

Figure 1. Unity-Gain Amplifier

VI+

CL = 100 pF RL = 2 k

VO

Figure 2. Gain-of-10 Inverting Amplifier

VI

+

10 k

1 k

RL CL = 100 pF

VO

N1

100 k

+

TL071

N2

1.5 k

VCC

OUT

IN

IN +

Figure 3. Input Offset Voltage Null Circuit


51/67


52/67






Figure 4

IIB

Inpu

tBias

Curren

tn

A

TA Free-Air Temperature C

INPUT BIAS CURRENT

vs

FREE-AIR TEMPERATURE

IBI

10

1

0.1

0.01

100

75 50 25 0 25 50 75 100 125

VCC = 15 V

Figure 5

VCC = 5 V

VCC = 15 V RL = 10 kTA = 25C

See Figure 2

15

12.5

10

7.5

5

2.5

0

VOM

Max

imum

Pea

kOu

tpu

tVo

ltage

V

f Frequency Hz

100 1 k 10 k 100 k 1 M 10 M

MAXIMUM PEAK OUTPUT VOLTAGE

vs

FREQUENCY

VOM

VCC = 10 V

Figure 6

10 M1 M100 k10 k1 k100

f Frequency Hz

VOM

Max

imum

Pea

kOu

tpu

tVo

ltage

V

0

2.5

5

7.5

10

12.5

15

See Figure 2

TA

= 25C

RL = 2 k

VCC = 10 V

VCC = 5 V


vs

FREQUENCY

VOM

VCC = 15 V

Figure 7

0

2.5

5

7.5

10

12.5

15

10 k 40 k 100 k 400 k 1 M 4 M 10 M

f Frequency Hz


vs

FREQUENCY

VOM

Max

imum

Pea

kOu

tpu

tVo

ltage

V

VOM

VCC = 15 V

RL = 2 k

See Figure 2

TA = 55C

TA = 25C

TA = 125C

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.


53/67





Figure 8

750

VO

M

Max

imum

Pea

kOu

tpu

tVo

ltage

V


125

15

50 25 0 25 50 75 100

2.5

5

7.5

10

12.5

RL = 10 k

VCC = 15 VSee Figure 2


vs


VO

M

RL = 2 k

Figure 9

0.10

RL Load Resistance k

10

15

2.5

5

7.5

10

12.5

VCC = 15 VTA = 25C

See Figure 2

0.2 0.4 0.7 1 2 4 7


vs

LOAD RESISTANCE

VO

M

Max

imum

Pea

kOu

tpu

tVo

ltage

V

VO

M

Figure 10

00

V

OM

Max

imum

Pea

kOu

tpu

tVo

ltageV

|VCC| Supply Voltage V

16

15

2 4 6 8 10 12 14

2.5

5

7.5

10

12.5

RL = 10 kTA = 25C


vs

SUPPLY VOLTAGE

V

OM

Figure 11

751

Vo

ltage

Amp

lifica

tion

V/mV


125

1000

50 25 0 25 50 75 100

2

4

10

20

40

100

200

400

VCC = 15 V

VO = 10 V

RL = 2 k

LARGE-SIGNAL

DIFFERENTIAL VOLTAGE AMPLIFICATION

vs


AVD

Large-S

igna

lDifferen

tia

l

AVD



54/67






0

45

180

135

90

1

1

f Frequency Hz

10 M

106

10 100 1 k 10 k 100 k 1 M

101

102

103

104

105

DifferentialVoltageAmplification

VCC = 5 V to 15 V

RL = 2 k

TA = 25C

Phase Shift

LARGE-SIGNAL

DIFFERENTIAL VOLTAGE AMPLIFICATION

AND PHASE SHIFT

vs

FREQUENCY

Vo

ltage

Amp

lifica

tion

AVD

Large-S

igna

lDifferen

tia

l

AVD

Phase

Shift

Figure 12

1.02

1.01

1

0.99

0.98

1.03

0.97

750.7

Norma

lize

dUn

ity-Ga

inBan

dw

idth


125

1.3

50 25 0 25 50 75 100

0.8

0.9

1

1.1

1.2 Unity-Gain Bandwidth

VCC = 15 V

RL = 2 k

f = B1 for Phase Shift

NORMALIZED UNITY-GAIN BANDWIDTH

AND PHASE SHIFT

vs


Norma

lize

dPhase

Shift

Phase Shift

Figure 13



55/67





Figure 14

7583

CMR

R

Common-Mo

de

Re

jec

tion

Ra

tio

dB


125

89

50 25 0 25 50 75 100

84

85

86

87

88

VCC = 15 VRL = 10 k

COMMON-MODE REJECTION RATIO

vs


Figure 15

00

|VCC| Supply Voltage V

16

2

2 4 6 8 10 12 14

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8TA = 25CNo SignalNo Load

SUPPLY CURRENT PER AMPLIFIER

vs

SUPPLY VOLTAGE

ICC

Supp

lyCurren

tPer

Amp

lifierm

A

CC

I

Figure 16

750


125

2

50 25 0 25 50 75 100

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

VCC = 15 V

No Signal

No Load

SUPPLY CURRENT PER AMPLIFIER

vs


ICC

Supp

lyCurren

tPer

Amp

lifier

mA

CC

I

Figure 17

750


125

250

50 25 0 25 50 75 100

25

50

75

100

125

150

175

200

225VCC = 15 V

No SignalNo Load

TL074

TL071

TOTAL POWER DISSIPATION

vs


TL072

PD

To

talPower

Diss

ipa

tionmW

PD



56/67






Figure 18

750.85


125

1.15

50 25 0 25 50 75 100

0.90

0.95

1

1.05

1.10

NORMALIZED SLEW RATE

vs


VCC = 15 V

RL = 2 k

CL = 100 pFs

Norma

lize

dSlew

Ra

te

V/

Figure 19

100

Vn

Equ

iva

len

tInpu

tNo

ise

Vo

ltagen

V/Hz

f Frequency Hz

100 k

50

10

20

30

40

VCC = 15 VAVD = 10

RS = 20

TA = 25C

40 100 400 1 k 4 k 10 k 40 k

EQUIVALENT INPUT NOISE VOLTAGE

vs

FREQUENCY

nV/

Hz

Vn

Figure 20

0.001

THD

To

talHarmon

icDistort

ion%

1

40 k10 k4 k1 k400 100 k

f Frequency Hz

100

0.004

0.01

0.04

0.1

0.4

TOTAL HARMONIC DISTORTION

vs

FREQUENCY

VCC = 15 V

AVD = 1

VI(RMS) = 6 V

TA = 25C

Figure 21

6

t Time s

3.5

6

0 0.5 1 1.5 2 2.5 3

4

2

0

2

4

Output

Input

VCC = 15 V

RL = 2 k

TA = 25C

VOLTAGE-FOLLOWER

LARGE-SIGNAL PULSE RESPONSE

CL = 100 pF

VO

VI

Inpu

tan

dOu

tpu

tVo

ltages

V

an

d


57/67





10%

4

VO

Ou

tpu

tVo

ltagem

V

t Elapsed Time s

0.7

28

0 0.1 0.2 0.3 0.4 0.5 0.6

0

4

8

12

16

20

24

VCC = 15 V

RL = 2 k

TA = 25Ctr

Overshoot

90%

OUTPUT VOLTAGE

vs

ELAPSED TIME

VO

Figure 22


58/67

DeviceOperating

Temperature Range Package

M C 1 4 9 6 , B

SEMICONDUCTOR

TECHNICAL DATA

BALANCED

MODULATORS/DEMODULATORS

ORDERING INFORMATION

MC1496D

MC1496PTA = 0C to +70C

SO14

Plastic DIP

PIN CONNECTIONS

Order this document by MC1496/D

D SUFFIXPLASTIC PACKAGE

CASE 751A(SO14)

P SUFFIXPLASTIC PACKAGE

CASE 646

Signal Input 1

2

3

4

5

6

7

10

11

14

13

12

9

N/C

Output

Bias

Signal Input

Gain Adjust

Gain Adjust

Input Carrier8

VEE

N/C

Output

N/C

Carrier Input

N/C

14

1

14

1

MC1496BP Plastic DIPTA = 40C to +125C

1MOTOROLA ANALOG IC DEVICE DATA

B a l a n c e d M o d u l a t o r s /

D e m o d u l a t o r s

These devices were designed for use where the output voltage is a

product of an input voltage (signal) and a switching function (carrier). Typical

applications include suppressed carrier and amplitude modulation,

synchronous detection, FM detection, phase detection, and chopper

applications. See Motorola Application Note AN531 for additional design

information.

Excellent Carrier Suppression 65 dB typ @ 0.5 MHzExcellent Carrier Suppression50 dB typ @ 10 MHz

Adjustable Gain and Signal Handling Balanced Inputs and Outputs High Common Mode Rejection 85 dB typical

This device contains 8 active transistors.

Figure 1. Suppressed

Carrier Output

Waveform

Figure 2. Suppressed

Carrier Spectrum

Figure 3. Amplitude

Modulation Output

Waveform

Figure 4. AmplitudeModulation Spectrum

IC = 500 kHz, IS = 1.0 kHz

IC = 500 kHzIS = 1.0 kHz

60

40

20

0

LogScaleId

499 kHz 500 kHz 501 kHz



499 kHz 500 kHz 501 kHz

LinearScale

10

8.0

6.0

4.0

2.0

0

Motorola, Inc. 1996 Rev 4


59/67

MC1496, B

2 MOTOROLA ANALOG IC DEVICE DATA

MAXIMUM RATINGS (TA = 25C, unless otherwise noted.)

Rating Symbol Value Unit

Applied Voltage

(V6 V8, V10 V1, V12 V8, V12 V10, V8 V4,

V8 V1, V10 V4, V6 V10, V2 V5, V3 V5)

V 30 Vdc

Differential Input Signal V8 V10

V4 V1

+5.0

(5+I5Re)

Vdc

Maximum Bias Current I5 10 mA

Thermal Resistance, JunctiontoAirPlastic Dual InLine Package

RJA 100 C/W

Operating Temperature Range TA 0 to +70 C

Storage Temperature Range Tstg 65 to +150 C

NOTE: ESD data available upon request.

ELECTRICAL CHARACTERISTICS(VCC = 12 Vdc, VEE = 8.0 Vdc, I5 = 1.0 mAdc, RL = 3.9 k, Re = 1.0 k, TA = Tlow to Thigh,all input and output characteristics are singleended, unless otherwise noted.)

Characteristic Fig. Note Symbol Min Typ Max Unit

Carrier Feedthrough

VC = 60 mVrms sine wave and

offset adjusted to zero

VC = 300 mVpp square wave:

offset adjusted to zerooffset not adjusted

fC = 1.0 kHz

fC = 10 MHz

fC = 1.0 kHzfC = 1.0 kHz

5 1 VCFT

40

140

0.0420

0.4200

Vrms

mVrms

Carrier Suppression

fS = 10 kHz, 300 mVrms

fC = 500 kHz, 60 mVrms sine wave

fC = 10 MHz, 60 mVrms sine wave

5 2 VCS

40

65

50

dB

k

Transadmittance Bandwidth (Magnitude) (RL = 50 )

Carrier Input Port, VC = 60 mVrms sine wave

fS = 1.0 kHz, 300 mVrms sine wave

Signal Input Port, VS = 300 mVrms sine wave

|VC| = 0.5 Vdc

8 8 BW3dB

300

80

MHz

Signal Gain (VS = 100 mVrms, f = 1.0 kHz; | VC|= 0.5 Vdc) 10 3 AVS 2.5 3.5 V/V

SingleEnded Input Impedance, Signal Port, f = 5.0 MHz

Parallel Input Resistance

Parallel Input Capacitance

6

ripcip

200

2.0

k

pF

SingleEnded Output Impedance, f = 10 MHz

Parallel Output Resistance

Parallel Output Capacitance

6

ropcoo

40

5.0

k

pF

Input Bias Current 7 A

IbS

+

I1 ) I42

; IbC

+

I8 ) I102

IbSIbC

12

12

30

30

Input Offset Current

IioS = I1I4; IioC = I8I10

7

IioSIioC

0.7

0.7

7.0

7.0

A

Average Temperature Coefficient of Input Offset Current

(TA = 55C to +125C)7 TCIio 2.0 nA/ C

Output Offset Current (I6I9) 7 Ioo

14 80 A

Average Temperature Coefficient of Output Offset Current

(TA = 55C to +125C)7 TCIoo 90 nA/ C

CommonMode Input Swing, Signal Port, fS = 1.0 kHz 9 4 CMV 5.0 Vpp

CommonMode Gain, Signal Port, fS = 1.0 kHz, |VC|= 0.5 Vdc 9 ACM 85 dB

CommonMode Quiescent Output Voltage (Pin 6 or Pin 9) 10 Vout 8.0 Vpp

Differential Output Voltage Swing Capability 10 Vout 8.0 Vpp

Power Supply Current I6 +I12

Power Supply Current I14

7 6 ICCIEE

2.0

3.0

4.0

5.0

mAdc

DC Power Dissipation 7 5 PD 33 mW


60/67

MC1496, B


GENERAL OPERATING INFORMATION

Carrier Feedthrough

Carrier feedthrough is defined as the output voltage at

carrier frequency with only the carrier applied (signal

voltage = 0).

Carrier null is achieved by balancing the currents in the

differential amplifier by means of a bias trim potentiometer

(R1 of Figure 5).

Carrier SuppressionCarrier suppression is defined as the ratio of each

sideband output to carrier output for the carrier and signal

voltage levels specified.

Carrier suppression is very dependent on carrier input

level, as shown in Figure 22. A low value of the carrier does

not fully switch the upper switching devices, and results in

lower signal gain, hence lower carrier suppression. A higher

than optimum carrier level results in unnecessary device and

circuit carrier feedthrough, which again degenerates the

suppression figure. The MC1496 has been characterized

with a 60 mVrms sinewave carrier input signal. This level

provides optimum carrier suppression at carrier frequencies

in the vicinity of 500 kHz, and is generally recommended for

balanced modulator applications.Carrier feedthrough is independent of signal level, VS.

Thus carrier suppression can be maximized by operating

with large signal levels. However, a linear operating mode

must be maintained in the signalinput transistor pair or

harmonics of the modulating signal will be generated and

appear in the device output as spurious sidebands of the

suppressed carrier. This requirement places an upper limit on

inputsignal amplitude (see Figure 20). Note also that an

optimum carrier level is recommended in Figure 22 for good

carrier suppression and minimum spurious sideband

generation.

At higher frequencies circuit layout is very important in

order to minimize carrier feedthrough. Shielding may be

necessary in order to prevent capacitive coupling betweenthe carrier input leads and the output leads.

Signal Gain and Maximum Input Level

Signal gain (singleended) at low frequencies is defined

as the voltage gain,

AVS

+

VoV

S+

RL

Re) 2rewhere re +

26 mVI5(mA)

A constant dc potential is applied to the carrier input terminals

to fully switch two of the upper transistors on and two

transistors off (VC = 0.5 Vdc). This in effect forms a cascode

differential amplifier.

Linear operation requires that the signal input be below a

critical value determined by RE and the bias current I5.

VS p I5 RE (Volts peak)

Note that in the test circuit of Figure 10, VS corresponds to a

maximum value of 1.0 V peak.

Common Mode Swing

The commonmode swing is the voltage which may be

applied to both bases of the signal differential amplifier,

without saturating the current sources or without saturating

the differential amplifier itself by swinging it into the upper

switching devices. This swing is variable depending on the

particular circuit and biasing conditions chosen.

Power Dissipation

Power dissipation, PD, within the integrated circuit package

should be calculated as the summation of the voltagecurrent

products at each port, i.e. assuming V12 = V6, I5 = I6 = I12

and ignoring base current, PD = 2 I5 (V6 V14) + I5)

V5 V14 where subscripts refer to pin numbers.

Design Equations

The following is a partial list of design equations needed to

operate the circuit with other supply voltages and input

conditions.

A. Operating Current

The internal bias currents are set by the conditions at Pin 5.

Assume:

I5 = I6 = I12,

IB t t IC for all transistors

then :

R5+

V*

* f

I5*

500W

where: R5 is the resistor between

where: Pin 5 and ground

where: = 0.75 at TA = +25CThe MC1496 has been characterized for the condition

I5 = 1.0 mA and is the generally recommended value.

B. CommonMode Quiescent Output Voltage

V6 = V12 = V+ I5 RL

Biasing

The MC1496 requires three dc bias voltage levels which

must be set externally. Guidelines for setting up these three

levels include maintaining at least 2.0 V collectorbase bias

on all transistors while not exceeding the voltages given in

the absolute maximum rating table;

30 Vdcw

[(V6, V12) (V8, V10)]w

2 Vdc

30 Vdcw

[(V8, V10) (V1, V4)]w

2.7 Vdc30 Vdcw

[(V1, V4) (V5)]w

2.7 Vdc

The foregoing conditions are based on the following

approximations:

V6 = V12, V8 = V10, V1 = V4

Bias currents flowing into Pins 1, 4, 8 and 10 are transistor

base currents and can normally be neglected if external bias

dividers are designed to carry 1.0 mA or more.

Transadmittance Bandwidth

Carrier transadmittance bandwidth is the 3.0 dB bandwidth

of the device forward transadmittance as defined by:

g 21C +io (each sideband)

vs

(signal) Vo + 0Signal transadmittance bandwidth is the 3.0 dB bandwidth

of the device forward transadmittance as defined by:

g 21S +io (signal)

vs (signal) Vc + 0.5 Vdc, Vo + 0


61/67

MC1496, B


Coupling and Bypass Capacitors

Capacitors C1 and C2 (Figure 5) should be selected for a

reactance of less than 5.0 at the carrier frequency.

Output Signal

The output signal is taken from Pins 6 and 12 either

balanced or singleended. Figure 11 shows the output levels

of each of the two output sidebands resulting from variations

in both the carrier and modulating signal inputs with a

singleended output connection.

Negative Supply

VEE should be dc only. The insertion of an RF choke in

series with VEE can enhance the stability of the internal

current sources.

Signal Port Stability

Under certain values of driving source impedance,

oscillation may occur. In this event, an RC suppression

network should be connected directly to each input using

short leads. This will reduce the Q of the sourcetuned

circuits that cause the oscillation.

Signal Input(Pins 1 and 4)

510

10 pF

An alternate method for lowfrequency applications is to

insert a 1.0 k resistor in series with the input (Pins 1, 4). In

this case input current drift may cause serious degradation of

carrier suppression.

TEST CIRCUITS

NOTE: Shielding of input and output leads may be neededto properly perform these tests.

Figure 5. Carrier Rejection and Suppression Figure 6. InputOutput Impedance

Figure 7. Bias and Offset Currents Figure 8. Transconductance Bandwidth

0.01F2.0 k

8.0 Vdc

I6

I9

1.0 k

I7I8

6.8 k

Zout+ Vo

+

+VoI9

3

RL3.9 k

VCC12 Vdc

8

C10.1 F

MC1496

1.0 k2

Re

1.0 k

C20.1 F

51

10 k

ModulatingSignal Input

CarrierInput

VC

Carrier Null

515110 k

50 k

R1

VS Vo

RL3.9 k

I6

I4

6

14 5

12

2

Re = 1.0 k

3

Zin

0.5 V 810

I1

41

Vo10

1 6

4

14 5

12

6.8 k

VI10

I5

8.0 VdcVEE

1.0 k

MC1496

MC1496MC1496 6

14 5

12

I10

6.8 k

8.0 VdcVEE

VCC12 Vdc

2

Re = 1.0 k

3

1.0 k

ModulatingSignal Input

CarrierInput

VCVS

0.1 F

0.1 F

1.0 k

51

1.0 k

14 5

6

12

1.0 k2 3

Re

VCC12 Vdc

2.0 k

+ Vo

Vo

6.8 k

10 k

Carrier Null

5110 k

50 k

V

8.0 VdcVEE

50 50810

41

810

41

51


62/67


63/67

MC1496, B


30

f, FREQUENCY (MHz)

20

10

0

10

20

0.1 1.0 10 1000.01

RL = 3.9 kRe = 500

RL = 3.9 kRe = 2.0 k

|VC| = 0.5 VdcRL = 500 Re = 1.0 k

RL = 3.9 k (StandardRe = 1.0 k Test Circuit)

A

,SINGLE-ENDEDVOLTAGEGAIN(dB)

VS

1001.0

Side Band

0.3

0.4

01000

fC, CARRIER FREQUENCY (MHz)

0.6

0.9

1.0

10

0.8

0.7

0.1

0.2

0.5

0.1

21,TRANSADMITTANCE

(mmho)

800

fC 3fS

800600400200

VS, INPUT SIGNAL AMPLITUDE (mVrms)

fC 2fS

0

60

5040

30

20

10

70

SUPPRESSIONBELOW

EACHFUNDAMENTAL

CARRIERSIDEBAND(dB)

fC

2fC

505.00.05 0.1 0.5 1.0 10

3fC

0

60

50

40

30

20

10

70


SUP

PRESSIONBELOWE

ACHFUNDAMENTAL

CARRIERSIDEBAND(dB)

TA, AMBIENT TEMPERATURE(C)

MC1496

(70C)

75 50

60

755025025

50

40

30

20

10

100 125 150 17570

CS

V

,CARRIERSUPPRESIO

N(dB)

AV +

RL

R

e

) 2r

e

TYPICAL CHARACTERISTICS (continued)

Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave),

VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25C, unless otherwise noted.

0.1

5010

10

1.0

0.011.0 5.00.05 0.1 0.5


V

,CARRIEROU

TPUTVOLTAGE(mVrms)

CFT

Signal Port

0

Figure 15. Sideband and Signal Port

Transadmittances versus Frequency

Figure 16. Carrier Suppression

versus Temperature

Figure 17. SignalPort Frequency ResponseFigure 18. Carrier Suppression

versus Frequency

Figure 19. Carrier Feedthrough

versus Frequency

Figure 20. Sideband Harmonic Suppression

versus Input Signal Level

g 21 +

IoutV

in Vout + 0 |VC| + 0.5 Vdc

g 21 +Iout (Each Sideband)

Vin

(Signal) Vout + 0Sideband Transadmittance

Signal Port Transadmittance


64/67

MC1496, B


500100 4003000 200VC, CARRIER INPUT LEVEL (mVrms)

fC = 10 MHz

0

60

50

40

30

20

10

70

CS

V

,CARRIERSUPPRESSION(dB)

2fC fS

2fC 2fS

3fC fS

fC, CARRIER FREQUENCY (MHz)50101.0 5.00.05 0.1 0.5

0

60

50

40

30

20

10

70SUPPRESSIONBELO

WE

ACHFUNDAMENTAL

CARRIERS

IDEBAND(dB)

Figure 21. Suppression of Carrier Harmonic

Sidebands versus Carrier Frequency

Figure 22. Carrier Suppression versus

Carrier Input Level

fC = 500 kHz

OPERATIONS INFORMATION

The MC1496, a monolithic balanced modulator circuit, is

shown in Figure 23.

This circuit consists of an upper quad differential amplifier

driven by a standard differential amplifier with dual currentsources. The output collectors are crosscoupled so that

fullwave balanced multiplication of the two input voltages

occurs. That is, the output signal is a constant times the

product of the two input signals.

Mathematical analysis of linear ac signal multiplication

indicates that the output spectrum will

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