application of soi to belle ii upgrade - indico · 2019-08-07 · • 0.2um fdsoi process by lapis...
TRANSCRIPT
Application of SOI to Belle II upgrade~The “DuTiP” Concept~
Yasuo Arai, Junji Haba, Akimasa Ishikawa, Ikuo Kurachi,
Taohan LiA, Shun Ono, Takehiro Takayanagi, Ayaki TakedaB,
Toru Tsuboyama, Miho YamadaC
KEK, TohokuA, MiyazakiB, TMCITC
20190708 [email protected]
Readout Method
• We would use the pixel detector with trigger signal based fast global shutter readout for Belle II upgrade. – Lower occupancy → better tracking and vertexing, smaller number of
readout cables
– Smaller data size → lower bandwidth, lower cost for storage
• We invented the “DuTiP” concept for this purpose.
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(Our) Requirements for 1st layer
• Work under at least 5 times larger luminosity
• geometry– 1.4cm radius
– Coverage of 17-150 degree in polar angle
– sensor thickness less than or equal to 75umt
• performance– Position resolution of ~10um in both r-f and z direction
– Occupancy enough smaller than O(10-3)
• Readout speed, rate and trigger latency– High data transfer rate (to be discussed)
– Trigger rate much more than 30kHz, less than 150kHz??
– Trigger latency more than 6us
• Radiation hardness– 0.5MGy
– 2.5x1014 neq/cm2
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The Concept “DuTiP”• Analog Circuit
– In Pixel Amplifier/Shaper/Discriminator.
– Binary signal sent to digital circuit in the pixel.
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One Pixel
The Concept “DuTiP”• Dual Timer Pixel
– Dual Timer (down time counters) in a Pixel to store signal and wait for trigger signal• When hit signal is sent to digital circuit, one of the timers start counting down.
– The starting time is set as trigger latency – 1 CLOCK.
• If the trigger signal is received when the timer is 1(2/0), the signal is readout as Current(Next/Previous) timing.
– If trigger signal is not received → reset the timer.
• Trigger latency is at most 2n x clock period (n is a number of flipflops in timer).
• To take into account for multi hits during trigger latency, sequencer and two timers are equipped.
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One Pixel
DuTiP with SOI technology
• 0.2um FDSOI process by Lapis semiconductor– talked by Arai-san yesterday.
• Pixel size– 35um x 35um → 35um/√12 ~ 10um resolution
• ASD– We can modify/optimize already developed ASD for
other SOI detectors, such as CNTPIX (shaper can be removed?), or fast and low power analog circuit fabricated for SOI by Strasbourg and KEK.
• Timer and digital circuit– 7bit x 2 (DFF circuit area reduction by active merge)
– 15.9MHz(62.9ns) CLK (SKB 509MHz(1.97ns) /25(*25) )• Trigger latency of at most 8us.
– According to Iwasaki-san, this latency is enough for CDC trigger.
• Trade-off between (CLK freq/occupancy) and (circuit area/power consumption).
– 7.95MHz with 6bit or 3.98MHz with 5bit should be also considered.
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CNTPIX : 1MIP@50umt
Input
Preamp input
Preamp output
Shaper output
Discri output
250ns
CNTPIX : 1MIP@50umt
Arai-san yesterday
Digital Circuit for PIXOR
• We developed the “PIXOR” detector, which is a kind of striplet detector using SOI pixel detector by taking analog OR, to replace SVD layer3.– "Development of the Pixel OR SOI detector for high energy physics
experiments", Y. Ono, A. Ishikawa, H. Yamamoto, Y. Arai, T. Tsuboyama, Y. Onuki, A. Iwata, T. Imamura, T. Ohmoto, NIM A 731, 266-269, 2013, doi:10.1016/j.nima.2013.06.044
– n by n pixel array can be read out as 2n channel
– The digital circuit is almost the same as DuTiP.
• But unfortunately, taking analog OR was hard for large size and large n (>8).– This is the reason we terminated the development.
• But fortunately, the digital circuit was completely working with 50MHz clock as expected!! – This is the reason we started to develop DuTiP.
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PIXOR2 digital flow
Schematic view of PIXOR4 by 4 case→8readout channels
Sensor for layer1• Layer1 : R=1.4cm, Z=7cm
• maximum mask size for SOI is 2.46 x 3.08 cm2
• We need three stitching shots to cover the acceptance in Z with single chip.
– Row : 35um x 384ch = 13.44mm
– Column : 35um x 2304ch = 80.6mm• 768ch x 3 (26.8mm x 3)
– Thickness : 50~75umt
– Stitching buffer width: ~10um
• 8 ladders to cover the acceptance in phi
384ch x 768ch
13.44mm
80.4 + a mm
Readout peripheralA few mm?
26.8mm
Pixel Array384ch x 768ch
384ch x 768ch
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26.8mm
Stithcing for SOPHIAS (X-ray sensor)26.7mm x 64 mm single chip
Occupancy at Upgarded SuperKEKB
• Assuming common initial requirements– 113MHz/cm2 for layer1
• Occupancies– Hit occupancy is for tracking
• Hit in 3frames ; Previous, Current and Next
– 2Timer occupancy is computed when both timers are occupied.• Even 1 Timer is occupied, the detector can work.
• Even under 5x larger luminosity, the occupancy is enough small.– We could use two times slower clock
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Time window Occupancy
Hit 3*62.9ns 0.026%
2Timer 4.4us (trg latency) 0.0037%
8us (trg latency) 0.012%
https://indico.cern.ch/event/810687/attachments/1827433/3072784/BELLE2-NOTE-TE-2019-011.pdf
Data Transfer Rate and Size• Assuming 150kHz trigger rate at Upgraded Belle II
• Only row address (9bit) and PCN timing (2bit) are transferred from the chip– Column selector should know the column address information.
• Data transfer Rate
• Need fast data transfer technology fabricated on SOI– LVDS
384ch x 768ch
384ch x 768ch
384ch x 768ch
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Data transfer rate Data size in 107s
Block (384ch x 768ch) 15.8MB/s
Chip (3Blocks) 47.4MB/s
Layer1 (8Chips) 379MB/s 3.79PB
Item should be studied
• Short term– Completion of the design for 1st prototype chip (JFY2019)
• We can use and modify the circuits already developed for other SOI pixel detectors
– Delivery and test of 1st prototype chip (JFY2020)
• Long term– Injection veto for analog circuit
– Sparse scan capability for hit readout• Readout speed dependent on trigger rate requirement
– Fast data transfer circuit• LVDS or other fast technology
• Study of better doping for fast circuit
– Radiation tolerance• 0.5MGy/2.5x1014 neq
• PDD structure
• Thinner BOX layer (tunneling effect reduce the trapped ions)
– Large real size sensor development• Fine tuning of the circuit parameters needed.
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Last but not least
• “DuTiP” is just a concept and does not specify any technologies.
• We would realize the “DuTiP” concept with SOI for Belle II but if other technology has enough fast circuit as SOI, this concept can be used.
• Not only for Belle II but “DuTiP” can be also used for layer7-8 of ILD@ILC pixel detector (time stamping pixel layers) .
– which require 500ns time resolution and moderate r-f position resolution of ~10um.
– Stitching is needed for larger coverage
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Summary
• The “DuTiP” concept invented.– Dual Timer Pixel.
• The SOI pixel detector with “DuTiP” concept shown.
– 35um pixel size → 10um position resolution
– 63ns clock period
– Occupancy is enough small• Hit occupancy of 0.026%
• 2Timer occupancy of 0.012%
• We are now developing the first prototype and hopefully have it in JFY2020.– We can use and modify the circuits already developed for other SOI pixel detectors
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Requirements Achieved for 1st layer
• Work under at least 5 times larger luminosity
• geometry✓ 1.4cm radiusk
✓ Coverage of 17-150 degree in polar angle
✓ Sensor thickness less than or equal to 75umt : thinning to 50umt done by TAIKO
• performance× Position resolution of ~10um in both r-f and z direction : need beam test with the prototype
✓ Occupancy enough smaller than O(10-3)
• Readout speed, rate, latency× High data transfer rate : need to fabricate LVDS driver on SOI chip
? Trigger rate much more than 30kHz, less than 150kHz?? : need guideline
✓ Trigger latency more than 6us
• Radiation hardness△ 0.5MGy : 0.1MGy tested for double SOI. 2MGy for single transistor. PDD to be studied.
× 2.5x1014 neq/cm2 : need test but basically the hardness is the same as bulk CMOS
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✓ done△middle of the way× not yet done? Requirement?
Large sensor by stitching done for SOPHIAS