area and power efficient up-down counter design by using full adder module

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

11 NITTTR, Chandigarh EDIT-2015

Area and Power Efficient Up-Down counterDesign by Using Full Adder Module

1Anjali Sharma, 2Richa Singh1PHD Scholar Chitkara University, Punjab, India,

2Assistant Professor Department of Electronics and communication Engineering, VSGOI Unnao,U.P. [email protected], [email protected]

Abstract- In this paper an area and power efficient 98T Up-Down counter design has been presented by using Passtransistor logic designing technique. The proposed Up-Downcounter design consist of 53 NMOS and 45 PMOS. Four PTLfull adder modules has been used to design this Up-Downcounter which consumes less area and power at 120 nm ascompared to CMOS, TG and GDI full adder designs. Theproposed Up-Down counter design is based on this area andpower efficient 10 transistors PTL full adder module. Theproposed Up-Down counter has been designed and simulatedusing DSCH 3.1 and Microwind 3.1 on 120nm. For proposeddesign Power variation with respect to the supply voltage hasbeen performed on BSIM-4 and LEVEL-3 using 120nmtechnology. Results show that Area of proposed PTL Up-Down counter design is 1288.4 µm2 on 120nm technology. At1.2V input supply voltage the proposed Up-Down counterdesign consumes 111µW power at BSIM-4.

Keywords- BSIM, CMOS, Gate Diffusion Input, NMOS,PMOS, PTL, Transmission Gate, VLSI.

I. INTRODUCTIONIn present technology world use of portable devices has

been increased and measurement of power and areaconsumption is major concern in schematic design of theseportable devices before their actual implementation in thelayout. Large power and area consumption is a keylimitation in many electronic devices and these parametersalso act as show stopper for VLSI applications. So there isneed of new VLSI designing techniques andmethodologies to control and limit power and areaconsumption [1]-[2]. In digital processing, there isrequirement of area and power efficient counter design.The critical path in VLSI circuit design is increased no oftransistors that produce the delay in the output signal [3]. Itis also the speed limiting and more power consumingelement of many VLSI applications. The design of faster,smaller and more efficient counter architecture should bethere for VLSI applications. Two most importantproperties of the counter architectures are powerconsumption and propagation which basically are againsteach other. Decrease in the power consumption can causedelay in the circuit and vice versa, hence, mostarchitectures referring to one of those important properties.

Traditional CMOS technology, results in full voltageswing but consume large area. Transmission gatetechnology consumes less area as compare to CMOStechnology because it consumes less no of transistors. Oneanother logic that consumes less power is PTL - pass-transistor logic. Advantages of PTL over standard CMOSlogic design are: High speed - due to the small nodecapacitances, Low power dissipation - as a result of thereduced number of transistors, Lower interconnectioneffects - due to a small area [5]. But implementations of

circuit by PTL logic have two basic problems [6] i.e.threshold drop across the single-channel pass transistorsand static power dissipation. Logic design which canovercome this problem is Complementary pass-transistorlogic (CPL) which features complementary inputs/outputsusing NMOS pass-transistor logic.

II. 4- BIT UP-DOWN COUNTER

In digital processing and computing applications,a counter is a device which stores and displays that withany clock input how many times aparticular event or process has been occurred. A mostcommon type of counter is a sequential digital logic circuitwith a clock input line and multiple output lines. Thevalues on the output lines represent a number inthe binary or BCD number system. Each pulse applied tothe clock input increments or decrements the number in thecounter. A counter circuit can be constructed by numberof flip-flops connected in cascade. Counters is most widelyused digital component in digital circuits which are furtherused in the various digital processing applications, and aremanufactured as separate integrated circuits and alsoincorporated as parts of larger integrated circuits. Up-Down counter design by using full adder module has beenshown in Fig.1.

Fig.1 Up-Down Counter by using Full adder modules

III. SCHEMATICS DESIGNS OF 1-BIT FULLADDER

Full adder is one of the basic building blocks ofarithmetic unit used in various digital electronic devices.Full adder can be designed by using different logics. Areaconsumption, speed and power consumption are the mainparameter estimation criteria’s and should be investigatedand analyzed for the efficient performance of the digitalcircuits [7].


NITTTR, Chandigarh EDIT -2015 12

Fig.2 CMOS Full Adder Design [7]

In Fig. 2 a full adder design has been shown by usingCMOS logic which consist 36T transistors and a TG Fulladder design by using 22 transistors has been shown in Fig3 [7]. As CMOS and TG based full adder designs consumeless power but it consists large transistors and henceconsume very large area.

Fig.3 TG Full Adder Design [15]

If a logic style shows good performance in terms of oneestimation criteria it can give degraded performance inother. The majority of the power dissipated in CMOSVLSI circuits is by dynamic power dissipation which is thepower dissipated during charging or discharging of theload capacitance of a given circuit. A full adder design byusing PTL logic has been shown in Fig 4. This design hasbeen implemented by using 10 transistors. This designconsists less transistors as compared to CMOS and TG fulladder designs so this design consumes less area ascompared to CMOS and TG design but disadvantage of

this circuit is that it can’t give full voltage swing at theoutput.

Fig.4 PTL Full Adder Design

In [7] also a new and area efficient full adder design hasbeen achieved by using GDI technique shown in Fig.5.Adder circuit by using GDI technique uses 10 transistors togenerate adder output. In this circuit simultaneouslygeneration of XOR and XNOR output has beenimplemented which further acts as a input for the SUM andCARRY Module. Sum and Carry output has been obtainedby using 2x1 MUX.

Fig.5 GDI Full Adder Design

IV.PROPOSED UP-DOWN COUNTERSCHEMATICS

In proposed Up-Down counter design four Full addermodules has been used as a basic building block shown inFig. 6. MICROWIND and DSCH 3.1 designing tool hasbeen used for the designing of this circuit. MICROWIND3.1 VLSI designing tool deals with both front end and backend designing of digital circuits. DSCH work in front endwhich has ability to design the circuit by using transistorsas well as gates. DSCH designing can generate VERILOGfile which can be compiled by the MICROWIND back enddesigning tool to observe parameters such as power andarea consumption.


13 NITTTR, Chandigarh EDIT-2015

Fig.6 Design of Proposed Up-Down Counter

Proposed PTL Up-Down counter is best in terms of areaas compared to CMOS, TG and GDI Up-Down counterdesign. Comparative analysis of various Up-Down counterdesigns on 120nm has been shown in Table.1. Up-Downcounter by conventional CMOS consist 202 transistors, TGUp-Down counter consists 146 transistors and GDI andPTL Up-Down counter consists 98 transistors.

V. LAYOUT ANALYSISFor a very complex circuit it is not possible to conduct themanual layout so an automatic layout generation approachis preferred. Required schematic diagram has been firstlydesigned and logically validated using DSCH tool at logiclevel. Although at logic level DSCH have feature toanalyze timing simulation as well as power consumptionbut accurate layout information is still missing. AVERILOG file is generated by the DSCH 3.1 designingtool which is understandable by the MICROWIND 3.1designing tool to construct the corresponding layout withexact desired design rules. Another way to create thedesign is by NMOS and PMOS devices using cellgenerator provided by the MICROWIND. The advantageof this approach is to avoid any design rule error. W/L canbe adjusted by the MOS generator option onMICROWIND tool [8]. Layout of Up-Down Counter hasbeen shown in Fig. 7.

Fig.7 Layout of Up-Down Counter

3D view of proposed Up-Down counters design has beenshown in Fig.8. Various steps used for the creation of thisstructure are- initial substrate creation, N- diffusion, SiO2

isolation, thin oxide growth, thin oxide reduction,polysilicon deposit, N+ implant, P+ implant, 2nd

polysilicon deposit, contact creation, metal layersdeposition and via hole creation, passivation oxidedeposition and passivation etching. This layout consist 6metal layers and 2 polysilicon layers.

Fig.8 3D view of proposed Up-Down counters design

VI. SIMULATION RESULTSArea and power consumption of proposed Up-Downcounters has been evaluated on 120nm technology byusing MICROWIND designing tool. Simulation ofproposed Up-Down counters has been performed to getpower and current variation with respect to the supplyvoltage. Parametric analyses of proposed Up-Downcounters have been performed using the MOS Emphericalmodel Level-3 and BSIM Model-4 at different power fivedifferent supply voltages.

Up-DownCounterdesign

CMOS

TG GDI Proposed PTL

NMOS 105 77 53 53

PMOS 97 69 45 45

Width(µm)

213.2 178.7

109.6

109.6

Height(µm)

13.7 11.3 12.2 11.8

Area (µm2

)2917.1

2015.5

134.1

1288.4


NITTTR, Chandigarh EDIT -2015 14

Fig.9 Power vs. Supply Voltage on BSIM-4

Threshold voltage has been taken as 0.4V for both levelswhich is the voltage above which the power and currentstarts increasing with the increase in supply voltage.Operating temperature has been taken 270C for bothLEVEL-3 and BSIM-4.MOS Empherical model Level-3and BSIM Model-4 provides the feature of different curvefitting parameters which is useful in parametric analysis.

Fig.10 Power vs. Supply Voltage on LEVEL-3

MOS Empherical model Level-3 has features of 10different curve fitting parameters whereas BSIM Model-4works with 19 different parameters. Graph for variation inpower with respect to Vdd has been shown in Fig.9 forBSIM-4 and in and Fig. 10 for LEVEL-3.

VII. CONCLUSIONAn alternative Up-Down counters design by using PTLapproach has been proposed which consists 98 transistors.Proposed Up-Down counters have been implemented byusing 58 NMOS and 45 PMOS transistors. Proposed Up-Down counters have been designed using an area efficientPTL Full adder module which has been implemented byusing only 10 transistors. Area and power consumption ofproposed Up-Down counters has been shown on120nmusing LEVEL-3 and BSIM-4 analytical models. Area ofproposed Up-Down counters design is 1288.4µm2 on120nm technology. At 1.2V input supply voltage theproposed Up-Down counters consumes 62.197µW powerat BSIM-4 and 32.824 µW power at LEVEL-3. Theproposed Up-Down counters circuit can work efficientlywith minimum voltage supply of 0.4V and can work onwide range of frequency range between 2MHz to 400MHz.

REFERENCESN. Weste and K. Eshraghian, (2002) “Principles of CMOSVLSI Design”A System Perspective Reading, Pearson Education, Addison–Wesley.Anjali Sharma, Richa Singh, Pankaj Kajla “Area Efficient 1-BitComparator Design by using Hybridized Full Adder Module based onPTL and GDI Logic,” International Journal of Computer Applications,Vol.82, No. 10, pp. 5-13.Chiou-Kou Tung; Yu-Cherng Hung; Shao-Hui Shieh; Guo-Shing Huang,”A Low -Power High-speed Hybrid CMOS Full Adder For EmbeddedSystem,” IEEE transactions on Design and Diagnostics of ElectronicCircuits and Systems, vol.13, No.6, pp.-1 – 4, 2007.Anjali Sharma, Richa Singh, Pankaj Kajla “Area Efficient 1-Bit

Comparator Design by using Hybridized Full Adder Module based onPTL and GDI Logic,” International Journal of Computer Applications,Vol.82, No. 10, pp. 5-13.A Morgenshtein, Fish, Wagner, “Gate - Diffusion input (GDI) - A novelpower efficient method for digital circuits: A Design Methodology ,”IEEE International Conference, pp. 39 – 43, 2001.

Morgenshtein, A.; Fish, A.; Wagner, I.A., “Gate-diffusion input (GDI): APower Efficient Method For Digital Combinational circuits,” IEEETransaction on Very Large Scale Integration Systems, Vol. 10 , No . 5,pp. 566 - 581, 2002.Anjali Sharma, Rajesh Mehra, “Area and Power Efficient CMOS AdderDesign by Hybridizing PTL and GDI Technique,” International Journalof Computer Applications, Vol.66, No. 4, pp. 15-22.Etienne Sicard, Sonia Delmas Bendhia, Basic of CMOS Cell Design, tatamc graw-hill, pp. 51-90, 2007.

area and power efficient up-down counter design by using full adder module

Documents