By: V.JAGATHI M.TECH VLSI DESIGN II YEAR II SEMESTER REG NO:1581320001 SRM UNIVERSITY

GUIDED BY MR. E.POOVANNAN

We present an efficient architecture for the implementation of a delayed least mean square adaptive filter. For achieving lower adaptation-delay and area-delay-power efficient implementation, we use a partial product generator and propose a strategy for optimized balanced pipelining across the time-consuming combinational blocks of the structure. From synthesis results, we find that the proposed design offers nearly 17% less area-delay product (ADP) and nearly 14% less energy-delay product (EDP) than the best of the existing systolic structures, on average, for filter lengths N = 8, 16, and 32. We propose an efficient fixed-point implementation scheme of the proposed architecture, and derive the expression for steady-state error. We show that the steady-state mean squared error obtained from the analytical result matches with the simulation result. Moreover, we have proposed a bit-level pruning of the proposed architecture, which provides nearly 20% saving in ADP and 9% saving in EDP over the proposed structure before pruning without noticeable degradation of steady-state-error performance.

For achieving lower adaptation delay and area delay power we need to propose an architecture of the main DLMS structure.

We have proposed two main computing blocks: 1. Error computation block 2. Weight update block

We proposed fixed point implementation and bit level pruning for the proposed architecture.

We implement an architecture with partial product generators, in which we are using L/2 number of 2-to-3 decoders and AND/OR cells and also the structure of adder tree for pipelining the structure of Error computation block. In Weight update block, each MAC units perform multiplication of shifted values of error with delayed input samples and N multiplications performed by N partial product generators (PPGs) of L/2, so that outputs of MACs update the weights which are to be used as the inputs for error computation block.

Proposed structure of PPG and AOC cells

By using this implementation for proposed architecture, we can derive the expression for steady state error and steady state mean squared error is obtained by analytical result which is of same as simulation result.

By the implementation for proposed architecture adder tree optimization technique is used for the computation of the filter length N=4, and the word lengths as L,W=8. And after final truncation there will be one bit difference in output due to pruning. So that it provides nearly 20% less saving in area delay product (ADP) and 9% in energy delay product (EDP) over the proposed structure before pruning.

We implement the coding for the proposed designs in VHDL and synthesized by the Synopsys Design Complier using CMOS 65-nm library for different filter orders.

We implement the coding for the proposed structures by using VHDL and synthesized by the Synopsys Design Complier Using 65-nm library for a better comparison.

The proposed designs are implemented on FPGAs of Xilinx devices.

The NOS and the MUF are being used for different devices of Spartan-3A and Virtex-4.