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VLSI Design, Vol. 7, No. 1 (1998) 111-129

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Page 1: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

Page 2: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

Page 3: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

Page 4: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

Z0

Zterm

Rpd

Rpu

Vsignal

Z0

Zterm

Vsignal

puW

Lpu

pd

W

L

pd

pu

pd

Ground

Vsignal

1W

2W

4W

8W

WD

WD

8W

4W

2W

1W

pu

pu impedance

pd impedance

pd

To Output Pad andTransmission Line

Page 5: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

0 T 2T Time

Vol

tage

see

n by

sou

rce

Vsignal

Vsignal

2

0 T 2T Time

Vol

tage

see

n by

sou

rce

Vsignal

Vsignal

2

0 T 2T Time

Vol

tage

see

n by

sou

rce

Vsignal

Vsignal

2

WN1

WP1

WN2

WP2

WN3

WP3

Vlogic

StandardLevelInput

21 Vsignal Ref. Input

Pad

diffusedinput

resistors

I1 I2 I3

Page 6: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

fixeddelay

LatchG

D Q

fixeddelay

LatchG

D Q

fixeddelay

LatchG

D Q

fixeddelay

LatchG

D Q

enablepulse

inputtarget

<sample register output value>

Page 7: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

LatchG

D Q

LatchG

D Q

LatchG

D Q

LatchG

D Q

enablepulse

inputtarget

<sample register output value>

LatchG

D Q

LatchG

D Q

LatchG

D Q

LatchG

D Q

LatchG

D Q

Counterclr

incr

count

ComparatorA

B

=

enable

config

inputtarget

<sample register output value>

Page 8: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

Page 9: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

finedelay

LatchG

D Q

Counterclr

incr

count

ComparatorA

B

=

enable

config

inputtarget

<sample register output value>

LatchG

D Q

LatchG

D Q

LatchG

D Q

LatchG

D Q

enablepulse

select

input

clk

<sample register output value>

Page 10: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

LatchG

D Q

LatchG

D Q

LatchG

D Q

LatchG

D Q

LatchG

D Q

Counterclr

incr

count

ComparatorA

B

=

FineDelay

in out

config

enable

fine config

config

select

inputclk

<sample register output value>

input

vctrl

gnd

output

Page 11: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

Mux

Imp

edan

ce R

egis

ter

Sam

ple

Reg

iste

r

output

enable

input

To/

Fro

m C

hip

Inte

rior T

o/From

Pad I/O

Circuitry

Bo

un

dar

y

Cel

l

0 4 8 12 16

0x3F

0x37

0x2F

0x27

0x1F

0x17

0x0F

0x07

0x00

Sample Bit (Time)

Impe

danc

e Se

tting

Page 12: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

-0.50

-0.25

0.00

0.25

0.50

0.75

1.00

1.25

1.50

2.00 ns per division

Vol

ts

-0.50

-0.25

0.00

0.25

0.50

0.75

1.00

1.25

1.50

2.00 ns per division

Vol

ts

Page 13: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

-1.00

-0.75

-0.50

-0.25

0.00

0.25

0.50

0.75

1.00

0.50 ns per division

Ref

lect

ivity

0 4 8 12 16

0x3F

0x37

0x2F

0x27

0x1F

0x17

0x0F

0x07

0x00

Sample Bit

Impe

danc

e Se

tting

output

delayselect

input

Page 14: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

Page 15: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

To/

Fro

m C

hip

Inte

rior

To/F

rom P

ad I/O C

ircuitry

Mux

Imp

edan

ce R

egis

ter

Sam

ple

Reg

iste

r

Bo

un

dar

y R

egis

ter

output

enable

input

Del

ay R

egis

ter

Delay

Delay

Page 16: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

BoundaryRegisters Sample Register

Receiver andPredriver

Imp

edan

ce

Fin

al D

rive

r

BondingPad E

SD

930 um

150

um

140 um 350 um 140 um 40 60 140 um 60

Page 17: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

Page 18: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

Page 19: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

Page 20: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129

Page 21: VLSI Design, Vol. 7, No. 1 (1998) 111-129andre/pdf/trsignal_vlsidesign98.pdfVLSI Design, Vol. 7, No. 1 (1998) 111-129 fixed delay Latch G D Q fixed delay Latch G D Q fixed delay Latch

VLSI Design, Vol. 7, No. 1 (1998) 111-129


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