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  • ARM Cortex-A57 MPCore ProcessorRevision: r1p0

    Technical Reference Manual

    Copyright 2013 ARM. All rights reserved.ARM DDI 0488C (ID121213)

  • ARM Cortex-A57 MPCore ProcessorTechnical Reference Manual

    Copyright 2013 ARM. All rights reserved.

    Release Information

    The following changes have been made to this book.

    Proprietary Notice

    Words and logos marked with or are registered trademarks or trademarks of ARM in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

    Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

    The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

    This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

    Where the term ARM is used it means ARM or any of its subsidiaries as appropriate.

    Confidentiality Status

    This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

    Product Status

    The information in this document is final, that is for a developed product.

    Web Address

    http://www.arm.com

    Change history

    Date Issue Confidentiality Change

    04 June 2013 A Confidential First release for r0p0

    04 October 2013 B Confidential First release for r0p1

    09 December 2013 C Non-Confidential First release for r1p0

    ARM DDI 0488C Copyright 2013 ARM. All rights reserved. iiID121213 Non-Confidential

  • ContentsARM Cortex-A57 MPCore Processor Technical Reference Manual

    PrefaceAbout this book ......................................................................................................... viiiFeedback ................................................................................................................... xii

    Chapter 1 Introduction1.1 About the Cortex-A57 MPCore processor ............................................................... 1-21.2 Compliance .............................................................................................................. 1-31.3 Features ................................................................................................................... 1-51.4 Interfaces ................................................................................................................. 1-61.5 Implementation options ............................................................................................ 1-71.6 Test features ............................................................................................................ 1-91.7 Product documentation and design flow ................................................................ 1-101.8 Product revisions ................................................................................................... 1-13

    Chapter 2 Functional Description2.1 About the Cortex-A57 MPCore multiprocessor functions ........................................ 2-22.2 Interfaces ................................................................................................................. 2-62.3 Clocking and resets ................................................................................................. 2-82.4 Power management ............................................................................................... 2-19

    Chapter 3 Programmers Model3.1 About the programmers model ................................................................................ 3-23.2 ARMv8 architecture concepts .................................................................................. 3-33.3 ThumbEE instruction set ........................................................................................ 3-113.4 Jazelle implementation .......................................................................................... 3-123.5 Memory model ....................................................................................................... 3-14

    ARM DDI 0488C Copyright 2013 ARM. All rights reserved. iiiID121213 Non-Confidential

  • Contents

    Chapter 4 System Control4.1 About system control ............................................................................................... 4-24.2 AArch64 register summary ...................................................................................... 4-34.3 AArch64 register descriptions ................................................................................ 4-144.4 AArch32 register summary .................................................................................. 4-1284.5 AArch32 register descriptions .............................................................................. 4-155

    Chapter 5 Memory Management Unit5.1 About the MMU ........................................................................................................ 5-25.2 TLB organization ...................................................................................................... 5-35.3 TLB match process .................................................................................................. 5-45.4 Memory access sequence ....................................................................................... 5-55.5 MMU enabling and disabling ................................................................................... 5-75.6 Intermediate table walk caches ............................................................................... 5-85.7 External aborts ....................................................................................................... 5-10

    Chapter 6 Level 1 Memory System6.1 About the L1 memory system .................................................................................. 6-26.2 Cache organization .................................................................................................. 6-36.3 L1 instruction memory system ................................................................................. 6-46.4 L1 data memory system .......................................................................................... 6-66.5 Program flow prediction ......................................................................................... 6-126.6 L1 RAM memories ................................................................................................. 6-15

    Chapter 7 Level 2 Memory System7.1 About the L2 memory system .................................................................................. 7-27.2 Cache organization .................................................................................................. 7-37.3 L2 RAM memories ................................................................................................... 7-87.4 L2 cache prefetcher ................................................................................................. 7-97.5 Cache coherency ................................................................................................... 7-107.6 Asynchronous errors .............................................................................................. 7-117.7 External coherent interfaces .................................................................................. 7-127.8 ACP ....................................................................................................................... 7-19

    Chapter 8 Generic Interrupt Controller CPU Interface8.1 About the GIC .......................................................................................................... 8-28.2 GIC functional description ........................................................................................ 8-38.3 GIC programmers model ......................................................................................... 8-8

    Chapter 9 Generic Timer9.1 About the Generic Timer .......................................................................................... 9-29.2 Generic Timer functional description ....................................................................... 9-39.3 Generic Timer register summary ............................................................................. 9-4

    Chapter 10 Debug10.1 About debug .......................................................................................................... 10-210.2 Debug register interfaces ....................................................................................... 10-410.3 AArch64 debug register summary ......................................................................... 10-610.4 AArch64 debug register descriptions ..................................................................... 10-810.5 AArch32 debug register summary ....................................................................... 10-1410.6 AArch32 debug register descriptions ................................................................... 10-1710.7 Memory-mapped register summary ..................................................

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