arm9 embedded book-guide
TRANSCRIPT
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LP TRNH THNG NHNG TRN
VI XL ARM(Programming the ARM Microprocessor
for Embedded Systems)
Nguyn Tn Thnh
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ARM Architecture and ARM Core Overview
1
I. GII THIU KIN TRC ARM
1.1 Introduction to ARM Ltd.
1.2 The ARM Architecture.
1.2.1 Example ARM based system:
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1.2.2 Which architecture is my processor?
Processor core Architecture
ARM7TDMI family v4T
ARM720T, ARM740T
ARM9TDMI family v4T
ARM920T,ARM922T,ARM940T
ARM9E family v5TE, v5TEJ
ARM946E-S, ARM966E-S, ARM926EJ-S
ARM10E family v5TE, v5TEJ
ARM1020E, ARM1022E, ARM1026EJ-S
ARM11 family v6
ARM1136J(F)-S v6
ARM1156T2(F)-S v6T2
ARM1176JZ(F)-S v6Z
Cortex family
ARM Cortex-A8 v7A
ARM Cortex-R4 v7R
ARM Cortex-M3 v7M
More information is available at arm.com
1.2.3 Data Sizes and Instruction Sets.
ARM is a RISC architecture
Many instructions execute in a single cycle
ARM is a 32-bit load / store architecture
When used in relation to the ARM:
Halfword means 16 bits (two bytes)
Word means 32 bits (four bytes)
Doubleword means 64 bits (eight bytes)
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Most ARMs implement two instruction sets
32-bit ARM Instruction Set
16-bit Thumb Instruction Set
Latest ARM cores introduce a new instruction set Thumb-2 Provides a mixture of 32-bit and 16-bit instructions
Maintains code density with increased flexibility
Jazelle cores can also execute Java bytecode.
1.2.4 Processor Modes.
The ARM has seven basic operating modes:
Each mode has access to
Its own stack space and a different subset of registers.
Some operations can only be carried out in a privileged mode.
1.2.5 The ARM Register Set.
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1.2.6 Register Organization Summary.
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1.2.7 Program Status Registers.
1.2.8 Program Counter (r15).
When the processor is executing in ARM state:
All instructions are 32 bits wide
All instructions must be word aligned
Therefore the pcvalue is stored in bits [31:2] with bits [1:0] undefined (asinstruction cannot be halfword or byte aligned).
When the processor is executing in Thumb state:
Condition code flags
N = Negative result from ALU
Z = Zero result from ALU
C = ALU operation Carried out
V = ALU operation oVerflowed
Sticky Overflow flag - Q flag
Architecture 5TE and later only
Indicates if saturation has
occurred
J bit
Architecture 5TEJ and later only
J = 1: Processor in Jazelle state
Interrupt Disable bits.
I = 1: Disables the IRQ
F = 1: Disables the FI
T Bit
T = 0: Processor in ARM state
T = 1: Processor in Thumb state
Introduced in Architecture 4T
Mode bits
Specify the processor mode
New bits in V6
GE[3:0]used by some SIMDinstructions.
Ebit controls load/store endianness.
Abit disables imprecise data aborts.
IT [abcde]IF THEN conditionalexecution of Thumb2 instruction
groups.
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All instructions are 16 bits wide
All instructions must be halfword aligned
Therefore the pcvalue is stored in bits [31:1] with bit [0] undefined (asinstructions cannot be byte aligned.
1.2.9 Exception Handling.
1.2.10 Data Alignment.
Memory accesses must always be appropriately aligned for size of access
Unaligned addresses will produce unexpected/undefined results.
When an exception occurs, the core:
Copies CPSR into SPSR_
Sets appropriate CPSR bits
Change to ARM state
Change to exception mode
Disable interrupts (if appropriate)
Stores the return address in LR_
Sets PC to vector address
To return, exception handler needs to:
Restore CPSR from SPSR_
Restore PC from LR_
This can only be done in ARM state.
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Detect invalid unaligned data accesses with Data Abort exception.
External logic required, or use MMU when available
Beware that instruction fetches may appear unaligned
Unaligned data can be accessed using aligned access combined with
shift/mask operations.
1.2.11 Endian Configuration.
Endianness determines how contents of registers relate to the contents of
memory.
ARM registers are word (4 bytes) width
ARM addresses memory as a sequence of bytes
ARM processors are little-endian.
But can be configured to access big-endian memory systems
Little-endian memory system
Least significant byte is at lowest address
Big-endian memory system
Most significant byte is at lowest address
ARM support three models of endianness.
LE Little-Endian
BE-32 Word Invariant Big-Endian
BE-8 Byte invariant Big-Endian (introduced in architecture v6).
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1.3 ARM Instruction Set.
All instructions are 32 bits long / many execute in a single cycle.
Instructions are conditionally executed.
A load / store architecture.
Example data processing instructions
SUB r0,r1,#5
ADD r2,r3,r3,LSL #2
ANDS r4,r4,#0x20
ADDEQ r5,r5,r6
Example branching instruction
B
Example memory access instructions
LDR r0,[r1]
STRNEB r2,[r3,r4]
STMFD sp!,{r4-r8,lr}
Thumb Instruction Set:
Thumb is a 16-bit instruction set
Optimized for code density from C code (~65% of ARM code size)
Improved performance from narrow memory
Subset of the functionality of the ARM instruction set
Switch between ARM and Thumb state using BX instruction
r0 = r1 - 5
r2 = r3 + (r3 * 4)
r4 = r4 AND 0x20 (set flags)
IF EQ condition true r5 = r5 + r6Branch forwards or backwards relative t
current PC (+/- 32MB range)
Load word at address r1 into r0
IF NE condition true, store bottom byte
r2 to address r3+r4
For most instructions generated by compiler:
Conditional execution is not used
Source and destination registers identical
Only Low registers used
Constants are of limited size
Inline barrel shifter not used
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Thumb-2 Instruction Set:
Thumb-2 is a major extension to the Thumb ISA
Adds 32-bit instructions to implement almost all of the ARM ISA
functionality
Retains the complete 16-bit Thumb instruction set
Supported by the ARM1156T2-S and Cortex Family
Cortex-M3 supports only Thumb-2
Cortex-M1 supports a subset of Thumb-2
Design objective: ARM performance with Thumb code density
No need to manually select instruction set split
Reduces need to profile code and understand execution patterns
Compiler can automatically select mix of 16 and 32 bit instructions
Gives access to ARM state behaviour
Exceptions may be handled directly
Coprocessors can be accessed
Advanced data handling of v5TE & v6 can be done
Conditional Execution via If-Then (IT) instruction
1-4 following instructions conditionally executed
Thumb 2 Performance / Density:
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Jazelle:
Jazelle-enabled ARM cores execute 8-bit Java bytecode
95% of bytecodes executed in hardware (typical)
Significantly more power-efficient
1.3.1 ARM Branches and Subroutines.
B
PC relative, 32 MB range
BL
Stores return address in LR
Returning implemented by restoring the PC from LR
For non-leaf functions, LR will have to be stacked
BX
Branch to address in register - with optional state change
Used in this context as a return instruction
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1.3.2 Coprocessors.
Up to 16 coprocessors can be defined
Expands the ARM instruction set
ARM uses them for internal functions so as not to enforce a particular memory
map (eg cp15 is the ARM cache controller)
Usually better for system designers to use memory mapped peripherals
Easier to implement.
1.4 ARM Processor Cores.1.4.1 The ARM7TDMI Processor Core.
ARM7TDMI features
3 stage pipeline
Von Neumann architecture
CPI ~1.9
T Thumb instruction set support 32-bit ARM instructions
16-bit Thumb instructions
D Debug supportM Enhanced multiplier (32x8) with
instructions for 64-bit results
I EmbeddedICE Logic
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The Instruction Pipeline.
The ARM7 family uses a 3 stage pipeline in order to increase the speed of the flow
of instructions to the processor.
Allows several operations to be undertaken simultaneously, rather than serially.
The PC points to the instruction being fetched, not the instruction being executed.
Optimal Pipelining.
All operations here are on registers (single cycle execution).
In this example it takes 6 clock cycles to execute 6 instructions.
Clock cycles per Instruction (CPI) = 1
LDR Pipeline Example.
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Branch Pipeline Example.
Interrupt Pipeline Example.
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1.4.2 ARM9TDMI.
Architecture v4T
5 stage pipeline
Improves CPI to ~1.5
Improved maximum clock frequency
Harvard architecture
Increases available memory bandwidth
Instruction memory interface
Data memory interface
Simultaneous access to instruction and
data memory can be achieved
Normally supplied with caches attached
ARM922T (pictured)
2 x 8K caches
Memory Management Unit (MMU)
Write Buffer
ARM920T
As ARM922T but with 2 x 16K caches
ARM940T
Has a Memory Protection Unit (MPU)
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Pipeline changes for ARM9TDMI.
Cached Processor Terminology.
MPU Memory Protection Unit
Controls memory access permissions
Controls cacheable and bufferable
attributes for memory regions
MMU Memory Management Unit
Has all the features of an MPU
Also provides Virtual to Physical
address translation
Cache
Fast local memory
Holds copies of recently accessed
memory locations
TCM Tightly Coupled Memory
Fast local memory
Located at particular address range
Write buffer
Decouples writes to external
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1.4.3 ARM9E Processor Core.
1.4.4 ARM10E Family Overview.
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1.4.5 ARM1136J(F)-S Overview.
1.4.6 ARM Cortex-M3 Processor.
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ARMv7M Architecture
No ARM instruction set support
Thumb-2 only
No Cache - No MMU
Debug is optimized for microcontroller applications
Vector table is addresses, not instructions
Interrupts automatically save/restore state
Exceptions programmed in C
No Coprocessor 15
All registers are memory-mapped
Interrupt controller is part of Cortex-M3 macrocell
1.4.7 ARM Cortex-A8 Processor.
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Processor highlights
High frequency, high efficiency, low power
In-order, dual-issue, superscalar microprocessor
Advanced dynamic branch prediction
Average IPC of 0.9 across 150+ ARM and industry benchmarks
Custom / synthesizable design
ARMv7 instruction set
Integrated NEON media processor
Unified level 2 cache
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AXI interface
1.5 AMBA
Advanced Microcontroller Bus Architecture aims to:
Make life easier for systems designers Standardize the bus interface
Reduce the support required
From ARM
Between internal design teams
Allows increased re-use of IP in designs
Enable the creation of upgrades and families of devices
AMBA 2.0: AHB.
Advanced High Performance Bus
High performance:
Full clock cycle to provide wait response
Burst signals for optimal memory interface
Split transaction for high access latency memory
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No overhead for arbitration or at start of bursts
Single Cycle Bus Master Handover
Data width extendable for high bandwidth
Synthesis friendly Uses only rising edge of clock
No combinatorial input to output paths
STA and test insertion friendly
No bias towards tri-state implementation
No requirement for latches
No state dependent timing parameters
AHB Structure.
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AMBA 3.0: AXI (AXI is the AHB component of AMBA3.0)
Design Objectives:
Suitable for high-bandwidth & low-latency design
High frequency without bridges
Flexibility in interconnection architecture
Good performance with long initial latency peripherals
Backwards-compatibility with AHB & APB
Features
Separate address/control & data phases
Support for unaligned data transfers
Burst transaction based on start address issue only
Separate read & write channels
Multiple outstanding addresses
Out-of-order transaction completion
AXI Multi-Master System Design.
More AMBA:
Advanced Peripheral Bus (APB)
Reduces loading on main system bus
Low power, with no requirement for a clock
Suitable for synthesizable design
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Robust with set-up and hold ensured by protocol
Suitable for D-type or transparent latch based design
Advanced System Bus
Based on the original ARM bus interface
Uses both clock edges
Low silicon / interconnect overhead
Interface used by ARM7x0T and ARM9x0T cores
1.6 Writing Software for ARM Processors.
Tools: ADS (CodeWarrior), RVDS, Keil, IAR, GNU,
1.6.1 Keil uVision4.2
RealView Compilation Tools (RVCT) 3.0 includes
Highly optimising single ISO C/C++ compiler
Ongoing code density and performance improvements with each
release.
Full ISO C++ support (including exceptions)
ABI compliant (see later)
Support for latest architectures (v6, v7A and v7M)
Support for Thumb-2 instruction set
Data compressor - reduces space required in ROM
Linker feedback mechanism - informs compiler of unused functions which
can be eliminated in subsequent builds
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Other Compilation Tool Components
ARM / Thumb assembler - armasm
Linker - armlink
Format converter - fromelf
Librarian - armar
C and C++ libraries
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1.6.2 Application Code and Data Size:
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1.6.3 Introduction to Scatterloading: In a real application, you will not want to load and execute your code at the default
address
Most embedded systems have memory devices spread across the memory
map Scatterloading provides a way of placing your code and data into the
appropriate locations in memory
Scatterloading defines two types of memory region
Load Regions - contain application code & data at reset/load time (typically
ROM)
Execution Regions - contain code and data whilst the application is
executing
One or more execution regions will be created from each load region
during application startup The details of the memory map used by a scatterloaded application
are contained in a description file which is passed as a parameter to
armlink
eg: armlink program.o --scatter scatter.scat -o program.axf.
Scatterloading (Simple Example):
RO code and data stays in ROM
C library initialization code (in __main) will :
o copy RW data from ROM to RAM
o initialize to zero the ZI data in RAM
Scatter Description Files
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To explain the syntax of a scatter-file :
In our scatter file we need to give both our load and execution regions a name.We also need to specify a start address. There is an optional length parameter which can
follow the address parameter. For our example, the following syntax describes our single
load region.
The header syntax for execution regions is very similar to the header syntax for
load regions. As you can see from the execution region names, the first is located in
ROM, and the second is located in RAM.
You must specify the contents of each execution region with the curly braces. In
this example, we make use of the wildcard (*) syntax which collects all sections with agiven attribute. In the EXEC_ROM region, we collect all sections with the RO attribute.
In the RAM region, we collect all sections with either RW or ZI attributes.
Note that the linker placement rules discussed earlier apply to each execution
region individually, so all RW code and data will be located before all ZI data. (As shown
in the diagram).
The best discussion of scatter file syntax can be found in the RVCT Linker and
Utilities Guide.
1.6.4 Supplied Libraries.
ANSI C library:
Full file handling, string, maths, etc., support on the target
By default uses semihosted SWIs to access host debugger facilities
e.g. file I/O
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Retargetable without rebuilding whole library
Automatic selection of the correct library variant
C++ library includes:
Libraries and Semihosting: Full file handling, string, maths, etc., support on the target
The linker will automatically link in the correct library variants for your
application
Depending on endianess, floating point requirements, position
independence, etc.
By default semihosting is used to access host debugger facilities
Library code runs on ARM target, low-level I/O provided by host debugger
User provides replacement implementations of specific functions forembedded use
Retargeting the C Library (1): You can replace the C librarys device driver lever functionality with an
implementation that is tailored to your target hardware
e.g. printf() should go to LCD screen, not debugger console
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To Retarget the C library, simply replace those C library functions whichuse semihosting SWIs with your own implementations, to suit your system
For example, the printf() family of functions (except sprintf()) allultimately call fputc()
The default implementation of fputc()uses a semihosting SWI
Replace this with:
extern void sendchar(char *ch);
int fputc(int ch, FILE *f)
{ /* e.g. write a character to an LCD */
char tempch = ch;
sendchar(&tempch);return ch;
}
See retarget.cin the examples directory for further examples of retargeting
1.5 Reference Material.
ARM Architecture Reference Manual - 2nd edition
edited by David Seal
ARM DDI 0100E is latest, covering v5TE DSP extensions
ISBN 0-201-737191 (Addison-Wesley)
Steve Furber ARM system-on-chip architecture - 2nd edition
ISBN 0-201-67519-6 (Addison-Wesley)
Sloss, Symes & Wright ARM System Developer's Guide
ISBN: 1-55860-874-5 (Morgan Kaufman)
Documentation (TRMs, datasheets, user guides, application notes, whitepapers)
http://www.arm.com/documentation
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II. AT91SAM9260
c in chnh:
-
Tc 180MHz, bxl ARM926EJ-S htrtp lnh Thumb v ARM.
8 Kbytes bnhchng trnh v 8 KBtytes bnhdliu v MMU.
- Bnh.
Giao din bus 32 bit htr4 bank SDRAM/LPSDR, Static memories,CompactFlash, SLC NAND Flash with ECC.
2 SRAM on-chip tc cao, mi SRAM 4-kbyte.
Mt ROM on-chip 32-kbyte, c nhng sn bootstrap (level 1).
-
Ngoi vi.
4 knh ADC 10 bit, (2 knh cho QFP, v 4 knh cho BGA).
2 UARTs,
4 USARTs,
1 Giao din giao tip I2C (two wire interface - TWI).
1 biu khin ni tip ng b(synchronous serial controller).
2 SPI htr2 chMaster/Slaver.
1 Giao din Memory Card Host tc cao (SD/MMC card interface).
1 Biu khin 10/100 Mbps Ethernet MAC.
1 Biu khin truyn nhn USB-B (device) on-chip.
1 Biu khin truyn nhn USB-A (host) on-chip.
1 Giao din ITU-R BT. 601/656 image sensor giao tip CMOS camera.
- Hthng (System).
22 knh DMA (direction memory access).
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Khi ng (boot) tNAND Flash, SDCard, DataFlash hoc serial
DataFlash.
Biu khin reset (reset controller).
Ma trn bus AHB 6 lp 32 bit hot ng tn s90MHz.
Mt PLL cho hthng, v mt cho USB.
Hai tn hiu xung ng hngoi c thlp trnh c.
Biu khin ngt cao cp (AIC) v debug.
Tch hp bgiao ng ni RC 32 kHz nng lng thp.
Cho php chn tn stit kim nng lng 32,768 Hz v bgiao ng
chnh 3-20 MHz.
Cho php ci t chtimer, watchdog timer, real time timer.
- Khi xut nhp (I/O).
3 biu khin xut nhp song song 32 bit.
96 ng I/O a mc ch.
2.1
Skhi AT91SAM9260.Bng 2-1: Cc tn hiu khng c trn kiu chn PQFP.
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Bng 2-2: Skhi AT91SAM9260.
2.2
Bng c tcc tn hiu.
Bng 2-3: c tcc tn hiu:
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2.3 Bng c tcc chn. (page 10 of doc6221.pdf)
Bng 2-4: Bng m tchn 208-PQFP
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2.4
Power considerations.
2.4.1
Power suplies.
VDDCORE pins: Power the core, including the processor, the embedded memories
and the peripherals; voltage ranges from 1.65V and 1.95V, 1.8V nominal. VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges between
1.65V and 1.95V (1.8V typical) or between 3.0V and 3.6V (3.3V nominal). The
expected voltage range is selectable by software.
VDDIOP0 pins: Power the Peripheral I/O lines and the USB transceivers; voltageranges from 3.0V and 3.6V, 3V or 3.3V nominal.
VDDIOP1 pins: Power the Peripherals I/O lines involving the Image Sensor Interface;voltage ranges from 1.65V and 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal.
VDDBU pin: Powers the Slow Clock oscillator and a part of the System controller;
voltage ranges from 1.65V to 1.95V, 1.8V nominal. VDDPLL pin: Powers the Main Oscillator and PLL cells; voltage ranges from 1.65V
and 1.95V, 1.8V nominal.
VDDANA pin: Powers the Analog to Digital Converter; voltage ranges from 3.0V and3.6V, 3.3V nominal.
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The power supplies VDDIOM, VDDIOP0 and VDDIOP1 are identified in the pinout table
and the multiplexing tables. These supplies enable the user to power the device differently
for interfacing with memories and for interfacing with peripherals.
Ground pins GND are common to VDDCORE, VDDIOM, VDDIOP0 and VDDIOP1 pins
power supplies. Separated ground pins are provided for VDDBU, VDDPLL and VDDANA.
These ground pins are respectively GNDBU, GNDPLL and GNDANA.
2.5
Processor and architecture.
ARM926EJ-S Processor. RISC ProcessorBased on ARM v5TEJ Architecture with Jazelle technology for Javaacceleration.
Two Instruction Sets.
ARM High-performance 32-bit Instruction Set.
Thumb High Code Density 16-bit Instruction Set.Slow Clock Selection:The AT91SAM9260 slow clock can be generated either by anexternal 32,768 Hz crystal or the on-chip RC oscillator.
OSCSEL Slow Clock Startup Time
0 Internal RC 240 s
1 External 32768 Hz 1200 ms16
The startup counter delay for the slow clock oscillator depends on the OSCSEL signal.
The 32,768 Hz startup delay is 1200 ms whereas it is 240 s for the internal RC oscillator.
The pin OSCSEL must be tied either to GND or VDDBU for correct operation of the
device.
DSP Instruction Extensions.
5-Stage Pipeline Architecture:
Instruction Fetch (F)
Instruction Decode (D)
Execute (E)
Data Memory (M)
Register Write (W)
8-Kbyte Data Cache, 8-Kbyte Instruction Cache:
Virtually-addressed 4-way Associative Cache.
Eight words per line.
Write-through and Write-back Operation.
Pseudo-random or Round-robin Replacement.
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Write Buffer.
Standard ARM v4 and v5 Memory Management Unit (MMU).
Access Permission for Sections.
Access Permission for large pages and small pages can be specified separately for
each quarter of the page. 16 embedded domains.
Bus Interface Unit (BIU).
Arbitrates and Schedules AHB Requests.
Separate Masters for both instruction and data access providing complete Matrix
system flexibility.
Separate Address and Data Buses for both the 32-bit instruction interface and the 32-
bit data interface.
On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit(Words).
Bus Matrix: has a 6-layer Matrix, handling requests from 6 mastersBoot Mode Select.
Non-volatile Boot Memory can be internal or external
Selection is made by BMS pin sampled at reset
Remap Command.
Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory.
Allows Handling of Dynamic Exception Vectors.The Bus Matrix of the AT91SAM9260 manages six Masters, which means that each
master can perform an access concurrently with others, according the slave it accesses is
available.
Each Master has its own decoder that can be defined specifically for each master. In order
to simplify the addressing, all the masters have the same decodings.
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Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be
programmed.
Master to Slave Access:
All the Masters can normally access all the Slaves. However, some paths do not make
sense, such as allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these
paths are forbidden or simply not wired, and shown - in the following table.
Peripheral DMA controllers:
Twenty-two channels.
Two for each USART.
Two for the Debug Unit. Two for each Serial Synchronous Co.
Two for each Serial Peripheral Interf.
One for Multimedia Card Interface.
One for Analog-to-Digital Converter.
Prefer to the datasheet for details of informations.
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AT91SAM9260 Sumary
41
2.6 Memories.
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AT91SAM9260 Sumary
42
Decoding breaks up the 4G bytes of address space into 16 banks of 256 Mbytes. The
banks 1 to 7 are directed to the EBI that associates these banks to the external chip selects
EBI_NCS0 to EBI_NCS7. Bank 0 is reserved for the addressing of the internal memories,
and a second level of decoding provides 1 Mbyte of internal memory area. Bank 15 is
reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the
master requesting such an access.
Each Master has its own bus and its own decoder, thus allowing a different memory
mapping per Master. However, in order to simplify the mappings, all the masters have a
similar address decoding.
Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves
are assigned to the memory space decoded at address 0x0: one for internal boot, one for
external boot, one after remap.
2.7
Peripherals.2.7.1
IdentifiersA peripheral identifier is required for the control of the peripheral interrupt with the
Advanced Interrupt Controller and for the control of the peripheral clock with the Power
Management Controller.
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AT91SAM9260 Sumary
43
Setting AIC, SYSC, UHP and IRQ0-2 bits in the clock set/clear registers of the PMC has no
effect.
2.7.2
Peripheral interrupts and clock control.2.7.2.1
System interrupt.The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming
from:
the SDRAM Controller. the Debug Unit.
the Periodic Interval Timer.
the Real-time Timer.
the Watchdog Timer.
the Reset Controller.
the Power Management Controller.
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be
used within the Advanced Interrupt Controller.
2.7.2.2
External interrupts.All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals
IRQ0 to IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated
with these peripheral IDs.
2.7.2.3 Peripheral signal multiplexing on I/O lines.
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AT91SAM9260 Sumary
44
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AT91SAM9260 Sumary
45
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AT91SAM9260 Sumary
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NAND Flash Support in AT91SAM9 Microcontrollers
47
III. NAND Flash Support in AT91SAM9
Microcontrollers
3.1 Flash Overview.Flash l bnhkhng bay hi (non-volatile storage chip), c thxa v lp
trnh li bng in. in hnh l EEPROM (electrically erasable programmableread-only memory). B nh Flash c s dng nhiu trong memory card, USBFlash drives, MP3 players v solid-state drives vi mc ch chung l lu tr vtruyn dliu gia my tnh vi cc thit bskhc, v.v
Lch s b nh Flash (both NOR and NAND) c pht minh bi tin sFujio Masuoka nm 1980 khi ang lm vic cho TOSHIBA v c trnh by tihi nghin tquc tIEEE nm 1984 ti San Francisco, California.
NOR: c bnhNOR flash ging nhc bnhRAMv c giao dindata bus v address bus ging RAM. Chnh v thrt nhiu vi xl c thsdng
NOR flash nhvng nh thc thi chng trnh (execute place memory), ngha lchng trnh lu trong NOR flash c ththc hin trc tip tNOR flash m khngcn copy ln RAM chy. Qun l bad block l mt c im mi ca NOR flash,i vi cc NOR flash ckhng htrchc nng ny m software or device driver
slm cng vic ny.
NAND Flash: c truy xut ging nh block devies nha cng, thnh. Each block consists of a number of pages. The pages are typically 512, 2048,4096 bytes in size. Each page are a few bytes (typically 1/32 of the data size) that
can be used for storage of an ECC (error correcting code) checksum.
NOR | NAND
CE# - chip enable | CE# - chip enable WP# - write protect
WE# - write enable | WE# - write enable R/B# - ready / busy
OE# - output enable | RE# - read enable PRE power on RE
D[15:0] - data bus | CLE - command latch enable
A[20:0] - address bus | ALE - address latch enable
WP# - write protect | I/O[7:0] or I/O[15:0] data bus
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NAND Flash Support in AT91SAM9 Microcontrollers
48
3.2 NAND Flash Connection on AT91SAM9260.
NAND Flash c iu khin bi SMC ca AT91 tm a ch NCS3(0x40000000 0x4FFFFFFF), (256MB)
Bng cu hnh hthng:
3.2.1 8-bit NAND Flash on AT91SAM9260.
3.2.2 16-bit NAND Flash on AT91SAM9260.
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NAND Flash Support in AT91SAM9 Microcontrollers
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Using SDRAM on AT91SAM9 Microcontrollers
50
IV. Using SDRAM on AT91SAM9 Microcontrollers
tham kho doc6256.pdf ca atmel.
4.1 RAM Overview.
c tnh:
RAM (random access memory) - bnhtruy xut ngu nhin.
RAM cn c hiu l bnhRW (read/write memory) v khc vi bnhROM.
Lu chng trnh v dliu trong sut qu trnh thc thi.
Phn loi:
SRAM (Static RAM):c chto theo cng nghECL (CMOS or BiCMOS),mi bit nhc thikbi cng logic vi 6 transistor MOS, tc cao vgiao din kt ni n gin.
DRAM (Dinymic RAM). s dng k thut MOS, Mi bit nh gm mttransistor v mt tin. Vic ghi nhdliu da vo vic duy tr in tchnp vo tin v nhvy vic c mt bit nhlm ni dung bit ny bhy.Do vy sau mi ln c mt nh, bphn iu khin bnhphi vit li
ni dung nh. V thgiao din kt ni DRAM c thm tn hiu Auto-recharge (auto-refresh). C mt sloi DRAM sau:
+ SDRAM( Synchronous Dynamic RAM) - DRAM ng b. SDRAM hinc cc loi: SDR, DDR, DDR2 v DDR3.
- SDR SDRAM (Single Data Rate SDRAM), gi tt SDR.- DDR SDRAM (Double Data Rate SDRAM), gi tt DDR.- DDR2 SDRAM (Double Data Rate 2 SDRAM), gi tt DDR2.
-
DDR III SDRAM (Double Data Rate III SDRAM): DDR3, 64-bit, 1.5V.
+ RDRAM( Rambus Dynamic RAM), gi tt "Rambus", cn tham khothm XDR memory architecture.
4.2 SDRAM Controller on AT91SAM9Overview.
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Using SDRAM on AT91SAM9 Microcontrollers
51
SDRAMC l biu khin m rng bnh ca 1 chip, giao din 16-bit or32-bit SDRAM. Kch thc memory page t 2048 - 4192 v s column l 256 -2048. SDRAMC cho php truy xut byte (8-bit), half-word (16-bit) v word (32-
bit).
SDRAMC cho php truy xut word burst (no byte or half word bust). Tlmti (self - refresh).
4.3 SDRAM Controller Signals Definition.
SDA10: lm vic nh l mt ng a ch SDRAM nhng cng c s dng nh lauto-precharge command bit. AT91 cung cp mt tn hiu output SDA10 chuyn dng cho
php hthng kch hot tnh nng tng precharge m khng nh hng bus a ch.
NBS[3:0]: tn hiu mt ndliu tng ng truy xut 8, 16 v 32 bit data.
SDRAMC_A[12:0]:cc ng a chca SDRAMC tng ng vi [A2:A14] ca vi xl ngoi tr SDRAMC_A10 (SDA10). SDRAMC_A[12:0] qun l a ch ln ti 11columns v 3 row.
4.4 SDRAM Connection on AT91SAM9.
AT91 cung cp NCS1 trong khng gian bnhkt ni vi 16-bit hoc 32-
bit SDRAM ngoi. DW bit trong thanh ghi cu hnh SDRAMC schn 16-bithoc 32-bit bus width.
Giao din 32-bit SDRAMC c thkt ni vi mt 32-bit SDRAM hoc hai16-bit SDRAM.
4.4.1 SDRAM 16-bit Connection.
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Using SDRAM on AT91SAM9 Microcontrollers
52
4.4.2 SDRAM 32-bit Connection
4.5 ARM926EJ-S Access.
Single access, 4-word burst access, 8-word burst access.
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V. Schematic of SAM9260-EK
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5.1. Power Suppy.
DOUT
5V
DS1
CR15V
POWER LED
CS
AUDIO DSSC C
R3
100K
U2 L1117_3V3
2
4
1
3
Output
Vout
Ajd/G
nd
Input1 3
5 7 9
11
5V
CLK
R1 1k
C810F
U3 L1117_1V
1
3
O
Ajd/Gnd
Input
S7
12
3V3
+
C1330F
C1510F
C1010PF
5V
C9
10F
S8
12
REGULATED
DIN
3V3
J1 12
3
5V_USB
5V ONLY
5.2. AT91SAM9260 (PQFP package).
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5.3. Memories.
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C73100NF
SDA10
SDA
3V3
D[0..7]
A3
A5
D6
D9
8-bit bus width
C86100NF
CLE
MN6B1
18
6
37
9
8
20
19
5
1234
21222324
7
26
27
28
29
3435
36
3839
12
13
17
1110
14
15
16
25
33
30
3231
474645
44434241
40
48
WE
N.C
VCC
CE
RE
N.C
WP
N.C
N.CN.CN.CN.C
N.CN.CN.CN.C
R/B
N.C
N.CN.C
I/O0
N.CN.C
VSS
PREN.C
VCC
VSS
ALE
N.CN.C
N.CN.C
CLE
N.C
N.C
I/O1
I/O3I/O2
N.CN.CN.C
I/O7I/O6I/O5
I/O4
N.C
N.C
D5
DAT3
D4
SDCKE
D4
SDCK
3V3_Memory
R4410K
C70100NF
CLK
3V3
D1
S5
CS
ALE
256 Mbits
RAS3V3
D10
A9
MT48LC16M16A2
MN72324252629
3031323334
22
20
36
24578
1011134244
454748505153
1
2841
327
40
38
37
1539
1718
1619
94349
6124652
14
54
35
21
A0
A1A2A3A4A5A6A7A8
A9A10
BA0
A12
DQ0
DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8
DQ9DQ10DQ11DQ12DQ13DQ14DQ15
VDD
VSSVSS
VDDQVDD
N.C
CLK
CKE
DQMLDQMH
CASRAS
WECS
VDDQVDDQVDDQ
VSSQVSSQVSSQVSSQ
VDD
VSS
A11
BA1
A8
A4
D5
C74100NF
D[0..15]SDRAM
NANDCS
D7
3V3
SCL
NBS0
D0
D13BA0
CFIOR_NBS1_NWR1
D8
A0
A[0..14]
NANDWE
D0
C71100NF
D6
A2
R4510K
A7
BA1
CMD
D2
D7
SCK
A13
NRST
D14
R41 470K
SDCS_NCS1
C84
100NF
D3
D15
R33 470K
A10
SDWE
NANDOE
S6
D1
3V3A14
D11D12
A6
DAT2
R29
470K
R35 1K
C69100NF
DAT1
D3
C72100NF
NANDFLASH
C68100NF
DAT0
3V3
A11
CAS
D2
RDYBSY
C83100NF
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5.4. MII_Ethernet.
COL
Y425MHz
1 2
TXD1
C101
10V10F
CRS
TX_EN
3V3
C98 100NF
VCCA
RX_CLK
GND_ETH
C94100NF
GND_ETH
RXD3
C90 100NF
3V3
C8822PF
MDIO
NRST
C97 100NF
R5149R91%
RXD0
TXD2
C95
100NF
R5249R91%
C96 100NF
C8922PF
RX_ER
R64 0R
TX_ER
R58
6,80K
1%
TX_CLK
R1031K
C99
10V10F
R127 10K
G
R65 0R
C92100NF
3V3
3V3
MDC
TXD3
TXD0
GND_ETH
VCCA
3V3R56 10K
MN11
DM9161AEP
16
36
24
4
3
8
7
4342
3437
38
21
48
1
2
41
44
15
56
131211
1718
2019
22
29282726
35
2532
10
33
40
9
39
30
23
46
47
14
45
31
TX_ER/TXD4
COL/RMII
MDC
RX-
RX+
TX-
TX+
XT1REF_CLK/XT2
RX_CLK/10BTSERRX_DV/TESTMODE
RX_ER/RXD4/RPTR
TX_EN
BGRES
AVDDR
AVDDR
DVDD
DGND
DGND
AGNDAGND
LED2/OP2LED1/OP1LED0/OP0
TXD3TXD2
TXD0TXD1
TX_CLK/ISOLATE
RXD0/PHYAD0RXD1/PHYAD1RXD2/PHYAD2RXD3/PHYAD3
CRS/PHYAD4
MDIOMDINTR
PWRDWN
DGND
RESET
AVDDT
DISMDIX
DVDD
DVDD
AGND
BGRESG
CABLESTS/LINKSTS
N.C
LEDMODE
MDINTR
VCCA
RX_DV
RXD2
C9310V10F
R5349R91%
R5449R91%
C91100NF
L3 742792093
RXD1
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5.5. Serial Interfaces.
C107100NF
3V3
R871,5K
HDMA
5V_USB
C12415PF
3V3R8115K
R6739R
TXD0
R6639R
C104100NF
5V
F2
500 mA
J19
1
4
2
3
56
RXD0
R8422K
USB DEVICE INTERFACE
C105100NF
R68100K
3V3
R79100K
R8939R
USBCNX
C12315PF
C109100NF
R7015K
USB HOST INTERFACE
R7115K
NOT POPULATED
US B_CNX
DDP
C11933PF
NOT POPULATED
C11147pF
DDM
Femal e
DRXD
Femal e
C120100NF
MA
15
16
10
1112
9
2
6
GND
VCC
T2IN
T1INR1OU
R2OU
V+
V-
C11047pF
R9039R
HDPA
A
J16
USB-A
14 23
65
DTXD
5.6. Expansions and Users Interfaces.
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PA19
PB11
ISI_DATA[11]
GPI O
PA29
PB23
PB5
PB18
PB26
PA2
ISI_DATA[9]
PB9
PA[0..31]
PC3PB3
ISI_DATA[7]
PC11
C13110V10F
PA20
PB31
PA10
PA30
PA11
PB2
PB19
PC4
PA21
PB20
PC1
PB24
1V8
AGNDPA31
PA1
PB25
SPI 1_MI SO
PB4PA4
PB14
LED2
ISI_MCK
PC1
SPI 1_SPCK
PB[0..31]
PC1
PC5
PB29
PA22
ISI_VSYNC
PA12PA13
PB7
PB10
PA24
PB21
R118 22
SPI 1_NPCS1
PA23
PC1
PB0
PB17
PC9
ISI_DATA[5]
PC15
ISI_HSYNC
PB1
C13210V10F
C133
100NF
ISI_PCK
PA3
PB2
PB22
AVDD
PA24
PA14PA15
PC9
PC5
PB26
PB27
PA5PC7
ISI_DATA[0]
PB12
ISI_DATA[3]
PB31
PA25
R188
220
R108 0R
R189
220
R190
220
PB27
LED3
PC15
PB29
PB10
PC0
PIO_CNTRL2
3V3
ISI_DATA[1]
PB19
PB12
PC[0..15
PB30
C
R187
220
PIO_CNTRL1
PB0
J28
1 23 45 67 89 10
11 121315
1719
1416
1820
21 2223 2425 26
27 2829 30
C130
100NF
ISI_DATA[2]PB24
PA26
PC7
PB11
PA16
PB22
PA6PA7
PB25
IMAGE SENSOR CONNECTOR
PB8
ISI_DATA[4]
PB30
PA27
R109 0R
LED4
5V
PC5
SP
PB20
PB9
PA17
TWDPA23
PA0
ISI_DATA[6]
PB16
LED1
PB28
PB23
TWCK
PB21
ISI_DATA[8]
PA18
PB13
PB15PC13
3V3
PB28
PB6
ISI_DATA[10]
PC6
DS5
GREEN
LEDS & US
PA28
PB13
PB11
PA8PA9
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Development Tools
62
VI. SAM9260-EK DescriptionsFeatures:
-
MCU AT91SAM9260, 16/32 bit ARM926EJ-S 180Mhz.
-
32MB SDRAM.-
256MB NAND FLASH.
- 512kB SPI serial dataflash.
-
Ethernet 10/100 base RJ45 connector.
- USB host, device connector.
-
RS232 connector: user + debug.
-
Micro SD/MMC card slot.
-
Three buttons: RST, WAKEUP, IRQ1.
-
Five LEDs.
-
Expansion Connector.
-
JTAG connector.
- 5 VDC power supply from adapter or USB-B conector.
Softwares:
- AT91BootStrap-1.1
- U-Boot-1.3.4, U-Boot-2009.09.1, U-Boot-2010.09
- Linux-2.6.27, Linux-2.6.30, Linux-2.6.36,
- Buildroot 2010, Angstrom, Debian rootfs.
-
Appication: Standalone (firmware), application in Embedded linux.
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Development Tools
63
6.1. Header comments
J7Default Close Open
Open Boot from EBI_NCS0 Boot from embedded rom
S1 Open
S2 OpenS3 Open
S5 Close CS data flash disconnect CS data flash
S6 Close CS nand flash disconnect CS nand flash
J13 Option1-3, 2-4: to select COM debug
5-3, 6-4: to select COM user
S7 Option Power supply from the 5Vdc adaptor
S8 Option Power supply from the USB-B cable
6.2. Map of Memories In SAM9260-EK.
Items Chip Select Address Comments Part number CapacitySDRAM nCS1 0x20000000 Physical MT48LC16M16A2 32MB
NANDFLASH nCS3 0x40000000 Physical K9F2G08UOM 256MB
Se.DataFlash SPI0_NPCS1 0xD0000000 Logical AT45DB041D-SU 512KB
6.3. Partition in The System.
6.3.1 The second level bootstrapcode in serial DataFlash.
Serial DataFlash:
Items Offset Comments
Bootstrap code 0x0
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Development Tools
64
a choffset0x00000000 Bootstrap
0x00020000 U-boot
0x00008400 Environments
Application Standalone
0x00200000 Kernel0x00500000 Rootfs (JFFS2)
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Development Tools
65
VII. Software Development Tools
7.1. SAM-BA (phn mm np code).
o Install AT91-ISP v1.13.exe.
o Chp thmc ATMEL Corporation ln thmc C:\Program Files\ ATMELCorporation\ y l bc custom AT91-Board theo thit kca mnh
o Qu trnh ci t SAMBA thnh cng.
Ch : driver ca USB-B ca cc device AT91 ca hng atmel nm trong thmcC:\Program Files\ATMEL Corporation\AT91-ISP v1.13\sam-ba 2.9\drv
7.1.1.1.
Np Bootloader vo board bng SAM-BA.1> Open S7&S8 after pluging the USB cable in the board.
2> Open S5 (if bootstrapcode in AT45DB041D-SU) or Open S6 (if bootstrapcode in
NAND).3> Close S8 to supply the power by the USB-B cable..
4> Installation driver of SAM-BA for the system.
5> Close S5.
6> Running the SAMBAStep 1:select the board and protocol for connection, Click Connect
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Development Tools
Flash the bootloader into serial Dataflash:
Step 2: Chn tab DataFlash AT45DB/DCB, trong list box "script" chn "EnableDataflash (SPI0 CS1)", n nt Execute khi ng AT45DB041D SPI serial dataflash.
Bc 3:Trong list box "script" chn "Send Boot File", n nt Execute, browse nthmc cha AT91BootStrap.bin (nh km theo a CD) v chn file ny. Chng trnhSAMBA stng np AT91BootStrap vo SPI dataflash ti a choffset 0.
Bc 4:Trong text box "Send File Name", n nt browse v trn file u-boot.bin(nh km trong a CD). Trong text box "Address" g vo a ch0x8400. n nt "SendFile" hon tt vic np u-boot vo SPI serial dataflash.
n nt reset v hthng c thboot bnh thng.