artwork, rohs compliant, ml505 virtex-5 lx … · artwork, rohs compliant, ml505 virtex-5 lx...
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01 OF 25 L1_TOPDesigned by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
Oct 04 2006
02 OF 25 L2_PWRDesigned by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
Oct 04 2006
03 OF 25 L3_GNDDesigned by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
Oct 04 2006
04 OF 25 L4_SIGDesigned by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
Oct 04 2006
05 OF 25 L5_SIGDesigned by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
Oct 04 2006
06 OF 25 L6_GNDDesigned by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
Oct 04 2006
07 OF 25 L7_SIGDesigned by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
Oct 04 2006
08 OF 25 L8_SIGDesigned by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
Oct 04 2006
09 OF 25 L9_GNDDesigned by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
Oct 04 2006
10 OF 25 L10_SIGDesigned by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
Oct 04 2006
11 OF 25 L11_PWRDesigned by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
Oct 04 2006
Oct 04 200612 OF 25 L12_GND
Designed by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
Oct 04 200613 OF 25 L13_GND
Designed by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
CLK GEN JTAG
1
DVI
RTSEL
1
TX DISABUSB
1
1
SPDIF
HOSTUSB
Systems Engineering GroupML505-ML509VIRTEX-5
VIDEO IN
10/100/1000 ETHERNET
SFP
1
ENET MODE SEL1
PC4 JTAG
LNK
SFP
USB PERIPH
REV A
SELCLKSATA
1 DIFF CLK IN
1
19 OF 25 SILK-SCREEN TOP
SYSACEPROG
USB ABORT BOOT
FAILSAFESACE1
CFG0
CFG1
CFG2
1
PROGCLK JTAG
1
PS/2MOUSE
PCIE FINGER 1X
P
RSTCPURST
1
N
TRACE/DEBUG
MOD0
MOD1
MOD2
1
KEYB1
LEDSENET
SATA HOST 2
SATA HOST 1
3V3 REG
MOUSE
EN
BCK
FALL
SACE
RXTXDUP
BYP
CHAR LCD
1FAN
TXP
TXN
1
10
1
MGTRXP
RXN
1V0 REG
PS/2
KEYB
1000
100
ERR2
ERR1
FAN
BDM
1
GPI/O
0 1 2
1V8
COM1
1
3
1
COM2
1
4
USR OSCSUPRCLK
SYSMON HDR
LINE OUT
COM1
GPI/O
5 6 7
1
1
SACE
STAT
ERR
AVDD SEL
DONE
INITCONTRAST
PLAT FASH 1
SELCLKOUT
LVDS
HEADPHONE
1
3V3
GNDTCK
TDO
1
TDITMS
INIT
BATT
1
1
LINE IN
SPI PROG
FRONT PANEL AUDIO
MICROPHONE
c
P
DIFF CLK OUT
VCCO_SELN
5V
2006 Xilinx, Incorporated
PIEZO
3V3
1
3V3
W
SOFTOUCH PRO
1V8 REG
1
2V5
S
N
USR CLOCK
GPIO DIP SW
C
ENCODER
GNDPINSDIFF
642V5
OFF
E
SCL
SDA64 GND
LED3
LED0
LED1
LED2
SWS
LEDE
SWE
LEDW
SWW
LEDS
SWN
LEDC
SWC
TDO
TDI
LEDN
TMS
TCK
VCC3V3
VCC5V
XGI
62
64PIN
56
58
60
50
52
54
44
46
48
38
40
42
32
34
36
26
28
30
20
22
24
14
16
18
8
10
12
2
4
6
ON
SW11
SW8
SW10
RP14
Q8
U38
C290
C47
X8
R199
DS41
J4
SW12
DS21
SW2
J7SW1
J5 J6
R96
R95
J12
J28
FB55
C158
C159
C152
R141R140
C156
MH7C399
R63
R62
C415 C66
C58
C317 RP26
RP28
RP25
RP29
RP27
RP30
C67
C318C53
C316
C319
P10
P20
SW13
U6B
C396
CP40
RP50
A27
A1
C294
C315
SP1
R139
C141
J13
TP1
J20
U45
J77
SW14DS23
C395
R85
U8
J16B27
X2
B1
R137
R138
X1
J15
DS22
DS24
DS20
Q9
R78
C295
C276
C275
U3
U1
MH6
RP59
R35 R36
C391
R69R67 C21
C20
C22
J17
C2
RP11
TP10
TP12
TP13
RP58
R38C309
C308
C321
R224R2
20
R221
X3
R222
X4
C23
C162
DS1
DS3
DS4
U4
TP11
R37
C303
C305
FB8
C164
R223
RP9
U22
C157
++
C163
C143
P11P13
DS2
J80CP13
U27
J2CP38
C311
CP130
C375
J54
R157
C416
CP12
R60
R61
C62
C61
C60
C63
RP31
Q12
C43
R83
C41
RP21
J63
C40
FB10
DS5
DS6
U31
U26
R87
J43
C403
U33C244
C260
J70
U13
U37
J51
C42
RP15
R84
C392
C414
R171
FB77
U30
C333
A1
C288
R91
C282
DS13
DS15
DS16
DS17
RP20
R163
RP53
C371
R195
C434R194
J60
DS10
DS11
DS12
DS14
RP54
RP55
C372
X5
FB3
C279 R3
1
U9
J9
R30
J61C1
4FB
2
P12
R151
DS35
DS34
DS33
J11
P22
U23
J19
C205
C206
U29
FB95
R211
Q14
J14FB13
FB12
C46
C45
SW4
DS32
DS31
DS30
J10
J33 J41
2
X7
C398C261
J26
J25
P21
SW7
J32
J45
R52R53R190
P4P5
RP10
J40
37
38
J44
U35
R191
C264RP22C4
17
Q11
FB14
FB11C44
RP35
J8
RP52
J42
CP3
C38 C39
CP1
J62
J24FB30C93
C103
U18
C102
C400
DS40
R173
SW5
J56
J23
J22
C280
J18
FB94
C204
R210
J1J21
RP2SW3
Q13R150
C170
P17
C401
U17
U16
P19
20
1
J3
R80 R79
RP6
R147
R146
R145
C166
P14FB61
C171
P18
P7
J83
J82
J81
FB60
FB40
FB31
R110
P6
P8
U19
C177
+
11
10
Designed by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
Oct 04 2006
15 OF 25 MASK TOPDesigned by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
Oct 04 2006
Designed by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
17 OF 25 PASTE TOPOct 04 2006
P7
R80
R79
RP6R146
R145
C166
R147
FB61
C171
FB40
P6
P8
J3
J83
J81
J82
P14
FB60
P18
FB31
R110
P19
U17
U19
C400
C177
MH8
C401C93
J24
FB30
C103
J23
J22U18
C102
U16
J1
DS40
R173
MH3
J56
J18
FB94
C204
R210
J21
RP2
C170
Q13
R151
R150
P17
SW5
J10
J11
C280
J19
C205 C2
06
U29
FB95
R211
J14Q14
FB13 C4
6C45
P21
SW4 SW7
J33
U23
X7
C261
SW3
FB12
P5
RP10
J41
J40
P22
U35
C398
R52R53
R190
J25
J26
FB14C44
DS35
DS34
DS33
J32
J45
J44
C264
R191CP3
RP22
C417
Q11 Q12
J63
J62
FB11 C43
P4
DS32
DS31
DS30
RP35
J8
RP52
J42
C39
CP1
U13
C38
C41
RP21
C40
R83
FB10
DS5
DS6
R87
J31
J43
U33
C244
C260
MH1
U37
C42
R84
RP15
DS15
DS16
DS17
U26
U31
C403
C414
R171
U30
FB77
C333
C288
J70
R91
J60
J51
DS13
RP20
R163
C392 RP53
C371
R195
R194
C279
C434
C282
J61
P3
DS14
RP54RP55
C372
X5
U9R31
R30
FB3
J9
C2
C14
FB2
DS10
DS11
DS12
U3
MH6
RP59
U1
R35
R69
X3
R67
C20
X4
C22
J17
P12
DS1
DS3
DS4
RP11
TP12
TP13
RP58
R38R3
6 C309
C321
C391
C308
R224
R220
R221
R222
C21
C23
C162
C163
P13
DS2
R86
U4
TP10
TP11
R37
C305
FB8
C303
R223
RP9
C143
J80
CP13
J2CP38
CP130
RP31
C375
B1
J54
J28
C164
C157
R157
U22
P11
C416
R60
CP12
U27
C415
C62
C61
C60
C311
C63
R96
R95
FB55
C159
C156
C152
R141
R140
C158
P10
MH7
C399
R63
R62
R61
C66
C317
C67
C316
J12
J13
J77
SW13
DS23
CP40
RP50
C58
RP26
RP28
J16
RP25
RP29
RP27
RP30
C319
C318
C53
C294
C315
SP1
R139
TP1
P20
U6B
C395
C396
MH2
R85
C295
C141
U45
R137
R138
J20
SW11
SW14
DS22
SW10
DS24
DS20
Q9
U8
X2
U38
C290
C275
C276
X8
X1
J15
RP14
Q8
R78
C47
DS41
R199
SW12
DS21
J7J4
MH4
SW8
SW2
J5
SW1
MH5
J6
B27
B1
++
A27
A1
A1
2
37
38
20
1
+
11
10
Designed by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
22 OF 25 ASSY_TOPOct 04 2006
CLK GEN JTAG
1
DVI
RTSEL
1
TX DISABUSB
1
1
SPDIF
HOSTUSB
Systems Engineering GroupML505-ML509VIRTEX-5
VIDEO IN
10/100/1000 ETHERNET
SFP
1
ENET MODE SEL1
PC4 JTAG
LNK
SFP
USB PERIPH
REV A
SELCLKSATA
1 DIFF CLK IN
1
19 OF 25 SILK-SCREEN TOP
SYSACEPROG
USB ABORT BOOT
FAILSAFESACE1
CFG0
CFG1
CFG2
1
PROGCLK JTAG
1
PS/2MOUSE
PCIE FINGER 1X
P
RSTCPURST
1
N
TRACE/DEBUG
MOD0
MOD1
MOD2
1
KEYB1
LEDSENET
SATA HOST 2
SATA HOST 1
3V3 REG
MOUSE
EN
BCK
FALL
SACE
RXTXDUP
BYP
CHAR LCD
1FAN
TXP
TXN
1
10
1
MGTRXP
RXN
1V0 REG
PS/2
KEYB
1000
100
ERR2
ERR1
FAN
BDM
1
GPI/O
0 1 2
1V8
COM1
1
3
1
COM2
1
4
USR OSCSUPRCLK
SYSMON HDR
LINE OUT
COM1
GPI/O
5 6 7
1
1
SACE
STAT
ERR
AVDD SEL
DONE
INITCONTRAST
PLAT FASH 1
SELCLKOUT
LVDS
HEADPHONE
1
3V3
GNDTCK
TDO
1
TDITMS
INIT
BATT
1
1
LINE IN
SPI PROG
FRONT PANEL AUDIO
MICROPHONE
c
P
DIFF CLK OUT
VCCO_SELN
5V
2006 Xilinx, Incorporated
PIEZO
3V3
1
3V3
W
SOFTOUCH PRO
1V8 REG
1
2V5
S
N
USR CLOCK
GPIO DIP SW
C
ENCODER
GNDPINSDIFF
642V5
OFF
E
SCL
SDA64 GND
LED3
LED0
LED1
LED2
SWS
LEDE
SWE
LEDW
SWW
LEDS
SWN
LEDC
SWC
TDO
TDI
LEDN
TMS
TCK
VCC3V3
VCC5V
XGI
62
64PIN
56
58
60
50
52
54
44
46
48
38
40
42
32
34
36
26
28
30
20
22
24
14
16
18
8
10
12
2
4
6
ON
SW11
SW8
SW10
RP14
Q8
U38
C290
C47
X8
R199
DS41
J4
SW12
DS21
SW2
J7SW1
J5 J6
R96
R95
J12
J28
FB55
C158
C159
C152
R141R140
C156
MH7C399
R63
R62
C415 C66
C58
C317 RP26
RP28
RP25
RP29
RP27
RP30
C67
C318C53
C316
C319
P10
P20
SW13
U6B
C396
CP40
RP50
A27
A1
C294
C315
SP1
R139
C141
J13
TP1
J20
U45
J77
SW14DS23
C395
R85
U8
J16B27
X2
B1
R137
R138
X1
J15
DS22
DS24
DS20
Q9
R78
C295
C276
C275
U3
U1
MH6
RP59
R35 R36
C391
R69R67 C21
C20
C22
J17
C2
RP11
TP10
TP12
TP13
RP58
R38C309
C308
C321
R224R2
20
R221
X3
R222
X4
C23
C162
DS1
DS3
DS4
U4
TP11
R37
C303
C305
FB8
C164
R223
RP9
U22
C157
++
C163
C143
P11P13
DS2
J80CP13
U27
J2CP38
C311
CP130
C375
J54
R157
C416
CP12
R60
R61
C62
C61
C60
C63
RP31
Q12
C43
R83
C41
RP21
J63
C40
FB10
DS5
DS6
U31
U26
R87
J43
C403
U33C244
C260
J70
U13
U37
J51
C42
RP15
R84
C392
C414
R171
FB77
U30
C333
A1
C288
R91
C282
DS13
DS15
DS16
DS17
RP20
R163
RP53
C371
R195
C434R194
J60
DS10
DS11
DS12
DS14
RP54
RP55
C372
X5
FB3
C279 R3
1
U9
J9
R30
J61C1
4FB
2
P12
R151
DS35
DS34
DS33
J11
P22
U23
J19
C205
C206
U29
FB95
R211
Q14
J14FB13
FB12
C46
C45
SW4
DS32
DS31
DS30
J10
J33 J41
2
X7
C398C261
J26
J25
P21
SW7
J32
J45
R52R53R190
P4P5
RP10
J40
37
38
J44
U35
R191
C264RP22C4
17
Q11
FB14
FB11C44
RP35
J8
RP52
J42
CP3
C38 C39
CP1
J62
J24FB30C93
C103
U18
C102
C400
DS40
R173
SW5
J56
J23
J22
C280
J18
FB94
C204
R210
J1J21
RP2SW3
Q13R150
C170
P17
C401
U17
U16
P19
20
1
J3
R80 R79
RP6
R147
R146
R145
C166
P14FB61
C171
P18
P7
J83
J82
J81
FB60
FB40
FB31
R110
P6
P8
U19
C177
+
11
10
Designed by XilinxLAYER:
ARTWORK, ROHS COMPLIANT, ML505 VIRTEX-5 LX EVALUATION PLATFORM, 1280415ARTMASTER # 0531630
22 OF 25 ASSY_TOPOct 04 2006