virtex-4 lx 100 prtoboard

OPERATIONAL MANUAL

FOR

VIRTEX-4 PROTOBOARD MODEL : MX4VFK-LX100

Rev : 001

MECHATRONICS TEST EQUIPMENT (I)PVT.LTD. B-3,MAYUR COMPLEX, OPP. BHELKE NAGAR,

NEAR YASHAVANTRAO CHAVAN NATYAGRUH, KOTHRUD, PUNE- 411038

PHONE : +91-20-25386926/ 29 FAX : +91-20-25464046 EMAIL : [email protected] URL : www.mte-india.com

LIST OF FIGURES

Figure 1: Block Diagram............................................................................................................... 3 Figure 2: FPGA – SDRAM Interface ............................................................................................ 5 Figure 3: FPGA –SRAM Interface ................................................................................................ 8 Figure 4: FPGA – USB Interface ................................................................................................ 13 Figure 5: FPGA – RS232 Interface ............................................................................................ 16 Figure 6: FPGA – RS422 Interface ............................................................................................ 17 Figure 7: PS/2 Connector........................................................................................................... 18 Figure 8: PS/2 Timing Diagram.................................................................................................. 19 Figure 9: PS/2 Keyboard with scan codes ................................................................................. 19 Figure 10: Data format for PS/2 mouse interface....................................................................... 21 Figure 11: Seven Segment Display............................................................................................ 23 Figure 12: FPGA –VGA Interface............................................................................................... 25 Figure 13: CRT Display Timing .................................................................................................. 27 Figure 14: VGA Timing............................................................................................................... 28 Figure 15: LCD Interface to VIRTEX-4 FPGA ............................................................................ 29 Figure 16: LAN 91C111 Interface to VIRTEX-4 FPGA............................................................... 31 Figure 17: JTAG Mode Selection ............................................................................................... 41 Figure 18: JTAG Mode Selection Jumper .................................................................................. 42

LIST OF TABLES Table 1: Address Bus Interface to VIRTEX-4 FPGA .................................................................... 6 Table 2: Bank Address Selection Interface to VIRTEX-4 FPGA .................................................. 6 Table 3: Data Bus Interface to VIRTEX-4 FPGA.......................................................................... 6 Table 4: Data Bus Interface to VIRTEX-4 FPGA.......................................................................... 7 Table 5: Control Lines Interface to VIRTEX-4 FPGA ................................................................... 7 Table 6: Pin Description for Flash Interface ................................................................................. 9 Table 7: Interface Details for SRAM1 And SRAM2 ...................................................................... 9 Table 8: Interface Details for SRAM 3 and SRAM-4 .................................................................. 11 Table 9: Data Bus Interface to VIRTEX-4 FPGA........................................................................ 14 Table 10: Control Lines Interface to VIRTEX-4 FPGA ............................................................... 14 Table 11: RS232 Interface to VIRTEX-4 FPGA ......................................................................... 16 Table 12: RS422 Interface to VIRTEX-4 FPGA ......................................................................... 17 Table 13: PS/2 Connector Details .............................................................................................. 18 Table 14: PS/2 Bus Timing......................................................................................................... 18 Table 15: Common PS/2 Keyboard Commands ........................................................................ 20 Table 16: LED Status ................................................................................................................. 20 Table 17: PS/2 Interface to VIRTEX-4 FPGA............................................................................. 21 Table 18: DIP switch Interface to VIRTEX-4 FPGA ................................................................... 22 Table 19: KEY switch Interface to VIRTEX-4 FPGA .................................................................. 22 Table 20: LED Interface to VIRTEX-4 FPGA ............................................................................. 22 Table 21: Seven Segment Display Interface to VIRTEX-4 FPGA .............................................. 24 Table 22: VGA Interface to VIRTEX-4 FPGA............................................................................. 26 Table 23: VGA signal timing....................................................................................................... 28 Table 24: Data Line Interface to VIRTEX-4 FPGA ..................................................................... 30 Table 25: Control Line Interface to VIRTEX-4 FPGA ................................................................. 30 Table 26: Address Bus Interface to VIRTEX-4 FPGA ................................................................ 32 Table 27: Data Bus Interface to VIRTEX-4 FPGA...................................................................... 32 Table 28: Synchronous Bus Interface to VIRTEX-4 FPGA ........................................................ 33 Table 29: Asynchronous Bus Interface to VIRTEX-4 FPGA ...................................................... 34 Table 30: Miscellaneous Signals Interface to VIRTEX-4 FPGA................................................. 34 Table 31: IO Connector Interface to FPGA ................................................................................ 35 Table 32: IO Connector Interface to FPGA ................................................................................ 36 Table 33: Stackable Connector Interface to FPGA .................................................................... 37 Table 34: IO Clock-Reset Interface to FPGA ............................................................................. 39 Table 35: Mode Selection Jumper Settings................................................................................ 40 Table 36: Mode Selection Table................................................................................................. 40 Table 37: Power Supply Details ................................................................................................. 43

TABLE OF CONTENTS

PREFACE .................................................................................................................................... 1 About This Manual .....................................................................................................................1

Manual Contents ....................................................................................................................................1

CHAPTER 1 ................................................................................................................................. 2 Introduction ................................................................................................................................2

Features .................................................................................................................................................2

CHAPTER 2 ................................................................................................................................. 5 High Speed Synchronous SDRAM ............................................................................................5

2.1 Address Bus Connection..................................................................................................................5 2.2 Bank Address Selection ...................................................................................................................6 2.3 Data Bus Connection .......................................................................................................................6 2.4 Data Mask Lines Connection ...........................................................................................................7 2.5 Control Lines Connection.................................................................................................................7

CHAPTER 3 ................................................................................................................................. 8 SRAM Interface..........................................................................................................................8

CHAPTER 4 ............................................................................................................................... 13 USB Interface...........................................................................................................................13

4.1 Data Bus Connection .................................................................................................................... 14 4.2 Control Lines: ................................................................................................................................ 14 4.3. FTDI Driver Installation ................................................................................................................ 14

CHAPTER 5 ............................................................................................................................... 16 Serial Interface.........................................................................................................................16

5.1 RS- 232 Interface .......................................................................................................................... 16 5.2 RS- 422 Interface .......................................................................................................................... 17

CHAPTER 6 ............................................................................................................................... 18 PS/2 Mouse/Keyboard Interface ..............................................................................................18

6.1 PS/2 KEYBOARD.......................................................................................................................... 19 6.2 PS/2 Mouse................................................................................................................................... 20 6.3 Control Signal Connection ............................................................................................................ 21

CHAPTER 7 ............................................................................................................................... 22 Switches And LEDs .................................................................................................................22

7.1 DIP Switches ................................................................................................................................. 22 7.2 Key Switches................................................................................................................................. 22 7.3 LEDS ............................................................................................................................................. 22

CHAPTER 8 ............................................................................................................................... 23 Seven Segment LED Display...................................................................................................23

CHAPTER 9 ............................................................................................................................... 25 VGA Interface ..........................................................................................................................25

9.1 VGA Display Theory...................................................................................................................... 26 9.2 VGA signal TIMING....................................................................................................................... 28

CHAPTER 10 ............................................................................................................................. 29 LCD Interface...........................................................................................................................29

10.1 Data Lines Connection................................................................................................................ 29 10.2 Control Line Interface:................................................................................................................. 30

CHAPTER 11 ............................................................................................................................. 31 10/100 Non PCI Ethernet Interface..........................................................................................31

11.1 System Address Bus Connection................................................................................................ 32 11.2 System Data Bus Connection ..................................................................................................... 32 11.3 Control Signals Connection......................................................................................................... 33

CHAPTER 12 ............................................................................................................................. 35 Connector Details ....................................................................................................................35

12.1 IO Connectors ............................................................................................................................. 35 12.3 Stackable Connector................................................................................................................... 37

CHAPTER 13 ............................................................................................................................. 39 Clock and Reset Sources ........................................................................................................39

CHAPTER 14 ............................................................................................................................. 40 VIRTEX-4 Configuration Details...............................................................................................40

14.1 Boundary Scan mode:................................................................................................................. 40 14.2 Master Serial Mode ..................................................................................................................... 40 14.3 Jumper Setting ............................................................................................................................ 40

CHAPTER 15 ............................................................................................................................. 43 Power Supplies ........................................................................................................................43

15.1 Voltage Regulators...................................................................................................................... 43

APPENDIX A ............................................................................................................................. 44 Operating Instruction To Start A New Design ..........................................................................44

A.1 Starting The ISE Software: ........................................................................................................... 44 A.2 Design Flow .................................................................................................................................. 44 A.3 Design Description........................................................................................................................ 45 A.4 Truth Table of Half adder: -........................................................................................................... 45 A.5 VHDL Code for Half adder............................................................................................................ 45 A.6 Steps to implement the Half adder in the FPGA using Xilinx iSE(8.1i) ........................................ 46

APPENDIX B ............................................................................................................................. 60 ADC–DAC Add On Card..........................................................................................................60

APPENDIX C ............................................................................................................................. 66 ASCII Table 5 X 7 LCD Display ...............................................................................................66

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PREFACE

About This Manual

This manual gives operational details for all the interfaces.

Manual Contents This manual contains following chapters: • Chapter 1, “Introduction” • Chapter 2, “High Speed Synchronous SDRAM ” • Chapter 3, “ SRAM Interface” • Chapter 4, “USB Interface” • Chapter 5, “Serial Interface” • Chapter 6, “PS/2 Interface” • Chapter 7, “Switches And LEDs” • Chapter 8, “Seven Segment LED Display” • Chapter 9, “VGA Interface” • Chapter 10, “LCD Interface” • Chapter 11, “10/100 Non PCI Ethernet Interface” • Chapter 12, “Connector Details” • Chapter 13, “Clock And Reset Sources” • Chapter 14, “VIRTEX-4 Configuration Details” • Chapter 15, “Power Supplies” • Appendix A Operating Instruction to Start a New Design • Appendix B ADC – DAC Add On Card. • Appendix C ASCII Table 5 X 7 LCD Display

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CHAPTER 1

Introduction

VIRTEX-4 Development Board (MX4VFK-LX100) provides an easy to use development platform for realizing various designs around VIRTEX-4 FPGA.

Features Figure 1 shows the VIRTEX-4 Development Board, which includes the following components and features: • VIRTEX-4 FPGA: 100K. Logic cells VIRTEX-4 FPGA in FF1148 in Ball Grid Array package

(XC4VLX100). o Three families LX/SX/FX o Xesium™ Clock Technology o XtremeDSP™ Slice

18x18, two’s complement, signed Multiplier Optional pipeline stages Built-In Accumulator (48-bits) & Adder/Subtracter

o Smart RAM Memory Hierarchy Distributed RAM Dual-Port 18-Kbit RAM blocks Optional pipeline stages High-speed memory interface support: DDR and DDR-2 SDRAM, QDR-II, RLDRAM-II, and FCRAM-II

o SelectIO Technology 1.5 to 3.3 V I/O Operation Built-In ChipSync™ Source-Synchronous Technology Digitally-controlled impedance (DCI) active termination Fine grained I/O banking (Configuration in one bank) Flexible Logic Resources

o Secure Chip AES Bitstream Encryption o RocketIO™ 622 Mb/s to 11.1 Gb/s Multi-Gigabit Transceivers (MGT) (FX only) o IBM PowerPC RISC Processor Core (FX only) o PowerPC 405 (PPC405) Core o Auxiliary Processor Unit Interface (User Coprocessor) o Multiple Tri-Mode Ethernet MACs (FX only)

• Platform Flash: 16 Mbit Xilinx XCF 32P in-system configurable platform flash for configuration through PROM in VO 48 package. 1.8V supply voltage Serial or parallel FPGA configuration interface (up to 33 MHz) Available in small-footprint VO48, VOG48, FS48, and FSG48 packages Design revision technology enables storing and accessing multiple design revisions for

configuration. Built-in data decompressor compatible with Xilinx advanced compression technology

• SDRAM : 4 Meg x 32 Micron SDRAM MT48LC4M32B2 as a high speed synchronous memory interface in TSOP-86 package PC100 functionality Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8, or full page Auto Precharge, includes concurrent Auto precharge, and Auto Refresh Modes Self Refresh Mode 64ms, 4,096-cycle refresh (15.6µs/row) LVTTL-compatible inputs and outputs Single +3.3V ±0.3V power supply

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Supports CAS latency of 1, 2, and 3

Figure 1: Block Diagram

• USB Controller: Cost effective, easy to use USB FIFO IC FT245BM from FTDI in LQFP-32

package to transfer data to / from FPGA and host PC at upto 1Mbyte per second. Single Chip USB ó Parallel FIFO bi-directional Data Transfer Transfer Data rate to 1M Byte / Sec - D2XX Drivers

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Transfer Data rate to 300 Kilobyte / Sec - VCP Drivers Simple to interface to MCU / PLD/ FPGA logic with a 4 wire handshake interface Entire USB protocol handled on-chip, no USB-specific firmware programming required 384 Byte FIFO Tx buffer / 128 Byte FIFO Rx Buffer for high data throughput. Integrated 3.3V regulator for USB IO Integrated Power-On-Reset circuit Integrated 6MHz – 48MHz clock multiplier PLL USB Bulk or Isochronous data transfer modes

• SRAM Interface: Four 256K x 16 bits SRAM using IS61LV25616AL from ISSI with access time of 12ns are provided in banked fashion with individual address and data bus..

• Ethernet Controller: 10/100 Non PCI single chip Ethernet controller LAN 91c111 from SMSC in QFP package. Supports full duplex switched Ethernet. Supports burst transfer. 8 Kbytes of internal memory for receive and transmit FIFO buffers. Optional configuration through serial EEPROM Supports 8, 16, 32 bit CPU accesses. Single 25 MHz Clock for both PHY and MAC. Fully integrated IEEE 802.3 / 802.3 u -100 Base –TX/ 10 Base-T physical layer.

• VGA display Port: 12 bit, 512 colours VGA display port.

• RS232 Serial Interface: 9 pin two channel serial interfaces. DB9 9-pin female connector (DCE connector) RS-232 transceiver/level translator using MAX3223 in SSOP package. Uses straight-through serial cable to connect to computer or workstation serial port.

• RS422 Serial Interface: 10 pin two channel serial interfaces. 10 pin berg connector. RS-422 dual differential drivers and receivers SN65C118 in TSSOP package

• PS/2 Interface: PS/2-style mouse and keyboard port.

• Seven Segment Display: Six -character, seven-segment LED display.

• DIP Switches: Eight DIP switches.

• LEDs: 13 onboard LEDS 8 user LEDs (RED) Single configuration status LED (GREEN) 4 Power on indicator LEDs(RED)

• Push Button Switches: Four momentary-contact push button switches.

• LCD interface: 16 character 2 row LCD.

• Mictor Connector: Facilitates provision for Logic Analyzer interface.

• Stackable Connector: Facilitates provision for interface of ADD ON Boards

• Free IOs: On Board 133 free IOs.

• Clock Oscillator: 40 MHz crystal clock oscillator. Socket for an auxiliary crystal oscillator clock source.

• JTAG port: 10 Pin FRC male connector for JTAG download cable (parallel III) interface that connects to the parallel port of host PC.

• Power Supplies: 5 volts regulated power supply provided along with the board.

On board 3.3V, 2.5V, 1.8V, 1.2 V regulators. On board generation of -5V supply.

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CHAPTER 2

High Speed Synchronous SDRAM

VIRTEX-4 Development Board has a single 4 M x 32 bit high speed synchronous SDRAM (MT48LC4M32B2), surface mounted on top side of the board. A detailed interface is as shown in Figure 2.

Figure 2: FPGA – SDRAM Interface

This SDRAM is internally configured as quad bank DRAM with synchronous interface (all signals registered on positive clock edge). The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.

2.1 Address Bus Connection • SDRAM has a 12 bit address bus interface with FPGA. • A0–A11 are sampled during the ACTIVE command (row-address A0–A10) and

READ/WRITE command (column-address A0–A8 with A10 defining auto precharge) to

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select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 [HIGH]) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command.

Table 1: Address Bus Interface to VIRTEX-4 FPGA

Address Bit FPGA Pin

“A0_S1” R6

“A1_S1” P5

“A2_S1” W5

“A3_S1” M5

“A4_S1” M6

“A5_S1” L5

“A6_S1” L6

“A7_S1” K6

“A8_S1” J5

“A9_S1” J6

“A10_S1” V5

“A11_S1” T6

2.2 Bank Address Selection Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

Table 2: Bank Address Selection Interface to VIRTEX-4 FPGA

Bank Address Selection Bit FPGA Pin

“BA0_S1” U6

“BA1_S1” U5

2.3 Data Bus Connection 32 bit bidirectional data bus interface.

Table 3: Data Bus Interface to VIRTEX-4 FPGA

Data Bit FPGA Pin Data Bit FPGA Pin

“D0_S1” R4 "D16_S1" AE4

"D1_S1" R3 "D17_S1" AE3

"D2_S1" T4 "D18_S1" AD4

"D3_S1" T3 "D19_S1" AC4

"D4_S1" U3 "D20_S1" AC3

"D5_S1" V3 "D21_S1" AB3

"D6_S1" V4 "D22_S1" AA4

7


"D7_S1" Y3 "D23_S1" AA3

"D8_S1" K4 "D24_S1" J4

"D9_S1" K3 "D25_S1" H3

"D10_S1" L4 "D26_S1" H4

"D11_S1" L3 "D27_S1" G3

"D12_S1" M3 "D28_S1" F3

"D13_S1" N4 "D29_S1" F4

"D14_S1" N3 "D30_S1" E3

"D15_S1" P4 "D31_S1" E4

2.4 Data Mask Lines Connection DQM is sampled high and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two clock latency) during a READ cycle. DQM0 corresponds to DQ0–DQ7, DQM1 corresponds to DQ8-DQ15, DQM2 corresponds to DQ16–DQ23 and DQM3 corresponds to DQ24–DQ31. DQM0–DQM3 is considered same state when referenced as DQM.



“DQM0_S1” AA6 “DQM2_S1” P6

“DQM1_S1” G6 “DQM3_S1” N5

2.5 Control Lines Connection • Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the

positive edge of CLK. • CKE activates (HIGH) and deactivates (LOW) the CLK signal. • CS# enables (registered LOW) and disables (registered HIGH) the command decoder. • Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the command.

Table 5: Control Lines Interface to VIRTEX-4 FPGA

Control Bit FPGA Pin Control Bit FPGA Pin

"WE#_S1" AA5 "CLK_S1" G5

“RAS#_S1” W6 "CKE_S1" H5

"CAS#_S1" Y6 "CS#_S1" T5

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CHAPTER 3

SRAM Interface

VIRTEX-4 board is rich in memory interface with four 256K X 16 SRAMs from ISSI.

The ISSI IS61LV25616AL is a high-speed, 4,194,304-bit static RAM organized as 262,144 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices.

All Four SRAMs have individual address and data bus interface.. Chip select signal CE is used to select a particular SRAM. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels.

Figure 3: FPGA –SRAM Interface

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Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. Active low write enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The interface details for the SRAM interface are as described below:

Table 6: Pin Description for Flash Interface

Name Pin Description

A0-A20 Address input during read and write operation

I/O 0- I/O 15 Data Input output pins.

CE# Chip Enable Input

OE# Output Enable Input

WE# Write Enable Input

LB# Lower Byte Control

UB# Upper Byte Control

Interface details of all four SRAMs that with VIRTEX-4 FPGA are as follows:

Table 7: Interface Details for SRAM1 And SRAM2

SRAM1

Data Line Interface:

DataBit FPGAPin DataBit FPGAPin

"SRAM1_D0" P2 “SRAM1_D8" Y8

"SRAM1_D1" P1 "SRAM1_D9" W7

"SRAM1_D2" R2 “SRAM1_D10" Y7

"SRAM1_D3" R1 “SRAM1_D11" V7

"SRAM1_D4" T1 "SRAM1_D12" U7

"SRAM1_D5" U2 "SRAM1_D13" T8

"SRAM1_D6" U1 "SRAM1_D14" U8

"SRAM1_D7" W1 "SRAM1_D15" R7

Address Line Interface:

Address Bit FPGA Pin Address Bit FPGA Pin

"SRAM1_A0" H2 "SRAM1_A9" AC2

"SRAM1_A1" K1 "SRAM1_A10" AB1

"SRAM1_A2" M2 "SRAM1_A11" Y2

"SRAM1_A3" K2 "SRAM1_A12" AD1

"SRAM1_A4" L1 "SRAM1_A13" AA1

"SRAM1_A5" V8 "SRAM1_A14" AE1

"SRAM1_A6" M1 "SRAM1_A15" Y1

"SRAM1_A7" AB2 "SRAM1_A16" V2

"SRAM1_A8" AD2 "SRAM1_A17" AE2

10

Control Line Interface:


"SRAM1_\CE\" N2 "SRAM1_\UB\" AA8

"SRAM1_\LB\" AB5 "SRAM1_\WE\" W2

"SRAM1_\OE\" AB6

SRAM2

Data Line Interface: Data Bit FPGA Pin Data Bit FPGA Pin

"SRAM2_D0" U30 "SRAM2_D8" N30

"SRAM2_D1" R33 "SRAM2_D9" N29

"SRAM2_D2" P34 "SRAM2_D10" M28

"SRAM2_D3" R34 "SRAM2_D11" M27

"SRAM2_D4" T33 "SRAM2_D12" L28

"SRAM2_D5" U33 "SRAM2_D13" K27

"SRAM2_D6" T34 "SRAM2_D14" M30

"SRAM2_D7" W31 "SRAM2_D15" L30

Address Line Interface


"SRAM2_A0" R29 "SRAM2_A9" L33

"SRAM2_A1" T29 "SRAM2_A10" L34

"SRAM2_A2" T30 "SRAM2_A11" M33

"SRAM2_A3" R27 "SRAM2_A12" N33

"SRAM2_A4" T28 "SRAM2_A13" J27

"SRAM2_A5" R28 "SRAM2_A14" AB32

"SRAM2_A6" U27 "SRAM2_A15" K28

"SRAM2_A7" U28 "SRAM2_A16" AA31

"SRAM2_A8" R29 "SRAM2_A17" Y32



"SRAM2_\CE\" N34 "SRAM2_\UB\" N27

"SRAM2_\LB\" P29 "SRAM2_\WE\" Y31

"SRAM2_\OE\" P30

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Table 8: Interface Details for SRAM 3 and SRAM-4

SRAM3

DataLineInterface:

DataBit FPGAPin DataBit FPGAPin

"SRAM3_D0" E16 "SRAM3_D8" H8

"SRAM3_D1" F16 "SRAM3_D9" H9

"SRAM3_D2" E14 "SRAM3_D10" G8


"SRAM3_D4" F13 "SRAM3_D12" G11


"SRAM3_D6" E12 "SRAM3_D14" H12

"SRAM3_D7" F11 "SRAM3_D15" H13



"SRAM3_A0" L8 "SRAM3_A9" G16

"SRAM3_A1" M7 "SRAM3_A10" F6

"SRAM3_A2" P7 "SRAM3_A11" F8

"SRAM3_A3" M8 "SRAM3_A12" G17

"SRAM3_A4" N7 "SRAM3_A13" E9

"SRAM3_A5" K8 "SRAM3_A14" G15

"SRAM3_A6" R8 "SRAM3_A15" E6

"SRAM3_A7" F14 "SRAM3_A16" G12

"SRAM3_A8" H14 "SRAM3_A17" H10



"SRAM3_\CE\" E17 "SRAM3_\UB\" G7

"SRAM3_\LB\" H7 "SRAM3_\WE\" F10

"SRAM3_\OE\" J7

SRAM4

Data Line Interface


"SRAM4_D0" U31 "SRAM4_D8" J32

"SRAM4_D1" T31 "SRAM4_D9" G32

"SRAM4_D2" G18 "SRAM4_D10" H32

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"SRAM4_D3" H18 “SRAM4_D11" F31

"SRAM4_D4" H20 “SRAM4_D12" E32

"SRAM4_D5" H22 “SRAM4_D13" D32

"SRAM4_D6" G21 "SRAM4_D14" E31

"SRAM4_D7" G23 "SRAM4_D15" D31


AddressBit FPGAPin AddressBit FPGAPin

"SRAM4_A0" N32 "SRAM4_A9" H28

"SRAM4_A1" P32 "SRAM4_A10" G28

"SRAM4_A2" R32 "SRAM4_A11" H25

"SRAM4_A3" M32 "SRAM4_A12" J30

"SRAM4_A4" P31 "SRAM4_A13" H27

"SRAM4_A5" G31 "SRAM4_A14" L29

"SRAM4_A6" R31 "SRAM4_A15" G27

"SRAM4_A7" U32 "SRAM4_A16" H19

"SRAM4_A8" K29 "SRAM4_A17" C32



"SRAM4_\CE\" H24 "SRAM4_\UB\" L31

"SRAM4_\LB\" K32 "SRAM4_\WE\" G25

"SRAM4_\OE\" M31

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CHAPTER 4

USB Interface

VIRTEX-4 Board has a USB interface using device FT245BM from FTDI. It offers data transfer rates up to 8 Million bits (1 Megabyte) per second. To send data from the FPGA to the host computer, simply write the byte-wide data into the module when TXE# is low. If the (384-byte) transmit buffer fills up or is busy storing the previously written byte, the device keeps TXE# high in order to stop further data from being written until some of the FIFO data has been transferred over USB to the host. TXE# goes high after every byte written. When the host sends data to the FPGA over USB, the device will take RXF# low to let the FPGA know that at least one byte of data is available. The FPGA can read a data byte every time RXF# goes low. RXF# goes high after every byte read. FTDI chip supports two drivers: • VCP Drivers • D2xx Drivers VIRTEX-4 board uses D2xx Drivers that allow application software to access the device “directly” through a published DLL based API. For more details on Drivers visit http://www.ftdichip.com

Figure 4: FPGA – USB Interface

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4.1 Data Bus Connection 8 bit bidirectional data bus for data transfer from / to FPGA and USB interface.


Data Bit FPGA Pin

"USB_D0" B26

"USB_D1" A26

"USB_D2" B25

"USB_D3" A25

"USB_D4" A24

"USB_D5" B23

"USB_D6" A23

"USB_D7" B22

4.2 Control Lines: Control group interface consist of following signals: • RD #: Enables reading of data byte from USB controller on data line interface when low. • WR#: Writes data byte from D0-D7 into the transmit FIFO of USB. • TXE #: Data write enable. • RXF #: Data read enable.

Table 10: Control Lines Interface to VIRTEX-4 FPGA

Control Bit FPGA Pin

"TXE#" B20

"WR#" A21

"RD#" B21

"RXF#" A20

4.3. FTDI Driver Installation • To install the FTDI drivers on your PC simply run the FTDI_Setup.exe file provided in the

CD accompanied with your Development board. • After successful installation following message will be displayed on screen

15

• After installation when USB device plugged in Device Manager will add USB Serial Converter controller into its USB Serial Bus Controller list as shown below:

• When USB device plugged in Device Manager will add USB Serial Converter

controller into its USB Serial Bus Controller list as shown below

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CHAPTER 5

Serial Interface

The VIRTEX-4 development board supports RS-232 and RS-422 (differential) serial interface. Details of both interface is described below.

5.1 RS- 232 Interface The RS-232 transmit and receive signals appear on the female DB9 connector, indicated as in Figure 5. The connector is a DCE-style port and connects to the DB9 DTE-style serial port connector available on most personal computers and workstations. Use a standard straight-through serial cable to connect the VIRTEX-4 development board to the PC’s serial port.

Figure 5: FPGA – RS232 Interface

Figure 5 shows the connection between the FPGA and the DB9 connector, including the Maxim MAX3223 RS-232 voltage converter. The FPGA supplies serial output data as LVTTL or LVCMOS levels to the Maxim device, which in turn, converts the logic value to the appropriate RS-232 voltage level. Likewise, the Maxim device converts the RS-232 serial input data to LVTTL levels for the FPGA. Hardware flow control is not supported on the connector. The port’s DCD, DTR, and DSR signals are left unconnected. Similarly, the port’s CTS and Ring Indicator are used as an auxiliary RS232 channel signals The FPGA connections to the Maxim RS-232 translator appear in Table 11.

Table 11: RS232 Interface to VIRTEX-4 FPGA


“TXD1-F” AG1

“TXD2-F” AF1

“RXD1-F” AG2

“RXD2-F” AH2

For more details on RS232 UART application please refer the following application note AN2141 from Maxim.

17

5.2 RS- 422 Interface Two – RS422 compatible transmit and receive channels are provided on board using SN65C1168 a dual differential driver and receiver. External connectivity is provided using 10-pin Berg connector for transmitter as well as receiver.

Figure 6: FPGA – RS422 Interface

Figure 6 shows the connection between the FPGA and the 10 pin external connector. The FPGA supplies serial output data as LVTTL or LVCMOS levels to the SN65C118.device. SN65C118.is a dual differential driver and receiver that converts the logic value to the appropriate RS-422 voltage level and vice versa. The FPGA connections to RS-422 dual differential transmitter/receiver appear as in Table 12.

Table 12: RS422 Interface to VIRTEX-4 FPGA


“TTL_IN1_QS” D7

“TTL_IN2_QS” C7

“TTL_OUT1_QS” D6

“TTL_OUT2_QS” C5

18

CHAPTER 6

PS/2 Mouse/Keyboard Interface

VIRTEX-4 development board includes a separate PS/2 port for mouse or keyboard interface using a standard 6 pin PS/2 connector as shown in figure 7.

Figure 7: PS/2 Connector

Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a host device, the VIRTEX-4 FPGA in this case. The PS/2 bus includes both clock and data. Both a mouse and keyboard drive the bus with identical signal timings and both use 11-bit words that include a start, stop and odd parity bit. However, the data packets are organized differently for a mouse and keyboard. Furthermore, the keyboard interface allows bidirectional data transfers.

Table 13: PS/2 Connector Details

PS/2 Connector Pin Signal

1 DATA(PS2D)

2 Reserved

3 GND

4 Voltage Supply

5 CLK(PS2C)

6 Reserved

The PS/2 bus timing appears Table 14 and Figure 8. The clock and data signals are only driven when data transfers occur, and otherwise they are held in the idle state at logic High. The timings define signal requirements for mouse-to-host communications and bidirectional keyboard communications. As shown in Figure 9, the attached keyboard or mouse writes a bit on the data line when the clock signal is high, and the host reads the data line when the clock signal is low.

Table 14: PS/2 Bus Timing

Symbol Parameter Min Max

TCK Clock high or low time 30µs 50µs

TSU Data to clock setup time 5µs 25µs

THLD Clock to data hold time 5µs 25µs

19

Figure 8: PS/2 Timing Diagram

6.1 PS/2 KEYBOARD The keyboard uses open-collector drivers so that either the keyboard or the host can drive the two-wire bus. If the host never sends data to the keyboard, then the host can use simple input pins. A PS/2-style keyboard uses scan codes to communicate key press data. Nearly all keyboards in use today are PS/2 style. Each key has a single, unique scan code that is sent whenever the corresponding key is pressed. The scan codes for most keys appear in Figure 9.

Figure 9: PS/2 Keyboard with scan codes

20

Some keys, called extended keys, send an “E0” ahead of the scan code and furthermore, they may send more than one scan code. When an extended key is released, a “E0 F0” key up code is sent, followed by the scan code. If the key is pressed and held, the keyboard repeatedly sends the scan code every 100 ms or so. When a key is released, the keyboard sends a “F0” key-up code, followed by the scan code of the released key. The keyboard sends the same scan code, regardless if a key has different “shift” and “non-shift” characters and regardless whether the Shift key is pressed or not. The host determines which character is intended. The most commonly used commands for PS/2 keyboard are as follows:

Table 15: Common PS/2 Keyboard Commands

Command Description

ED

Turn on/off Num Lock, Caps Lock, and Scroll Lock LEDs. The keyboard acknowledges receipt of an “ED” command by replying with an “FA”, after which the host sends another byte to set LED status. The bit positions for the keyboard LEDs appear in Table 16. Write a ‘1’ to the specific bit to illuminate the associated keyboard LED.

EE Upon receiving an echo command, the keyboard replies with the same scan code “EE”.

FE Resend. Upon receiving a resend command, the keyboard resends the last scan code sent.

FF Reset. Resets the keyboard.

F3 Set scan code repeat rate. The keyboard acknowledges receipt of an “F3” by returning an “FA” after which the host sends a second byte to set the repeat rate.

Table 16: LED Status

7 6 5 4 3 2 1 0

caps lock

num lock

scroll lock

The keyboard sends data to the host only when both the data and clock lines are High, the idle state. Because the host is the “bus master”, the keyboard checks whether the host is sending data before driving the bus. The clock line can be used as a “clear to send” signal. If the host pulls the clock line Low, the keyboard must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by eight bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. When the keyboard sends data, it generates 11 clock transitions at around 20 to 30 kHz, and data is valid on the falling edge of the clock as shown in Figure 8.

6.2 PS/2 Mouse A mouse generates a clock and data signal when moved; otherwise, these signals remain High indicating the Idle state. Each time the mouse is moved, the mouse sends three 11-bit words to the host. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 data bits (LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Each data transmission contains 33 total bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 10, 21, and 32 are ‘1’ stop bits. The three 8-bit data fields contain movement data as shown in Figure 10 .Data is valid at the falling edge of the clock, and the clock period is 20 to 30 kHz.

21

PS/2 mouse employs a relative coordinate system wherein moving the mouse to the right generates a positive value in the X field, and moving to the left generates a negative value. Likewise, moving the mouse up generates a positive value in the Y field, and moving down represents a negative value. The XS and YS bits in the status byte define the sign of each value, where a ‘1’ indicates a negative value. The magnitude of the X and Y values represent the rate of mouse movement. The larger the value, the faster the mouse is moving. The XV and YV bits in the status byte indicate when the X or Y values exceed their maximum value, an overflow condition. A ‘1’ indicates when an overflow occurs. If the mouse moves continuously, the 33-bit transmissions repeat every 50 ms or so. The L and R fields in the status byte indicate Left and Right button presses. A ‘1’ indicates that the associated mouse button is being pressed.

Figure 10: Data format for PS/2 mouse interface

6.3 Control Signal Connection Table 17: PS/2 Interface to VIRTEX-4 FPGA

KEYBOARD Control Bit FPGA Pin

"KBD_CLOCK_QS" C30

"KBD_DATA_QS" D29

MOUSE


"MOUSE_CLOCK_QS" C29

"MOUSE_DATA_QS" C28

22

CHAPTER 7

Switches And LEDs

7.1 DIP Switches The VIRTEX-4development board has eight DIP switches. The switches connect to an associated FPGA pin, as shown in Table 18 A 4.7KΩ series resistor provides nominal input protection.

Table 18: DIP switch Interface to VIRTEX-4 FPGA

Control Bit “IL0” “IL1” “IL2” “IL3” “IL4” “IL5” “IL6” “IL7”

FPGA Pin AP15 AN15 AP14 AN14 AN13 AP12 AN12 AP11

When in the UP or ON position, a switch connects the FPGA pin to VCCO, a logic High. When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuitry, although such circuitry could easily be added to the FPGA design programmed on the board.

7.2 Key Switches The VIRTEX-4 development board has four momentary-contact Key switches. These are located along the lower edge of the board, toward the left edge. The switches are labelled K0 through K3.key switch K3 is the left-most switch, K0 the right-most switch. The switches connect to an associated FPGA pin, as shown in Table 19. Pressing a key generates logic High on the associated FPGA pin. There is no active debouncing circuitry on the key switches.

Table 19: KEY switch Interface to VIRTEX-4 FPGA

Control Bit “KEY0” “KEY1” “KEY2” “KEY3”

FPGA Pin AP10 AN10 AP9 AN9

7.3 LEDS The VIRTEX-4 development board has eight individual surface-mounts red LEDs located above the key switches. The LEDs are labelled LED7 through LED0. LED7 is the left-most LED, LED0 the right-most LED. Table 20 shows the FPGA connections to the LEDs. A series current limiting resistor of 270Ω is associated with every LED. To light an individual LED, drive the associated FPGA control signal High

Table 20: LED Interface to VIRTEX-4 FPGA

Control Bit FPGA Pin “TESTLED0” AN8

“TESTLED1” AP7

“TESTLED2” AN7

“TESTLED3” AP6

“TESTLED4” AP5

“TESTLED5” AN5

“TESTLED6” AP4

“TESTLED7” AN4

23

CHAPTER 8

Seven Segment LED Display

The VIRTEX-4 development board has Four-character, seven segment LED display controlled by FPGA user-I/O pins. Each digit shares eight common control signals to light individual LED segments. Each individual character has a separate cathode control input. To light an individual signal, drive the individual segment control signal High along with the associated cathode control signal for the individual character. The control signal is high, enabling the control inputs for the left-most character. The segment control inputs, A through G and DP, drive the individual segments that comprise the character. A High value lights the individual segment, a Low turns off the segment.

Figure 11: Seven Segment Display

The two types of the seven segment displays are as shown below • Common Cathode Display: In this type of display the cathode of all the LEDs are tied

together and the anode terminals decides the status of the LED, either ON or OFF. • To turn ON the LED i.e segment value of driven segment should be 1 and 0 for turn OFF.

• Common Anode Display: In this type of display all the anode terminals of LEDs are tied

together and the cathode terminals decide the status of the LED either ON or OFF. • To turn ON the LED i.e. segment value of driven segment should be 0 and 1 for turn OFF.

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Interface details for the seven segment display with VIRTEX-4 display is as follows

Table 21: Seven Segment Display Interface to VIRTEX-4 FPGA


“SEGA” AM1

“SEGB” AM2

“SEGC” AN2

“SEGD” AN3

“SEGE” AC5

“SEGF” AD5

“SEGG” AD6

“SEGDP” AM1

“CSDIS1” AK2

“CSDIS2” AK1

“CSDIS3” AJ2

“CSDIS4” AJ1

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CHAPTER 9

VGA Interface

The VIRTEX-4 development board includes a VGA display port and DB15 connector, indicated as in Figure 12. This port connects directly to most PC monitors or flat-panel LCD displays using a standard monitor cable. VGA stands for Video Graphics Array, sometimes referred to as Video Graphics Adapter. It is a video card, which is an interface between a computer and its corresponding monitor. The VGA card is the most common video card – nearly every video card has VGA compatibility – and it is fairly easy to program. It offers many different video modes, from 2 colours to 256 colour, and resolutions from 320x200 to 640x480.

Figure 12: FPGA –VGA Interface

26

As shown in Figure 12, the VIRTEX-4 FPGA controls 9 VGA signals: three for Red, three for Green, three for Blue, Horizontal Sync, and Vertical Sync, all available on the VGA connector. The FPGA pins that drive the VGA port appear in Table 22.

Table 22: VGA Interface to VIRTEX-4 FPGA


"BLUE_0" AH4

"BLUE_1" AH3

"BLUE_2" AG3

"GREEN_0" AK4

"GREEN_1" AK3

"GREEN_2" AJ4

“RED_0” AM3

“RED_1” AL4

“RED_2” AL3

"HOR_SYNC" AF3

"VER_SYNC" AF4

Each colour line comprises of 3 bits .Thus total of 23 x 23 x23 i.e. 256 colours are generated. The series resistor uses the 75Ω VGA cable termination to ensure that the colour signals remain in the VGA-specified 0V to 0.7V range. The HS and VS signals are TTL level. Red, Green Blue bits are driven High or Low to generate different colours.

9.1 VGA Display Theory CRT-based VGA displays use amplitude-modulated, moving electron beams (or cathode rays) to display information on a phosphor-coated screen. LCD displays use an array of switches that impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel-by-pixel basis. Although the following description is limited to CRT displays, LCD displays have evolved to use the same signal timings as CRT displays. Consequently, the following discussion pertains to both CRTs and LCD displays. Within a CRT display, current waveforms pass through the coils to produce magnetic fields that deflect electron beams to transverse the display surface in a “raster” pattern, horizontally from left to right and vertically from top to bottom. As shown in Figure 13, information is only displayed when the beam is moving in the “forward” direction—left to right and top to bottom—and not during the time the beam returns back to the left or top edge of the display. Much of the potential display time is therefore lost in “blanking” periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass.

27

Figure 13: CRT Display Timing

The size of the beams, the frequency at which the beam traces across the display and the modulation frequency of electron beam determine the display resolution. Modern VGA displays support multiple display resolutions, and the VGA controller dictates the resolution by producing timing signals to control the raster patterns. The controller produces TTL-level synchronizing pulses that set the frequency at which current flows through the deflection coils, and it ensures that pixel or video data is applied to the electron guns at the correct time. Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location. The controller indexes into the video data buffer as the beams move across the display. The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel. As shown in Figure 13, the VGA controller generates the HS (horizontal sync) and VS (vertical sync) timings signals and coordinates the delivery of video data on each pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the “refresh” frequency of the display, or the frequency at which all information on the display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz range. The number of horizontal lines displayed at a given refresh frequency defines the horizontal “retrace” frequency.

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9.2 VGA signal TIMING The signal timings in Table 23 are derived for a 640-pixel by 480-row display using a 25 MHz pixel clock and 60 Hz ±1 refresh. Figure 14 shows the relation between each of the timing symbols.

Figure 14: VGA Timing

The timing for the sync pulse width (TPW) and front and back porch intervals (TFP and TBP) are based on observations from various VGA displays. The front and back porch intervals are the pre- and post-sync pulse times. Information cannot be displayed during these times.

Table 23: VGA signal timing

Vertical Sync Horizontal Sync Symbol Parameter

Time Clocks Lines Time Clocks

TS Sync pulse time 16.7 ms 416,800 521 32µs 800

TDISP Display time 15.36 ms 384,000 480 25.6 µs 640

TPW Pulse width 64 µs 1,600 2 3.84 µs 96

TFP Front porch 320 µs 8,000 10 640 µs 16

TBP Back porch 928 µs 23,200 29 1.92 µs 48

29

CHAPTER 10

LCD Interface

VIRTEX-4 development board includes the Oriole’s Display Module a dot matrix liquid crystal display that displays alphanumeric, Kana (Japanese) characters and symbols. Built in controller provides connectivity between LCD and FPGA. This LCD has a built in Dot Matrix controller, with font 5x7 or 5x10 dots, display data RAM for 80 characters ( 80 x 8 bit) and a character generator ROM which provides 160 characters with 5x7 font and 32 characters with font of 5x10. All the functions required for LCD are provided internally. Internal refresh is provided by the Controller. The Interface details of the LCD display are as shown in figure 15.

Figure 15: LCD Interface to VIRTEX-4 FPGA

10.1 Data Lines Connection LCD has 8 bit bidirectional data bus interface to FPGA. The data bus interface has a three state construction. When Enable signal is at low level, these data bus terminal remain in high impedance state. Interface details of the data lines with VIRTEX-4 FPGA are as in Table 24.

30

Table 24: Data Line Interface to VIRTEX-4 FPGA

Data Bit FPGA Pin

“DL0_QS” C23

“DL1_QS” C24

“DL2_QS” D24

“DL3_QS” C25

“DL4_QS” D25

“DL5_QS” D26

“DL6_QS” C27

“DL7_QS” D27

10.2 Control Line Interface: The control lines of LCD comprises of RS, R/W# and E The significance of the above mentioned control signals is as follows • RS: Register select signal used to select Data register or a Command/Status register.

High on RS selects the data register. Low on RS selects the Command/Status register.

• R/W#: Read/Write select control line.

High on R/W # selects the read operation Low on R/W # selects the write operation.

• E: Enable signal used to enable or disable the data bus.

Low on the enable signal puts the data bus into a high impedance state. High on the enable signal selects the data bus.

The control line interface of LCD with FPGA is as shown in table 25

Table 25: Control Line Interface to VIRTEX-4 FPGA


“E_QS” C22

“R/W_QS” D21

“RS_QS” C8

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CHAPTER 11

10/100 Non PCI Ethernet Interface

VIRTEX-4 development board has a 10 / 100 Mbps Ethernet interface using LAN 91C111 from SMSC. The block diagram for the same is as shown in figure 16. This interface is designed to facilitate the implementation of fast Ethernet connectivity for embedded applications. LAN 91C111 is a mixed analog/digital device that implements MAC and PHY portion of CSMA /CD protocol at 10 and 100 Mbps.

SMSC LAN 91C111 provides a flexible slave interface to industry standard bus interface. Supports 32, 16 and 8 bit bus host interface with synchronous and asynchronous data transfer modes. Two different interfaces are supported on network side. The first interface is standard magnetics transmit –receive pair interfacing to 10/100 Base –T utilizing internal physical layer block. Second is a MII (Media Independent Interface) specification standard that use nibble wide data transfer. This is applicable for both 10 and 100 Mbps speed.

Interface details for the Ethernet interface are as mentioned below.

Figure 16: LAN 91C111 Interface to VIRTEX-4 FPGA

32

11.1 System Address Bus Connection These consist of A1-A15, AEN and nBE0-nBE3 signals. • A1-A15: Address bus input. LAN 91C111 uses A1-A3 to access internal registers selection

while A4-A15 is used for address decoding for register access. • AEN: Address enable signal, active low on these signals enables the address decoding. • nBE0 – nBE3: Active low byte valid used to define the width of access and registers being

accessed. Table 26: Address Bus Interface to VIRTEX-4 FPGA

Address Bit FPGA Pin

“LAN_A1” AH33

“LAN_A2” AJ34

“LAN_A3” AK34

“LAN_A4” AK33

“LAN_A5” AN28

“LAN_A6” AN27

“LAN_A7” AP29

“LAN_A8” AN29

“LAN_A9” AP30

“LAN_A10” AN30

“LAN_A11” AP31

“LAN_A12” AP32

“LAN_A13” AN32

“LAN_A14” AN33

“LAN_A15” AM33

"LAN_AEN" AK29

“LAN_nBE0” AL25

“LAN_nBE1” AM26

“LAN_nBE2” AL26

“LAN_nBE3” AM25

11.2 System Data Bus Connection 32 bit bidirectional data bus used to access the LAN 91C111 internal registers. Data bus has an internal weak pull-up.



“LAN_D0” AN22 “LAN_D16” AM28

“LAN_D1” AN23 “LAN_D17” AL28

“LAN_D2” AP24 “LAN_D18” AL29


33



“LAN_D6” AP26 “LAN_D22” AM32


“LAN_D8” AH34 “LAN_D24” AC34

“LAN_D9” AG33 “LAN_D25” AB33

“LAN_D10” AF33 “LAN_D26” AA33

“LAN_D11” AF34 “LAN_D27” AA34

“LAN_D12” AE33 “LAN_D28” Y33

“LAN_D13” AE34 “LAN_D29” V33

“LAN_D14” AD34 “LAN_D30” V34

“LAN_D15” AC33 “LAN_D31” AG30

11.3 Control Signals Connection Control signals are broadly categorized into three types • Synchronous Bus interface signals • Asynchronous Bus interface signals • Miscellaneous control signals 10.3.1 Synchronous bus interface signals Following are the synchronous bus interface signals: • nCycle : Active low synchronous signal used to control EISA burst cycle. • nVL Bus: Active low signal to enable VL Bus interface. • W/nRD : Defines the direction of the cycle. High enables write cycles and low enables read

signals. • LCLK : Synchronous bus clock . Maximum limit is 50 MHz. During asynchronous cycle this

pin is tied high. • nSRDY : This signal is used to extend the access in VL Bus interface mode. Falling edge of

this signal indicates the cycle completion • nRDYRTN: Input to SMSC LAN 91C111 used to control completion of read cycle. Sampled

on falling edge of LCLK and synchronous cycles are delayed until it is sampled high.

Table 28: Synchronous Bus Interface to VIRTEX-4 FPGA


LAN_CYCLE" AK26

"LAN_nSRD" AJ29

"LAN_RDYRTN" AF29

"W/nR" AK27

"\VLBUS\" AK28

11.3.2 Asynchronous bus interface signals Following are the asynchronous bus interface signals • ARDY: Used to extend the bus access in asynchronous bus interface.

34

• nRD : Active low read strobe • nWR: Active low write strobe. • nADS: Address A1-A15 and AEN are latched on rising edge of nADS.

Table 29: Asynchronous Bus Interface to VIRTEX-4 FPGA


"LAN_ARDY" AJ27

“LAN_nRD” AM27

“LAN_nWR” AL34

“nADS”

11.3.3 Miscellaneous Signals: • Reset: When this pin is asserted controller performs system reset.(MAC + PHY ) • INTR: Active high input to interrupt the FPGA. • nCS: Output chip select used to provide for mapping of PHY functions into LAN 91C111

decoded space. • nLDEV: It is a combinatorial decode of unlatched address and AEN signal. • IOS0, IOS1, and IOS2: Select the predefined EEPROM configuration. • ENEEP: Enables access to external serial EEPROM.

Table 30: Miscellaneous Signals Interface to VIRTEX-4 FPGA


LAN_rst AD21

LAN_INTR" AD20

"LAN_nCS" AD23

LAN_nDEV" Y25

IOS0 AD18

IOS1 AC18

IOS2 AD19

ENEEP AC19

For detailed of SMSC LAN91C111 refer its datasheet and application note an96.

35

CHAPTER 12

Connector Details

VIRTEX-4 Development Board has provision for six connectors that can be categorized as follows:

12.1 IO Connectors These provide access to free IOs on board. • IOCON1: A 50 pin box type connector – provides 40 IOs • IOCON2 : A 50 pin box type connector – provides 40 IOs • IOCON4: A 26 pin box type connector – provides 21 IOs Table 31 gives the interface details of IO connectors to FPGA

Table 31: IO Connector Interface to FPGA

Control Bit

FPGA Pin Control Bit FPGA

Pin

“F_IO1_QS” AE6 “F_IO51_QS” AJ9

“F_IO2_QS” AF5 “F_IO52_QS” AK8

“F_IO3_QS” AF6 “F_IO53_QS” AK9

“F_IO4_QS” AH5 “F_IO54_QS” AJ10

“F_IO5_QS” AJ5 “F_IO55_QS” AJ12

“F_IO6_QS” AJ6 “F_IO56_QS” AK12

“F_IO7_QS” AK6 “F_IO57_QS” AK13

“F_IO8_QS” AB8 “F_IO58_QS” AJ14

“F_IO9_QS” AC7 “F_IO59_QS” AK14

“F_IO10_QS” AC8 “F_IO60_QS” AJ15

“F_IO11_QS” AL6 “F_IO61_QS” AK16

“F_IO12_QS” AM6 “F_IO62_QS” AJ17

“F_IO13_QS” AM7 “F_IO63_QS” AK17

“F_IO14_QS” AL8 “F_IO64_QS” AG10

“F_IO15_QS” AM8 “F_IO65_QS” AH10


“F_IO17_QS” AL10 “F_IO67_QS” AH12

“F_IO18_QS” AM10 “F_IO68_QS” AG13

“F_IO19_QS” AL11 “F_IO69_QS” AH14




“F_IO23_QS” AM13 “F_IO73_QS” AH17

“F_IO24_QS” AL14 “F_IO74_QS” AJ20




36




“F_IO31_QS” AM20 “F_IO81_QS” D9

“F_IO32_QS” AL19 “F_IO82_QS” C9

“F_IO33_QS” AL18 “F_IO83_QS” D10


“F_IO35_QS” AM21 “F_IO85_QS” D11


“F_IO37_QS” AM22 “F_IO87_QS” C12

“F_IO38_QS” AM23 “F_IO88_QS” C13



“F_IO41_QS” AD7 “F_IO91_QS” C15

“F_IO42_QS” AE7 “F_IO92_QS” D16

“F_IO43_QS” AE8 “F_IO93_QS” D17

“F_IO44_QS” AF8 “F_IO94_QS” C17

“F_IO45_QS” AG7 “F_IO95_QS” C18

“F_IO46_QS” AG8 “F_IO96_QS” C19

“F_IO47_QS” AH7 “F_IO97_QS” D19

“F_IO48_QS” AH8 “F_IO98_QS” C20

“F_IO49_QS” AJ7 “F_IO99_QS” D20

“F_IO50_QS” AK7

• MICTOR Connector: IOs on connector IOCON3 are also mapped to MICTOR connector

(J10) for interface of Logic Analyzer. This connector provides 34 IOs for interface. Table 32 gives the interface details of Mictor connector to FPGA.

Table 32: IO Connector Interface to FPGA

Control Bit

FPGA Pin Control Bit FPGA

Pin

“MICTOR1_QS” A13 “MICTOR18_QS” B8

“MICTOR2_QS” B13 “MICTOR19_QS” G2


“MICTOR4_QS” B12 “MICTOR21_QS” F1

“MICTOR5_QS” B15 “MICTOR22_QS” A6

“MICTOR6_QS” A11 “MICTOR23_QS” E1


“MICTOR8_QS” B11 “MICTOR25_QS” E2

“MICTOR9_QS” D5 “MICTOR26_QS” A5

“MICTOR10_QS” A10 “MICTOR27_QS” D1

37

“MICTOR11_QS” C4 “MICTOR28_QS” B5

“MICTOR12_QS” B10 “MICTOR29_QS” D2

“MICTOR13_QS” D4 “MICTOR30_QS” A4


“MICTOR15_QS” C3 “MICTOR32_QS” A3

“MICTOR16_QS” A8 “MICTOR33_QS” C2

“MICTOR17_QS” G1 “MICTOR34_QS” B3

12.3 Stackable Connector Two stackable connectors J1 and J2 are provided on board for the interface of ADD ON daughter boards (optional) provided along with the VIRTEX-4 Development board. Table 33 gives the interface details of Stackable connector to FPGA.

Table 33: Stackable Connector Interface to FPGA

Control Bit

FPGA Pin

Control Bit

FPGA Pin

“STEC_IO0” E18 “STEC_IO45” B27

“STEC_IO1” K34 “STEC_IO46” W29

“STEC_IO2” F18 “STEC_IO47” AH18

“STEC_IO3” K33 “STEC_IO48” Y29

“STEC_IO4” E19 “STEC_IO49” AG18

“STEC_IO5” J34 “STEC_IO50” AA30


“STEC_IO7” H34 “STEC_IO52” AA29

“STEC_IO8” E21 “STEC_IO53” AH20

“STEC_IO9” H33 “STEC_IO54” AB30

“STEC_IO10” F21 “STEC_IO55” AG20

“STEC_IO11” G33 “STEC_IO56” AC30


“STEC_IO13” F34 “STEC_IO58” AC29


“STEC_IO15” F33 “STEC_IO60” AD30


“STEC_IO17” E34 “STEC_IO62” AD29


“STEC_IO19” E33 “STEC_IO64” AE29


“STEC_IO21” D34 “STEC_IO66” AB31


“STEC_IO23” C34 “STEC_IO68” AC32


“STEC_IO25” C33 “STEC_IO70” AD32

38

“STEC_IO26” E27 “STEC_IO71” AH27

“STEC_IO27” B33 “STEC_IO72” AD31


“STEC_IO29” B32 “STEC_IO74” AE32


“STEC_IO31” B31 “STEC_IO76” AE31


“STEC_IO33” A31 “STEC_IO78” AF31

“STEC_IO34” F29 “STEC_IO79” AF28

“STEC_IO35” B30 “STEC_IO80” AG32

“STEC_IO36” F30 “STEC_IO81” AE27

“STEC_IO37” A30 “STEC_IO82” AG31

“STEC_IO38” G30 “STEC_IO83” AD27

“STEC_IO39” A29 “STEC_IO84” AH32

“STEC_IO40” H29 “STEC_IO85” AC27

“STEC_IO41” B28 “STEC_IO86” AJ32

“STEC_IO42” H30 “STEC_IO87” AC28

“STEC_IO43” A28 “STEC_IO88” AJ31

“STEC_IO44” J29 “STEC_IO89” AB28

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CHAPTER 13

Clock and Reset Sources

The VIRTEX-4 Development board has a dedicated 40 MHz oscillator source and an optional socket for another clock oscillator source. This dedicated clock source can be used to derive other frequencies using DCM (digital clock mangers) available in VIRTEX-4 FPGA. Another clock oscillator can be mounted on 8 pin DIP Socket whose footprint is compatible with oscillators upto 200 MHz. VIRTEX-4 development board has a on board reset circuitry (a key switch) that is used to reset (active high) the hardware present on the board. Board also has a facility for external clock connection using a jumper JP1. Connecting jumper JP1 selects the external clock. The interface details of clock and reset with FPGA is given in Table 34.

Table 34: IO Clock-Reset Interface to FPGA


“CLOCK” AL5

“CLOCK1” AM5

“RESET” AK18

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CHAPTER 14

VIRTEX-4 Configuration Details

VIRTEX-4 development board supports two configuration modes as stated below • Boundary Scan mode • Master Serial Mode

14.1 Boundary Scan mode: In boundary scan mode of configuration the VIRTEX-4 FPGA is directly configured via a JTAG port using the dedicated configuration pins TCK, TMS, TDI and TDO. The jumper setting for selection of boundary scan mode is discussed in jumper setting section (section 12.3).

14.2 Master Serial Mode In master serial mode the VIRTEX -4 is configured through a FLASH PROM. In Master Serial mode, the FPGA automatically loads the configuration bitstream in bit-serial form from configuration flash synchronized by the configuration clock (CCLK) generated by the FPGA. Upon power-up or reconfiguration, the FPGA's mode select pins are used to select the Master Serial configuration mode. Master Serial Mode provides a simple configuration interface. Only a serial data line, a clock line, and two control lines (INIT and DONE) are required to configure an FPGA. Data from the PROM is read out sequentially on a single data line (DIN), accessed via the PROM's internal address counter which is incremented on every valid rising edge of CCLK. The serial Bitstream data must be set up at the FPGA’s DIN input pin a short time before each rising edge of the FPGA's internally generated CCLK signal. The jumper setting for selection of Master Serial Mode is discussed in jumper setting section (section 14.3).

14.3 Jumper Setting • Mode Selection Jumpers: M0, M1, M2 are the mode selection jumpers used to select the

configuration mode either Boundary Scan or Master Serial Mode. Table 35: Mode Selection Jumper Settings

Configuration Mode 1 2

MODE0 (M0)

MODE1 (M1)

MODE2 (M2)

• Connecting 1-2 selects Logic –0,

• Disconnecting 1-2 selects Logic- 1

Table 36: Mode Selection Table

Configuration Mode MODE0 MODE1 MODE2

Boundary Scan Mode 1 0 1

Master Serial Mode 0 0 0

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• JTAG Chain Selection Jumper: JP2 jumper is used to select the JTAG chain for configuration. When jumper is connected between 2-3, then PROM and FPGA both get added in the JTAG Chain where as connecting jumper between 1-2 brings only FPGA in Chain.

Figure 17: JTAG Mode Selection

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14.4 JTAG Header: An on board JTAG connector is provided for configuring the FPGA through parallel port of PC via a parallel III cable. The details of this connector are as shown in figure 19.

Figure 18: JTAG Mode Selection Jumper

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CHAPTER 15

Power Supplies

VIRTEX-4Development board is provided with a regulated power supply of + 5V DC output. This supply is used to generate the required on board supply voltages. Output of the regulated power supply is given to power connector present on board. The power LED (Red LED) lights up when power is properly applied to the board.

15.1 Voltage Regulators The list of various voltage regulators present on board are as given in Table 37.

Table 37: Power Supply Details

Voltage Source

+ 5 V DC Generated from external power supply provided along with the development Board.

+ 3.3 V DC A regulated 3.3 V DC supply is generated on board using a DC-DC converter PTH05010W with input voltage of 5 Volts

+2.5 V DC A regulated 2.5 V DC supply is generated onboard using a linear low drop out regulator LT1963 with input voltage of 3.3 Volts

+1.8 V DC A regulated 1.8 V DC supply is generated onboard using a linear low drop out regulator LT1963 with input voltage of 3.3 Volts

+1.2 V DC A regulated 1.2 V DC supply is generated on board using a DC-DC converter PTH05010W with input voltage of 5 Volts

-5V DC A negative supply is generated on board using a inverting charge pump MAX889 with input voltage of 5 Volts

Overall, the 5V DC switching power adapter powers the board. A 3.3V regulator, powered by the 5V DC supply, provides power to the inputs of the 2.5V and 1.0V regulators. Similarly, the 3.3V regulator feeds all the VCCO voltage supply inputs to the FPGA’s I/O banks and powers most of the components on the board. The 2.5V regulator supplies power to the FPGA’s VCCAUX supply inputs. The FPGA configuration interface on the board is powered by 3.3V. Consequently, the 2.5V supply has a current shunt resistor to prevent reverse current. Finally, a 1.2V regulator supplies power to the FPGA’s VCCINT voltage inputs, which power the FPGA’s core logic.

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APPENDIX A

Operating Instruction To Start A New Design

A.1 Starting The ISE Software: • Start ISE from the Start menu by selecting Start -> Programs -> Xilinx ISE Project

Navigator.

A.2 Design Flow • DESIGN ENTRY • SIMULATION • SYNTHESIS • IMPLEMENTATION • DEVICE PROGRAMMING

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Sample Design of Half Adder is used to explain the Design Flow.

A.3 Design Description

Half Adder

A

B

Sum

Carry

A.4 Truth Table of Half adder: -

Inputs Output A B Sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1

A.5 VHDL Code for Half adder library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity half_adder is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end full_adder; architecture Behavioral of half_adder is begin sum <= a xor b ; carry <= a and b; end Behavioral;

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A.6 Steps to implement the Half adder in the FPGA using Xilinx iSE(8.1i) Step 1 : Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start

Programs Xilinx ISE (8.1i)

Source Window

Process Window

Workspace

Transcript

Step 2 Create a new project In the window go to FILE New project. Specify the project name and location and say NEXT

Select Device. Use the pull-down arrow to select the Value for each Property Name. Click in the field to access the pull-down list.

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Say FINISH. Project summary is seen.

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Step 3: Creating a new VHD file

Click on the symbol of FPGA device and then right click Click on new source VHDL module and give the File name

VHDL Module

Then say Next Define ports.In this case

• a and b are the input ports defined as in • sum and carry are output ports defined as out

after this say Next twice and then Finish Skeleton of the design is shown in the VHDL editor.

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Step 4: Writing the Behavioral VHDL Code in VHDL Editor

Sample code is given below for this experiment.

Design Entry

Step 5 Check Syntax Run the Check syntax Process window synthesize check syntax >, and remove errors if present.

Step 6 Creating a test bench file Verify the operation of your design before you implement it as hardware. Simulation can be done using ISE simulator. For this click on the symbol of FPGA device and then right click Click on new source Test Bench Waveform and give the name Select entity Finish.

Select the desired parameters for simulating your design. In this case combinational circuit and Simulation time.

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Step 7: Simulate the code

Simulation Tools ISE tool supports the following simulation tools: • HDL Bencher is an automated test bench creation tool. It is fully integrated with

Project Navigator. • ModelSim from Model Technology, Inc., is integrated in Project Navigator to

simulate the design at all steps (Functional and Timing). ModelSim XE, the Xilinx Edition of Model Technology, Inc.’s ModelSim application, can be installed from the MTI CD included in your ISE Tool

In source Window from the Drop-down menu select Behavioral Simulation to view the created test Bench file.

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For simulation

Click on test bench file. Test bench file will open in main window. Assign all the signals and save File. From the source of process window. Click on Simulate Behavioral Model in Process window.

Verify your design in wave window by seeing behaviour of output signal with respect to input signal. Close the ISE simulator window

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Simulated Output

Step 8: Synthesize the design using XST. Translate your design into gates and optimize it for the target architecture. This is the synthesis phase. Again for synthesizing your design, from the source window select, synthesis/Implementation from the drop-down menu.

Synthesis

Highlight file in the Sources in Project window. To run synthesis, right-click on

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Synthesize, and the Run option, or double-click on Synthesize in the Processes for Current Source window. Synthesis will run, and

• a green check will appear next to Synthesize when it is successfully completed.

• a red cross indicates an error was generated and • a yellow exclamation ! mark indicates that a warning was generated,

(warnings are OK). Check the synthesis report. If there are any errors correct it and rerun synthesis..

Synthesis completed successfully

Step 9: Create Constraints File(UCF) Click on the symbol of FPGA device and then right click Click on new source

Implementation Constraints File and give the name Select entity Finish. Click on User Constraint and in that Double Click on Assign Package Pins option in Process window. Xilinx PACE window opens. Enter all the pin assignments in PACE., depending upon target device and number of input and outputs used in your design. (sample code is given below for given design.)

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Pin assignments

Step 10: Implementing a Design

Once synthesis is complete, you can place and route your design to fit into a Xilinx device, and you can also get some post place-and-route timing information about the design. The implementation stage consists of taking the synthesized netlist through translation, mapping, and place and route. To check your design as it is implemented, reports are available for each stage in the implementation process. Use the Xilinx Constraints Editor to add timing and location constraints for the implementation of your design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option, or double left-click on Implement Design.

Implementation done

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Step 11: Generating Programming File

Right-click on Generate Programming File, choose the Run option, or double left-click on Generate Programming File. This will generate the Bit stream

Step 12 Downloading in Boundary Scan Mode. Note : Xilinx provides 2-tools for downloading purpose, viz. • iMPACT - is a command line and GUI based tool • PROM File Formatter

Boundary Scan Mode

Procedure for downloading using iMPACT • Boundary Scan Mode

1. Right click on “Configure Device (iMPACT)” -> and Say RUN or Double click on “Configure Device (iMPACT)”.

2. Right click in workspace and say Initialize chain .The device is seen. 3. Right click on the device and say Program.

If the device is programmed properly, it says Programming Succeeded or else. Programming Failed. The DONE Led glows green if programming succeeds.

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Note: Before downloading make sure that Protoboard is connected to PC's parallel port with the cable provided and power to the Protoboard is ON.

Step 13: Apply input through DIP Switches, output is displayed on LEDs Step 14: Configuration through PROM: Generating PROM file:

FPGA can also be configured in Master Serial Mode through PROM. For this you need to program the PROM through a .mcs file.

Right click on “Generate PROM,ACE or JTAG file” -> and Say RUN or Double click on “Generate PROM,ACE or JTAG file”

Specify the PROM file name and location where it is to be generated.

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Specify the desired parameters of the PROM on board and say ADD then FINISH

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Say Generate File from the Process Window.

PROGRAMMING THE PROM

Note: Check the Jumper setting on the board. Refer the Chapter jumper Setting Similar to Step 12.Initialize chain through iMPACT. PROM and FPGA devices on board are seen .Assign the generated mcs file and bit file as desired. Right click the PROM symbol and say PROGRAM.

Now, whenever the board is powered on in master serial mode, FPGA is configured through PROM automatically.

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APPENDIX B

ADC–DAC Add On Card

About this Card: ADC- DAC add on card provides an analog interface to the VIRTEX-4, VIRTEX-4 and SPARTAN-3 based development board developed by Bitmapper Integration Technologies PVT Ltd.. This interface enables the user to implement design that involve dual channel analog input and output function that can be used for communication, video and DSP based applications. Add On Card Details: ADC-DAC add on card comprises of a two single channel ADC AD9240 and DAC 7541 form TI. The specifications of the above mentioned are as follows: ADC AD9240: • 14 bit analog to digital converter with sampling rate of 10 MSPS. • Operates on single supply voltage of 5 V. • A single-ended CLK input controls converter operation. • Input range of 0 to 5.0 V. DAC AD7541: • 12 bit 10 MSPS digital to analog converter. • Dual input channel. • Single supply voltage of 5V. Control of the A/Ds and D/As is handled by the FPGA through a SAMTEC connector interface provided on mother board and add on card. The supply voltage for the ADC/DAC interface is also provided via a SAMTEC connector. The interface details for the ADC and DAC unit with FPGA are as mentioned in section B-1 and B-2. B-1: ADC Interface Details: Block diagram for ADC interface as shown below:

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Unipolar analog input of amplitude range 0 – 5.0 V can be applied at analog in of SMA connector J3 and J4. ADC can sample the input at up to 10Msps sampling rate with a resolution of 14 bit. Data lines of ADC are interfaced to FPGA to process the sampled data. OTR signal provides the over-range indication. Clock to ADC is provided through FPGA. The AD9240 uses four-stage pipeline architecture with a wideband input sample-and-hold amplifier (SHA) implemented on a cost-effective CMOS process. Each stage of the pipeline, excluding the last, consists of a low resolution flash A/D connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier amplifies the difference between the reconstructed DAC output and the flash in put for the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash A/D. The pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. This means that while the converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the conversion to be fully processed and appear at the output. This latency is not a concern in most applications. The digital output, together with the out-of-range indicator (OTR), is latched into an output buffer to drive the output pins. The output drivers can be configured to interface with +5 V or +3.3 V logic families.

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The timing diagram for ADC is as shown below:

Output of ADC is in straight binary format with lowest value representing all ‘0’s and highest value representing all ‘1’s. For more details on ADC AD9240 please refer the datasheet provided along with this board

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B-2: DAC Interface Details: Block diagram for DAC interface is as shown below

Data lines of both the DACs are interfaced to FPGA. Analog output of DACs is available on SMA connector J5 and J6.The range available at DAC output extends from 0 to 5V for a reference voltage of 2.5V. This range can be varied by adjusting the value of Vref by varying the value of preset PR11 and PR12 for DAC1 and DAC2 respectively. AD7541A does not require an input clock for its operation and has a conversion time of 100ns with 12 bit resolution. Input to DAC is in straight binary format with lowest value represented by all ‘0’s and highest value represented by all ‘1’s. For more details on DAC please refer the datasheet provided along with the board.

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The User constraint file for the ADC –DAC add on card is as in table B-1. NET NAME CONNECTOR

PIN NO. FPGA PIN NO.

VIRTEX-4 PROTOBOARD

SPARTAN-3 5M

PROTBOARD

SPARTAN-3 5M PCI

PROTOBOARD

VIRTEX-4 PROTOBOARD

DAC-1 "DAC1-D0" IO-34 #J1-42 LOC = H21 LOC = H30 LOC = G6 LOC = M24 "DAC1-D1" IO-36 #J1-44 LOC = G24 LOC = J29 LOC = F5 LOC = N23 "DAC1-D2" IO-38 #J1-46 LOC = H23 LOC = J30 LOC = F6 LOC = N24 "DAC1-D3" IO-40 #J1-48 LOC = H24 LOC = K29 LOC = E6 LOC = P24 "DAC1-D4" IO-42 #J1-50 LOC = J23 LOC = L29 LOC = F8 LOC = P23 "DAC1-D5" IO-44 #J1-52 LOC = K23 LOC = L30 LOC = F7 LOC = R23 "DAC1-D6" IO-32 #J1-40 LOC = H22 LOC = H29 LOC = T4 LOC = R21 "DAC1-D7" IO-28 #J1-36 LOC = J22 LOC = M26 LOC = G11 LOC = P21 "DAC1-D8" IO-26 #J1-34 LOC = K21 LOC = M25 LOC = H12 LOC = N22 "DAC1-D9" IO-24 #J1-32 LOC = K22 LOC = L26 LOC = G12 LOC = N21 "DAC1-D10" IO-22 #J1-28 LOC = L21 LOC = L25 LOC = H13 LOC = M22 "DAC1-D11" IO-20 #J1-26 LOC = N22 LOC = K25 LOC = G14 LOC = M21 DAC-2 "DAC2-D0" IO-0 #J1-2 LOC = C24 LOC = K18 LOC = J12 LOC = K20 "DAC2-D1" IO-1 #J1-1 LOC = D16 LOC = H19 LOC = K13 LOC = J19 "DAC2-D2" IO-5 #J1-5 LOC = D17 LOC = H20 LOC = K14 LOC = T25 "DAC2-D3" IO-7 #J1-7 LOC = D18 LOC = G21 LOC = J14 LOC = P26 "DAC2-D4" IO-9 #J1-11 LOC = C19 LOC = H22 LOC = K15 LOC = P25 "DAC2-D5" IO-11 #J1-13 LOC = D19 LOC = G23 LOC = M3 LOC = G21 "DAC2-D6" IO-12 #J1-16 LOC = G23 LOC = H23 LOC = H8 LOC = P20 "DAC2-D7" IO-10 #J1-14 LOC = F24 LOC = G24 LOC = G7 LOC = N19 "DAC2-D8" IO-8 #J1-12 LOC = F23 LOC = J21 LOC = J9 LOC = M20 "DAC2-D9" IO-6 #J1-8 LOC = E24 LOC = K20 LOC = J10 LOC = M19 "DAC2-D10" IO-4 #J1-6 LOC = E23 LOC = K19 LOC = K11 LOC = Y12 "DAC2-D11" IO-2 #J1-4 LOC = D24 LOC = J19 LOC = K12 LOC = L19 ADC-1 "ADC1_D1" IO-82 #J2-46 LOC = V23 LOC = T27 LOC = AD3 LOC = AB24"ADC1_D2" IO-72 #J2-34 LOC = AA24 LOC = P24 LOC = U3 LOC = AB20"ADC1_D3" IO-68 #J2-28 LOC = V22 LOC = R24 LOC = AD20 LOC = AB19"ADC1_D4" IO-59 #J2-15 LOC = U21 LOC = L21 LOC = AE6 LOC = U20 "ADC1_D5" IO-57 #J2-13 LOC = J20 LOC = M21 LOC = AE5 LOC = U19 "ADC1_D6" IO-55 #J2-11 LOC = K20 LOC = M22 LOC = AD6 LOC = V19 "ADC1_D7" IO-53 #J2-7 LOC = L19 LOC = N21 LOC = AC6 LOC = W20 "ADC1_D8" IO-51 #J2-5 LOC = L20 LOC = N22 LOC = AC5 LOC = W19 "ADC1_D9" IO-49 #J2-3 LOC = M19 LOC = P21 LOC = AB6 LOC = Y20 "ADC1_D10" IO-47 #J2-1 LOC = M20 LOC = P22 LOC = AB5 LOC = Y18 "ADC1_D11" IO-50 #J2-6 LOC = P20 LOC = U22 LOC = AC13 LOC = Y12 "ADC1_D12" IO-46 #J2-2 LOC = R20 LOC = V22 LOC = AC12 LOC = Y10 "ADC1_D13" IO-48 #J2-4 LOC = P19 LOC = U21 LOC = AD12 LOC = Y11 "ADC1_D14" IO-62 #J2-22 LOC = W21 LOC = U24 LOC = AC18 LOC = AB17"ADCCLK1" IO-58 #J2-16 LOC = Y21 LOC = R21 LOC = AD16 LOC = AA15"OTR1" IO-86 #J2-52 LOC = U24 LOC = N29

LOC = AE3 LOC = AA24

ADC-2 "ADC2_D1" IO-67 #J2-25 LOC = R23 LOC = N23

LOC = AF8 LOC = Y22

"ADC2_D2" IO-69 #J2-27 LOC = P22 LOC = M24 LOC = AE9 LOC = W21 "ADC2_D3" IO-71 #J2-31 LOC = R24 LOC = M23 LOC = AF9 LOC = U21

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NET NAME CONNECTOR PIN NO.

FPGA PIN NO.

VIRTEX-4 PROTOBOARD

SPARTAN-3 5M

PROTBOARD

SPARTAN-3 5M PCI

PROTOBOARD

VIRTEX-4 PROTOBOARD

"ADC2_D4" IO-73 #J2-33 LOC = P23 LOC = L24 LOC = AE10 LOC = U22 "ADC2_D5" IO-75 #J2-35 LOC = P24 LOC = L23 LOC = AE11 LOC = T22 "ADC2_D6" IO-77 #J2-37 LOC = N24 LOC = K24 LOC = AF11 LOC = W23 "ADC2_D7" IO-79 #J2-41 LOC = N23 LOC = J23 LOC = W4 LOC = W24 "ADC2_D8" IO-81 #J2-43 LOC = M24 LOC = P25 LOC = Y3 LOC = V23 "ADC2_D9" IO-83 #J2-45 LOC = M23 LOC = N26 LOC = Y4 LOC = V24 "ADC2_D10" IO-85 #J2-47 LOC = L24 LOC = N25 LOC = AA3 LOC = U24 "ADC2_D11" IO-87 #J2-51 LOC = L23 LOC = M29 LOC = AB4 LOC = T23 "ADC2_D12" IO-89 #J2-53 LOC = K24 LOC = M30 LOC = AG3 LOC = T24 "ADC2_D13" IO-88 #J2-54 LOC = T23 LOC = N30 LOC = AF4 LOC = Y23 "ADC2_D14" IO-63 #J2-21 LOC = T21 LOC = K21 LOC = AE7 LOC = AA22"ADCCLK2" IO-61 #J2-17 LOC = U22 LOC = K22 LOC = AF6 LOC = T19 "OTR2" IO-65 #J2-23 LOC = T24 LOC = J22 LOC = AE8 LOC = Y21

Table B-1: ADC – DAC Add on Card User Constraint File

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APPENDIX C

ASCII Table 5 X 7 LCD Display

The ASCII code for 5 x 7 LCD Display is as shown below:

virtex-4 lx 100 prtoboard

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