asic technology trends - smithsonian institution

OVERVIEW

This section will discuss three general trends associated with todayÕs ASIC industry: the rapidadvancement of process technologies, the move toward specialization, and a blurring of the dis-tinctions between each of the ASIC product categories. There is also an underlying trend linkingthese together: each new ASIC generation requires greater cooperation between ASIC vendorsand customers.

Distinguishing between each of the ASIC product categories is becoming increasingly difficult.Until recently, the ASIC industry could be divided up into the three well-defined product groupsdefined in Section 1: semicustom ICs (gate arrays and linear arrays), custom ICs (standard cellsand full custom devices), and programmable logic devices (simple and complex PLDs, FPGAs,and EPACs). However, the lines separating those three categories are getting blurry. The best fea-tures of products from one category are increasingly showing up in products of other categories.

Take, for example, embedded arrays, which are based on a gate array structure but have largemegacells such as compiled memories or microprocessor cores embedded in them (Figure 6-1).The cells/cores provide a higher level of integration than a pure gate-array structure, but can leadto longer prototype leadtimes, though, still shorter than the leadtimes for pure cell-based ASICs.

Another example of the convergence of ASIC technologies is ActelÕs (co-developed withSynopsys) so-called SPGA (system-programmable gate array), shown in Figure 6-2. Ultimately,Actel will be using combinations of antifuse-, SRAM-, and/or flash-based PLD circuitry, mask-programmable gate array logic, and cell-based cores to serve the diverse ASIC customer base.

One thing thatÕs true for all types of ASIC devices is that they are becoming more specialized toserve the needs of systems companies. The ASIC industry is moving away from a one-size-fits-allapproach, toward a tighter market focusÑone that places greater emphasis on performance,power, functionality, and cost considerations on a per customer basis. ASICs are no longer just onthe periphery of a system (i.e., glue logic), they are being designed as the core of the system. Asa result, ASIC vendors are becoming more segmented or specialized in what they have to offer,including such devices as digital video, networking, telecommunications, or audio ASICs.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 6-1

6 ASIC TECHNOLOGY TRENDS

To meet their complex chip requirements, ASIC customers are having to rely more on the designgroups of ASIC vendors or third-party design houses (see Appendix for listing). This is in con-trast to the past, when it was basically only a matter of drawing up a schematic and sending thedesign off to be implemented in silicon by an ASIC manufacturer.

ASIC Technology Trends

INTEGRATED CIRCUIT ENGINEERING CORPORATION6-2

RAMROM

SerialI/O

SpecialFunction

Sea of Gates Array

19190BSource: EDN

Figure 6-1. Typical Embedded Array ASIC

Field -Programmable

Logic

66MHzPCI Core

Field -Programmable

Logic

MaskProgrammable

ASIC

Instrumentation• Data Acquisition• Image Processing

Computer• DMA• Graphics

Datacom• Router• Bridge

• • •

(a) (b)

Source: Electronic Products 21735

An SPGA could either be standard – an FPGA with widely used cells on chip (a)or customer specific – a combination FPGA and gate array (b).

Figure 6-2. ActelÕs System-Programmable Gate Array (SPGA)

Additionally, the use of third-party cell/core library providers (e.g., Aspec Technology, CadenceDesign Automation, Compass, the Silicon Architects Group of Synopsys, and VLSI Libraries) andfoundries is becoming an attractive option for ASIC customers. This strategy is sometimes calledcustomer-owned-tooling (COT) ASIC design. COT customers purchase third-party libraries,create a tape of their mask layout using ASIC and physical design tools, and then take the designto foundries like TSMC and Chartered. Figure 6-3 provides a sampling of companies offeringASIC foundry services. Third-party library firms are attracting not only customers of ASICs, butalso vendors of ASICs who may be seeking to broaden their own core libraries.



CompanyLocation

TechnologiesOffered

Feature Size Metal Pitch

CMOS

Bipolar

BiCMOS and CMOS

CMOS

CMOS

BiCMOS and CMOS

BiCMOS, CMOS,EECMOS, and High-

Voltage CMOS

CMOS

CMOS

BiCMOS, Bipolar,CMOS, and DMOS

CCD and CMOS

CMOS

CCD, CMOS, andCMOS Mixed Signal

Bipolar,Complementary

Bipolar, andComplementary

BiCMOS

GaAs HBT

0.5µm

1.0µm

BiCMOS—1.5µmCMOS—1.5µm to 5µm

0.6, 0.5, and 0.35µm

0.5 and 0.35µm

BiCMOS—0.6µmCMOS—0.75µm

0.8 to 5µm

CMOS 0.35µm

0.8, 0.6, 0.5, and0.35µm

Bipolar—1.0µmCMOS—1.2µm

CCD—2.5µmCMOS—1.2µm

0.5µm

0.6, 0.8, 1.2µm2.0 to 5.0µm

Bipolar—4µmCbipolar—2µm

CBiCMOS—2µm

2.1µm (Emitter Width)

1.2µm

3.0µm

1.2µm and 5.0µm

0.6µm / 1.6µm0.5µm / 1.2µm

0.35µm / 0.9µm0.25µm / 0.7µm

0.5µm / 1.60µmContacted

0.35µm / 0.25µmContacted


2.4µm

1.2µm

0.8µm / 2.0µm0.6µm / 1.7µm0.5µm / 1.3µm

0.35µm / 1.0µm

6.0µm

2.1µm

1.6µm

1.6µm

Bipolar—11µm.Cbipolar—7µm

CBiCMOS—7µm

3.6µm min.

Source: Integrated System Design 23174/23175

American MicrosystemsPocatello, ID

AMCCSan Diego, CA

California Micro DevicesMilpitas, CA

Chartered SemiconductorMilpitas, CA

Fujitsu MicroelectronicsSan Jose, CA

IC WorksSan Jose, CA

IMPSan Jose, CA

Kawasaki LSI USASanta Clara, CA

LG Semicon AmericaSan Jose, CA

Micrel SemiconductorSan Jose, CA

Mitel SemiconductorBromont, Quebec, Canada

Newport Wafer-FabPalo Alto, CA

Orbit SemiconductorSunnyvale, CA

Raytheon Electronics,Semiconductor DivisionMountain View, CA

Rockwell SemiconductorSystemsNewport Beach, CA

Number of Layers(Metal/Poly)

Wafer Size Packages Available

3/1 and 3/2

3/2

2/2

1, 2, 3, or 4 Metaland 1 or 2 Poly

0.5µm—3/10.35µm—4/1

1, 2, or 3 Metal1 or 2 Poly

2/2

3/1

0.8, 0.6, and0.5µm—3/1

0.35µm—4/1

2/3

2/2

3/2

3/2

2 Metal

3 Metal

125mm and200mm

100mm

125mm and100mm

150mm and200mm

0.5µm—150mm0.35µm—200mm

150mm

125mm

150mm

0.8 and 0.6150mm

0.5 and 0.35µm200mm

100mm or150mm

100mm

150mm

150mm

100mm

100mm

All Open-Tooled Packages

Most Standard Packages

PLCC, DIP, SOIC, SSOP,and QSOP

BGA—225 to 313 LeadsMQFP—48 to 240 LeadsTQFP—32 to 208 Leads

PLCC—44, 68, and 84 LeadsThermally Enhanced MQFP

QFP, SQFP, PGA, and BGA

N/A

DIP, PLCC, SOIC, SSOP,TSSOP, QFP, and TQFP

DIP, SDIP, QFP, SQFP,and PGA

PLCC, PQFP, TQFP, and BGA

All

Standard Packages

All High Pin-Count MoldedPackaging (PDIF, QFP,

and BGA)

Any Commercial

LCC, DIP, Side Braze, MetalCan, Flat Pack, PGA, allOther Packages are withSubcontract Agreementswith Assembly Houses

Not Offered at this Time

ProductCommitment

RequiredTurnaround Time

Negotiable

50 WafersPer Year

1,000 WafersPer Year

Varies

Minimum 600Wafers Per

Year, Negotiable

500-1,000

Negotiable

6,000 WafersPer Year Min.

CustomerDependent

None

100 WafersPer Year Min.

Minimum LotSize of 25

Wafers

12 Die

240 WafersMin.

ContactFactory

4-5 Weeks

10 Weeks

3 Weeks Minutes

Prototypes—1-2Days Per Mask LayerProduction—2 Days

Per Mask Layer

Standard 4-6 Weeks

3 Weeks

6 Weeks, ExpediteAvailable

7 Weeks

Wafers in 4 WeeksAssembled and Tested

in 6 Weeks

12-16 Weeks

10 Weeks

2.5 Days Per Mask

Process DependentCMOS DLP 21 Days

Bipolar—12 WeeksCbipolar—16 Weeks

CBiCMOS— 16 Weeks

16 Weeks

Figure 6-3. Foundries

The increase in the functionality of ASICs has been realized by the industryÕs quick migration todeep-submicron process technologies. Figure 6-4 lists several ASIC producers that have been dis-cussing their advanced ASIC technologies. Note that the companies listed offering this leading-edge technology are all major ASIC producers. The rapid advancement in ASIC technology hasnot come without challenges or compromises, as will be discussed.

FULL CUSTOM ICs

As was shown in Section 4, the full custom or ÒhandcraftedÓ IC market is not expected to showmuch strength in the late 1990Õs. Still, at $2.8 billion (1996), the market for full custom ICs is sizable.



CompanyLocation

TechnologiesOffered

Feature Size Metal Pitch

BiCMOS, CMOS,DMOS, FRAM, and

Flash

Bipolar and MetalGate CMOS

CMOS

25C10 CMOS—2.5VCMOS. Timeline

18C07 CMOS—1.8VCMOS

BiCMOS, BiCMOSAnalog, CMOS,CMOS Analog,

and CMOS HighVoltage

CMOS and EPROM

CMOS

GaAs E-D MESFET

BiCMOS and CMOS

CMOS

CMOS and Flash—0.35, 0.5, and 0.6µmBipolar—2 to 4µm

BiCMOS—0.6 to 1.7µm

4µm

0.35µm (200mm)and 0.75µm

(150mm)

25C10.A5L—0.25µm

18C07.A5L—0.18µm


CMOS HighVoltage—0.8µm

CMOS—0.8µm,Capacitor Module

CMOS—0.6µm,Polycide, Double

Poly, EPROMCMOS—0.5µm,

Polycide

STD 0.6µm—0.58µm. HS 0.6µm—

0.36. HS 0.4µm—0.3µm

0.5µm

CMOS—0.35µm(DRAM, SRAM,

Logic, Mixed Signal,Embedded Nonvolatile)

BiCMOS—0.8µm

0.35µm

1.2µm

8µm

1.0µm

25C10.A5L—1.0µm(Uncontacted) and1.2µm (Contacted).

18C07.A5L—0.70µm(Uncontacted) and0.85µm (Contacted)

Metal 1, 0.6µm—1.7µm. Metal 2,0.6µm—.7µm.

Metal 3, 0.6µm—2.3µm. Metal 1,0.8µm—2.1µm.Metal 2, 0.8µm

—2.3µm

0.8µm—2.4µm0.6µm—1.6µm0.5µm—1.2µm

1.5

2µm Line,2µm Space

CMOS: Metal 1—0.7µm

0.95µm

Source: Integrated System Design 23175/23180

RohmKyoto, Japan

Semtech (FormerlyECI Semiconductor)Santa Clara, CA

Symbios LogicFort Collins, CO

Texas Instruments,Advanced CustomProducts (ACP)Dallas, TX

Thesys Gesellschaft FuhrMikroelektronikErfurt, Germany

Tower SemiconductorMigdal Haemek, Israel

Toshiba AmericaElectronic ComponentsSan Jose, CA

TriQuint SemiconductorBeaverton, OR

TSMCHsin-Chu, Taiwan, R.O.C.

UMSHsin-Chu, Taiwan, R.O.C.

Number of Layers(Metal/Poly)

Wafer Size Packages Available

4/2

2 Metal

4/2 (200mm) and3/2 (150mm)

5 Metal

2 or 3 Metal1 or 2 Poly

0.8µm—3/10.6µm—3/20.5µm—3/1

2 or 3 Metal1 or 2 Poly

Up to 4 Layers,Up to 6.3µm

Thick Plated Gold

5/4

4/4 (8" Fab) and3/2 (6" Fab)

150mm and200mm

100mm and125mm

150mm and200mm

200mm

150mm

150mm

150mm and200mm

100mm

150mm and200mm

150mm and200mm

QFPs and BGAs

Standard Open ToolingPackages

PDIP, QFP, TQFP, SOIC,PLCC, and BGA

BGA, CPGA, PPGA, QFP,and TQFP

All Typical Standard

All Commercially Available

PLCC, QFP, PGA, BGA,TAB-FP, TCP, AINCFP,

and FlipChip

SOIC, SSOP, QSOP, andMSOP Surface Mount

Packaging Contracted Out:all Packages Available

TPFP, TSOP, PDIP, SKWY,SOJ, SSOP, and TSSOP

ProductCommitment

RequiredTurnaround Time

3,000 PerYear at 200mm

1,200 WafersPer Year Min.

Under PurchaseAgreement

500 (200mm)and 1,500(150mm)

3,000 WafersPer Year

50 WafersPer Year

ProjectDependent

Negotiable

No Minimum

Negotiable

250

7 Weeks

PG to Wafer Out—14 Weeks

4-8 Weeks

Process Dependentand Expedite Fee

Required. Prototypein 30-65 Days

6 Weeks

33 Days

5-7 Weeks

10 Weeks

Prototype Lots—30Days from Tape toShip. Production—

8 Weeks for P.O.to Ship

5 Weeks (Eng.) and8 Weeks (Normal)

Figure 6-3. Foundries (continued)

The full custom methodology is generally used where the absolute smallest die size or highestperformance is desired or if the technology required is unusual. However, it is an expensiveoption due to the complexity of the layout process.

Figure 6-5 compares the silicon area needed for two circuit modules used in MotorolaÕs68HC08XL36 customer-specific microcontroller by a standard-cell version and a full-custom ver-sion. Although the standard-cell version required over two-times as much area as the custom ver-sion, it was produced more quickly.

Overall, the flexibility and shorter turnaround times of the standard cell-based approach, as com-pared to full custom, will make the cell-based methodology a more popular choice for customASICs in the late 1990Õs and beyond. Nevertheless, there will continue to be some demand forÒhandcraftedÓ ASICs for high-volume, long life, cost-sensitive systems that require the most effi-cient device designs.



Figure 6-4. Sampling of Leading-Edge ASIC Technologies

1995

1996

1997

1996

1997

1998

1995

1997

1996

1997

1998

1995

1997

1996

1997

1996

IBMMicroelectronics

VLSI Technology**

NEC

Toshiba

LSI Logic

LucentTechnologies

Samsung

TexasInstruments

CMOS 5S

CMOS 5X

CMOS 6S

VCS8

VSC9

VSC10

CMOS-9

CMOS-10

TC220

TC230D

TC240D

G10

G11

System-ASIC

STD/KG/MDL90

Timeline

0.25µm

0.4µm

0.18µm

0.3µm

0.18µm

0.15µm

0.27µm

0.18µm

0.3µm*

0.25µm*

0.25µm*

0.25µm

0.18µm

0.32µm

0.35µm*

0.18µm

6

5

6

5

6

6

4

5

3

5

5

5

6

6

4

6

90

70

—

80

55

40

—

—

—

—

—

—

60

50/65

—

—

3.3V

2.5V

2.5V

3.3V

2.5V

1.8V

2.5V/3.3V

1.8V/2.5V

3.3V

3.3V

2.5V

2.5V/3.3V

1.8V/2.5V

2.5V/3.3V

3.3V

1.8V/2.5V

Year Series FeatureSize (Leff)

MetalLayers

GateOxide (Å)

VoltageCompany

19177ESource: ICE

* Drawn gate length** Developed jointly with Hitachi

GATE ARRAY, EMBEDDED ARRAY, AND CELL-BASED ASICs

The primary ASIC methodologies in use today are CMOS gate array, embedded array, and stan-dard cell. Which methodology to use depends on the particular application. Figure 6-6 shows acomparison of the three techniques.

As already mentioned, the ASIC methodology is increasingly being used to build systems on achip, which requires blocks (or cores) of high-performance memory, processor, and special I/Ofunctions. This rise in complexity is the reason behind the prediction that standard cell andembedded array ASICs will dominate over gate arrays before the end of the decade. The transis-tors in gate arrays are generally not laid out conveniently for some of the more-complex logicfunctions, resulting in more interconnections (and a larger chip).

Cores may be selected from a vendorÕs core library and ordered, like a product off the shelf, fordesign into a standard cell or embedded array ASIC. Advanced cores featured in some corelibraries include high-performance RISC or CISC microprocessors, MPEG coder/decoders, net-work communications controllers, high-density memories, and high-performance analog functions.



STANDARD-CELLVERSION

FULL-CUSTOMVERSION

SCI08

SIM08130mils

48mils

SIM08 SCI08 48mils

48mils

Source: EBN/Motorola 21256

Figure 6-5. Comparison of Silicon Requirement for Standard Cell andFull Custom Layouts (Based on MotorolaÕs 68HC08XL36 MCU)

Shown in Figure 6-7 is a macrocell/core roadmap for Lucent Technologies, the worldÕs largeststandard cell ASIC supplier in 1996. Several other companies offering hardware-based and soft-ware-based cores and megacells are listed in Figures 6-8 and 6-9.



21257Source: Computer Design

DesignFlexibility

Number ofStandard Die

Sizes (Typical)

PrototypeManufacturing

TimeDesign Changes Core Availability Memory Density NRE Cost

FactorDetermining Use

Design cost, time tomarket

Megacell performance/density; standardmasters for customizedvariations (i.e., µP-basedprint engines)

Maximum customizationability; need for highpercentage ofcustomized design (i.e.,data paths with littlestandard logic)

Lowest

Needs to coverfull mask setand processing

Needs to coverfull mask setand processing

Low (metal limited)

High (diffused) +very high (DRAM)

High (diffused) +very high (DRAM)

MetallizedRAM/ROM;controllers; standardfunctions, etc.

Microcontrollers;microprocessors;DSP; SRAM; DRAM

Microcontrollers;microprocessors;DSP; SRAM; DRAM

Fast (onlymetal layers)(QTAT = 3 days)

Fast (if onlymetal changerequired)

Usually needsall mask stages

Fast (only metallayers); typicalTAT* = 1-2 weeks;QuickTAT = 3 days

Needs all maskstages (base layerscan be signed offearly, reducingTAT); typical TAT =1-12 weeks

Needs all maskstages; typicalTAT = 6-12 weeks

14

30

30

Medium

High

High

GateArray

EmbeddedArray

StandardCell

* Turn-around time

Figure 6-6. Gate Array, Embedded Array, and Cell-Based ASIC Comparison

Video ScalerVideo Decoder

Video-DACAudio DAC/ADC

Card Bus InterfaceI2C Bus Interface

68K RISCSPARCDSP

LCD ControllerZ180 µC

USB Interface

C5x DSP12-bit DAC/ADC

Fiber Channel Controller

ISDN-S InterfaceTI/EI Framer

FDDI/Tx Transceiver1627 DSP

Multimedia, PLLExtensions

RISC Core ExtensionsP1394 Serial Port

DSP Core ExtensionsFiber Channel Transceiver

ATM InterfaceRAMBUS Interface

MPEG DecoderPCI Controller

Fast SRAM120-200MHz PLL

960-RISCZ80 µC

C2XLP DSP

10 Base-T MAC updates10/100 Base-T MAC

6-port SRAMHDLC Controller

PC

OfficeAutomation

DataCommunications

Telecom

Application 1995 1996 1997

21200Source: Lucent Technologies

Figure 6-7. Lucent TechnologiesÕ Macrocell Roadmap



CompanyLocation

Functions Process Rules Models Test

ARM 7 32-bit RISC L-drawn: 0.6µm— ASIC/ASP for simulators JTAGprocessor 3 metal & 1 poly

ARM7TDMI 32-bit RISC 0.6µm—3metal & ASIC/ASP for simulators JTAG parallel vectorsprocessor 1 poly

ARM810 RISC processor 0.5µm—3 metal & ASIC/ASP for simulators JTAG1 poly

DSP 0.6 & 0.5µm— Verilog behavioral timing Serialized functional2 metal & 1 poly accurate test using 1 dedicated

and 9 mixed pins

ARM7DMI 32-bit RISC & 0.7µm—2 metal Verilog and VHDL Testbenches andARM7TDMI 16-bit RISC 0.5µm—3metal interface C model vectors

0.7µm—2metalEEPROM

FIFO, RAM, & ROM 3 metal Gate level & RTL Verilog From simulationvectors

Programmable PLL and 0.35µm (& larger)— None AvailableVCXO cores for frequency 2 or 3 metal & 1 orsynthesis 2 poly

ARM7TDMI Thumb RISC 0.6µm drawn Cycle accurate, VHDL, Test vectors for core32-bit MPU CMOS Cadence Verilog included

Oak DSP 0.6µm drawn Behavioral, instruction N/ACMOS accurate, & RTL

Pine DSP 0.6µm drawn Behavioral, instruction N/ACMOS accurate, & RTL

Processors H8, SH1, SH3, N/A RTL Available& H8S

PowerPC 401, cMC186, PCI, 0.18 & 0.36µm— ATPG, floorplanning, ATPG & full scanUSB, RAMBUS, VGA, MPEG2 6 metal static timing, synthesis,decoder, RAMDAC, Ethernet, Verilog, & VHDLSonet, triple 10-bit VideoDAC, & JPEC compression

CAM 0.5µm & 0.35µm Verilog & VHDL Test vector for coreincluded

ASIC DRAM 0.8µm & 0.35µm Verilog & VHDL Test vector for coreincluded

ATM-interworking multi-layer 0.65µm, 0.5µm, & Verilog & VHDL Test vector for coreswitching core 0.35µm included

8-bit CPU & peripherals 0.65µm, 0.5µm, & Verilog & VHDL Test vector for core0.35µm included

USB & PCI 0.5µm & 0.35µm Verilog & VHDL Test vector for coreincluded

PLL 0.65µm, 0.5µm, & Verilog & VHDL Test vector for core0.35µm included

ADC & DAC 0.65µm, 0.5µm, & Verilog & VHDL Test vetor for core0.35µm included

32- & 64-bit RISC cores, DSP, 0.35µm—3 metal Behavioral, Verilog, Scan & vectorsPCI-64, Fibre channel, Ethernet, & 1 poly & VHDL modelsATM SAR, NTSC/PAL encoder, 0.6µm—2 metalViterbi decoder, Reed-Solomon & 1 polydecoder, D-A & A-D converters

Advanced RISCMachinesLos Gatos, CA

Analog DevicesNorwood, MA

AtmelSan Jose, CA

Chip ExpressSanta Clara, CA

Focus SemiconductorLower Gwynedd, PA

GEC PlesseySemiconductorsSan Jose, CA

Hitachi America,Semiconductor &I.C. DivisionBrisbane, CA

IBM MicroelectronicsHopewell Junction, NY

Kawasaki LSI, USASanta Clara, CA

LSI LogicMilpitas, CA

23182Source: Integrated System Design

Figure 6-8. Hardware-Based Megacells and Cores



CompanyLocation

Functions Process Rules Models Test

68000 microprocessors 0.65µm Timing accurate Verilog Broadside vectorsBLM

ColdFire 2M 0.65 & 0.42µm Gate-level timing Scanaccurate

68020 0.65µm Gate-level timing Scanaccurate

68030 0.65µm Gate-level timing Scanaccurate

DMA controller, Ethernet, 0.5-0.8µm DLM & Gate & RTL ATPG & boundaryPCI, PCMCIA, & UART w/FIFO TLM scan

UART (with FIFO) 0.6µm CMOS EDIF & RTL Simulation vector

CPU (4 & 8 bits) 0.6µm CMOS Behavioral Simulation vector

CPU (8 bits, Z80 compatible) 0.6µm CMOS Behavioral Simulation vector

SIO (for Z80) 0.6µm CMOS EDIF & RTL Simulation vector

PIO (for Z80) 0.6µm CMOS EDIF & RTL Simulation vector

Multiplier 0.6µm CMOS RTL N/A

Adders 0.6µm CMOS RTL N/A

Subtracter 0.6µm CMOS RTL N/A

ALU 0.6µm CMOS RTL N/A

ROM (Asynchronous, 128Kbits) 0.6µm CMOS RTL N/A

SRAM (Dual Port, 32Kbits) 0.6µm CMOS RTL N/A

SRAM (Synchronous, 32Kbits) 0.6µm CMOS RTL N/A

SRAM (Asynchronous, 64Kbits) 0.6µm CMOS RTL N/A

FIFO controller 0.6µm CMOS RTL Simulation vector

100-Mbit Ethernet TX PHY 0.5µm CMOS Schematic & HSPICE N/ASimulation

SYM7TDMI (ARM7 Thumb VS350, 3 metal, 0.5 Testbench, timing Scan support orcore) L-drawn, 0.35 accurate, Verilog, & parallel vectors

L-effective wrapped C

TMS320C2xLp, TMS320C52C, 0.35-0.55µm—3 Behavioral & gate-level JTAGand TMS320C54x metal & 3-D 1/2 simulation, timing accurate,

poly Mentor, Verilog, & VHDL

High-speed memories 0.25-0.35µm—3, 4, Verilog & VHDL Optional scanor 5+ metal & 1 poly & test vectors

Low-power memories 0.25-0.35µm—3, 4, Verilog & VHDL Optional scanor 5+ metal & 1 poly & test vectors

High-speed cache memories 0.25-0.35µm—3, 4, Verilog & VHDL Optional scanor 5+ metal & 1 polu & test vectors

High-speed multipliers 0.25-0.35µm—3, 4, Verilog & VHDL Optional scanor 5+ metal & 1 poly & test vectors

W65C816C 0.8µm—2 metal Behavioral, extracted Sentry test vectors& 1 poly Spice, layout, testbench, & simulation vectors

transistor, & Verilog gate







Motorola, HighPerformanceEmbeddedSystems DivisionAustin, TX

Oki SemiconductorSunnyvale, CA

ROHM Electronics,a Division ofROHM Corp.San Jose, CA

Sierra Research andTechnologyWestlake Village, CA


Texas InstrumentsHouston, TX

VLSI LibrariesSan Jose, CA

Western DesignCenterMesa, AZ

Source: Integrated System Design 23183

Figure 6-8. Hardware-Based Megacells and Cores (continued)



CompanyLocation

Number ofGates

TargetProcesses

Functions Language Models

8-, 16-, 32-bit microcontrollers, Verilog & VHDL Gate & RTL 4k-40k All vendorsDSP, Ethernet, floppy controller,LAN, peripheral controllers,PCMCIA, & SCSI interface

PCI—Master, Target, Bridge, Verilog & VHDL RTL 2.7k-7.6k Actel ACT 3 PCI& Combinations

Sonet & SDH UNI processor for Verilog RTL 30k-100k CMOS 0.8µmATM (OC3 & OC12), QUAD UNI or betterprocessor core (OC3), SARprocessor core, Sonet & ATMclock core

8-bit microprocessor 6502 Altera AHDL Functional gate 7k Altera FLEX

DMA controller 8237 Altera AHDL Functional gate 3.7k Altera FLEX& VHDL

Arithmetic & datapath Verilog, VHDL, Gate Depends on All AMI processesfunctions & various function, width,

schematics & speeds

Synchronous & Same as above Gate & RTL Depends on All AMI processesasynchronous FIFOs width & depth

DSPs Same as above Gate & RTL 16k-40k All AMI processes

Microprocessors & controllers Same as above Gate 1k-10k All AMI processes

UARTs, USARTs, & Same as above Gate & RTL 600-13,000 All AMI processescommunication controllers

Floppy disk controller Same as above Gate & RTL 7.1k All AMI processes

Floppy disk controllers & Same as above Gate & RTL 900-8,100 All AMI processesinterfaces

RAM & ROM Same as above RTL Depends on All AMI processeswidht & depthof memory

Microcontrollers 8031, Verilog HDL 7.5k-9k + Depends on8032, 8051, & Turbo-8031 SRAM synthesis target

libraries

Communications 8530 Verilog HDL 13k Same as above

Peripheral 8237 Verilog HDL 4k Same as above

Bus controllers 82365 Verilog HDL 11k Same as above(PCMCIA Host i/f)

Microcontrollers 8031 & 8051 Verilog HDL RTL 8k + SRAM 0.6 & 0.5µm UMC+ ROM -8051

Interrupt controller 8259 Gate Verilog Gate 4k 0.5 & 0.6µm UMC

8051, 8237A DMA, 82530, Structural Verilog & VHDL 4k-12k AT26K (0.6µm TLM),PCI, USB, PCMCIA/PC Card netlist, ecpd07 (0.7µm DLM),

schematics, ecat05/AT55KVerilog & VHDL (0.5µm TLM) e19600

(0.7µm DLMEEPROM process)

High-end DSP, FFTs, digital filters VHDL RTL 10k CMOS 0.8µm,DFT filter banks, modulators, 0.5µm, & 0.35µmADSL, OFDM, polyphase, etc.

C2910 VHDL Gate, RTL, & 1.5k Alltiming

DMA VHDL Gate, RTL, & 18k Alltiming

ActelSunnyvale, CA

Advancel LogicSan Jose, CA

AlteraSan Jose, CA

AmericanMicrosystemsPocatello, ID

ARM SemiconductorTechnologiesHyderbad, India

ASIC SemiconductorInternationalSanta Clara, CA

AtmelSan Jose, CA

Butterfly DSPVancouver, WA

CASTPomona, NY

3Soft, a MentorGraphics CompanySan Jose, CA


Figure 6-9. Software-Based Megacells and Cores



CompanyLocation

Number ofGates

TargetProcesses


PCI, RISC processors, ATM Verilog RTL 10k-40k 0.8µm & 0.6µm& Ethernet controller

8- & 16-bit microcontrollers, Verilog & VHDL Gate & RTL 4k-50k 0.8µm & lessperipheral controllers, SCSI,LAN, Ethernet, & DSP

PCI target VHDL RTL 4k Cypress

MIDI (extended MIDI) Altera AHDL, Gate & timing 2.5k Altera MAX-7000protocol interface schematic, & FLEX-10K, EDIF

& VHDL

PCI target EC100; PowerPC bus Verilog & VHDL RTL 4k All ASIC vendorsslave EP100, bus master EP201, + FPGA& bus arbiters EP300/310

Communications controller Cadence Verilog Gate & RTL 18k 0.8µm & 0.6µmM85C30 netlist, Mentor, drawn CMOS

Verilog RTL,& VHDL RTL

Communications controller Same as above Gate & RTL 13k 0.8µm & 0.6µmM82530 drawn CMOS

Floppy disk controller Same as above Gate & RTL 11k 0.8µm & 0.6µmsystem MFDC drawn CMOS

Floppy disk controller M765A Same as above Gate & RTL 10k 0.8µm & 0.6µmdrawn CMOS

Microcontroller M8051 Same as above Gate & RTL 8k 0.8µm & 0.6µmdrawn CMOS

DMA controller M8237A Same as above Gate & RTL 4k 0.8µm & 0.6µmdrawn CMOS

Third-party provider MPEG, Verilog & VHDL RTL 5k-30k Hitachi 0.6µm &UART, PCI, PCMCIA, IEEE 1284 0.35µmparallel port Ethernet, SCSI-IICRT controller, & others

PowerPC microprocessor Verilog & VHDL Floorplanning, 25k IBM's CMOS5Ssynthesis test, (0.36µm L-effective)& timing process. Other

ASIC libraries

PowerPC on-chip peripheral Verilog & VHDL Bus functional 3.9k IBM standard cellbus controller model, design library

source, synthe-sis, & timinganalysis scripts

Memory or peripheral interface Verilog & VHDL Design source, 14k IBM standard cellto off-chip resources synthesis, & library

timing analysisscripts

Four-channel DMA controller Verilog & VHDL Same as above 16k IBM standard celllibrary

UART with FIFO Verilog & VHDL Same as above 5.5k IBM standard celllibrary

ADPCM VHDL Gate 14.8k, + 280 bits All vendors(structural) RAM per channel

FIR filter VHDL RTL approx. 20k Altera Flex10k

Crosspoint SolutionsMilpitas, CA

Cypress SemiconductorSan Jose, CA

Chip ExpressSanta Clara, CA

Digital Design &DevelopmentMeise, Belgium

Eureka TechnologyLos Altos, CA

GEC PlesseySemiconductorsSan Jose, CA

Hitachi America,Semiconductor &I.C. DivisionBrisbane, CA

IBM MicroelectronicsHopewell Junction, NY

Integrated SiliconSystemsBelfast, Northern Ireland


Figure 6-9. Software-Based Megacells and Cores (continued)



CompanyLocation

Number ofGates

TargetProcesses


64-bit PCI bus master Verilog & VHDL HDL & netlist N/A All vendors appli-cation specificports to Altera,Xilinx, & LucentTechnology PLDs

32-bit PCI bus master Verilog & VHDL HDL & netlist N/A All vendors

2-bit PCI bus target Verilog & VHDL HDL & netlist N/A All vendors

ATM switch Verilog & VHDL HDL & netlist N/A All vendors

JTAG TAP, Logic BIST control- Verilog or VHDL RTL models & Depends on All vendorsler, & memory BIST controller testbench implementation

DSP Verilog & VHDL N/A Variable ORCA 2C, 2CA,(parameterized) 2TA & FPGAs

PCI master Verilog & VHDL N/A 8k ORCA 2C, 2CA,2TA & FPGAs

PCI target Verilog & VHDL N/A 6k ORCA 2C, 2CA,2TA & FPGAs

Flex peripherals, SRAM, Verilog RTL Design 0.65 & 0.43µmdual-port RAM, ROM, SPI dependent& 1284

PCI & PCMCIA Verilog & VHDL Gate & RTL 15.5k-22k N/A

MAC110—dual-speed Verilog RTL 5k-12k All vendors,media access controller 0.8µm or better

UART16550, FastATA/ATAPI Verilog Behavioral, 4k-10k All vendorsUSB, JPEG compression ECC synthesizable(triple correction) RTL, & timing

UART (with FIFO) Verilog & VHDL RTL 10k 0.6µm ROHM

SIO (for Z80) Verilog & VHDL RTL 10k 0.6µm ROHM

PIO (for Z80) Verilog & VHDL RTL 10k 0.6µm ROHM

FIFO controller Verilog & VHDL RTL 10k 0.6µm ROHM

Adders Verilog & VHDL RTL Adjustable 0.6µm ROHM

Multiplier Verilog & VHDL RTL Adjustable 0.6µm ROHM

ALU Verilog & VHDL RTL Adjustable 0.6µm ROHM

32- & 34-bit PCIs Verilog & VHDL RTL 10k All vendors,technologyindependent

USB device, host, & hub Verilog & VHDL RTL 5k-20k All vendors,technologyindependent

National Semiconductor Verilog Gate & RTL 5k (no RAM & All vendorsCOP8 microcontroller ROM)

PCI arbiter, master, & target Verilog Gate & RTL 12k All vendors

8237 DMA controller with Verilog Gate & RTL 12k All vendorsscattered/gathered

LogicVisionSan Jose, CA

Lucent TechnologiesAllentown, PA

Motorola, HighPerformanceEmbedded SystemsDivisionAustin, TX

Oki SemiconductorSunnyvale, CA

Packet EnginesSpokane, WA

PalmchipLos Gatos, CA

ROHM ElectronicsSan Jose, CA

Sand MicroelectronicsSanta Clara, CA

ScenixSemiconductorSanta Clara, CA

Logic InnovationsSan Diego, CA



Demand for DSP core-based ASICs is surging in high-volume, cost-sensitive applications such aswireless and wireline communications, consumer electronics, and multimedia computers.Although a DSP core can be used to process analog functions, it may or may not be the most effec-tive solution, depending on the application. As a result, demand for ASICs incorporating analogcircuitry continues to be strong. Furthermore, functions like audio, imaging, temperature sensing,and frequency modulation will always require at least an analog, or Òreal worldÓ interface.



CompanyLocation

Number ofGates

TargetProcesses


ATM SAR 622Mbits Verilog Gate & RTL 275k 0.8µm CMOS

Ethernet controller 100/10-Mbits Verilog Gate & RTL 55k 0.8µm CMOS

CPU core R3000 Verilog Gate& RTL 40k 0.8µm CMOS

Micro VGA Verilog Gate, RTL, & 17k All vendorstiming

SYM1000 Verilog RTL behavioral 8k 0.5µm & 0.35µm& timing

PCI Verilog RTL behavioral 10k 0.5µm & 0.35µm& timing

Datapath (DesignWare Verilog & VHDL Synthsizable N/A N/AFoundation Library—100+ RTL & simula-components—ALU, advanced tionmath, sequential, test anddebug, data integrity families)

ISA plug-and-play bus Verilog & VHDL Bus functional 6k N/Ainterface controller model, simula-

tion & synthe-sizable RTL

Microcontrollers 8051, 8052, Verilog & VHDL Simulation & 10k-13k N/A8031, & 8032 synthesizable

RTL

8- & 6-bit microprocessor, Verilog & VHDL RTL 4k-28k TechnologyEthernet, & HDLC independent

(Altera & 0.8µmCMOS numbersavailable)

PCI Verilog & VHDL Synthesizable Approximately All vendorsRTL. Test envi- 7k gatesronment includ- (excludinging bus simula- FIFOs)tion models

USB Function Verilog RTL. Test envi- 7k-9k All vendorsronment includ-ing bus simula-tion modelsalso available

W65C02C Verilog Behavioral & 3,244 All vendorssynthesizable

PCI slave & PCI master Verilog & VHDL Bus model, gate, Slave 4.5k & XC4000E-2Verilog, & VHDL Master 5.5k

Silicon EngineeringScotts Valley, CA


SynopsysMountain View, CA

VAutomationNashua, NH

Virtual Chips Groupof PhoenixTechnologiesSan Jose, CA

Western DesignCenterMesa, AZ

XilinxSan Jose, CA

Sierra Researchand TechnologyWestlake Village, CA



Applications such as HDTV, cellular communications, multimedia, teleconferencing, voice syn-thesis/recognition, modems, etc., are pressuring standard cell vendors to offer state-of-the-artmixed-signal capabilities. Unfortunately, the sophisticated design, manufacturing, and testing ofmixed-signal devices continues to pose formidable challenges.

As evidence to the significance of the mixed-signal ASIC industry, NEC has said that about one-third of its standard cell customers desire analog circuitry in their chip designs. SGS-Thomson isone example of a large standard analog IC supplier using its analog expertise and experience toenhance the mixed-signal capabilities of its standard cell product line. National, Harris, andLucent Technologies are other examples of this trend.

Analog and mixed-signal arrays continue to represent a niche ASIC technology. Most of theanalog array companies do less than 25-50 designs per year, quite small when compared to thelarge number of digital gate array designs realized each year. Overall, very high-end analog andmixed-signal ASIC requirements are still best handled by standard cell or full custom approaches.

One of the hottest ASIC segments is the embedded-DRAM cell-based market. Although theembedded-DRAM ASIC market will be only about $1.0 billion in 1997, Toshiba expects thismarket to surge to $5-$6 billion in 2002. Figure 6-10 shows some of the companies offering embed-ded-DRAM technology.

As is shown in Figure 6-11, the initial applications for embedded-DRAM ASICs were for graphicsand desktop imaging applications. In these systems only 1M or 2Mbits of DRAM were required.In 1998, embedded-DRAM 0.25µm ASICs with up to 128Mbits of DRAM are expected to be avail-able from Toshiba.



Chartered Semiconductor

Hitachi

LSI Logic/Micron*

Mitsubishi

Motorola

NEC

Oki

Samsung

SGS-Thomson

Toshiba

TSMC

VLSI Technology

Company

Licensed technology from Toshiba

Plans to begin offering embedded-DRAM ASICs in October 1997

Joint effort to embed 1M-2M bytes of DRAM in ASICs

In March 1996 combined 2M bytes of DRAM with a 32-bit RISC CPU

Acquired rights to Mitsubishi technology

Developing embedded-DRAM ASICs

Developed embedded-DRAM graphics controller with Silicon Magic

Began offering embedded-DRAM ASICs in late 1996

Developing MPU/DRAM devices

Targeting ASIC marketplace

Will offer foundry customers a 0.35µm embedded-DRAM process in 2H97

Plans to begin offering embedded-DRAM technology in 1998

Comments

Source: ICE 22743

* Micron will fab base wafers while LSI Logic will add final metal layers.

Figure 6-10. Sampling of Embedded-DRAM Offerings

Although large blocks of DRAM will most likely be available from ASIC vendors in the future, thesystem needs for such large amounts of on-chip DRAM are not obvious. The cost/benefit of on-chip DRAM becomes less clear about 24M-32Mbits. Many of the current embedded-DRAM ASICproducers have already voiced concern over the current lack of clear customer roadmaps for sys-tems needing large blocks of on-chip DRAM.

Recent notable announcements regarding gate array, embedded array, and standard cell tech-nologies are provided below.

¥ Toshiba has developed a MIPS embedded processor architecture that it will use to launch itscore-based ASIC business. Based on the MIPS 16 instruction-set architecture, the TX19family will comply with the Virtual Socket Interface alliance guidelines and will use the com-panyÕs 0.35µm TC220 ASIC process. Toshiba is also looking to combine its reusable proces-sor cores with embedded DRAM (trench capacitor) using its new 0.25µm TC240 process.Some details concerning the TC240 process are provided below.



Set-Top Box

3D/2D Graphics

DVD

PC Peripheral

Network Computer

Printer

Wireless Communication

CDG

CDP

Video CD

Digital Camera

Sound Systems

Mass Storage

Alpha CPUArm 7 Family

OakDSPCoreVideo Encoder/Decoder

JAVA80C52

Z-80A/D, D/A

PCIMPEG

CODEC300MHz RAMDAC/PLL

0.5 micron

0.35 micron

0.25 micron

0.18 micron

400K

100K

60K

1996 1997 1998 1999

1Mbit

24Mbits

~32Mbits

TBD

Gat

e C

ou

nt

Source: Samsung 22719

Figure 6-11. Optimization of Cell-Based Logic/DRAM/Analog for System-On-A-Chip Solutions

Technology: 0.25µm drawn gate length, 5-layer metalMax. Gate Count: Over 10M (35K/sq. mm.)Gate Delay: 80ps (loaded 2-input NAND, FO=5, 2.5V)Cores: MIPS MCU, MPEG2, JPEG, up to 128M DRAMProduction Volumes: 100,000/month starting May 1998Cost: Approx. $345 for a 3M-gate device in lots of

10,000 units/month

¥ Hitachi recently introduced its first ASICs with embedded DRAM to the U.S. market*.Based on a 0.28µm DRAM process that is merged with a 0.35µm logic process, the HG73MSeries integrates 200,000 logic gates and 16M embedded DRAM. The company claims theASICs can support up to 140M of DRAM when the chip size is enhanced.

¥ SGS-ThomsonÕs new high-performance multimedia PC on a single chip device, known as theST PC Consumer, was designed using an ASIC-like reusable modular design technique,which allows for custom variants to be rapidly created. The heart of the ST PC Consumer isan advanced 64-bit processor block that contains a 32-bit x86 PC-compatible MPU, a 64-bitDRAM controller, a 64-bit accelerated graphics and video controller, and a high-speed PCIlocal bus controller.

¥ Mitsubishi has developed a 1V ASIC technology using an SOI (silicon-on-insulator) wafer.Sample shipments will start in November 1997 of a 560,000-gate ASIC that is implementedin a 0.35µm process, operates at 50-150MHz on 1.0-2.0V, and has a gate delay time of 200ps.

¥ Samsung unveiled in 2Q97, a 0.35µm ASIC family capable of integrating up to 24M ofsingle-transistor synchronous or EDO DRAM. Details regarding the technology are pro-vided below. The company plans to move to a 0.25µm process technology in 1998 and0.18µm in 1999.

Technology: 0.35µm, 3/4-layer metal, 3-layer poly/Ti-salicideMax. Gate Count: Over 2M (18K/sq. mm.)Gate Delay: 150ps (3.3V, loaded 2-input NAND)Cores/Macrocells: ARM MPU, Oak DSP, MCU, A/D and D/A,

RAMDAC, video encoder/decoder, up to 24M single-transistor DRAM

Production Volumes: Start in 4Q97Cost: NRE charges begin at $100,000



* Hitachi has been embedding DRAM internally for two years and has been selling them to limited OEMs in Japan.

¥ In April 1997, VLSI Technology announced a pair of deep-submicron standard-cell ASICprocesses. The VSC9 process is optimized for 2.5V operation and uses 0.25µm drawn gates.The VSC10 process is optimized for 1.8V operation and uses 0.2µm drawn gates. Advancedfeatures common to both processes, which were jointly developed with Hitachi, include shal-low-trench isolation, self-aligning salicide, and CMP of vias as well as oxide.

¥ NEC announced that in October 1997 it will begin commercial production of ASICs with0.25µm drawn gate lengths. The new CMOS-10 family of ASICs will be targeted at high-endworkstations and cellular base stations. Details are provided below.

Technology: 0.25µmMax. Gate Count: Up to 20MGate Delay: 40ps (2.5V, loaded 2-input NAND, FO=2)Clock Frequency: Up to 300MHzCores/Macrocells: Mips/ARM RISC MPUs, V-series MPU, DRAMCost: NRE charges will be in the $410,000 range

¥ In early 1997, GaAs IC vendor, Vitesse introduced its first family of standard cell ASICs,which are targeted at telecommunications and high-speed switching applications. Dubbedthe SLX line, the family consists of five devices with gate densities ranging from 10K to 220Kgates while operating from a single 3.3V power supply. The SLX family is based on a 0.4µmfour-layer metal HGaAs-IV process.

¥ In early 1997, TSMC revealed the specifics of its 0.35µm process that combines embeddedDRAM with ASIC devices. The process, called BlendIC, employs a triple-well base method,which allows the four-poly, two-metal DRAM process to be combined with the single-poly,three- or four-metal ASIC process.

¥ In early 1997, LSI Logic announced its next-generation G11 process technology featuring a0.25µm (drawn) gate length, providing up to 64 million transistors or 8.1 million usablegates. Initial production of G11 ASICs is due to begin in 4Q97.

PLDs (CPLDs AND FPGAs)

ICE includes under the generic term PLD the simple PAL devices, the complex programmable(CPLD) devices and the field programmable gate arrays (FPGA).

The first field programmable logic devices were introduced almost 25 years ago. Figure 6-12 showsa programmable logic device timeline with product introduction highlights labeled. Basically, thebenefits of using programmable logic have been shortening time to market and risk reduction.This has been true for over 20 years and will continue to be true in the foreseeable future.



In an industry as dynamic as the IC industry, the natural trend has been toward high-density andhigh-performance technologies. In the PLD market this is very obvious as simple bipolar PLDs arenow steadily losing marketshare to the more flexible and higher density CMOS PLD technologies.

Figure 6-13 shows how PLDs fit in an overall logic alternative comparison. As was mentioned,Òdevelopment lead timeÓ and Òease of design changesÓ are where PLD technology shines.

Figure 6-14 shows the PLD gate densities expected to be achieved by the end of the decade. Thefigure also shows that along with the large increases in PLD gate density come some of the sameÒdesign productivityÓ issues that the gate array and cell-based ASIC suppliers must deal with.Luckily, the programmable logic design tool industry can pull some productivity enhancementstrategies from existing gate array and cell-based tools.

A hot topic in PLDs is the Intellectual Property (IP) integration. Megafunctions are pre-designed,pre-tested logic building blocks and are developed either by the manufacturers or by third-partiesdesign houses. By utilizing these megafunctions in CPLDs and FPGAs, test/characterization aswell as test vector generation of these circuits takes zero hours and other design characteristicstake significantly less time than traditional ASICs, as illustrated in Figure 6-15. The use of mega-functions allows also one to improve the chip size.



1972FirstFPLA

Introduced

1979NationalSecondSources

PAL

1978MMI'sPAL

Debuts

1980PAL

DeviceBecomesStandard

1984Altera'sEPLD

Introduced

1989AMDReplacesUV withSecondSourceGAL Device

GAL DeviceBecomesStandard

1995MultipleHigh-Density (>10KGates)PLDs Emerge

1991High-DensityCompetitors

EnterMarket

1982-3OthersEnterPAL

Market

1985FirstE2CMOSPLD GALDevice

XilinxSRAMFPGA

18556ASource: Lattice

1970 1980 1990

Figure 6-12. Programmable Logic History



Time to market

Development lead time

Development cost

Availability

Available sources

Volume independence(sensitivity)

Application support

Architectural flexibility

Ease of design changes

Performance

Density

Cost of design changes

Solution efficiency

Short/medium

Immediate

None

High

Many

Low

Much

Low

Medium

Low/medium

Low

Low/medium

Low

Short

Immediate

Low

High

Many

Low

Much

Medium/high

High

Medium

Medium

Low

Medium

Medium

Weeks/months

Medium/high

Medium

Few

High

Some

High

Low

High

Very high

High

High

Medium

Weeks/months

Medium/high

Medium

Few

High

Some

Higher

Lower

High

Very high

High

High

Long

Years

Very high

Low

Few

High

None

Highest

Lowest

Very high

Very high

Very high

Very high

18557ASource: AMD

StandardComponents PLDs Gate Arrays Standard Cells Full

CustomCriterion

Figure 6-13. Selection Criteria for Different Logic Alternatives

Figure 6-14. PLD Design Productivity Gap

Year

1985 1990 1995 2000

100

1,000

10,000

100,000

1,000,000

DesignProductivity

Gap

HDL Impact

Gat

es

PLD IntegrationCapability

PLD DesignerProductivity(Gates/month)

Source: Altera 21202

Megafunctions developed by PLD manufacturers are optimized for their products. Every majorCPLD/FPGA supplier has recently announced the availability of a library of system-levelcores/megacells that can be embedded in their device designs, thereby allowing PLDs to be usedas system-level chips. Blocks of circuitry that can be embedded in some of todayÕs PLDs includeSRAMs, ROMs, ALUs, DSP filters, and even MPU and MCU functions.

Embedded functionality is opening up a variety of new applications for PLDs, includingAsynchronous Transfer Mode (ATM) data communications, Peripheral Component Interconnect(PCI), and DSP functions such as filtering. Some of the companies offering DSP-tailored PLDsinclude Altera, Atmel (AT6000 FPGAs), and Xilinx (XC4000 series).

Megafunctions developed by independent design houses typically are portable, and dependingon the purchase agreement, can be modified. Independent developers of Intellectual Property (IP)offer the largest libraries available today.

Altera has been one of the main companies active on IP. Altera developed an alliance of inde-pendent developers call Altera Megafunction Partners Program (AMPP).

The application requirement tends to drive the decision in determining to specify CPLDs orFPGAs. Figure 6-16 shows comparisons between these two architectures. The CPLD is a hierar-chical arrangement of multiple PAL-like blocks. The building block of a CPLD is a product-term-based architecture. A programmable AND-OR array is used to implement sum-of productequations. The FPGA offers fully flexible interconnects, fully flexible logic arrays, and requiresfunctional placement and routing. The building block of a FPGA is a function generator, with ann-bit lookup table, capable of generating any output of n inputs.

But the CPLD and FPGA market is evolving very fast. The designer should consider a new designan opportunity to investigate new architectures and new tools. A change in methodology mayyield dividends for the new design.



ASIC

PLD/Megafunction

ArchitectSystem

SystemDesign

Test VectorGeneration

Prototype/Debug

TestCharacterization

80 Hours

80 Hours

960 Hours

240 Hours

160 Hours

0 Hours

120 Hours

80 Hours

160 Hours

0 Hours

Source: Altera 23181

Figure 6-15. ASIC Versus PLD/Megafunction

CPLDs

In-System-Programming (ISP) allows CPLDs to be programmed after they have been mountedon a printed circuit board (PCB). In the prototyping stage, design revisions can be compiled andprogrammed into the devices in minutes. In production, ISP simplifies the manufacturing flowby allowing devices to be programmed during board test by automated test equipment. Figure 6-17 illustrates the conventional PLD flow versus an ISP PLD flow.

Another advantage of ISP is the possibility of programming fine-pitch packages on-the-board,eliminating a potentially damaging programmer insertion.



Function CPLD FPGA

Logic Cell

Granularity

Interconnect

Register Intensive

Density

Performance

Program Storage

Power Consumption

On-Chip RAM

Cores

Sum-of-products

Coarse-grained, efficientlysynthesizes wide logic

functions

Continuous

Typically one flip-flop perlogic cell

Up to 12,000 gates, 560logic cells

Very high performance andvery predictable

On chip-EPROM, EEPROM,flash, many are now in-system

programmable

Typically high due to EEPROMor flash

None

None

Lookup table

Fine-grained, wide logicfunctions require multiple

logic cells

Segmented, distributed

At least one flip-flop per logiccell plus additional flip-flops

in the I/O

Up to 130,000 gates, 6,500logic cells, surpassing 250,000

gates by 1998

High performance, but veryrouting-dependent

On chip-anitfuse; off-chipexternal RAM or ROM

required

Typically high-antifuse,typically low-SRAM

Up to 32Kbits, suitable forFIFOs, register files, PROM

tables, dual ports, etc.

Increasing quantity of DSP,micro-peripheral, micro-controller, interface and

communications cores arebeing developed by third-party intellectural-property

vendors specifically forFPGA synthesis

Source: Wyle Electronics 23186

Figure 6-16. Traditional Differences Between CPLDs and FPGAs

In the field, systems using ISP, enabled devices can be upgraded with new configurations down-loaded via modem or other data links. This ability to make changes is also called In-System-Reprogrammability (ISR). ISR has to avoid pinout and/or timing changes.

Some possible early system applications for reprogrammable logic include telecommunications,geophysical information processing, medical imaging, and computer architecture simulation. Inthe telecommunications area one can easily envision the need for a PLD device to dynamicallyreconfigure itself to accommodate multiple interface or telecommunications protocols and stan-dards (Figure 6-18).

As another example of a reconfigurable application, Altera states that its reprogrammable PLDscan be configured as a display accelerator or circuit simulator as needed. Altera says Òthat byusing reprogrammable logic the potential exists to configure the hardware for more direct pro-cessing of the data.Ó estimated at approximately $200 million.

There is little doubt that reconfigurability will be a powerful tool to enhance a systemÕs efficiency.Still, it should be noted that in-system-reconfigurable PLD logic is still in its infancy. Currentdesign tools and programs are still not sufficient to manage dynamically reconfigurable hardwareefficiently. However, as system designers continue to explore ways to increase system perfor-mance, ICE expects that reconfigurable PLDs will find an increasing market to serve.



Blank PLD Inventory

Program and Mark

Pre-Patterned PLD Inventory

Board Assembly

Board Test

* In-system programmable

Buy Replacement PLDs

Lead Rework

Reprogram

Conventional PLD Flow ISP PLD Flow

Blank ISP PLD Inventory

Board Assembly

Board Test and Program

Source: Lattice Semiconductor 23187

Figure 6-17. Conventional Versus ISP PLD Flows

It is expected that CPLDs with ISP feature will represent 80 percent of the CPLDs sold in 2000.Moreover, PLD manufacturers are also looking at implementing In-System-Programming (ISP)in SPLDs.

In mid-97, a group of companies involved in In-System-Programming (ISP) for CPLD, proposeda new standard through the JTAG (Joint Test Action Group) called Jam language.

The Jam language consortium includes: PLD manufacturers Altera and Cypress Semiconductor;programming equipment vendors BP Microsystems and Data I/O Corporation; US test equip-ment manufacturers Asset InterTech Corporation, GenRad Corporation; and TeradyneCorporation, as well as Gopel and JTAG Technologies B.V. of Europe.

This new programming language is compatible with current PLDs that offer in-system program-mability (ISP). But it is not clear if this program will become a standard. Lattice, who is the ISPinventor, did not join the Jam Consortium.



(a) Telecom T1/T1E

(b) Sonet/Synchronous Networks

(c) Algorithm Engine

(d) ATM

(e) Graphics-Accelerator Card

DSP Algorithm Engine Line Interface Card

Line Interface Card

Line Interface Card

Synchronizer

DSP Algorithm Engine

Fixed Algorithm Engine

Dual-Port RAM DSP Core Microcontroller

ATM Switch Fabric

Hard Disk Compression/Decompression FPGA Video Engine

Synchronizer

2.048 Mbits/s (Europe)1.544 Mbits/s (U.S.)

Extract timing from T1/T1E source

Extract timing from T1/T1E source or bits

DS3: 45 Mbits/sSTS1E: 52 Mbits/s

Overhead channelsFraming

Source: Lucent Technologies 20180

Figure 6-18. FPGA Can Reconfigure to Meet Various Standards

Figure 6-19 illustrates the flow using the Jam language. This language consists of two parts, theJam Composer and the Jam Player. The Jam composer writes files that contain the user data andprogramming algorithm for the device. The Jam Player interprets the Jam file and manages theJTAG port program devices. The Jam instruction set includes JTAG-based and algorithmicinstructions. These elements create an universal language and tools that address all PLDs and allprogramming methodologies.

Shown below is a sampling of some of the major CPLD technology announcements made recently.

¥ Philips Semiconductors completes CoolRunner with 128 Macro CPLD. CoolRunner devicesbegin at 32 macrocell density and will range to 960 macrocells. PhilipsÕ FZP (Fast Zero Power)and XPLA (eXtended Programmable Logic Array) architecture, form the basis of theCoolRunner family. The design technique, FZP, offers low power without a performancepenalty through the elimination of sense amplifiers. The XPLA architecture combines PALand PLA structures to offer maximum effective densities, higher performance for complexfunctions, and superior support for making design changes while maintaining a fixed pin-out.

¥ Altera announced the introduction of the FLEX6000 family. This family offers 10,000 to24,000 gates of logic and is manufactured on a 0.5-micron, triple-layer metal SRAM process,moving to 0.35-micron triple-layer process end of 1997. Altera claims it is the industryÕs firstto offer die sizes and cost directly comparable with gate arrays. This breakthrough is made



PLD VendorSpecific

PLD Vendor and PlatformIndependent

JamComposer

Jam File(.jam)

Jam Player

JTAG Chain

Platform Specific

AnyJTAG

Device

TargetDevice

AnyJTAG

Device

Source: ICE 23188

Figure 6-19. Flow Using the Jam Language

possible by the FLEX6000 OptiFLEX architecture, which combines advanced bond pad tech-nology, interleaved logic array blocks (LABs), and optimized I/O structure to produce a newlevel of programmable logic efficiency.

FPGAs

Shown below is a sampling of some of the major FPGA technology announcements made recently.

¥ Lucent Technologies introduced a 0.3µm series of ORCA FPGAs. The 0.3µm line includeseight densities, ranging from 4,000 to 40,000 usable, logic-only gates with up to 100,000usable gates possible when using on-chip RAM. The architecture features three layers ofmetal and an advanced 3.2 mil bond pad pitch, which allows the company to reduce the chiparea by 19 percent over the previous 0.35µm generation. In addition, Lucent plans to sample0.25µm FPGAs by the end of 1997.

¥ Xilinx announced that its next generation of low-cost FPGAs, the XC5200XL family, willachieve die-size parity with gate arrays and is expected to be sampling in 4Q97. The deviceswill use a 0.35-micron process and will operate at 3.3 Volts. To reduce the size, Xilinx elimi-nates RAM and flip-flop I/Os and deploys segmented interconnect technology.

¥ In mid-1997, Dynachip demonstrated what it claimed to be the industryÕs fastest FPGA.Using a BiCMOS process technology and drive circuitry within on-chip interconnects, thecompanyÕs DL5000 series of FPGAs are said to be capable of operating at clock speeds ofmore than 100MHz (compared to 50 to 70MHz for mainstream parts).

¥ Motorola unveiled its first field programmable analog array (FPAA) device called MPAx020.The FPAA is based on switched capacitor technology. The architecture offers an uncon-strained topology similar to its digital FPGA counterpart. The analog array can be pro-grammed to perform many of the routine tasks associated with control systems design. Thelinear and non-linear signal processing ability can provide a wide range of waveform gen-eration functions. The device can also be programmed for precise phase and magnitudecharacteristics. Figure 6-20 shows a block diagram of this device. The principle feature is anarray of 4 by 5 programmable analog cells. Some RAM is local to each cell to control thefunction of the cell.

ASIC PROCESS TECHNOLOGY ISSUES

In the mid-1980Õs, ASIC devices were typically using process technology that was 2-3 years behindhigh-volume memory part types (Figure 6-21). Today, however, processes rivaling the technologi-cal advancement of state-of-the-art memory devices are being developed specifically for ASICs(Figure 6-22). Figures 6-23 through 6-27 describe the state-of-the-art ASIC process technologies



offered by LSI Logic and VLSI Technology. As shown, LSI LogicÕs G10 and the newest G11processes are primarily targeting the cell-based ASIC market segment. In fact, both the G10 and G11technologies describe the availability of DRAM cells for additional system-on-a-chip capability.

VLSI Technology and Hitachi have worked together to develop a leading-edge ASIC process thatVLSI labels VSC9 and VSC10. As shown, the VSC10 process offers 0.15mm Leff channel lengthsand gate oxide thickness of only 40�!

One of the key aspect of VLSIÕs technology is the use of trench isolation (Figure 6-28). The trenchisolation allows greater packing density of transistors and thus a small die size.

It should be noted that both the G11 and VSC10 processes will not be used for high volume ASICproduction until 1998. However, even in 1998 these technologies will represent two of the ÒbestÓof the ASIC processes available.



Shift Register

Config Logic

4

x

i/o

4

x

i/o

ProgRef

5 x i/o

Source: Motorola 23189

Figure 6-20. FPAA Architecture From Motorola



1.67

1.5

1.33

1.25

1.00

MOS Gate Array

DRAM

64K

256K

1M

4M

16M

'83 '84 '85 '86 '87 '88 '89 '90 '91 '92 '93Year

= Gate Array/DRAM Feature Size Ratio

Fea

ture

Siz

e (µ

m)

0.1

0.2

0.3

0.40.5

2.0

3.0

4.05.0

18531ASource: ICE

1.00

64M

1.0

10.0

'94 '95 '96 '97

Figure 6-21. ASICs Narrow Technology Gap

Figure 6-22. Roadmap: CMOS Logic Technology Platforms for ASICs

Process Generation(Drawn, µm)

Gate Density(Gates/mm2)

VolumeManufacturing

Start

2.0

1.2

0.7

0.5

0.35

0.25

0.18

100 to 200

300 to 500

1,250 to 1,500

5,000 to 6,000

15,000 to 20,000

30,000 to 40,000

45,000 to 60,000

1986

1989

1992

1994

1996

1998

2001

Source: SGS-Thomson 21734



500KG10™ FamilyG11™ Family

Source: LSI Logic 22710

Effective

Drawn

Architectures

Metal Interconnect

Operating Voltages

LSI LogicCMOS Process

0.18µ

0.25µ

Cell Based

3,4,5, and 6 Layer

2.5 and 1.8 Volts

0.25µ

0.35µ

Cell Based

2,3,4, and 5 Layer

3.3 and 2.5 Volts

0.38µ

0.5µ

Cell BasedEmbedded Array

Gate Array

2,3, and 4 Layer

3.3 Volts

Gate Capacities

Usable (Max)

Typical (Used)

Power Dissipation

8,100,000

100K to 3,500K

0.03-0.25µW/Gate/MHz

5,000,000

100K to 2,500K

0.4-0.7µW/Gate/MHz

1,500,000 Max.

60 to 500K

1.0µW/Gate/MHz

Figure 6-23. LSI Logic ASIC Technology Products

Product Comparison

Introduced

0.25µ Leff/0.35µ Drawn

5,000,000 Gates

6,500,000 Bits(50% of Die)

10,800,000 Bits(50% of Die)

49,500,000(Logic 50% and SRAM

50% of Die)

0.18µ Leff/0.25µ Drawn

8,100,000 Gates

8,000,000 Bits(50% of Die)

12,000,000 Bits(50% of Die)

64,000,000(Logic 50% and SRAM

50% of Die)

G10™ G11™

MAXIMUMS

Random Logic

SRAM Memory

3-Transistor CellDRAM Memory

Transistor Count

1995 1997

Theoretical Comparisons(Assuming No Interconnect Or Power Limitations)

MIPS RISC Microprocessor

R10000 - 64bit CPU = 5,600,000-transistors(LSI Logic could put the equivalent of over elevenMIPS R10000 processors onto a single G11 chip)

INTEL

P6 CPU Die = 5,500,000-transistorsSRAM Die = 16,000,000-transistorsTotal P6 Multi Chip Module = 21,500,000-transistors(LSI Logic could put the equivalent of over eleven Intel P6processors or three complete P6 modules onto a single G11 chip)

Source: LSI Logic 22709

Figure 6-24. LSI Logic 0.18µm Process Statistics (Drawn Channel Length = 0.25µm)



Drawn Gate Length

Effective Channel Length

Supply Voltage

Max I/O Voltage

Gate Oxide Thickness

Isolation

Metal Layers

Stacked Vias

Plug Material

M1 Contacted Pitch

M2 Contacted Pitch

M3 Contacted Pitch

M4 Contacted Pitch

M5 Contacted Pitch

M6

SRAM Cell Size (6T Cell)

Power (µW/MHz/Gate)

Minimum Inverter Stage Delay @ Vcc

Logic Gates/22 x 22mm Die

Pad Pitch

100% Utilization (Gates/mm2)

0.25µ

0.18µ

2.5V

3.3V

55Å

Trench

Six

Yes (CMP)

Tungsten

0.85µ

0.90µ

0.90µ

1.4µ

1.4µ

Flip Chip Layer

10.5µ2

0.04

35ps @ 2.5Vdd

18,000,000

42µ

40K

0.20µ

0.15µ

1.8V

3.3V

40Å

Trench

Six

Yes (CMP)

Tungsten

0.85µ

0.90µ

0.90µ

1.4µ

1.4µ

Flip Chip Layer

10.5µ2

0.02

35ps @ 1.8Vdd

18,000,000

42µ

40K

VSC9 VSC10

Source: VLSI Technology 22713

Figure 6-25. VLSI TechnologyÕs ASIC Process Overview

Figure 6-26. What VSC9 and VSC10 Give You

0

2,000,000

4,000,000

6,000,000

8,000,000

10,000,000

12,000,000

14,000,000

0.5 1.0 2.0 4.0

Max

Usa

ble

Gat

es

Die Area in cm2

VSC9 and VSC10 Process, 0.85µ Metal Pitch,18,000,000 Max Gates at 4.84cm2

VLSI 0.35µ Process, 1.4µ Metal Pitch,6,200,000 Max Gates at 4.84cm2


While deep-submicron integration has allowed for unprecedented performance and economies ofscale, it has also brought with it a new set of design challanges. With larger geometries chips, cir-cuit timing is limited primarily by gate delays. However, as geometries shrink, delay from theresistance and capacitance of the wiring interconnect between transistors begins to dominate(Figure 6-29). Interconnect delays have increased, as a percent of total delay, from 15-30 percentat the 1.0µm level to 50-75 percent at the 0.35µm level.

As an example, Figure 6-30 shows ToshibaÕs DRAM and ASIC technology convergence.

For ASICs devices to become increasingly dense, feature sizes must shrink. Both gate oxides andgate lengths need to operate at lower voltage to avoid an increase in electrical field (Figure 6-31and 6-32).




Metal Pitch:

Pro

cess

Voltage:

3.3V w 5VSignaling

2.5V w 3.3VSignaling

1.8V w 3.3VSignaling

0.20µ VSC100.15µLeff

0.25µ VSC90.18µLeff

0.35µ VSC80.30µLefftox = 80Å

tox = 55Å

tox = 40Å

Density1.0X 2.4X

1995 1997

1.4µ 0.85/0.90µ

Figure 6-27. Technology Transitions

Figure 6-28. Trench Versus LOCOS Isolation

Photos by ICE 22712

TRENCHOXIDE

LOCOS Isolation

FIELDOXIDE

Trench Isolation

ASICs are making the transition from the 5 Volts power supply to the 3.3 Volts power supply andprobably soon to the 2.5 Volts power supply and below. The question of compatibility betweenmultiple voltages is becoming a concern for many vendors as well as users. Altera introduced aninterface designed for multiple voltage level application down to 1.8 Volts and below. Figure 6-33illustrates that interface. The designer can configure the I/O power at a different voltage than thecore power without utilizing external level shifters.



Del

ay (

nse

c)

1.5µm

20

1.2µm

30

1.0µm

60

0.8µm

150

0.5µm

500

0.3µm

1,000

Feature Size:

Circuit Size: (thousands of gates)

0.1

1

Average Wiring Delay

Typical Gate Delay

Source: OKI Semiconductor 20407B

Figure 6-29. Wiring (Interconnect) Delay Versus Gate Delay

Figure 6-30. Transition of the DRAM and ToshibaÕs Gate Array Development

0.1

0.2

0.5

1.0

2.0

1984 1986 1988 1990 1992 1994 1996 1998 2000

Fiscal Year19170ASource: Toshiba/JEE

Des

ign

Ru

le (

µm)

DRAMToshiba's gate array

1M-BitDRAM

4M-Bit DRAM

16M-Bit DRAM

64M-Bit DRAM

TC110G

TC140G

TC160G

TC180G

TC200GTC220G



160

140

120

100

80

60

40

20

0

0 0.1 0.2 0.3 0.4 0.5 0.6

Gate Length (µm)

Gat

e O

xid

e T

hic

knes

s (Å

)

Published Data

Trend Line

20284ASource: Intel

Figure 6-31. Gate Oxide Versus Gate Length

6

5

4

3

2

1

00 0.1 0.2 0.3 0.4 0.5 0.6

Published Data

Trend Line

Op

erat

ing

Vo

ltag

e (V

)

Gate Length (µm)

20285ASource: Intel

Figure 6-32. Gate Length Versus Operating Voltage

Significant decrease of gate length determines MOS circuit density. But a more accurate indicatoris metal pitch, which is defined as the sum of the metal line width at a via and the space betweenthe via and an adjacent line. It is a measure of how closely the metal lines can be placed together.Thus, as shown in Figure 6-34, metal pitch sets the drain-to-source pitch in an individual transis-tor and the drain-to-drain pitch of isolated transistors.



Level Shifters

Source: Industry 23190

Vcc, I/O

Vss, I/O Vss, I/O

Vcc, I/OVcc, Core

Vss, Core

��

yyyyyyyyy

Figure 6-33. Altera I/O Interface

Figure 6-34. Influence of Metal Pitch on Deep-Submicron Device Layout

Gate Gate

Source: Computer Design/VLSI Technology 21244

Drain Drain SourceSource

Furthermore, ASIC cell libraries are generally based on some fixed multiple of the metal pitch.That is to say, when library elements are placed and routed, the interconnect line lengths are mul-tiples of the interconnect metal grid. Thus, metal pitch, not gate length, determines cell dimen-sions and library elements shrink proportionally to the pitch. Figure 6-35 provides a list of typicalmetal pitch measurements for several submicron technology generations.

The rapid increase in gate density and clock frequency in advanced ASIC devices is driving theneed for new packages, like the ball grid array (BGA), plastic quad flats (PQFP) and thin plasticquad flat packs (TQFP) packages that can support the requirements for higher pin counts andimprove heat dissipation. Figure 6-36 shows these CPLD package options. We see in that Figurethat as CPLD densities exceed 10,000 gates and device pin counts surpass 160 pins, vendors areoffering a wide array of package options to meet thermal, electrical, and mechanical requirements.



TechnologyGeneration (µm)

0.6

0.5

0.35

0.25

Metal Pitch (µm)

3.0 - 2.4

2.4 - 1.8

1.8 - 1.2

1.2 - 0.8

Number of Layers

3

3 - 4

3 - 5

3 - 5

Source: Computer Design/ VLSI Technology 21245

Figure 6-35. Typical Metal Pitch Measurements

Figure 6-36. CPLD Package Options

2,500 5,000 10,000 15,000 20,000

352

208

160

144

120

100

84

68

44

Pin

Co

un

t

Gate Count

PQFP TQFP PQFP

PQFP PQFP

PQFP

PQFP RQFP MQFPRQFP

RQFP

MQFP

TQFP PQFP TQFP

TQFP

TQFP

PQFP TQFP

TQFPCQFP

CQFP

CQFP

PLCC

PLCC

PLCC JLCC

JLCC

PGA

PGA

PGA

PQFPPGA

HQFP RQFP

PQFP TQFP PQFP

BGA

BGA

TQFP

CQFP HQFP

PQFP RQFPHQFP

RQFPCQFPHQFP

PQFP TQFPPGA

RQFP MQFP CQFP

PQFP TQFPPGA

PGA

RQFP MQFP CQFP

PQFP TQFPPGA

PQFPPGA

PGA

PQFP VQFPTQFP

Source: Computer Design 23192

ASIC DESIGN TOOLS

With the increase in complexity and density of ASICs has come the need for higher levels ofabstraction in circuit simulation in order to meet time-to-market requirements. The use of hard-ware-description languages (HDLs)ÑVerilog and VHDLÑand the synthesis of these languages,has significantly improved the productivity of ASIC designers. It has been estimated that the pro-ductivity of HDL users is 3 to 10 times that of users of schematic capture when measured in termsof the number of gates created in a given timeframe.

The three primary levels of abstraction in HDL simulators are the gate (or logic) level, the regis-ter-transfer level (RTL), and the most abstractÑbehavioral level (Figure 6-37). While HDL toolsare being readily used at each of the three levels, most are focused on the RTL level of abstraction.Figure 6-38 provides a listing of HDL simulation tool vendors.



Partitioning

Pipelining

Scheduling

Register Allocation

Resource Allocation

Register Inferencing

State Machine Synthesis

Multi-Level Logic Opto

Two-Level Logic Opto

Redundancy Removal

Technology Mapping

Technology Translation

Physical SynthesisPhysical

Logic

RTL

Behavioral

System

Synthesis Level Synthesis Tasks

Source: Synopsys 18581A

Figure 6-37. Levels of Abstraction



Companyand Location

ProductName

ProductDescription

SimulationLevel(s)

Accolade DesignAutomationDuvall, WA

AldecHenderson, NV

Alta Group of CadenceSunnyvale, CA

AnalogBeaverton, OR

Bell Labs DesignAutomationMurray Hill, NJ

Cadence DesignSystemsSan Jose, CA

Fintronic USAMenlo Park, CA

Frontline DesignAutomationSan Jose, CA

FTL SystemsRochester, MN

PeakVHDL

ACTIVE-VHDL

Hardware DesignSystem

Saber Mixed-TechnologySimulator

ATTSIM

Verilog-XL andVerilog-XL Turbo

NC-Verilog

Leapfrog VHDLSimulator

FinSim ECST

FinSim

FinSimDeveloper

PureSpeedDeveloper,OverDrive,

and CycleDrive

Auriga

Includes built-in source-code browser, source-fileeditor, VHDL Wizards, and tight integration withPeakFPGA synthesis and third-party analysis tools

Simulator based on Microsoft Foundation Class(MFC) framework. Includes interactive source-code debugger, waveform analyzer, and hierarchynavigation for browsing VHDL objects

A system-level hardware architecture designenvironment integrated with Alta Group's SignalProcessing Worksystem. It automaticallygenerates synthesizeable VHDL and Verilog

An IC through system-level analog andmixed-signal simulator. Its MAST hardwaredescription language can describe analog, digital,and mixed technologies

A mixed-signal simulator that efficiently performsanalog and digital simulations for systems onsilicon

For design of ICs, ASICs, and systems. Turbooption for behavioral speed ups and VHDLco-simulation. For use across the simulationprocess, from architectural design code creation,batch simulation, systems simulation, and sign-off

Native compiled-code simulator for largesimulations. Mixed-language simulation

VHDL simulator based on native compiled codetechnology. Verilog co-simulation with Verilog-XL.Sign-off VITAL simulator

A cycle-based Verilog simulator. Its multi-enginearchitecture supports compiled and interpretedsimulation, interactive source-level debugging,and code coverage

A Verilog simulator. Its multi-engine architecturesupports compiled and interpreted simulation,interactive source-level debugging, and codecoverage

An interpreted Verilog simulation environment.Its accelerated interpreter supports interactivesource-level debugger, real-time waveformdisplay, and code coverage

A Verilog simulator with both cycle-based andevent-driven support. The product family deliversa full range of choices for both Unix and Windows

HDL compiler/simulator utilizing workstation,networked, or massively parallel computers.Integrated compiler/simulator brings parallel,optimizing compilation to HDL simulation

Behavior, RTL,and structural

Behavioraland structural

Behavioraland RTL

Behavioral,mathematical,transistor, andsystem

Digital behavioraland RTL in VHDL.Verilog and C, gateand switch. Analogbehavioraland transistor

Behavioral,gate, RTL, andmixed and switch

Behavioral, gate,RTL, and mixed

Behavioral, gate,RTL, and mixed

Gate, RTL,and switch



Behavioral,gate, and RTL

Full IEEE 1076VHDL (gatethroughbehavioral)


Figure 6-38. Simulation Tool Vendor List



Companyand Location

ProductName

ProductDescription

SimulationLevel(s)

GAIO TechnologyTokyo, Japan

IKOS SystemsCupertino, CA

Mentor GraphicsWilsonville, OR

Model TechnologyBeaverton, OR

Nextwave DesignAutomationSan Jose, CA

OrCADBeaverton, OR

Pendulum DesignWaltham, MA

SimucadUnion City, CA

Asim-G

Voyager VS

Voyager CS

Voyager CSX

Gemini CSX

QuickHDL

QuickHDL Lite

QuickHDL Pro

V-System/VHDL

V-System/VLOG

V-System/PLUS

Epilog-MX

OrCAD Simulatefor Windows

vls

SILOS III

Asim-G is an integrated simulator with a general-purpose architecture that inputs software modelsof RTL and behavior descriptions to simulate MPUand ASIC functions at the system level

A top-down VHDL system verificationenvironment for complex system designs. FullyIEEE 1076-compliant simulator with support forindustry-standard software and hardware models

Combines VHDL and gate-level simulationalgorithms with certified IKOS ASIC vendorlibraries to create a concept-to-silicon softwareverification environment for top-down design

A mixed-level simulator with integration to IKOS'NSIM hardware accelerator. It co-simulates fully1076-compliant VHDL simulator and IKOS' NSIMhardware accelerator with certified vendor libraries

A mixed-level acceleration of designs integratingVerilog-XL with the NSIM hardware accelerator.Delivers design and debug environment withacceleration and access to vendor libraries

A direct-compiled simulator that supportsVHDL, Verilog, or mixed VHDL/Verilog designs

A Windows version of QuickHDL for VHDLsimulation. It includes and HDL text editor andStd_Developers Kit VHDL packages

A co-simulation option to QuickHDL that addscosimulation between QuickHDL and MentorGraphics' QuickSim II simulator

Model Technology's HDL tools are compliantwith leading industry standards. V-System/VHDL supports VHDL only

Model Techology's HDL tools are compliantwith leading industry standards. V-System/VLOGsupports Verilog only

Model Technology's HD: tools are compliantwith leading industry standards. V-System/PLUS supports VHDL and/or Verilog at any levelof hierarchy or complexity

A multi-level Verilog spread-delay timing simulatorthat catches timing problems in submicronASICs missed by a Verilog min/max simulation

Digital simulator for debugging and verifying theperformance of CPLD and FPGA designs. Uses asubset of VHDL '93 and VITAL for timing simulationand test benches

Verilog simulator incorporating cycle-basedtechnology

A mixed-level logic and fault simulator usingVerilog to support top-down design methodology




Behavioral,gate, RTL,and mixed

Behavioral,gate, RTL,and mixed




Gate and RTL

Gate and RTL

Gate and RTL

Gate and RTL

Gate

Gate



Figure 6-38. Simulation Tool Vendor List (continued)



Companyand Location

ProductName

ProductDescription

SimulationLevel(s)

SpeedSimWestford, MA

Synario DesignAutomationRedmond, WA


Veda DesignAutomationSanta Clara, CA

VeriBestBoulder, CO

VHDL TechnologyGroupBethlehem, PA

Viewlogic SystemsMarlboro, MA

Wellspring SolutionsSutton, MA

ZycadFremont, CA

SpeedSim/3 v2.3

SynarioSimulator-VHDL

and SynarioSimulator-Verilog

VHDL SystemSimulator (VSS)

VerdictFault

Vulcan

VeriBest VerilogSimulator

VeriBest VHDLSimulator

Vantage VHDLDragster

ChronologicVCSi

ChronologicVCS

VantageUltraSpec

VantageFusionHDL

VeriWell

VXI (CadenceVerilog-XL)Accelerator.

Synopsys VSSAccelerator.

Vantage VHDLAccelerator

Simulates asynchronous loops, multiple clockdomains, gated clocks, and transparent latches

Windows-based HDL simulators. Complyingwith industry standards; VHDL simulator meetsIEEE 1076-1993 specifications, Verilog simulator isOVI compliant

VSS is a multi-engine, VHDL event simulator. It iswell integrated with Synopsys synthesis tools

A VITAL compliant fault simulator. Works withexisting VHDL simulator to give fault simulationwithout having to leave your VHDL designenvironment

VITAL compliant logic simulator, offering sign-offperformance comparable with Verilog.Complements existing VHDL logic simulators

Full OVI and IEEE-1364 compliant Verilogsimulator

Full IEEE 1076-93-compliant VHDLsimulator

VHDL model generation too suite and openarchitecture database

A lower-cost version of VCS. It offers fastercompile times but lower simulation speed thanVCS. Suited for model building and debugging

Uses compiled code to offer memory-efficientsimulations. Capabilities for model development,interactive debugging, regression testing, andASIC sign-off. Fully standards compliant

A cycle-based functional simulator that handlescomplete VHDL language, including test benches,non-synthesizeable descriptions, and complexdesign styles

A bilingual simulator that integrates theChronologic VCS engine with the VantageSpeedWave engine. It offers Verilog and VHDLsimulation in a single environment with acommon user interface

A Verilog simulator that includes IEEE-1364compliance, syntax-coloring editor, waveformviewer, interpretive simulator, and PLI/SDF andmultiple third-party tool support

HDL co-simulation interfaces with the ParadigmXP accelerates gate-level models up to ten timesover software simulators, while preserving thenative HDL debugging environment

Verilog RTLand gate

Gate and RTL


Mixed-level:gate and

embeddedblocks

Behavioral, gate,and RTL

Behavioral, gate,RTL, and switch

Behavioral, gate,RTL, and switch


RTL to ASICsign-off

All

RTL

Gate and RTL


Behavioral,gate, RTL, and

transistor


Figure 6-38. Simulation Tool Vendor List (continued)

VHDL and Verilog are industry-standard HDLs for chip design. Both languages are used world-wide and have been adopted by the IEEE. VHDL and Verilog modeling constructs encompassslightly different regions of system behavioral abstraction. Many view Verilog HDL as best at sup-porting logic simulation from the gate level to the RTL level and VHDL as more efficient operat-ing at more abstract levels. More than likely, Verilog and VHDL will coexist for quite some time(Figure 6-39).

Technological advancements have increased the complexity of ASICs, resulting in the Òsystem-on-a-chipÓ concept. A Òtop-downÓ design methodology is the only practical option for designingsuch complex chips of 100,000 gates and more. Top-down methodology takes the HDL model ofhardware, written at a high level of behavioral abstraction (system or algorithmic), down throughintermediate levels, to a low (gate or transistor) level as also illustrated Figure 6-40. As a result,the traditional ASIC has evolved into a more complex design flow (Figure 6-41).

Synthesis technology has had a profound impact on the ASIC industry. In less than ten years, ithas grown from merely a research topic to an essential part of high-level ASIC design. Synthesis isquickly becoming essential for CPLD and FPGA designs as well. Synthesis tools translate abstractdesigns (generally starting from HDL descriptions) into actual logic that can be implemented in sil-icon, as well as optimize the logic given a set of circuit design constraints such as timing, power,loading, area, and testability. Figure 6-42 provides a listing of logic synthesis tool vendors.

Over the past few years, synthesis tools have struggled to keep pace with deep submicron designmethodology shifts, especially in the case of timing. As discussed earlier, interconnect delay hasbecome as much, or more, of a concern as gate delay in the design of advanced ICs. And, sinceactual interconnect delay is dependent upon the layout of the IC itself, physical layout informa-tion is needed very early in the design cycle in order to accurately estimate timing conditions.



Abstract System DesignHardware/Software Codesign

ArchitecturalSystem Design

BehavioralDesign

RTLDesign

Gate-levelDesign

VHDL

Verilog HDL

Need forexperimentation

Need for standard practicesandelimination of duplication of effort

Source: Cadence 18586

Figure 6-39. VHDL, Verilog Capabilities Overlap

The required tighter link between logic and physical chip design has put the pressure on designtool vendors to create more sophisticated tools that use ÒfloorplanningÓ (or Òdesign planningÓ)techniques to constrain variability in delay estimation and to manage the rapidly growing amountof functionality in silicon. The modern design flow involves an iteration between synthesis andfloorplanning, with final routing performed only when the floorplanning netlist meets all require-ments. Figure 6-43 provides a listing of floorplanner tool vendors.

The tools for analog and mixed-signal ASIC design are recognized to be several generationsbehind those for digital. So far, a way to synthesize analog circuits has not been developed. Theprecise control of voltage and current levels just doesnÕt easily lend itself to a structured designmethodology. However, the industryÕs move toward mixed-signal Òsystems on a chipÓ is drivingprogress in efforts to develop standard analog HDLs. Both Verilog and VHDL have committeesdefining analog extensions to their digital HDLs. Current plans are to have an IEEE workinggroup for Verilog-AMS (Verilog with analog and mixed-signal extensions) to make the languagean IEEE standard in 1998. An other IEEE working group is reviewing VHDL-AMS (VHDL withanalog-and mixed-signal extensions) as specification 1076.1which is an analog and mixed-tech-nology extension to the 1076 digital VHDL language. Listed in Figure 6-44 are several vendors ofanalog/mixed-signal design tools.



SystemConcept

Algorithm

Architecture

RTL

Gate

Translator

IncreasingBehavioralAbstraction

IncreasingDetailed

Realizationand

Complexity

Source: EDN 23205

Figure 6-40. High-Level ASIC Design Flow

Several ASIC design tool highlights from 1996 and 1997 are described below.

¥ An industrial-wide effort is ongoing for developing a new System-Level Design Language(SLDL). The SLDL effort was kicked off end of 1996 by the EDA Industry Council ProjectTechnical Advisory Board (PTAB). U.S. governmentÕs Wright Labs kicks in $1 million tofund research in System-Level Design Language. The SLDL Committee plans to offer apublic presentation of language requirements first quarter of 1998.

¥ Cadence Design Systems Inc. has announced that its most popular software products, theVerilog-XL and Verilog-XL Turbo simulators, are moving to NT platforms. These tools werepreviously available only under Unix.



DelayEstimates

SimulationSimulation Simulation

Timing Analysis

BehavioralModeling

Write RTL/Behavioral Synthesis

RTLFunctional

Floor-planning

SpecificationArchitectural Design

and Analysis

Delay Data

PhysicalFloor-

planning

FullPlace

GlobalRouting

DelayComputation

PowerAnalysis

ParasiticExtraction

LayoutVerification

to Fab

Datapath Synthesis

Memory Compilation

Cell Lib

Simulation

Timing Analysis

Logic Synthesis Test Synthesis


CTS

Figure 6-41. High-Level ASIC Design Flow

¥ Xilinx introduced an innovative web-based tool for fast FPGA CORE design for PCI. Thenew on-line CORE Generator tool enables a designer to instantly access, customize anddownload optimized PCI cores with predictable performances and use them in VHDL,Verilog and Schematic design flows.

¥ The Bell Labs Design Automation (BLDA) group of Lucent Technologies introducedFormalCheck, the first product in a line of system-level model checkers for advanced devicedesign. FormalCheck accepts the customerÕs design model in a synthesizable subset of bothVerilog and VDHL.



ACEO TechnologyFremont, CA

AlteraSan Jose, CA

Ambit Design SystemsSanta Clara, CA

Cadence Design SystemsSan Jose, CA

Compass DesignAutomationSan Jose, CA

DASYSPittsburgh, PA

Exemplar LogicAlameda, CA


OrCADBeaverton, OR

Asyn

VHDL Synthesis forPC

VHDL Synthesis forWorkstations

BuildGates

Synergy

FPGA Designer

Visual Architect

ASIC Synthesizer

RapidPath

Leonardo

AutoLogic II

Galileo

Leonardo

AutoLogic II

OrCAD Express

RTL

RTL

RTL

RTL

RTL

RTL

Behavioral input andRTL output

RTL

Behavioral

RTL

RTL

RTL

RTL

RTL

Behavioral simulationand RTL synthesis

ASIC and FPGA

Programmable logic

Programmable logic

High-end, high-performance ASICs

or ICs

ASICs

FPGAs

ASICs and FPGAs

ASICs and custom

ASICs

ASIC, CPLD, and FPGA

ASIC

CPLD and FPGA

ASIC, CPLD, and FPGA

ASIC

CPLD and FPGA

Verilog and VHDL

VHDL

VHDL

Verilog and VHDL

Verilog and VHDL

Verilog and VHDL

Behavioral VHDL andgraphical block

diagram

EDIF, Verilog, and VHDL

Verilog and VHDL

EDIF, Verilog, VHDL,and XNF

Verilog and VHDL



Verilog and VHDL

Schematic/VHDL

Companyand Location

Product Name Abstraction Level Target Hardware Input Types

Source: Integrated Circuit Design 23206

Figure 6-42. Logic Synthesis Tool Vendors

ASIC TESTING

As the number of gates per pin has risen along with gate count (Figure 6-45), fully testing, debug-ging, and diagnosing an ASIC has become more difficult, yet increasingly important so as toensure quality and reliability. But the requirement for fully testing ASIC devices is a top priorityfor ASIC manufacturers and users.

Due to relatively faster advances in design automation, as compared to test development, theexpensive test equipment needed for an increasing complexity of new designs, test costs arebecoming a bigger portion of total IC development costs (Figure 6-46).

With the average ASIC hitting 50,000 gates, and devices with several hundred thousand gates oreven millions (see Figure 6-47), designers must consider adding testability features to their cir-cuits. Design-for-test (DFT) techniques are now becoming mainstream.



Synario DesignAutomationRedmond, WA


SynplicityMountain View, CA


Synario VHDLSynthesis

Synario FPGAExpress VHDL and

Synario FPGAExpress Verilog

Synopsys DesignCompiler

Synopsys DesignCompiler Expert

Plus

Synopsys PowerCompiler

SynopsysDesignPower

Synopsys TestCompiler

FPGA Express

Synopsys FPGACompiler

Synplify

ViewSynthesis

RTL

RTL

RTL

RTL

Gate level

Gate level

RTL

RTL

RTL

RTL

Architectural RTL

CPLDs, FPGAs, andPLDs

CPLDs and FPGAs

ASICs and ICs

ASICs and ICs

ASICs and ICs

ASICs and ICs

ASICs

FPGAs

FPGAs

FPGAs and CPLDs

FPGAs and CPLDs

VHDL

Verilog and VHDL

EDIF, PLA, TDL,Verilog, and VHDL

EDIF, PLA, TDL,Verilog, and VHDL

Verilog and VHDL

Verilog and VHDL

Verilog and VHDL

Verilog/VHDL

Verilog and VHDL

Verilog and VHDL

VHDL

Companyand Location

Product Name Abstraction Level Target Hardware Input Types


Figure 6-42. Logic Synthesis Tool Vendors (continued)



Design-for-test methods range from those that are simple, use no overhead (i.e., silicon area), andprovide low effectivity to those that are complex and costly but provide thorough testability.Figure 6-48 shows a sampling of some of the DFT software tools available to the ASIC industry.The DFT as including functional tests, full and partial scan insertion, BIST, JTAG, automatic test-pattern generation (ATPG), IDDQ, and fault grading. But the test solution will be complete if theDFT criteria is built into the ASIC vendorÕs base sign-off methodology and manufacturing testthat is cost-effective for high-pin-count packages. If design core macros are used from third partydesign houses, it may however be necessary to develop core-isolation techniques and circuitry fortesting the core.

Built-in self-test (BIST) techniques offer benefits such as the ability to run at intended chip oper-ating speeds, the potential to significantly cut costs in test equipment hardware and softwaredevelopment, and the ability to carry test programs through to systems and field testing. In addi-tion, the integration of a larger number of cores in ASICs requires that BIST structures be designedinto each core to prevent the need to add significant unwanted routing and logic overhead to thechip. For example LogicVision, a supplier which is specialized exclusively in BIST technology, hasintroduced software that promises true-at-speed testing for high speed ASICs. This softwarecalled icBIST integrates logic BIST, memory BIST, and JTAG boundary scan.

Company Product Name Product Description Input Types

Avant!Sunnyvale, CA



High Level DesignSystemsSanta Clara, CA

Silicon Valley ResearchSan Jose, CA

Planet

Preview

ChipPlanner-RTL

Physical DP

Top Down DP

SVR FloorPlacer

Timing-driven hierarchical floorplanner

Mixed-level, foundry-independent floorplan-ning and analysis environment, effectivelylinking logical and physical design in theIC development process

ChipPlanner-RTL, along with theTimingTuners (ShowTime, MakeTime, andFixTime), is an RTL floorplanner that allowsthe designer to meet timing constraintsbefore logic synthesis

Targeted for deep submicron IC and supportsconstraint-driven floorplanning for all designstyles and all physical design routing tools

RTL floorplanner and timing analysis tool forpre-synthesis HDL. Creates floorplan directlyfrom HDL, predicts design size, timing, andpower consumption before logic synthesis

Gate array floorplanner for the front-enddesigners. Features timing and routabilityanalysis, automatic floorplanning, and specialsupport for embedded arrays

RTL and Gates

Gates

Verilog or VHDL RTL,gates, gray boxes, black

boxes, and physical

Gates

RTL

Gates and macroblocks


Figure 6-43. Source of Floorplanner Vendors



Company andLocation

Product Name Funtionality Analysis TypeTypes of Models

Supported

AnagramSunnyvale, CA

AnalogBeaverton, OR

AnsoftPittsburgh, PA

Avista DesignSystemsFolsom, CA

Avant!Sunnyvale, CA

Avista DesignSystemsFolsom, CA

Bell Labs DesignAutomation, LucentTechnologiesMurray Hill, NJ

ADM

Saber Simulator

QVS (Saber,QuickSim II—mixed-signal;mixed-analog/

digital simulation)

Saber/Verilog

Saber/ViewSim

Maxwell Strata

Maxwell Eminence

Maxwell Spicelink

Avista Spectre/XL

ADM

MetaCircuit

HSPICE

Avista Spectre XL

ATTSIM

Analog, digital,and mixed-signal

Mixed-signal

Mixed-signal

Mixed-signal

Mixed-signal

Analog RF

Analog RF andmixed-signal

Analog

Analog

Analog, digital,and mixed-signal

Analog

Analog

Analog and RFsimulation

Mixed-signal

DC and transient

AC, DC, Monte Carlo, parametric,transient, noise, Fourier, stress,sensitivity, and model synthesis




MOM (method of moments)

FEM

All Berkeley functions plus FFT,PWL transient, noise, transferfunction

AC, DC, distortion, Fourier,harmonic balance (nonlinearspectral), Monte Carlo, noise,optimization, parametric, perfor-mance, s-parametric, sensitivity,temperature, and what-if

DC and transient

Transient

AC, DC, distortion, Fourier, pole-zero data driven, S-parameter,Monte Carlo, noise, optimization,parametric, mixed AD/transient,violations

Spectre, Spice, Excel workbook.Graphics tabular results, and circuitsare OLE2 objects for use inMicrosoft Office applications

Transient

All Spice MOS levels,bipolar, and diode

All types of modelssupported




N/A

Microwave, RF, and Antennas

Saber templates, MaxwellSpice subcircuits, BerkeleySpice compatible subcircuits

Spice, plus microstripand lossy transmissions lines,s-parameter blocks, andmacromodels

All Spice MOS levels,bipolar, and diode

MetaMos1 (Level 28), BSIM,MOS 9, and custom models

MetaMOS1 (Level 28),BSIM3.3, MOS 9 Level15 and 16, and custom models

Spice and HP/EEsof Libramodels, plus microstrip andlossy transmissions lines,s-parameter blocks, andmacromodels

HSPICE MOS models,SPICE2G6 models, BSIM3,ASIM3, CSIM, ExtendedGummel-Poon BJT, Mixed-signal behavior models(ABC), Verilog, VHDL and C


Figure 6-44. Analog/Mixed-Signal Simulation Tools



Company andLocation

Product Name Functionality Analysis TypeTypes of Models

Supported


CAD-MigosSoftware ToolsRedwood City, CA


EPIC DesignTechnologySunnyvale, CA

HP EEsof DivisionWestlake Village, CA

IntusoftSan Pedro, CA

Analog ArtistDesign System

Analog WorkbenchDesign System

Spectre advancedanalog simulator

SPICE-It! forWindows

SPICE-It! forWindows NT

SPICE-Client(companion prod-uct to SPICE-It for

Windows NT)

Mixed-SignalDesign Option for

Navigator

ArcadiaPathMill

PowerMill

RailMill

TimeMill

Series IV and MDS

ICAP/4 Windowsand ICAP/4Macintosh

ICAP/4Lite

Analog andmixed-signal


Analog and RF

Mixed-signal

Mixed-signal

Mixed-signal


Analog and digitalmixed-signal





Interactivenative mixed

mode

Interactivenative mixed

mode

AC, DC, transient, optimization,parametric, statistics, RF, noise,corners, Fourier, post-layout,and sensitivity

AC, DC, transient, optimization,statistics, Fourier, parametric,pole-zero, stress, sensitivity,noise, and thermal reliability

DC, AC, transient RF, RF transferfunction, and RF nonlinear noise

AC, DC, noise, transient, Fourier,pole-zero, and sensitivity



AC, DC, Monte Carlo, parametric,noise, transient, optimization,and Fourier

ExtractionTiming analysis

Piece-Wise-Linear analysis forR/F, glitches and timing and powereffects due to cross talk

Piecewise linear simulation ofpower and device network

Transient

All plus electromagnetic

AC, DC, Monte Carlo, noise, para-metric, optimization, transient,Fourier, pole-zero, temperature,distortion, and sensitivity

AC, DC, Monte Carlo, noise, para-metric, optimization, transient,Fourier, pole-zero, temperature,distortion, and sensitivity

Verilog-A, VHDL-A, Verilog,VHDL, MOS9, Spice3,Spice2G6, C, and BSIM3v3

7,000 templates andcomponent models; Verilog-A, VHDL-A, Verilog, VHDL,BSIM3v3, Spice, powerMOS,and nonlinear magnetics

Verilog-A, VHDL-A,BSIM3v3, MOS9, Spice, and C

Analog, digital, and mixed-signal

Analog, digital, andmixed-signal

Analog, digital, andmixed-signal

Berkeley Spice; 2G6 Levels2 and 3; BSIM2; ASPEC;Gummel-Poon and powerbipolar Merckel 1, 2, and 3

N/ABlack, grey box

Analog, digital, and C-basedmodels using EPIC's ADMFI

Analog, digital, and C-basedmodels

Analog, mixed-signal, andC-based models usingEPIC's ADMFI

High-frequency circuitsystem models

Over 7,000 models: analog,digital, sampled-data andelements, RF and powerdevices, and mechanical

Over 500 models: analog,digital, mechanical elements,RF and power devices


Figure 6-44. Analog/Mixed-Signal Simulation Tools (continued)



Company andLocation


Supported


MicroSimIrvine, CA

Quad DesignTechnologyCamarillo, CA

Quantic LaboratoriesWinnipeg, Manitoba,Canada

SimucadUnion City, CA

Tanner ResearchPasadena, CA

Mixed Signal Pro

MS Analyzer

Accusim II

Continuum-Quick HDL

Continuum

MicroSim PSpiceand MicroSim

PSpice A/D

XTK/BASIL

BoardScan

PCB Greenfield

Compliance

WaveProbe

SILOS III

T-Spice Pro

Mixed-signal

Mixed-signal

Analog

Mixed-signal

Mixed-signal

Analog simula-tion (MicroSimPSpice), mixed-signal simula-tion (MicroSim

PSpice A/D)

Mixed-signal

Mixed-signal

Mixed-signal

Mixed-signal

Mixed-signal

Behavioral, logic,analog and digital,fault simulation,

source codedebugging,waveform

displays, signaltracing tools

Mixed-signal

All types

Transient, AC, DC, noise, andparametric

Transient, AC, DC, worst-case,Monte Carlo, noise, parametric,and Fourier

Transient and VHDL debugging

Transient

AC sweep, DC sweep, parametric,noise, transient, Fourier, MonteCarlo and sensitivity/worst-case,performance analysis, circuitoptimization with MicroSimPSpice Optimizer, digital, andworst-case timing analysis

Transmission line, time domain.Spice co-simulation of devices

(PCB) layouts, crosstalk, ringing,time delays, overshoot, under-shoot, reflections, settling timeand noise margin violations

Multi-conductor, transmission line,pre- and post-layout, and analysisfor a multi-board system

Radiated EM fields from multiplePCBs, MCMs or hybrids within anenclosure including internal andexternal cabling

Signal integrity from the layoutand at any stage of the PCB design

Analog behavioral mixed withdigital, Verilog HDL

AC sweep, DC sweep, noise,transient, parametric, table-basedanalysis, and temperature

User defined models, Bsim 3,MOS 9, Spice, HP Precise,AMS, BNR, SCFM, and EPFL

Schematic, VHDL, and HDL-A

Spice, C, and 1076.1(proposed)

Spice, C, VHDL, Verilog,gate, schematic, table, andhardware

Spice, C, gate, schematic,and table

Spice (all devices), GaAsFETs, BSIM 1 and 3, non-linear magnetics,transmission lines, libraryof analog and digitalcomponents

IBIS, Spice, and Quad DesignXTK

Behavioral, IBIS, and Zeelan

Behavioral, IBIS, Spice, and Zeelan

Behavioral, IBIS, and Zeeland

Behavioral, IBIS, Spice, andZeelan

Verilog, Verilog-A, realnumbers, and transcendentalfunctions

Spice, Bsim 4, Bsim 3, Maher-Mead, MOSFET, table-baseddevices, coupled transmissionlines, and user defined





For the internal scan method, circuitry is designed into the chip for scan test data and control lines,which are then chained together to allow serial access for shifting in test patterns and shifting outtest results. Internal scan may either be implemented as full scan or partial scan. Partial scan hasthe benefit of reducing area and performance impact, but reduces fault coverage.

Boundary scan was officially codified by the IEEE-1149.1 standard in 1990, but is still oftenreferred to as JTAG, after the Joint Test Action Group, which started the standardÕs process inEurope. It has become a popular test method due to the increased usage of high-density surfacemount ASICs. It provides a way to directly access the inputs and outputs of a chip where physi-cal contact with the device pins is impossible. ItÕs even being used to program FPGAs. The diearea penalty paid by implementing the IEEE 1149.1 boundary scan architecture depends on thedensity of ASIC being designed. The TAP (test access port) controller and registers require about500 gates of circuitry while the gates needed for the I/O cells are dependent upon the number of

Company andLocation


Supported

Tatum LabsAnn Arbor, MI

TESOFTRoswell, GA


SpiceAge*4W

ALLTED

ECA-2

TESLA BlockDiagram Simulator

ViewSpice

Mixed-signal

Mixed-signal

Analog only

Mixed-signal


AC, DC, transient, Fourier,sensitivity, noise, parametric,Monte Carlo, and worst-case

AC, DC, transient, Fourier,sensitivity, parametric, MonteCarlo, worst-case, optimization,and tolerance assignment

AC, DC, transient, Fourier,sensitivity, parametric, MonteCarlo, and worst-case

Behavioral, transient, MonteCarlo, noise, and Fourier

AC, DC, Monte Carlo, noise,parametric, transient, and Fourier

R, L, C, diode, opamp, BJT,JFET, MOSFET (Spice andproprietary versions)

R, L, C, diode, opamp, BJT,JFET, MOSFET; plusHydraulic, pneumatic andmechanical components insingle or mixed technology;ASICs complete system

R, L, C, diode, opamp, BJT,JFET Filters, mixers, A/Dand D/A converters

Sample-and-hold, integrator,Laplace, quantizer, peakdetector—over 65 parameter-ized blocks in library

Standard R, L, C, trans diodeplus advanced CMOS andlossy transmission-line



Figure 6-45. Gates Per Pin Trend

USABLE GATES

PINS

GATES/PIN RATIO

750

50

15

2,000

90

22

5,000

150

33

10,000

220

45

30,000

300

100

150,000

528

284

15578BSource:ICE

1,300,000

936

1,389



I/Os. For example, a 3,000-gate device with 44 pins would suffer a hefty 60 percent die areaincrease, whereas a 10,000-gate, 100-pin ASIC would incur only a 12 to 15 percent die area penalty.Moreover, a pad limited die could incur no extra die area, and thus a negligible increase in cost.

Another test method that has gained popularity over the past couple of years is called IDDQ (i.e.,quiescent supply current) testing. Duet Technologies describes the rational behind IDDQ testingas follows.

ÒUnder normal conditions, IDDQ is typically within pre-determined limits in defect-free CMOSVLSI circuits. A defect that causes current drain in excess of those limits is considered a leakageor IDDQ fault. By monitoring the power supply of a circuit directly, IDDQ detects manufacturingdefects such as transistor-level shorts and metal bridging. Many defect types are only detectableby IDDQ tests and, as such, users of IDDQ testing have reported lower levels of defective partsshipped to customers when IDDQ testing is used a supplement to their existing test techniques,including functional or scan tests.Ó

As even Duet Technologies recommends when discussing IDDQ testing, it is most beneficial whenused as a supplement to other test procedures. It has been suggested that a combination of teststrategies are necessary for obtaining the best results. For example, using full scan on randomlogic portions of the IC, partial scan elsewhere, boundary scan on I/O lines, BIST (built-in self-test)on regular structures (e.g., memory), as well as IDDQ and delay fault tests, may be appropriate.

1988 1989 1990 1991 1992 1993 1994 1995 1996 1997

40

35

30

25

20

15

Per

cen

t o

f T

ota

l Ch

ip D

evel

op

men

t C

ost

s

YearSource: Indusrty 23213

Figure 6-46. Test Development Cost Evolution For ICs

As one can see, those looking for an easy Òcure-allÓ ASIC test solution will quickly be disap-pointed. Not only do different system applications require individualized test program strategies(Figure 6-49), but each IC may also need to implement numerous external and on-chip testmethodologies including full scan, BIST for embedded memories, scan access to core macro, andboundary scan, as illustrated Figure 6-50. Figure 6-51 illustrates the combination of the differenttests combined in order to attain a high-level (99-100 percent) of fault coverage.

But to improve ASIC release to production delays, multidimensional-design-for-test (MDFT) hasbeen defined. MDFT includes the DFT factors describes above, but also take into account pro-duction test economics, test equipment constraints, methodology, vendor constraints, and designschedules (Figure 6-52).

The Virtual Socket Interface (VSI) Alliance is a group of 150 companies representing all segmentsof the system-chip industry (systems companies, EDA vendors, IP providers, and semiconductorsvendors). The strategy of the VSI Alliance is to establish intra- and inter- company networkswhich would enable the exchange of IP in the form of macros, cores, or megacells. The use ofIntellectual Property (IP) integration in ASIC, megafunctions pre-designed and pre-tested logicbuilding blocks developed either by the manufacturers or by third-parties design houses, bringsthe problem of verification. When these IP blocks are integrated together, the interface to the IPchanges. The VSI Alliance is working toward technical standards for the mixing and matching ofthese elements on a same chip. For every creation step in the design flow of both the IP providerand the IP integrator, there has to be a corresponding verification step.



Source: Electronic Products 23197

0

10

20

30

40

50

60

70

80

90

0

200

400

600

800

1,000

1,200

Clock Speed

Logic TransistorDensity

Mill

ion

s o

f D

evic

es

Clo

ck F

req

uen

cy (

MH

z)

1995 1998 2001Year

2004 2007 2010

Figure 6-47. Increasing Integration of ASICs



CompanyLocation

Name ofTool

Test Types Tool Function

VBIT JTAG JTAG with interfaces Automatically inserts IEEE 1149.1 (JTAG)Synthesis to scan & BIST boundary scan at the RTL in VHDL or Verilog.

Also outputs functional testbench & BSDL file

Asset JTAG, ATPG, Provides IEEE 1149.1 (JTAG) boundary-scanin-system program- diagnostic & in-system programming softwareming, & BIST & hardware for circuits, boards, & systems

on PC & VXI platforms

Intellect ATPG; full-, partial-, Sequential ATPG/DFT for ASICs with no& no-scan design rules. Allows testing of clock & async

logic. Native Verilog environment. Automatedtestability selection, insertion, & analysis

CurrenTest Iddq Verifies a design's Iddq testability byidentifying static-current draining & gradingthe effectiveness of a set of functionaltest vectors

FS-ATG Test ATPG & JTAG Automatically generates test vectors for PLDs,Vector CPLDs, & FPGAs. Includes fault scoring &Generation DFT reports, DFT circuit analysis tools. AlsoSoftware supports ISP/boundary scan devices

TestBench Full-, partial-, & no- Test synthesis, testability analysis, test genera-scan; BIST; & LSSD tion, fault simulation, & diagnostics, support-

ing multiple test approaches for each chip

Test Designer AMDTA (analog & Automatic analog & mixed-signal faultmixed-signal design diagnosis, test synthesis, & sequencingand test automatic)

icBIST BIST & JTAG Automatically generates & inserts at-speedBIST for logic & embedded memories(SRAM, ROM, & DRAM) plus insetrs IEEE1149.1 (JTAG) boundary scan

memBIST-IC BIST Automatically generates & inserts at-speedBIST for embedded memories of all types,including SRAM, ROM, & DRAM

memBIST-XT BIST Automatically generates at-speed BIST IPhardware for testing board & MCM-levelmemory arrays

FastScan ATPG & BIST Creates a compact set of test pattens for full-& structured partial-scan designs, faultsimulation, BIST fault simulation, & diagnosisof failing patterns

FastScan CPA Full- & partial-scan Critical Path ATPG (CPA) option to FastScanATPG allows users to generate test vectors under

the path delay fault model to test the criticalpaths in their design

FastScan Full- & partial-scan Provides diagnostic capability for FastScanDiagnostics patterns failing on the tester, allowing

users to isolate the cause of the failure

Alternative SystemsConcepts (ASC)Windham, NH

Asset InterTechRichardson, TX

ATG TechnologyRamsey, NJ

Duet TechnologiesSan Jose, CA

Flynn SystemsNashua, NH

IBMEndicott, NY

IntusoftSan Pedro, CA

LogicVisionSan Jose, CA



Figure 6-48. Design-For-Test Tools



CompanyLocation

Name ofTool


DFTAdvisor Full- & partial-scan Testability analysis, design rule checking, &test synthesis for full- & partial-scan designs:scan selection for partial-scan & test logicinsertion to improve testability

BSDArchitect JTAG RTL test synthesis of IEEE 1149.1 (JTAG)boundary scan for ASIC/IC designs. Automaticgeneration of HDL testbench & BSDL model

DFTInsight Mentor Graphics & Graphical interface to accelerate the testSynopsys debugging & generation process using Mentor

Graphics' DFT solution. Graphical test designrules debugging for full- & partial-scan designs

FlexTest ATPG & partial- and An ATPG tool capable of creating a compactno-scan set of test patterns for partial- & no-scan

designs. Fault simulation capability for usergenerated functional patterns

FlexTest & Fault simulation & Provides fault simulation capabilities for user-FaultSim Iddq generated functional patterns. Patterns can be

fault-graded for stuck-at, transition, or Iddq

MBISTArchitect Memory BIST Synthesizes the BIST controller & interconnectsit to single or multiple memories. Also gener-ates a VHDL or Verilog testbench for verification

LBISTArchitect Logic BIST Synthesizes the BIST controller & interconnectsit to single or multiple blocks of logic & to IEEE1149.1 (JTAG) boundary scan. Also generatesa VHDL or Verilog testbench for verification

QuickFault II General-purpose full- Full-timing fault simulation & graphicaltiming fault simula- testability feedback for ASICs, boards, & MCMstion for stuck-at faults

QuickGrade II Fault coverage Probabilistic fault analysis & graphicaltestability feedback for ASICs, boards, & MCMs

FaultMaxx Transistor-level ana- Analog fault computation for both soft & hardlog fault dictionary faults& fault coverage

TestMaxx Analog ATPG for AC, Analog test condition generation for maximumDC, & transient fault coverage based on sensitivity analysisconditions

TurboFault Fault simulator for Concurrent fault simulationgrading vectors

Pioneer, ATPG, BIST, DFT Suite of testability analysis, scan synthesis,Pyramid, repairs, & Iddq & ATPG tools. Support for full-, almost-full-,& Picasso & partial-scan design. Vector compaction

Protocol JTAG IEEE 1149.1 (JTAG) boundary scan. SupportsBSDL & parmetric tests. Generates testpatterns for BSD logic. Fast turnaround(15-20 minutes per design)

Mentor Grpahics(Continued)Wilsonville, OR

OpmaxxBeaverton, OR

SynTest TechnologiesSunnyvale, CA


Figure 6-48. Design-For-Test Tools (continued)



CompanyLocation

Name ofTool


PowerFault- Iddq "Push-button" Iddq test solution for VerilogIDDQ circuits. Gives engineers a system for selecting

Iddq test vectors, clculating test coverage, &optimizing test vector selection

Sunrise TestGen ATPG, fault DFT solution for complex ASICs & ICs, includ-simulation, JTAG, & ing scan logic insertion, IEEE 1149.1 (JTAG)full- & partial-scan boundary scan implementation, testability

analysis, DRC, ATPG, & ASIC sign-off testbench

HTX RTL rule checker for Verilog RTL rule checker for scan DFTfull- & patial-scan methodologycircuits

DFT Explorer Graphical test data Graphical test data analysis environment foranalysis for full- & scan DFT, including circuit hierarchy reportspartial-scan circuits of fault coverage & testability, schematic logic

browsing, & test vector waveform display

FaultSim Fault Simulation Functional vector fault simulator for ASICs& ICs

START Full- & partial-scan, & DFT implementation tool kit, includingJTAG testability analysis, scan DRC, full- &

partial-scan DFT synthesis, & IEEE 1149.1(JTAG) boundary scan implementation

SHERLOC Fault diagnosis for Fault diagnosis for full- & partial-scan circuitsfull- & partial-scan identifies location of silicon defects following

device failure on the test equipment

ScanPlanner Scan chain routing Scan chain routing optimization supportinglinks to Cadence & Avanti place & route tools

Parallel TestGen ATPG for full- & Enables network-distributed ATPG for full-partial-scan & partial-scan circuits when used with

Sunrise TestGen. Reduces overall run timefor test development of complex ASICs & ICs

Parallel Network-distributed Enables network-distributed fault simulationFaultSim fault simulation when used with FaultSim

PathTest Path delay & Automates at-speed test development for full-transition fault ATPG & partial-scan circuits. Supports transition &

path delay fault models. Links to static timinganalysis tools, including Viewlogic's Motive

Test Gen IDDQ Iddq fault grading, Automates Iddq testing for ASICs & ICs.ATPG, & vector Includes support for fault grading of existingselection functional vectors; ATPG & Iddq vector

selection

TDX & Paradigm Full-, partial-, & no- Full timing fault simulation solutions, DFTXP scan ATPG; functional analysis & synthesis, & ATG & Iddq products

test optimization; &Iddq

Systems SciencePalo Alto, CA

Viewlogic SystemsFremont, CA

ZycadFremont, CA


Figure 6-48. Design-For-Test Tools (continued)



Design Methodology:Synchronous

Test Methodology:Optimized Scan

Partial Scan DelayFault Testing

Design Methodology:Asynchronous &

SynchronousTest Methodology:

Optimized ScanPartial ScanTest Grids




Consumer

High-End Telecom

High-End EDP


Test Methodology:Full Scan Delay

Fault TestingTest Grids





Test Methodology:Optimized Scan

Partial ScanAd-Hoc TestGrids/BIST

Military & Aerospace

LAN & WAN

File Server

19201Source: LSI Logic

Figure 6-49. Providing Test Strategies for Different Target Markets

BIST

BIST

ROM RAM

Coremacro

PLL FeedbackClock

Test I/O

Test I/O

Test I/O Test I/O

ReducedPin-Count

Testing ForLower Test Costs

Boundary Scan–Supports High I/O

Packages andExtensions to

IEEE 1149.1 andBoard-Level Test

Embedded MemoryWith Built-In Self-Test

Full-ScanSupport for

Internal Logic

Full-Scan CoreMacros


Figure 6-50. Integration of Multi-Style Design-In-Test Methodologies



Figure 6-51. DFT Test Coverage

100%

Func.Test Core

Logic

RAMBIST

FullScan

JTAGTest

PLLTest

RandomLogic

Test Modules

Async.Control

CoreTest

CumulativeFault

Coverage

Total Stuck at Fault Coverage =

(Block Fault Coverage) x (Block to Chip Size Ratio)i = 1

n

Σ23204Source: LSI Logic


ProductionTest

Economics

VendorConstraints

BIST,JTAG,ATPG,

FunctionalScan Tests,

Fault Grading

DesignSchedules

TestEquipmentConstraints

Methodology

Figure 6-52. ASIC Multidimensional DFT Components

Figure 6-53 illustrates the verification/creation flows for virtual components designed to plug intoVirtual Socket Interface. The verification and creation flows highlight the various design abstrac-tion levels and types of data needed. VSI Alliance currently has two specs out for member review:ÒAnalog/Mixed Signal VSI ExtensionÓand ÒStructural Netlist and Hard VC Physical Data TypesÓ.



SystemDesign

Bus FunctionalVerification

RTLDesign

RTL FunctionalVerification

FloorplanningSynthesisPlacement

Gate FunctionalVerification

PerformanceVerification

Routing

SystemDesign

Bus FunctionalVerification

RTLDesign

RTL FunctionalVerification

Gate FunctionalVerification

SystemModeling/Analysis

FloorplanningSynthesisPlacement

SystemRequirementGeneration

FinalVerification

Data SheetISA Model

Behavioral ModelsEmulation ModelEval. Testbench

Bus FunctionalModels

RTLSW Drivers

Functional TestTestbench

Synthesis ScriptTiming ModelsFloorplan Shell

Gate Netlist

Timing ShellClockPower Shell

Interconnect ModelsP&R Shell

PerformanceVerification

Routing

FinalVerification

SystemCharacterization

SystemIntegration

Test VectorsFault CoveragePolygon Data

VerificationFlow

VerificationFlow

CreationFlow

CreationFlow

BoardDesign

SoftwareDesign

Emulation/Prototype

VC IntegratorVirtual SocketInterface

VC Provider


Figure 6-53. Verification/Creation Flows for Virtual Components Designed to Plug Into VSI

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