asynchronous logical networks ii 1 digital systems m
TRANSCRIPT
Asynchronous logical networks II
1
Digital Systems M
2
State variable coding impact on the behaviour ?
Safe again…. With the last coding..
The transition indicated by the red arrow is very dangerous. Theoretically from 10 (stable for input 01) with input 11 the state should switch to 01 (stable – dashed red arrow). But one of the two state variables necessarily switches before the other
0
0
0
1
11
00 01 11 10
00 00
X1X2
00
11 10 00 0011
00 10 01 0010
00 00 01 0001
Y1
Y2
00
11
00 01 11 10
00 00 00
X1X2
0A 00
11 10 00 00 0B 11
00 10 01 00 0C 10
00 00 01 00 1D 01
Y1Y2
(Transition table NOT a Karnaugh map)
Z
In the case of the green arrow (10->00) Y1 is the first to change and the system reaches the state 00 (wrong !) which is stable with input 11 !
In the case of the blue arrow (10->11) where Y2 switches first the system reaches the state 11 which for 11 input shows a further race (once again a double state change from 11 to 00). If in this case Y2 switches first the system reaches the wanted state 01 (stable) with input 11 otherwise the system goes back to state 10 with a possible oscillation. Everything depends on the combinatorial network delays
A race is a state transition where two ore more state variables must switch concurrently A race is critical if a wrong stable state is reached because of non concurrent state variables change
3
In this table we have supposed a double input change which must in any case be avoided
Another (non primitive) state table N.B. this isn’t the safe
Combined inputs-states effects
Karnaugh
blue -> transitionGreen -> race Red -> stable state
11
00 01 11 10
10A 00
01 00 00B 01
00 10C 10
11 00 11 00D 11
0
0
1
0
Y2Y1
00 01
01
10 10
X2 X1
Z
0
0
1
D
00 01 11 10
A C B
X2 X1
A 00
B A A BB 01
A C C CC 10
D A D AD 11
Y2Y1Z
0
0
0
1
This table (among other problems) has a critical race. A is stable with input 01. If the input should switch to 10 (double input change) the state to be reached should be B (black solid arrow).
In practice there are two possibilities: either X1 switches first or the other way round. If X2
switches first the input transition indicated by the red arrow (00->10->10) occurs leading to to stable state C with 10 !
If X1 switches first the blue transition occurs which in turn can lead to different situations if starting from state A-00 (with input 00 and theoretical destination D-11) either Y1 or Y2 switches first. In the first case it is possible that the wanted final state is reached (violet dashed transition). In the second case (dashed green transition) the system reaches C stable again! It must be noticed that further input or states delays could provoke even different dynamic transitions!!
4
How to cope with this situation ?Setting aside the input problems let’s analyse all the races (green) of the state variables that is all transitions which imply the change of two state variables. The previous table can be modified. Multiple transitions. In circled orange the modifications
Some remarks:
• Multiple transitions are not always possible (more are the stables states in a column more unlikely are multiple transitions)
• In the columns where only a stable state is present it is not necessary to insert multiple transitions provided no oscillations can occur
• Multiple transitions induce network delays
Synthesize and simulate
11
00 01 11 10
10A 00
01 00 00B 01
00 10C 10
11 00 11 00D 11
0
0
1
0
Y2Y1
00 01
01
10 10
X2 X1
Z
Future state
change
01
MultipleTransition 10
MultipleTransition
01
Transitionchange
11
In the first column from C the system should switch to A and then to D. It is therefore possible to switch directly to D. By so doing a multiple transition from A(00) to D(11) (A->C->D) is possible.
5
Let’s consider the safe initial synthesis
01
00 01 11 10
00 00 00
X1X2
000
01 11 00 00 001
00 11 10 00 011
00 00 10 00 110
y1y2
Z = Y1 !Y2
Y1 = y1t+t = (!x1x2y2 + x1x2y1) t
Y2 = y2t+t = (!x1!x2!y1 + !x1x2 y2) t
Here we have a race . Theoretically since there is only one stable state in the column no problems should arise but if the variables switching times are different an oscillation is always possible. Better a multiple transition (11->01->00)
Z
6
Analysis of this asynchronous sequential circuit (inputs X1,X2 , Reset and output Z)
1. Detect the state variables and their equations and using the algebra theorems simplify them indicating what theorems have been used
2. Detect the state transition table and its problems (if any)3. Detect all possible malfunctions and provide a table solving them4. Synthesize the initial transition table (after removing the possible races) using SR feedback
7
Y1= !(!x1 !x2) (y1 + x1y2) = (x1+x2)(y1+ x1y2)= x1y1 + x1y2 + x2y1 + x1x2y2= = x1y1 + x1y2 + x2y1
Y2 = !(!x2y1 + !(x1x2 + y2)) = !(!x2y1) (x1x2+y2)= (x2 +!y1) (x1x2+y2)= = x1x2 + x1x2!y1 + x2y2 + !y1y2= x1x2 + x2y2 + !y1y2
Z = y1!y2
Idempotence !
Y1
Y2
Leaving aside Reset
Z = y1!y2
00
00 01 11 10
00 01 00
X1
X2
000
01 01 11 11 001
00 11 11 10 011
00 10 11 10 110
y1y2
01 is never stable and reacheable (it can be reached only from 00 with 11 input BUT is unstable)
8
Y2 = x1x2 + x2y2 + !y1y2
Y1= x1y1 + x1y2 + x2y1
00
00 01 11 10
00 01 00
X1X2
000
01 01 11 11 001
00 11 11 10 011
00 10 11 10 110
y1y2
In red the only critical race
00
00 01 11 10
00 01 00
X1X2
000
01 01 11 11 001
10 11 11 10 011
00 10 11 10 110
y1y2
Table without critical races
9
00
00 01 11 10
00 01 00
X1X2
000
- - 11 - 001
10 11 11 10 011
00 10 11 10 110
y1y2
Simplified equivalent table (how must it be modified to insert a don’t care in the only transition using state 01 ?)
Y1 = y2 + X2y1 + X1y1
Y2 = X2y2 + X1X2
S1 = X1y2R1 = !X1!X2!y2
S2 = X1X2R2 = !X2y1
00
00 01 11 10
00 01 00
X1X2
000
01 01 11 11 001
10 11 11 10 011
00 10 11 10 110
y1y2
Initial table without critical race(zeros red/blue -> R=1 S=0 with black zeros , ones red/blue -> S=1, R=0 with black ones)
10
Removedrace
11
Incompletely specified state/transition tables
00
00 01 11 10
01 00 10
X2
000
00 01 11 11 001
00 01 11 10 011
00 00 11 10 110
y1y2
X1
The green transitions can NEVER occur since two simultaneous inputs changes can never occur …..
00
00 01 11 10
01 -- 10
X2
000
00 01 11 -- 001
-- 01 11 10 011
00 -- 11 10 110
y1y2
X1
… and therefore can be substituted with ”don’t care”
Y1=X1
Y2=X2
The network is combinatorial as it could be immediately detected (the stable states coincide with the inputs !!!).
A table where each state is stable for only one input configuration is a primitive table
Z
Z
12
How is an asynchronous sequential network designed? - 1
1st step: a primitive state diagram must be designed. If for each transition a new state is reached (or inserted) no problem, provided the history of the circuit is correctly interpreted otherwise the state number explodes. It must be understood the time development of the circuit and to detect the states which correct represent this develooment. There are no algorithms to design the state diagram but the human brain only
Safe again
01,0
01,0
11,1
11,-
01,0
E
10,0
11,0
F
11,0
10,0
01,0
11,0
01,-
10,0
D
10,-
00,000,0
00,0
01 1) Mealy (but could be Moore)2) The transitions outputs are don’t cares since
their values are not important (the difference is only WHEN the change occurs)
3) Primitive table4) From C with input 01 the transition is not to
B otherwise the output would be activated without the correct sequence (see circuit history)
5) The states D,E and F do not belong to the correct sequence
X1X2,Z00,0
A B C
13
A
X1X2,Z00,0
B
01,0
01,0C
11,1
11,-
01,0
E
10,0
11,0
F
11,0
10,0
01,0
11,0
01,-
10,0
D
10,-
00,000,0
00,0
How is an asynchronous sequential network designed? - 2
2nd step: primitive state table (the transition which would imply the change of two inputs variables are don’t cares)
A,0
00 01 11 10
B,0 -,- D,0
X1X2
A
A,0 B,0 C,- -,-B
-,- E,- C,1 D,-C
A,0 -,- F,0 D,0D
-,- E,0 F,0 D,0
E
F
A,0 E,0 F,0 -,-
14
How is an asynchronous sequential network designed? - 33rd step: compatible states detection for the state reduction. Two states are compatibile if, where
specified, for the same inputs they provide the same outputs (where specified) and switch to the same states or to compatible states. Implication triangular table.Two by two comparison between states. If the outputs (where defined) are different for the same input configuration the states are incompatible. Otherwise in the square the condition (if any) uder which they could be compatible is recorded.
A B C D E
B
C
D
E
F
A,0
00 01 11 10
B,0 -,- D,0
X1X2
A
A,0 B,0 C,- -,-B
-,- E,- C,1 D,-C
A,0 -,- F,0 D,0D
A,0 E,0 F,0 -,-E
-,- E,0 F,0F
Two states are compatible if the implications are cyclic or if there are no conditions (as is the case for DE , AB etc).
The compatibility IS NOT transitive
--
BE
BE
BE
CF
CF
BECF
--
-- --
--
A and B uncoditionally
compatible
BE
A and C compatible if B
and E compatible
C and D incompatible becuase of the outputs
D,0
([AB]) ([AB], [AD])
([AB], [AD],C, [DE]) ([AB], [AD],C, [DE], [DF])
([AB], [AD],C, [DE], [DF], [EF])
([AB], [AD],C]) Two by two compatible states (introducing step by step the
couples)
A state can be added to a state set if compatible with all belonging states (and so on) Maximal compatibility classes ([AB], [AD],C, [DEF). NB A state can belong to more classes
15
NB In case of fully specified tables (without don’t cares) the coverture consists of all maximal classes (disjoint !) which obviously satisfy the closure condition too (indistinguishable states)
[A,B] => a[C] => b[D,E,F] => g
These are three maximal compatibility classes (not all the compatibility classes !!) which satisfy the closure and the coverture (the maximal class [AD] hasn’t been used)
A,0
00 01 11 10
B,0 -,- D,0
X1X2
A
A,0 B,0 C,- -,-B
-,- E,- C,1 D,-C
A,0 -,- F,0 D,0D
A,0 E,0 F,0 -,-E
-,- E,0 F,0F D,0
Compatibility classes: states set two for two compatible
Maximal compatibility class: a class to which no states can be added
“Coverture” condition: each state of the initial table must be present in a least one final class
“Closure” condition: the future states of a class for each input , if not indifferent, must belong to the same compatibility class
The set of all naximal compatibility class is always closed and e covered
The minimum states set doesn’t consist necessarily of maximal classes
If not all maximal classes or non-maximal classes are chosen coverture and closure must be carefully checked
A,0
00 01 11 10
B,0 -,- D,0
X1X2
A
A,0 B,0 C,- -,-B
-,- E,- C,1 D,-C
A,0 -,- F,0 D,0D
A,0 E,0 F,0 -,-E
-,- E,0 F,0F D,0
16
How is an asynchronous sequential network designed? - 4
4° step: coding
X1X2
00a
01b
11g
10
NB In this coding there is a problem; races !
00 01 11 10
00,0 00,0 01,- 11,0
-,- 11,- 01,1 11,-
00,0 11,0 11,0 11,0
-,- -,- -,- -,-
y2
y1
If in a table there are no multiple transitions which solve the races, the only possible solution is to increase the number of states (which allow multiple transitions removing the races)
y1 00 01 11 10X1
X2
00,0 00,0 01,- 10,000
-,- 11,- 01,1 11,-01
10,0 11,0 11,0 11,011
00,0- -,- -,- 11,0-10
y2
00 01 11 10X1
X2
,0a ,0a ,-b ,0ga
-,- ,-g ,1b ,-gb
,0a ,0g ,0g ,0gg
[A,B] => a (right sequence)
[C] => b (safe opened)
[D,E,F] => g (out of the right sequence)
17
How is an asynchronous sequential network designed ?- 5
00 01 11 10X1
X2
00,0 01,- 10,000
-,- 11,- 01,1 11,-01
10,0 11,0 11,0 11,011
00,0 -,- -,- 11,0-10
Direct feedback
y1y2
Y1= !X1y2 + y1y2 + X1!X2
Y2= X2y2 + X1X2 + X1y1 + X1y2
And with SR feedback???
Why these networks differ from the previous ones ?1) Mealy2) States minimizationn3) Different coding
Z = !y1y2 00 01 11 10X1
X2
00,0 00,0 01,- 10,000
-,- 11,- 01,1 11,-01
10,0 11,0 11,0 11,011
00,0 -,- -,- 11,010
y1y2
00,0
18Xilinx asynchronous safe Mealy
19
Using all maximal compatibility classes - 6
[A,B] => a[C] => b[D,E,F] => g[AD] => d
All maximal classes
What about A and D found in two maximal compatibility classes? What choice? It is indifferent, possibly avoiding the races !!!
([AB], [AD],C, [DE], [DF], [EF])
Couples of compatible states
00 01 11 10X1
X2
/ ,0a d ,0a ,-b / ,0g da
-,- ,-g ,1b / ,-g db
/ ,0a d ,0g ,0g / ,0g dg
/ ,0a d ,0a ,0g / ,0g dd
00 01 11 10X1
X2
,0d ,0a ,-b ,0ga
-,- ,-g ,1b ,-gb
,0d ,0g ,0g ,0gg
,0d ,0a ,0g ,0gd
00 01 11 10X1
X2
00a
01b
11g
10,0 00,0 01,- 11,0
-,- 11,- 01,1 11,-
10,0 11,0 11,0 11,0
10,0 00,0 11,0 11,0 10d
A,0
00 01 11 10
B,0 -,- D,0
X1X2
A
A,0 B,0 C,- -,-B
-,- E,- C,1 D,-C
A,0 -,- F,0 D,0D
A,0 E,0 F,0 -,-E
-,- E,0 F,0F D,0
Multiple choices
20
00 01 11 10X1
X2
00a
01b
11g
10,0 00,0 01,- 11,0
-,- 11,- 01,1 11,-
10,0 11,0 11,0 11,0
10,0 00,0 11,0 11,0 10d
This table has two columns with only one stable state (inputs 00 and 10) and therefore no critical races. It is however always better to avoid the double state variables change. Therefore in a with input 10 we insert 01 as future state.
01,0
y1y2
Using all maximal compatibility classes - 7
With SR ??
11,0
If we want to avoid output glitches during the transition we can insert a 0
Y2 = X1 + X2y2
Y1 = !X1!X2 + !X1y2 + X1y1 + !X2y2 Z = !y1y2
21
Previous exampleMultiple transitions (races in green)
This is a Karnaugh map
Synthesize and simulate
00 01 11 10Y3Y2Y1
X2 X1
100 010A 000
001 000 000B 001
000 010C 010
011 111 011 111D 011
0
0
1
0
000 001
001
010 010
110 ---E 100
--- --- ---F 101
111 100H 110
011 110 --- 110G 111
-
-
-
-
000 000
---
--- 100
Right ?
11
00 01 11 10
10A 00
01 00 00B 01
00 10C 10
11 00 11 00D 11
0
0
1
0
Y2Y1
00 01
01
10 10
X2 X1
Z
00 01 11 10Y3Y2Y1
X2 X1
011 010A 000
001 000 000B 001
000 010C 010
011 000 011 000D 011
0
0
1
0
000 001
001
010 010
? ?E 100
? ? ?F 101
? ?H 110
? ? ? ?G 111
?
?
?
?
? ?
?
? ?
Z
100
110
111
011
111
110
100
000
111
110
100
000
22
A previous exercise again
GFEDCBA
H
G
F
E
D
C
B
BD
BD
-----
CF
CF
-----
-----
CF CF
-----
GE GE
00 01 11 10X1 X2
A -A
H - CB
A -D
- E C DC
0
1
0
0
E B
B
C D
A FE
- G FF
H EH
H G F -G
0
1
1
1
E -
B
- B
a AEb BHg CDd FG
00 01 11 10X1 X2
da
a gb
bd
a a gg
0
1
0
1
ba a
bb
g
d d b
An asynchronous sequential network has two inputs X1 and X2 and an output Z. The inputs X1 and X2 never change at the same time. The output Z modifies its value only when a rising edge of X1 or of X2 occurs: in the first case Z=1, in the latter Z=0
11
01
23
10,0000,01X1,X2
11,10
11
,0g
10
01,11
00,01
,0a
10,00
,1b
,1d
00 01 11 10X1 X2
da
a gb
bd
a a gg
0
1
0
1
ba a
bb
g
d d b
Resulting network
Two stable states per column; races risks !!!
Please notice that the table is not primitive: this because we
reach a through different paths
24
00 01 11 10X1 X2
da
a gb
bd
a a gg
0
1
0
1
ba a
bb
g
d d b
First coding (with races)
00 01 11 10X1 X2
10 00a
00 01 01g
10d
01 11b
0
0
1
1
1100 00
0100
11
1010
0000
01 0111
00
11
11
y1y2
Z = y1
Y2 = X1y2 + X1!X2 + !X2y1
Y1 = !X2y1 + X1!y2 + y1!y2
Critical race (green)
25
00 01 11 10X1 X2
da
a gb
bd
a a gg
0
1
0
1
ba a
bb
g
d d b
00 01 11 10X1 X2
10 00a
00 01 01g
10d
01 11b
0
0
1
1
1100 00
0100
11
1010
0000
01 0111
00
11
11
y1y2
Error !!10 stable !!
Races elimination
00 01 11 10X1 X2
10 00a
00 01 01g
10d
01 11b
1100 00
0100
11
1010
0000
01 0111
00
11
11
y1y2
01
Z = y1 10Y1 = y1y2 + !X2y1 + X1y2 + X1!X2
Y2 = !X2y1 + y1!y2 + X1!y2
26
00 01 11 10X1 X2
010 000a
000 011 001b
001 010d
000 001 011g
0
1
0
0
001
000
-- 100e
-- -- 101z
110q
111h
-
-
-
-
--
000 000
001 001
011011
010 010
--
--
-- -- --
---- --
111
101
100
000??
Another solutionFirst redundant coding
00 01 11 10X1 X2
da
a gb
bd
a a gg
0
1
0
1
ba a
bb
g
d d b
--
X1 X2
00 01 11 10
010 000a
000 100 001b
001 010d
011
0
1
-
1
001
001
-- -- --
000 000
001 001
000
--
0
-
-
-
000
-- -- --
100g
101
110
111
010 010
100 100
-- -- -- --
-- -- -- ----
----
y3 y2 y1
27
00 01 11 10X1 X2
da
a gb
bd
a a gg
0
1
0
1
ba a
bb
g
d d b
Second redundant coding
g100
a000
b001
d010
101
011
Adjacency diagram001
100
001
001
011
100
101
001
011
28
X1 X2
00 01 11 10
010 00a
000 100 01b
001 10d
11
0
1
-
1
001
001
-- -- --
000 000
001 001
--
010 010001
100
001
001
011
101
001
011
y2 y1
y3 = 0
000 0
-
-
-
000
-- -- --
00g
01
10
11
100 100
-- -- -- --
-- -- -- ----
----
100
y3 = 1
y3
00 01 11 10
-0
- 1001
10 1
0 -100-
y2y1
Z = y1 + y2
Y3 = X1X2y1 + X1y3
Y1 = X1!X2!y3 + X1y1!y3 + !X2y1 + !X2y2
Y2 = y2!y1 + X1X2!y1!y3
Second redundant coding
29Xilinx asynchronous no_race_multiple
30
A Moore asynchronous sequential network has two inputs X («Input»)and CK («Clock») and an output Z («Output»). Both X and CK are initially 0.
a) Upon the first positive edge of CK (0 to 1) following the condition X=1 the output becomes 1 and so remains until the successive positive transition of CK when the output becomes in any case 0
b) The output remans 0 until a positive edge sampling X=0. After this event back to point a)
NB: In the following solution the time distance beween two consecutive positive edges of CK is called «period»
Example IV
BA zero was
sampled 01
01
00
10
10
10
11
00
10
00
11 10
11
01
01
11
10
00
11
01
0010
01 11
11
01C,0
00
00X,CK
J,1 N,0
NB. After generating a 1 between two consecutive positive edges of CK, a period with output=0 is must elapse and CK MUST sample a X=0 input before the output can become 1 again
A,0
W,1
X,0
01
B,0
10 11
Y,1 Z,1
M,0
10
Ready for activating the
output=1
Here the output is 1 for a CK periodCareful! Before a new output=1 is possible one period with output=0 must be inserted
and X=0 must be sampled !
X=0 sampledRestart
M,N,R,Q -> X=1 sampled again. A period with X=0 sampled must in any case elapse
00
01
00
31
R,0
Q,0
A Moore asynchronous sequential network has two inputs X («Input») and CK («Clock») and an output Z («Output»). Both X and CK are initially 0.a) Upon the first positive edge of CK (0 to 1) following the condition X=1 the output becomes 1 and so keeps until the successive positive
transition of CK when the output becomes in any case 0b) The output keeps 0 until a positive edge sampling X=0. After this event back to point a)
Here output=0 since a period with output=1
period is elapsed
11
32
00 01 11 10X, CK
A
B
X
C
0
0
0
0
Y
Z
1
1
J
W 1
1
M
N
Q
R
0
0
0
0
WZYXCBA
J
W
Z
Y
X
C
B -----
M
N
R
Q
RNMJ
-----
BQXNARXN
XN
BQAR
-----
CY
BQCMARCM
AR
ARCM
CY
BQXNXNCM
XN
BQCM
YMXNARYMARXNARYM
-----
YM
ZB
YM
ZB -----
----
BQ
-----
-----
----- BQ
-
A C
A -
- B X
B X
Y X
-
J YZ
Y W
-
B
C
J B
J WM
- W
- Q
R - N
QR
BR - N
M N
M
M -
-
Z
-
A
-----
33
WZYXCBA
J
W
Z
Y
X
C
B -----
M
N
R
Q
RNMJ
-----
BQXNARXN
XN
BQAR
-----
CY
BQCMARCM
AR
ARCM
CY
BQXNXNCM
XN
BQCM
YMXNARYMARXNARYM
-----
YM
ZB
YM
ZB -----
----
BQ
-----
-----
----- BQ
00 01 11 10X, CK
A
B
X
C
0
0
0
0
Y
Z
1
1
J
W 1
1
M
N
Q
R
0
0
0
0
-
A C
A -
- B X
B X
Y X
-
J YZ
Y W
-
B
C
J B
J WM
- W
- Q
R - N
QR
BR - N
M N
M
M -
-
Z
-
A
[ABC] [AX] [YZ] [JW] [MNQ] [NR] [ ] [ ] [ ] [ ] [ ] [ ]a b g d e z
Maximal compatibility classes
-----
34
00 01 11 10X, CK
,a ba
,a b gb
ad
d g dg
0
0
1
1
b
b
e d
e
e ,e zz
0
0
e
a a
a
g
d
z e ,e z
z a
00 01 11 10X, CK
A
B
X
C
0
0
0
0
Y
Z
1
1
J
W 1
1
M
N
Q
R
0
0
0
0
-
A C
A -
- B X
B X
Y X
-
J YZ
Y W
-
B
C
J B
J WM
- W
- Q
R - N
QR
BR - N
M N
M
M -
-
Z
-
A
[ABC] [AX] [YZ] [JW] [MNQ] [NR] [ ] [ ] [ ] [ ] [ ] [ ]a b g d e z
With all maximal classes
35
Race
00 01 11 10X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
110
110 110111
0
0
110
000 000
000
011
010
111 110 110
111 000
a
b
d
g
e
z
ABC
X
YZ
JW
MNQ
NR
[ABC] [AX] [YZ] [JW] [MNQ] [NR] [ ] [ ] [ ] [ ] [ ] [ ]a b g d e z
00 01 11 10X, CK
,a ba
a,b gb
ad
d g dg
0
0
1
1
b
b
e d
e
e e,zz
0
0
e
a a
a
g
d
z e e,z
z a
In red the chosen states
36
00 01 11 10X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
110
110 110111
0
0
110
000 000
000
011
010
111 110 110
111 101
101
- -100
0
0
-- 100 -
- 000
Multiple transition
Y2Y1Y000 01 11 10
X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
110
110 110111
0
0
110
000 000
011
010
111 110 110
111 000
a
b
d
g
e
z
Y2Y1Y0
000
37
00 01 11 10X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
000 000
000
011
010
110 0110111 110 110
110 110111 0111 101
101 0 -- 100 -
- -100 0 - 000
Y2Y1Y000 01 11 10
X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
110
110 110111
0
0
110
000 000
000
011
010
111 110 110
111 101
101
- -100
0
0
-- 100 -
- 000
Y2Y1Y0
Y2,Z
Z = !Y2 Y1Y2 = y2y1 + y2y0 + XCKy1!y0
38
00 01 11 10X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
110
110 110111
0
0
110
000 000
000
011
010
111 110 110
111 101
101
- -100
0
0
-- 100 -
- 000
Y2Y1Y0
Y1
00 01 11 10X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
000 000
000
011
010
110 0110111 110 110
110 110111 0111 101
101 0 -- 100 -
- -100 0 - 000
Y2Y1Y0
Y1 = Xy1 + !y2y1y0 + y2y1!y0 + !CKy1 + XCK!y2y0
39
00 01 11 10X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
110
110 110111
0
0
110
000 000
011
010
111 110 110
111 101
101
- -100
0
0
-- 100 -
- 000
Y2Y1Y0
000
Y0
Y2Y1Y000 01 11 10
X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
000 000
000
011
010
110 0110111 110 110
110 110111 0111 101
101 0 -- 100 -
- -100 0 - 000
Y0 = X!y1y0 + !X!CKy2 + X!CK!y1 + CK!y2y1y0 + !Xy2y1y0
40Example IV - Schematic – maximal classes
41
00 01 11 10X, CK
A
B
X
C
0
0
0
0
Y
Z
1
1
J
W 1
1
M
N
Q
R
0
0
0
0
-
A C
A -
- B X
B X
Y X
-
J YZ
Y W
-
B
C
J B
J WM
- W
- Q
R - N
QR
BR - N
M N
M
M -
-
Z
-
A
Non maximal classes
Covered and closed set
00 01 11 10X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
110
--- 111111
0
0
110
000 000
---
011
010
111 110 110
111 101
101
- -100
0
0
-- 100 -
- 000
a
b
d
g
e
z
00 01 11 10X, CK
aa
a gb
ad
d g dg
0
0
1
1
b
b
e d
e
e zz
0
0
e
a a
--
g
d
z e z
z a
[ABC] [AX] [YZ] [JW] [MNQ] [NR] [ ] [ ] [ ] [ ] [ ] [ ]a b g d e z
[ABC] [X] [YZ] [JW] [MNQ] [R] [ ] [ ] [ ] [ ] [ ] [ ]a b g d e z
42
Y2,Z
00 01 11 10X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
000 000
000
011
010
110 0110111 110 110
110 110111 0111 101
101 0 -- 100 -
- -100 0 - 000
Y2Y1Y0
Z = !Y2 Y1Y2 = y2y1 + y2y0 + XCKy1!y0
Max
00 01 11 10X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
000 000
---
011
010
110 0110111 110 110
--- 111111 0111 101
101 0 -- 100 -
- -100 0 - 000
Y2Y1Y0
Z = !Y2 Y1Y2 = y2y1 + y2y0 + XCKy1!y0
Non Max
43
Y1
00 01 11 10X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
000 000
000
011
010
110 0110111 110 110
110 110111 0111 101
101 0 -- 100 -
- -100 0 - 000
Y2Y1Y0
Y1 = Xy1 + !y2y1y0 + y2y1!y0 + !CKy1 + XCK!y2y0
Max
00 01 11 10X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
000 000
---
011
010
110 0110111 110 110
--- 111111 0111 101
101 0 -- 100 -
- -100 0 - 000
Y2Y1Y0
Y1 = Xy1 + CK!y2y0 + y2y1!y0 + !CKy1
Non Max
44
Max
Y0 = X!y1y0 + !X!CKy2 + X!CK!y1 + CK!y2y1y0 + !Xy2y1y0
Y2Y1Y000 01 11 10
X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
000 000
000
011
010
110 0110111 110 110
110 110111 0111 101
101 0 -- 100 -
- -100 0 - 000
Y0
Y0 = CK!y2y0 + !X!CKy2 + X!CK!y1 + y2y1y0
Y2Y1Y000 01 11 10
X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
000 000
---
011
010
110 0110111 110 110
--- 111111 0111 101
101 0 -- 100 -
- -100 0 - 000
Non Max
45Esempio IV - Schematic – non maximal classes
46
entity Soluzione is Port ( Reset : in STD_LOGIC; Input : in STD_LOGIC; Clock : in STD_LOGIC; Output : out STD_LOGIC; State : inout STD_LOGIC_VECTOR(2 DOWNTO 0)
);
-- 8 states
end Soluzione;
architecture Behavioral of Soluzione is beginmono: process (Reset, Input, Clock, State)begin
if (Reset ='1') then state <= "000";else
case state is when "000" =>
if (Input ='1' and Clock ='0') then state <= "001";
end if; when "001" =>
if (Input ='0' and Clock ='0') thenstate <= "000";
elsif (Input ='1' and Clock ='1') thenstate <= "011";
end if;
when "011" => if Clock = '0' then
state <= "010"; end if;
VHDL program representing the transition table
(with races)
Y2Y1Y000 01 11 10
X, CK
000000
000 011001
000010
010 011 010011
0
0
1
1
001
001
110 010
000 000
---
011
010
110 0110111 110 110
--- 111111 0111 000
Non Max
47
when "010" =>
if (Input ='0' and Clock = '1') thenstate <= "000";
elsif (Input ='1' and Clock = '1') thenstate <= "110";
end if;
when "110"=>if (Input ='0' and Clock = '0') then
state <= "111"; end if;
when "111" => if (Input ='0' and Clock = '1') then
state <= “000" ; end if;
when others => null;
end case;
if (State = "010" or State = "011") then Output<= '1';
else Output <='0';
end if;
end if;end process mono; end Behavioral;
48
Exercise
Starting from the initial description write and test a VHDL program of the previous sequential machine
49
A music playback device has volume regulation system with three keys ‘+’ , ‘–‘ and ‘■’ whose behaviour is the following; when no key is depressed – ■ + are all 0, and at any time only one key can be depressed. A release of a key and the concurrent depression of another is impossible.
- ■ +
Design an asynchronous sequential circuit with two outputs I(ncrease) and D(ecrease), used to increase (ID=10) or decrease (ID=01) the volume.
• If the volume must not be regulated or the as soon as ‘■’ key is depressed the volume must not change.
• When the +’ ( ‘–‘) key is depressed the volume must be increased (decreased) upon the release of the key. The increase (decrease) of the volume stops either when the +’ ( ‘–‘) is released after being depressed again or as soon as ‘■’ is depressed.
• If ‘–‘ (+) is depressed while the volume increases (decreases) the volume change is stopped immediately and is reversed as soon as ‘–‘ (+) key is released
000,-0
001,10+ key depressed
again - Ready to stop volume change
000,-0+ key releasedVolume increase
50
010,00 000,00
D
001,10
001,00+ key depressed
Surely a simmetrical state diagram!
Here the output is a «don’t care» because it does not matter when the
output changes
• If the volume must not be regulated or as soon as when the ‘■’ key is depressed the volume must not change
• When the +’ ( ‘–‘) key is depressed the volume must be increased (decreased) upon the release of the key. The volume increase (decrease) stops either when the +’ ( ‘–‘) is released after being depressed again or as soon as ‘■’ is depressed.
• If ‘–‘ (+) is depressed while the volume increases (decreases) the volume change must sbe reversed as soon as ‘–‘ (+) key is released
000,0-
000,0-
- key releasedVolume decrease
100,01- key depressed again - Ready to
stop volume change
H
100,01
001,0-
Volume decreaseimmediate stop
000,01
G
010,0- ■ Key depressedVolume decreaseImmediate stop
010,00
E
010,-0 ■ Key depressedVolume increaseImmediate stop
100,-0
Volume decreaseimmediate stop
000,10
C
100,00
F
001,00
B
100,00- key depressed 000,00
A
-■+,ID
51
AG
GF
--
E
--
DC
AC
BA
H
G
AGF
--E
D
C
ACB
AGAGCG
--AC
AC
Maximal compatibility classes[AE],[B],[C],[DEH],[F],[G]
For the coverture all of them are necessary But could I leave A alone ?
X1 = -X2 = ■
A
B
C
D
E
F
X3 = +
G
A,00
000 001 011 010
B,00 -,- E,00
C,-0 B,00 -,- -,-
C,10 D,10 -,- E,-0
A,-0 D,10 -,- -,-
A,00 -,- -,- E,00
G,0- -,- -,-
G,01 B,0- -,- E,0-
A,0- -,- -,-H
F,00
100 101 111 110
-,- -,- -,-
-,- -,- -,- -,-
F,-0 -,- -,- -,-
-,- -,- -,- -,-
-,- -,- -,- -,-
F,00 -,- -,-
H,01 -,- -,- -,-
H,01 -,- -,-
-,-
-,-
-,-
-,-
52
[AE] => a[B] => b[C] => c[DEH] => d[F] => f[G] => g
X1 = -X2 = ■
A
B
C
D
E
F
X3 = +
G
A,00
000 001 011 010
B,00 -,- E,00
C,-0 B,00 -,- -,-
C,10 D,10 -,- E,-0
A,-0 D,10 -,- -,-
A,00 -,- -,- E,00
G,0- -,- -,-
G,01 B,0- -,- E,0-
A,0- -,- -,-H
F,00
100 101 111 110
-,- -,- -,-
-,- -,- -,- -,-
F,-0 -,- -,- -,-
-,- -,- -,- -,-
-,- -,- -,- -,-
F,00 -,- -,-
H,01 -,- -,- -,-
H,01 -,- -,-
-,-
-,-
-,-
-,-
X1 = -X2 = ■
X3 = +
a,00
000 001 011 010
,b 00 -,- /a d,00
c,-0 ,b 00 -,- -,-
c,10 d,10 -,- /a d,-0
a,00 d,10 -,- /a d,00
g,0- -,- -,-
g,01 b,0- -,-
f,00
100 101 111 110
-,- -,- -,-
-,- -,- -,- -,-
f,-0 -,- -,- -,-
d,01 -,- -,- -,-
f,00 -,- -,- -,-
d,01 -,- -,- -,-
[AE] => a
[B] => b
[C] => c
[DEH] => d
[F] => f
[G] => g
-,-
/a d,0-
53
X1 = -X2 = ■
X3 = +
a,00
000 001 011 010
,b 00 -,- a,00
c,-0 ,b 00 -,- -,-
c,10 d,10 -,- a,-0
a,00 d,10 -,- ,a 00
g,0- -,- -,-
g,01 b,0- -,-
f,00
100 101 111 110
-,- -,- -,-
-,- -,- -,- -,-
f,-0 -,- -,- -,-
d,01 -,- -,- -,-
f,00 -,- -,- -,-
d,01 -,- -,- -,-
[AE] => a
[B] => b
[C] => c
[DEH] => d
[F] => f
[G] => g
-,-
,a 0- -,-
X1 = -X2 = ■
X3 = +
000,00
000 001 011 010
001,00 -,- 000,00
011,-0 001,00 -,-
011,10 010,10 -,-
000,00 010,10 -,- 000,00
101,0- -,- -,- -,-
101,01 001,0- -,-
-,- -,- -,- -,-
-,- -,- -,-
100,00
100 101 111 110
-,- -,- -,-
-,- -,- -,-
-,- -,- -,-
010,01 -,- -,- -,-
100,00
-,-
-,- -,-
-,- -,-
-,- -,- -,-
-,- -,-
-,-
-,--,-
000a
001b
011c
010d
100f
101g
y3 y2 y1
111
110
-,-
000,-0
000,0-
-,-
100,-0
010,01
-,-
-,-
010,-0 111,-0
110,-0
100,-0
No way with this codingFind and alternative coding!!
000,0-
100,0-
54
Can we transform a Moore table into a Mealy table?
B
00 01 11 10
A A A
X1X2
0A
B C A A 0B
A C D A 0C
A A D A 1D
Moore
B,0
00 01 11 10
A,0 A,0 A,0
X1X2
A
B,0 C,0 A,0 A,0B
A,0 C,0 D,1 A,0C
A,0 A,0 D,1 A,0D
Mealy
B,0
00 01 11 10
A,0 A,0 A,0
X1X2
A
B,0 C,0 A,0 A,0B
A,0 C,0 D,- A,0C
A,- A,- D,1 A,-D
Mealy
Let’s associate to each transition the output value of the destination state (or of the source state)
Obviously in the transitions the outputs can be don’t care if we
are not interested whether the network anticipates or delays
the outputs
55
B,1
00 01 11 10
A,0 A,1 A,1
X1X2
A
B,1 C,- A,1 A,-B
A,1 C,0 D,1 A,0C
A,- A,0 D,1 A,1D
Mealy
Same state with different ouptuts. The
state must be doubled
Multiple transitionsRemoved
B
00 01 11 10
A0 A1 A1
X1X2
A0
B C A1 A1B
A1 C D A1C
B A0 D A1D
B A0 A1 A1A1
0
1
1
0
1
Moore
Stable output 1
B
00 01 11 10
A0 A1 A1
X1X2
A0
B C A1 A1B
A1 C D A0C
A1 A0 D A1D
B A0 A1 A1A1
0
1
1
0
1
Can we transform a Mealy table into a Moore table?
01
00
11
56
A particular synthesis - 1
Design an asynchronous sequential network whose output Z assumes the value of the input D upon the positive transition (sampling) of an input C(lock). The output is stable until C samples a different input. (Obviously a symmetrical diagram)
01
11
11
B,0
01
00
11
01
10
10DC
11
01
100001
10
10
11
00
00
10
D
G
00 01 11 10
A B ---
C
A
--- A B CB
G --- D CC
--- E D HD
F E D ---E
F A --- HF
G A --- CG
F --- D HH
0
0
0
1
1
1
0
1
00
C,0
D,1 H,1E,1F,1
A,0G,0
A one is sampled: the
output changesA zero is
sampled: the output changes
Blue states => output 0 stableRed states => output 1 stable
Yellow states are the only states from where an output change can occur
57
A particular synthesis - 2
G
00 01 11 10
A B ---
C
A
--- A B CB
G --- D CC
--- E D HD
F E D ---E
F A --- HF
G A --- CG
F --- D HH
0
0
0
1
1
1
0
1
D
a
00 01 11 10
a a b
C
a
a -- g bb
d g g gg
d a -- gd
0
0
1
1
D
00
00 01 11 10
00 00 01
C
00
00 -- 11 0101
10 11 11 1111
10 00 -- 1110
0
0
1
1
D
y2
y1
---
BD BD
---
AE AE
--- --- ---
--- --- ---
B
C
D
E
F
G
H
A B C D E F G
[ABG] => a[C] => b[DEH] => g[F] => d
Here we don’t use the maximal compatibility classes but coverture and closure are verified
58
00
00 01 11 10
00 00 01
C
00
00 -- 11 0101
10 11 11 1111
10 00 -- 1110
D
y2
y1
A particular synthesis - 3
0
0
1
1
Y1= Y2C + Y1!CY2= Y2C + D!CZ = Y1
D(elay) Flip Flop – The D name will be explained later - The arrows indicate the output variations
It is the only FF used in the synchronous networks
NB: The correct behaviour takes for granted obviously (as is the case with all asynchronous networks) that the input D is stable during the transition 0 to 1 of the C(lock) ( -> b g and ->d a) which means the a little time t1 (setup time) before the C transition and t2 (hold time) after the C transition D must be stable. t1 and t2 values depend on the technology. If this condition is violated the output behaviour is unpredictable (aliasing - metastability)
a
b
g
d
59
Xilinx D asynchronousHow must this circuit be modified in order to insert two inputs
Reset (Z=0) and Preset (Z=1)?
Notice that if both true and inverted values of the output an inverter should be added. BUT in this case the two outputs
wouldn’t be synchronous
!ZY1=Z
60
Post-route simulation(the behavioural doesn’t work: why?)
D Flip-Flop
DFF
D
CK
QD
CK
Q
FFD: An asynchronous sequential network whose output Q copies the logical value of D input during the rising edges (positive edge triggered) of input CK
The FFD is typically used as memory elementary cell in the synchronous sequential networks (see later). In that case CK signal normally (but not necessarilty) has a periodical waveform (clock).
CK
D
Q
61
No change without ck
Correct use of DFF
Setup (tSU), Hold (tH) and Answer (tR) times
DFF
D
CK
QD
CK
Q
CK
D
Q
tHtSU
tR
The behaviour is correct only if tSU≥ tSUmin and tH ≥ tHmin, otherwise metastability.
62
63
Metastability
CK
D
tHtSU
Q1
Q2
Q3
Unpredictable and non-repetitive behaviour
64
D type FF 7474
As is the case with all FFs it is required that both true and inverted outputs are available at the same time. To this end in pratice the DFF is synthesized with a redundant coding using three state variables (R,S e Q) with the following schematic
CP=CK
65
Edge Triggered DFF with SET and PRESET
!Asynchronous Set
!Asynchronous Reset
Obviously both !S and !R must not be 0 concurrently (what happens in this case ?)
66
67
68
69
70
71
C
Analysis … three state variables S R QIf SR=0 (!S+!R=1) Q and !Q are complementary
Her e!S is indicated as S and !R as RAsybchronous Set and missing
Only stable states
C D00 01 11 10
---000
--- ---001
---010
011
---
---
111 011 011
--- ---
--- ---
110
111
110
111 011 100
100
101
110
111
--- ---
100 100
110 110 011 100
-- -- -- ----
S R Q
The first two columns with C=0 lead potentially to a possible Q transition (C=0)The last two columns with C=1 do NOT lead potentially to a possible Q transition (C=1)
Not reachebale or instable
X
First level FFs are NOT SR (the outputs are not complementary)
NB: Here X is not equal to !R
(S=0 R=1 D=0 -> X=1)
If S=0 (=> R=1) e C=1 Q=1 and D has no impact (row 011 right comlumns-> S is stable independently from X). If C=0 the future state is 111 (S=R=1) and Q does not change
S=R=0 and Q any value is unstable (S=0 => R=1 )
S= 0 R=1 and Q=0 is impossible (S=0 implies Q=1)
S= 1 R=0 e Q=1 is impossble (R=0 implies Q=0)
If C=0 ->S=R=1 and then Q stable (in green)
111
C=0 C=1
Q switch
Row 111. With C=0 S=R=1 and Q is stable If C becomes 1 with D=1 X=0 and then R remains 1 and only S changes which becomes 0 (therefore Q=1). If D=0 X=1 and with C=1 R becomes 0 (while S remains 1) and therefore !Q=1 and Q=0. Similar behaviour for row 110
72
C D00 01 11 10
---000
--- ---001
---010
A 011
---
---
111 011 011
--- ---
--- ---
110
111
110
111 011 100
B 100
101
D 110
C 111
--- ---
100 100
110 110 011 100
-- -- -- ----
--111
S R Q
A 011 C,1 A,1 A,1
D,0
C,1
D,0
C,1 A,1 B,0
B 100
D 110
C 111
B,0 B,0
D,0 D,0 A,1 B,0
--C,1
C D00 01 11 10
“De-synthesizing” …
A 00 10,1 00,1 00,1
11,0
10,1
11,0
10,1 00,1 01,-
B 01
D 11
C 10
01,0 01,0
11,0 11,0 00,- 01,0
--10,1
C D00 01 11 10
Y2Y1
Critical races!
A 00 10,1 00,1 00,1
11,0
10,1
11,0
10,1 00,1 11,-
B 01
D 11
C 10
01,0 01,0
11,0 11,0 10,- 01,0
--10,1
C D00 01 11 10
Y2Y1
Multiple transitions
Le frecce indicano le transizioni di Q
73
Y1 = !Cy1 + !y2y1 + C!Dy2
A 00 10,1 00,1 00,1
11,0
10,1
11,0
10,1 00,1 11,-
B 01
D 11
C 10
01,0 01,0
11,0 11,0 10,- 01,0
--10,1
C D00 01 11 10
y2y1
Y2 = !C + !Dy2!y1 + Dy2y1
Z = !y1
Synthesis…
But y2 is not the complement of y1: it is not a FF in strict sense
74
C D00 01 11 10
---000
--- ---001
---010
011
---
---
111 011 011
--- ---
--- ---
110
111
110
111 011 100
100
101
110
111
--- ---
100 100
110 110 011 100
-- -- -- ----
--111
S R Q
Re-syntehesizing…
C
Races removal
Races
C D00 01 11 10
---000
--- ---001
---010
011
---
---
111 011 011
--- ---
--- ---
110
111
110
111 011 101
100
101
110
111
--- 011
100 100
110 110 010 100
-- -- -- 100--
--111
S R Q
Non minimal synthesis
S = !C + !DS + S!R = !C + S(!R + !D)= !C +S !(RD) =!(C !(S !(RD)))
Unused!
R = !C + !S + RD = !(C S !(RD))Q = !S + RQ = !(S !(RQ))
S = !C + !DS + S!R = !C + S(!R + !D)= !C +S !(RD) =!(C !(S !(RD)))R = !C + !S + RD = !(C S !(RD))Q = !S + RQ = !(S !(RQ))
757474 – Schematic 2
76
Post route
Forbidden configurationInputs !S=!R=0
A D variation between to clock rising edges has no impact on
the output
CD Latch
CD
C
D
Q
Q*
C
D
Q
Q*
C D
0 0
0 1
1 0
1 1
Q Q*
Q Q*
Q Q*
0 1
1 0
SR
S
R
Q
Q*
C
D
Q
Q*
tSU ≥ tSUmin
tH≥ tHmin
Constraints:
Response time tR = tSU+ tH
C
D
QtSU tH
77How would you implement a Latch from a state table or a DFF with a two inputs MUX ?
78
CD Latch
11
B,1
01
11
01
00
10
10
E,0
00
C,0
10
D,1
00 11 1011
00
10
00F,1
01
01
A,0
DC
[ACE] [BDF] a b
B
C
D
E
F
A B C D E
---
---
---
---
---
---
C
00 01 11 10
A B ---
C
A
--- A B DB
C
D
C --- EE
F
0
1
0
1
0
1
D
C A E
DF A
F DA ---
B
---
---
a
00 01 11 10
a b a
C
a
b a b bb
0
1
D
0
00 01 11 10
0 1 0
C
0
1 0 1 11
0
1
D
y
Y= CD + !CyWith SR ?
79
DFF
D
CK
QD
CK
QMux O
1
0
S
CD Latch
80
373
D0
D1
D2
D3
D4
D5
D6
D7
00
O1
O2
O3
O4
O5
O6
O7
CK OE*
74XX373
CK
Di
QiOE*
Oi Z
C Qi
D
CK
Di
OE*
Oi
Latch CD
8 bit Latch register3-state outputs
81
374
D0
D1
D2
D3
D4
D5
D6
D7
00
O1
O2
O3
O4
O5
O6
O7
CK OE*
74XX374
CK
Di
QiOE*
Oi Z
Qi
D
CK
Di
OE*
Oi
Flip-Flop D
8 bit Edge-Triggered register3-state outputs
82
83
8484
Exercise
The control of a sliding gate is based on an asynchronous sequential machine with three input signals (S,T,P) and two output signals (A,C)• S=1 is a key indicating whether the gate is fully open or fully closed• T is a telecontrol: T=1 orders to the machine to keep the gate open (if it is already)
or to open it• P is a photocell with detects obstacles on the gate: P=1 orders to the machine to
keep the gate open (if it is already) or to open it• T=P=0 condition triggers the closure of the gate• A=1 and C=0 opens the gate• A=0 and C=1 closes the gate• A=0 and C=0 keeps the gate stopped either fully closed or fully open
Bclosed
1,1,01,0
COpening
tlc
0,1,01,0
IObstacle
Open
0,0,11,0
GOpen
1,0,00,1
E Open
tlcobstacle
1,1,10,0
1,1,10,0
L open
tlconstacle
0,1,11,0
FOpen
obstacle
1,0,10,0
DOpen
tlc
1,1,00,0
S gate open or closed sensorT Telecontrol open gateP Obstacle detected
A=C=0 keeps open or closed A=1 open C=1 cclosesOnce the telecontrol is activated the gate reaches a full open state and then immediately closes again with no telecontrol and no obstacle (which on the contrary trigger the reopening or keep the gate open)0,1,0
1,0Telecontrol
0,0,01,0No
telecontrolH
closure
0,0,00,1
0,1,01,0
Telecomando
1,1,00,0Telecontrol
1,1,10,0Ostacle
Telecontrol
1,1,00,0
No obstacle telecontrol
1,0,00,1
Notelecomando
1,1,00,0
Telecontrolreactivated
1,0,10,0
Obstacle only
0,0,00,1
Closure
1,0,00,1
No obstacle
1,1,10,0
Obstacle telecontrol
0,0,11,0
Obstacle
0,0,00,1 No telecontrol
no obstacle !
1,0,10,0
Obstacle
0,1,11,0
Obstacletelecontrol
0,0,11,0
Obstacle
MOpening
0,0,01,0
1,0,00,1
Motion end
1,0,00,0
End position
Aclosed
1,0,0A,C0,0
S,T,P
Closed gateNo motion
Telecontrol0,1,01,0
0,1,01,0
Telecontrol
0,0,11,0Stato I
obstacle
1,1,01,0
Telecontrolactivation
Nclosed
1,0,01,0
1,0,01,0
Telecontroldeactivated
0,0,01,0
1,1,01,0
Telecontrolreactivated
Gate closed
Gate open1,0,10,0 Obstacle
Obstacletelecontrol
0,1,11,0
A and B => gate closed – obstacle not possible: A => sensor S inactive not possible
D => gate fully open => telecontrol active attivo D => sensor S inactive not possible
B => telecontrol active – gate about to open to the end
E => gate open with obstacle and telecontrol active. If telecontrol released gate stopped because of obstacle and the same if ostacle removed
C => gate opening with telecontrol until S active. If the telecontrol is released the gate opens anyway to the end
F => gate open and obstacle => telecontrol inactive. Gate starts closing if obstacle removed
G => gate open -=> closure if telecontrol inactive and no obstacle
H => gate closing - reopening if telecontrol or obstacle
I => obstacle =>. If obstacle removed closure
L => gate opening with telecontrol active and obstacle
M => gate opening with telecontrol inactive. When fully open if no telecontrol and no obstacle closure
N => gate still closed.(obstacle impossible) but telecontrol activated and released. Gate opens to the end
A
B
C
D
E
F
ST
P
G
-,-
000 001 011 010
-,- -,- -,-
-,- -,- -,- C,10
M,10 -,- L,10 C,10
-,- -,- -,- -,-
-,- -,- -,- -,-
-,- -,- -,-
H,01 -,- -,- -,-
H,01 I,10 -,-H
A,00
100 101 111 110
-,- -,- B,10
N,10 -,- -,- B,10
-,- -,- -,- D,00
G,01 -,- E,00 D,00
-,- F,00 E,00 D,00
G,01F,00 E,00
G,01 F,00 -,- D,00
A,00 -,- -,-
-,-
-,-
-,-
C,10
I
L
M
H,01 I,10 L,10
-,- I,10 L,10 C,10
M,10 -,-
-,- F,00 -,-
-,- -,- E,00 -,-
G,01 -,- -,-
-,-
-,-
-,-
C,10
sensore S disattivo sensore S attivo
I,10
M,10 -,- N,10 -,- -,- B,10-,- -,-N
GFEDCBA
H
G
F
E
D
C
B
I
L
M
LIH
--
--
-
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Non maximal compatibility classes closed and covered[AHIL] [CDEFM] [BN] [G]
a b g d
N --
M
A
B
C
D
E
F
ST
P
G
-,-
000 001 011 010
-,- -,- -,-
-,- -,- -,- C,10
M,10 -,- L,10 C,10
-,- -,- -,- -,-
-,- -,- -,- -,-
-,- -,- -,-
H,01 -,- -,- -,-
H,01 I,10 -,-H
A,00
100 101 111 110
-,- -,- B,10
N,10 -,- -,- B,10
-,- -,- -,- D,00
G,01 -,- E,00 D,00
-,- F,00 E,00 D,00
G,01F,00 E,00
G,01 F,00 -,- D,00
A,00 -,- -,-
-,-
-,-
-,-
C,10
I
L
M
H,01 I,10 L,10
-,- I,10 L,10 C,10
M,10 -,-
-,- F,00 -,-
-,- -,- E,00 -,-
G,01 -,- -,-
-,-
-,-
-,-
C,10
sensore S disattivo sensore S attivo
I,10
M,10 -,- N,10 -,- -,- B,10-,- -,-N
--
[AHIL] [CDEFM] [BN] [G] a b g d 00 01 11 10A
B
C
D
E
F
ST
P
G
-,-
000 001 011 010
-,- -,- -,-
-,- -,- -,- C,10
M,10 -,- L,10 C,10
-,- -,- -,- -,-
-,- -,- -,- -,-
-,- -,- -,-
H,01 -,- -,- -,-
H,01 I,10 -,-H
A,00
100 101 111 110
-,- -,- B,10
N,10 -,- -,- B,10
-,- -,- -,- D,00
G,01 -,- E,00 D,00
-,- F,00 E,00 D,00
G,01F,00 E,00
G,01 F,00 -,- D,00
A,00 -,- -,-
-,-
-,-
-,-
C,10
I
L
M
H,01 I,10 L,10
-,- I,10 L,10 C,10
M,10 -,-
-,- F,00 -,-
-,- -,- E,00 -,-
G,01 -,- -,-
-,-
-,-
-,-
C,10
sensore S disattivo sensore S attivo
I,10
M,10 -,- N,10 -,- -,- B,10-,- -,-N
00 01 11 10
00
01
11
10
Y1 Y0
T P
00,01 00,10
01,10 00,10
00,10 01,10
00,10 01,10
01,10
00,01 -,-
-,-
-,- -,-
00 01 11 10
00
01
11
10
00,00 01,00
01,01 01,00
01,00 11,10
01,00 01,00
11,10 -,-
10,01 01,00
-,- 11,00
-,- 01,00
S=0
S=1
Y1 Y0
T P
-,- -,-
Critical races: add states
00 01 11 10
00
01
11
10
Y1 Y0
T P
00,01 00,10
01,10 00,10
00,10 01,10
00,10 01,10
00,01 -,- -,- -,-
00 01 11 10
00
01
11
10
00,00 01,00
01,01 01,00
01,00 11,10
01,00 01,00
11,10 -,-
10,01 01,00
-,- 11,00
-,- 01,00
S=0
S=1
Y1 Y0
T P
Race requiring multiple transitions
01,10 -,--,- -,-