atmel’s at94k series field programmable system level

AT94 Training 2001Slide 1 Embedded Systems Lecture 1/19/08

AtmelAtmel’’s AT94K Seriess AT94K SeriesField Programmable System Level Field Programmable System Level

Integrated Circuit (FPSLIC)Integrated Circuit (FPSLIC)

Embedded Systems BasedEmbedded Systems BasedBuiltBuilt--In SelfIn Self--Test and DiagnosisTest and Diagnosis

of the FPGA Coreof the FPGA Core


FPGAGlue Logic

MemorySRAM

CPUAnalogue

PowerManagement

Clock

ASSPLogic

NVM

System-On-Chip Issues• $250K+ NRE

•CES note: these are old numbers – much higher now

• $100K+ design tools •CES note: these are old numbers – much higher now

• Large volume requirements

• Custom product

• Long design time

• High risk

• IP issues (availability, costimplementation)

>> System level integration not viable for most customers


Field Programmable System Level Integrated Circuit Field Programmable System Level Integrated Circuit reducing power consumptionreducing power consumption

MCU MEM

ASIC/FPGA

Most of power usedin I/O pads

Discrete Solution Monolithic Solution

MEM

MCU FPGA

Power is reduced by more than 50%• Standby <100uA• Active 2-3mA/MHz


AT40KxxAL

Low $

AT40KxxAL

Low $

2000 2001 2002 2003

Feat

ures

AT40KxxAV

Low $

AT40KxxAV

Low $

3.3V 0.35u

ASIC FPSLICTM with Embedded AT40K FPGA coreASIC FPSLICTM with Embedded AT40K FPGA core

AT40K with RISC uCAVRTM FPSLICTM

AT40K with RISC uCAVRTM FPSLICTM

AT40KxxAX

Low $

AT40KxxAX

Low $1.8V 0.12u

AT40K with ARMARM FPSLICTM

AT40K with ARMARM FPSLICTM

Atmel Programmable SLi Roadmap

1.8V 0.18u


User-Defined Logic Spectrum

ATF22V10ATF16V8ATF20V8

ATV2500BATF1500 FamATV750B

AT6000AT40K

ATL25 SeriesATL35 Series ATL50 SeriesATL60 Series

Decoders,Glue Logic

State machines,Timing, Control

RAM/Logic,Computing,Co-processing System Level Integration

Den

sity

Macrocells0.25, 0.35, 0.5, 0.6�Analog / Digital

Analog / Digital/NV Memory, RF

Total CustomizationVery High Volume

PAL-Type

CPLD

FPGA

GateArray

Custom ASIC

FPSLIC

AT94K

Cell based ASIC

High Volume/Low CostProgrammableSLI with AVR


Atmel’s Flash MCU FamiliesPrice vs Performance

AVR

ARM-7Laser Printer

$1 $2 $5 $10 $20

Keyless Entry

Appliances

Auto Elect.

Cellphones

Settop Boxes

Internet

Disk Drives

Engine Control

C51

Performance

Price


Configurable SRAM

8 Bit RISC MCUAT40K FPGA

Monolithic SRAM Based FPSLICMonolithic SRAM Based FPSLIC

20 MIPS* 20 MIPS* -- 8bit RISC MCU8bit RISC MCU120+ instructions120+ instructions

Up to 36K bytes of SRAMUp to 36K bytes of SRAM

From 5K to 40K gates FPGAFrom 5K to 40K gates FPGA*30 MIPS version available Q4 2001


Designer Defined Program and Data SRAM Allocation

10K10K** Words Words Instruction (x 16)Instruction (x 16)

20Kbytes20KbytesProgramProgramMemoryMemory Fixe

d 4K B

yte

for Data

RAM

• Memory partition is user defined during development• Easy to trade-off Program and Data SRAM* 2K Words (x16) for µFPSLIC (AT94K05)

2K x

82K

x 8

2K x

82K

x 8

2Kx 8

2K x

8Designer Allocated Memory

in 4Kbyte chunks


Data SRAM (DPRAM)4K byte up to 16Kbyte

AVR-Add

[15:0]

Avr-Data

[7:0]

AVR-R/W

AVR-Clk

8 Bit RISC MCU

FPGA-A

dd[15

:0]

FPGA-R/W

FPGA-Clk

FPGA-Data

[7:0]

AT40K FPGA

Internal Data SRAM Access

True Dual Port AccessTrue Dual Port AccessAVR can disable writing from FPGA AVR can disable writing from FPGA


Configurable SRAM

SRAM interface

AVR/AT40

K inter

face

FPSLIC Embedded Blocks

• Software configurable interface between blocks already implemented• Pre-implemented Interface blocks save 2000-5000 FPGA gates

AT40K FPGA8 Bit RISC MCU


8 Bit RISC MCU

I/O select[15:0]R/W

Data[7:0]

Int[15:0]

AT40K FPGA

02Data[7:0]

W

Internal I/O space and Interrupts

I/Oselect[0]

Write:ldi r16,0x00 ldi r17,0x02out FISCR,r16 ; I/O select 0out FISUA,r17 ; r17 data on the bus


AVRAVR--FPSLIC FamilyFPSLIC Family

• 5K, 10K and 40K gate AT40K FPGA options• AVR microcontroller

– 120+ instructions

DDeevviiccee AArrrraayy SSiizzee

44--LLUUTTss FFFFss

FFPPGGAA GGaatteess

FFrreeeeRRAAMMss

SSRRAAMM bbiittss FFPPGGAA

II//OO PPrrooggrraamm MMeemmoorryy

DDaattaa SSRRAAMM

AATT9944KK0055 1166xx1166 225566 55KK 1166 RRAAMMss 22004488 bbiittss

9966 mmaaxx

44KK––1166KK BByytteess// 44KK--1166KK BByytteess

AATT9944KK1100 2244xx2244 557766 1100KK 3366 RRAAMMss 44009966 bbiittss

119922 mmaaxx


AATT9944KK4400 4488xx4488 22,,330044 4400KK 114444 RRAAMMss 1188443322 bbiittss

338844 mmaaxx



• AVR– Harvard

architecture– 32 8-bit regs– ALU

w/multiplier– 120+

instructions


RSA

3 DES

Software

Applicati

on

Data/K

eys

8 Bit RISC MCU

X[7:0]Y[7:0]

Z[7:0]D[7:0]write

32 bits

X

Y

Z

RSA3 D

ESFPSLIC - Partial Reconfiguration using AVR

CacheLogicTM

• Hardware implemented for the AVR to control partial reconfiguration• Enable Hardware context switching


Cache Logic ModeCache Logic Mode• Mode designed for CacheLogic applications

– Device treated as an SRAM by the system– Microprocessor treats FPGA as memory mapped I/O.– Simple 24 bit Address and 8 bit Data structure.

31 0

32 Bit word defines address and data Information for one byte per clock cycle

X Address Y Address Z AddressTag Data

8 Bits 8 Bits 4 Bits 4 Bits 8 Bits

MSB LSB


BYTE 1

BYTE 0

BYTE 2BYTE...

BYTE n

BYTE 1

BYTE 0

BYTE 2BYTE...

BYTE nZ Z

Cell 0,0 Cell 1,0

BYTE 1

BYTE 0

BYTE 2BYTE...

BYTE n

BYTE 1

BYTE 0

BYTE 2BYTE...

BYTE n

Z Z

Cell 1,1Cell 0,1

Core Cells (PLBs)

Vertical RepeatersHorizontal Repeaters

North/South I/O

And so on ........

Cell X Location

Cel

l Y

Loca

tion

• Tag Defines Page being written• X,Y Define Array Location• Z defines which byte at a given X,Y Location is written

4 Dimensional Memory Map

TAG Addressed PAGES

AT40K Logical Memory Map

atmel’s at94k series field programmable system level

Documents