auto-adaptive reconfigurable architecture for scalable multimedia applications
DESCRIPTION
Auto-adaptive reconfigurable architecture for scalable multimedia applications. PhD student : Xun zhang Director of project : Professor Serge WEBER Co-director of project : Hassan RABAH. Université Nancy Laboratoire d’Instrumentation d’Electronique de Nancy (LIEN). Outline. - PowerPoint PPT PresentationTRANSCRIPT
Auto-adaptive reconfigurable architecture for scalable multimedia applications
PhD student: Xun zhangDirector of project :Professor Serge WEBERCo-director of project : Hassan RABAH
1
Université NancyLaboratoire d’Instrumentation d’Electronique de Nancy (LIEN)
Outline
• Introduction▫ The need of auto-adaptation▫ Platform et auto-adaptation▫ Solution reconfigurable hardware
• Implementation challenge • Exploration of auto-adaptive reconfigurable
architecture ▫ Multi-level adaptation ▫ Multi-level reconfigurable Architecture
• Test & analyze▫ Motivation of experiment ▫ Application described ▫ Result analyse
• Summary and outlook
2
Introduction3
The need of auto-adaptation ?
Auto-adaptation is not only a solution to adapt the change of applicationthe change of application , but also a solution to make the system optimize itself to adapt the best performance optimize itself to adapt the best performance in run-time, when a reconfiguration event is being happen.
auto-adaptation in multimedia application ?
•Auto-adaptation on the choose of different filter different filter in the different frequency domain (DCT, DWT)
•Auto-adaptation on the choose of the scale of algorithme kernels(DCT, DWT,FIR,etc) different size of resource ( size of image, level of decomposition or reconstruction) different energy mode to adapt the energy computation
-- Auto-adaptation et Plateforme
4
•GPPs can execute any software, but performance can be slow
•ASICs can execute only one application, but quickly
•Reconfigurable computing seeks to bridge this gap
•Reconfiguration allows same hardware to execute multiple applications
•Executing application in hardware leads to higher performance than in software
MicroprocessorsASICs
Highest flexibility
Performance?
High flexibility
High performance
Highest performance
Lowest flexibility
ReconfigurationComputing
Introduction
Hardware Solution
ASIC 1 ASIC 2 ASIC 3
Input 1 Input 2Input 1 Input 2Input 1 Input 2
Software Solution
ALU
Banc de registres
µP
output
REGREGREGREG
Instructions resources memories
Input 1 Input 2
flexible Solution Solution performante
--reconfigurable hardware Solution
5
Physic Reconfigurable architecture
Configurable elements of computations and memories
Configurable network of connexions
architecture 1
configuration 1
application 1
configuration
Architecture 2
configuration 2
application 2
reconfiguration
Introduction
Implementation Challenge --FPGA Perform Processing Both in Space and Time--FPGA Perform Processing Both in Space and Time
Increasing of reconfiguration frequency
Increasing of the size of reconfigurable module
Requirement of client
Complexity of application •Effective Organization solution for those reconfiguration resource on chip!!•Auto-adaption the status of platform in real-time for optimization of the reconfiguration process
Space --Memory size/Gate Number/Silicon area Refers to Physical Implementation of different
functionality in vast hardware resources (parallel processing)
Time --the reconfiguration Latency FPGA be reconfigured at various steps of the
application algorithm to instantiate different architectures at different run times(dynamic)
• Exploration of auto-adaptive reconfigurable architecture
• Multi-level adaptation • Multi-level reconfigurable Architecture
7
Two-levels adaptation8
sub tasks
common processing tasks
• Application adaptation --the switching between
different applications The process of configuration from
one application to another , which is happen to one or group of application task .
• task adaptation --the switching different
versions of a task of an application
View of architecture
Specific processing tasks
Multi-levels reconfiguration structure
• Global reconfiguration level
9
• Local reconfiguration level
It is possible to remove or replace totally one RPM and the communication between elements on chip in order to meet a particular need.
the modification is happened into RPM, one part of RPM is reconfigured for adapting the Configuration need.
processor
memory IP
IP_1
RC1 C3
C2C1
IP_2
RC2
•Reusable and fixed component (Ips)(Reconfigurable Processing module –
RPM)•Reconfigurable interconnection •Partial reconfiguration
Auto-adaptive reconfigurable architecture
•Multi-Reconfigurable Pressing Module (RPM)Register file Reconfigurable Data pathOn chip memoryRPM interface
•Reconfigurable Interface Inter-RPMIntra-RPM
•Reconfiguration manager answer the reconfiguration request from exernal Identify reconfiguration level active the reconfiguration process
10
Exploration flow
Reconfiguration event activation
architecturale Organisation
Architecture chosin g
Estimation of architecture
F6F5
F4F3
F2
F1
Spécification DAG desfonctions de l’application
ESTIMATION of application
Modélisée(DBRC)
n°1
Configuration flow
11
Event Library
Configuration
resource library
On-line Status of platform
Which modules are necessary?
When?
ID of those modules
Configuration resource
12
• Test and analyses
▫ objectives of experiment ▫ Application described ▫ Result analyse
RGB2YCbCr
DWT
Quantize
EBCOT
Application described 13
t1
t2
t4
t5
t3
Wavelet filter(5,3)
Event library
Configuration Event Definition
JPEG2000
14
Discrete Wavelet Transform(DWT)
Exemple of two levels copression and reconstruction DWT
1. Define two different DWT filter mode
2. Perform 2 level DWT decomposition on FPGA
3. Change the chosen DWT filter in run-time through partial reconfiguration
Experiment step:
Application described
•Discrete Wavelet Tranform (DWT)
15
(5,3)
(9,7)’
Communication’
Filter(5,3) Filter(9,7)
communication
Configuration resource library
Implementation phase
With an unique ID
Event libraryEvent library
update
16
• Experiment : Xilinx Virtex4 Partial reconfiguration platform
More than one partial reconfiguration module (RPM) within a CLB colum
Configuration frame is 16CLBs High
distributed LUT RAM scan be placed above or below a partial reconfiguration module
ICAP (100 MHz)
Target Technique
Implementation result
Experimental results17
Place in tool PlanAhead View in FPGA Editor
The reconfiguration time
Ticap = L/rL: the length of the partial reconfiguration file
r: the transfer rate with configuration clock frequency
Experimental results(Continue)
Tconfig = TICAP + TBRAM
filter(5,3): part2+part3filter(9,7): Part1+part3+part4
Discussion
•Summary• Definition of auto-adaptation from the view of architecture • Based-cluster models consist hierarchic reconfiguration modules • Multi-levels adaptation represents practically the complex application
system • Experimental result to represent the implementation of this architecture
19
Thanks for your attention
20
Nancy University http://www.uhp-nancy.fr Laboratoire d’Instrumentation Electronique de Nany (LIEN) http://www.lien.uhp-nancy.fr
•Any question