scalable and reconfigurable digital front-end for sdr wideband

Computer EngineeringMekelweg 4,

2628 CD DelftThe Netherlands

http://ce.et.tudelft.nl/

2006

MSc THESIS

Scalable and Reconfigurable Digital Front-End forSDR Wideband Channelizer

Gil Savir

Abstract

Faculty of Electrical Engineering, Mathematics and Computer Science

CE-MS-2006-16

In recent years, RF receiver designers concentrated on replacing ana-log components with digital ones, striving towards the ideal SoftwareDefined Radio (SDR) where all signal processing is done in software.

Such an ideal SDR platform may form an exceptionally flexible and re-programmable receiver that can cope with many different standards,e.g., IS-95, GSM, UMTS, and especially the various military standards.A wideband receiver has to simultaneously deal with hundreds to fewthousands channels, which lay in the same spectrum interval. One of themost computation intensive tasks in such receiver is channelization [1]. Awideband channelizer decomposes its RF input signal into separate out-puts, each containing the signal of single channel. In the past, practicallimitations such as state-of-the-art digitizers’ speed and computing ca-pacity prevented the realization of a wideband SDR receiver. At present,these implications can be overcome using digital front-end architectures,comprising reconfigurable and scalable components (e.g., FPGA, FFT-processors) allowing flexible and efficient implementation. The goalof the presented research is to study, design, and implement a flexibleand reconfigurable wideband channelizer architecture that can be imple-mented on state-of-the-art FPGAs. In this dissertation, we present ourwork where we first choose a suitable algorithm for wideband channel-ization. The chosen algorithm employs an analysis DFT filterbank [2]that requires fewer hardware resources compared to other channeliza-tion algorithms. Subsequently, we simulate this algorithm for a broadrange of practical parameters in order to determine hardware design re-quirements and performance trade-offs. Using the parameters survey, atest-case is devised and implemented on FPGA using our implementationarchitecture. Subsequently, the implementation results are compared tothe simulation results in order to validate the parameter ranges survey.

Scalable and Reconfigurable DigitalFront-End for SDR Wideband Channelizer

MSc THESIS

submitted in partial fulfillment of therequirements for the degree of

MASTER OF SCIENCE

in

COMPUTER ENGINEERING

by

Gil Savirborn in Afula, Israel

Computer EngineeringDepartment of Electrical EngineeringFaculty of Electrical Engineering, Mathematics and Computer ScienceDelft University of Technology

Scalable and Reconfigurable DigitalFront-End for SDR Wideband Channelizer

by Gil Savir

Abstract

In recent years, RF receiver designers concentrated on replacing analog components with digi-tal ones, striving towards the ideal Software Defined Radio (SDR) where all signal processingis done in software. Such an ideal SDR platform may form an exceptionally flexible and re-

programmable receiver that can cope with many different standards, e.g., IS-95, GSM, UMTS,and especially the various military standards. A wideband receiver has to simultaneously dealwith hundreds to few thousands channels, which lay in the same spectrum interval. One of themost computation intensive tasks in such receiver is channelization [1]. A wideband channelizerdecomposes its RF input signal into separate outputs, each containing the signal of single chan-nel. In the past, practical limitations such as state-of-the-art digitizers’ speed and computingcapacity prevented the realization of a wideband SDR receiver. At present, these implicationscan be overcome using digital front-end architectures, comprising reconfigurable and scalablecomponents (e.g., FPGA, FFT-processors) allowing flexible and efficient implementation. Thegoal of the presented research is to study, design, and implement a flexible and reconfigurablewideband channelizer architecture that can be implemented on state-of-the-art FPGAs. In thisdissertation, we present our work where we first choose a suitable algorithm for widebandchannelization. The chosen algorithm employs an analysis DFT filterbank [2] that requiresfewer hardware resources compared to other channelization algorithms. Subsequently, we sim-ulate this algorithm for a broad range of practical parameters in order to determine hardwaredesign requirements and performance trade-offs. Using the parameters survey, a test-case isdevised and implemented on FPGA using our implementation architecture. Subsequently, theimplementation results are compared to the simulation results in order to validate the parameterranges survey.

Laboratory : Computer EngineeringCodenumber : CE-MS-2006-16

Committee Members :

Advisor: Stephan Wong

Advisor: Laurens Bierens

Chairperson: Stamatis Vassiliadis

Member: Alle-Jan van der Veen

Member: Sorin Cotofana

i

To my mother and in memory of my father

iii

Contents

List of Figures vii

List of Tables ix

Acknowledgements xi

1 Introduction 11.1 Background & Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Research Question & Goals . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.5 Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Software Defined Radio 52.1 The SDR Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Channelization Algorithms Study 93.1 Channelization Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1.1 The per-channel Approach . . . . . . . . . . . . . . . . . . . . . . 103.1.2 Pipelined Frequency Transform . . . . . . . . . . . . . . . . . . . . 103.1.3 Polyphase FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2 Algorithms Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.2.1 Hardware Complexity Comparison . . . . . . . . . . . . . . . . . 153.2.2 Qualitative Comparison . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4 Channelizer Architecture 214.1 Modules Decomposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.2 IQ Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2.1 Conventional IQ demodulator . . . . . . . . . . . . . . . . . . . . 224.2.2 Wideband IQ Demodulator . . . . . . . . . . . . . . . . . . . . . . 224.2.3 Hilbert Transformed IQ Demodulator . . . . . . . . . . . . . . . . 234.2.4 Chosen Implementation Algorithm . . . . . . . . . . . . . . . . . 23

4.3 Filterbank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.3.1 Equiripple Prototype Filter . . . . . . . . . . . . . . . . . . . . . . 244.3.2 1/f Ripple Prototype Filter . . . . . . . . . . . . . . . . . . . . . . . 25

4.4 FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.5 Post-Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

v

5 Parameter Ranges Survey 275.1 Simulation setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1.1 IQ demodulator Filter Design Parameters . . . . . . . . . . . . . . 275.1.2 Prototype Filter Design Parameters . . . . . . . . . . . . . . . . . 28

5.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315.2.1 IQ Demodulator Filter Design Simulation Results . . . . . . . . . 315.2.2 Prototype Filter Design Simulation Results . . . . . . . . . . . . . 33

5.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6 Validation 376.1 Filterbank Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.1.1 Test-Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376.1.2 Filterbank Implementation Approach . . . . . . . . . . . . . . . . 386.1.3 Filterbank Architecture . . . . . . . . . . . . . . . . . . . . . . . . 38

6.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406.2.1 Functional Verification . . . . . . . . . . . . . . . . . . . . . . . . . 406.2.2 Test-Case Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416.2.3 General Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416.2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7 Conclusions & Recommendations 457.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457.2 Main Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477.3 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Bibliography 51

vi

List of Figures

1.1 4-channels channelizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 Typical superheterodyne radio receiver . . . . . . . . . . . . . . . . . . . 52.2 Ideal SDR receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.3 Feasible SDR receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1 Single channel digital front-end channelizer . . . . . . . . . . . . . . . . . 93.2 Per-channel channelizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.3 DDC-SRC tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.4 DDC-SRC tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.5 Modifications to the kth single channel channelizer . . . . . . . . . . . . . 123.6 l branches in the filterbank decomposition of the kth single channelizer . 133.7 Applying the noble identity in the kth filterbank . . . . . . . . . . . . . . 143.8 Discarding M-1 filterbanks . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.9 Polyphase FFT channelizer . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.10 Comparison of LUT utilization . . . . . . . . . . . . . . . . . . . . . . . . 163.11 Comparison of memory bits employment . . . . . . . . . . . . . . . . . . 16

4.1 Channelizer architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.2 IQ-demodulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224.3 HBF/CHBF Impulse and frequency response . . . . . . . . . . . . . . . . 234.4 Hilbert transformed HBF Impulse and frequency response . . . . . . . . 244.5 Hilbert transformed IQ demodulators . . . . . . . . . . . . . . . . . . . . 244.6 Equiripple vs. 1/f ripple prototype filters . . . . . . . . . . . . . . . . . . 254.7 1/f ripple prototype filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.1 rPB as function of rSB in HBF . . . . . . . . . . . . . . . . . . . . . . . . . . 295.2 Prototype filter design parameters choice for 2 and 4 channels . . . . . . 295.3 Number of channels vs. taps . . . . . . . . . . . . . . . . . . . . . . . . . . 315.4 Stopband Attenuation vs. number of taps . . . . . . . . . . . . . . . . . . 325.5 Passband width vs. number of taps . . . . . . . . . . . . . . . . . . . . . . 325.6 Quantization limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335.7 Taps per channel vs. stopband attenuation; various passband ripple values 345.8 Taps/channel per 10dB vs. passband ripple . . . . . . . . . . . . . . . . . 345.9 Quantization limit for 3dB passband ripple . . . . . . . . . . . . . . . . . 355.10 Minimal coefficients word-length vs. stopband attenuation performance

for different number of channels . . . . . . . . . . . . . . . . . . . . . . . 35

6.1 Filterbank implementation architecture for 4 channels with 5 taps perchannel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.2 HW testbench configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 406.3 SNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

vii

List of Tables

3.1 Qualitative Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1 Test-case parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386.2 HW-cost and performance for various feasible implementation schemes 43

ix

Acknowledgements

I would like to thank Laurens Bierens for his guidance during this research and toEONIC BV for supporting this project. I would also like to thank EONIC’s employeesthat always had time for helping me when necessary.A special thank that cannot be said or written in words to family Koedood, that becamemy family in The Netherlands and to my mother, who made me what I am.

Gil SavirDelft, The NetherlandsSeptember 25, 2006

xi

Introduction 1Advances in technology in the recent decades led to a gradual migration of RF

systems from the analog to the digital domain. It gave birth to the concept ofsoftware defined radio (SDR) - a radio platform that digitally processes RF signals on asoftware-driven platform (i.e., digital signal processor, general purpose processor, etc.)and thereby provides flexible reconfigurable transceiver architecture that may cope withmultiple standards and air-interfaces, dynamically adapting to its radio environment[3]. However, hitherto, SDR implementations do not take full advantage of the SDRconcept due to current limited performance of software-driven platforms. In order toalleviate this problem some computationally intensive tasks are performed on a digitallyreconfigurable platform, such as FPGAs. Late progress in reconfigurable technologymakes SDR implementations closer than ever to reach the full potential of the SDRconcept.

1.1 Background & Scope

SDR has a broad range of applications, both in civil and in military environments. Thisstudy, however, is focused on military electronic warfare (EW) applications such aselectronic intelligence (ELINT), signal intelligence (SIGINT), and especially communi-cations intelligence (COMINT) equipment. Many wireless (and wired) communicationmethods are based on frequency division multiplexing (FDM) encoding. In this methodall communication channels of certain application are spread in a frequency band, whichis allocated for this purpose by the local communication authority. The channels areallocated in equally, non-overlapping frequency spaces. In oder to intercept and processsuch communication, the RF signal has to be channelized first.

Channelization (in this context) is the process of separating a mixture of communi-cation channels into distinct signals, each of single channel. Figure 1.1 illustrates thefunctionality of a 4-channels channelizer. It has a single input that contains 4 commu-nication channels in one signal, and it has 4 distinct outputs, each providing a singlechannel filtered from the rest and down-converted to baseband frequency (DC), readyfor further processing.

In COMINT applications, a channelization of wide frequency band needs to be per-formed in real-time for the aim of signal interception. Channelization, however, mayalso be useful in civil environment (e.g., cellular base-stations and satellite communica-tion). The scope of this work is a study, design, and implementation of digital front-end

1

2 CHAPTER 1. INTRODUCTION

��

Figure 1.1: 4-channels channelizer

for SDR receiver, containing a wideband1 channelizer.

1.2 Related Work

In this section we present a brief account of several works on related channelizationalgorithms, which are suitable for digital front-end channelizer. Most of this relatedwork is further explained in details in Chapter 3.

In the past two decades, several digital channelization algorithms were introduced.Some of them, such as the per-channel approach [4], emerged from existing analogmethods already in use. This algorithm employs a stack of single-channel channelizers,where each one is a digital realization of the traditional manner for realizing analog-based single-channel channelizer. However, rapid improvements in silicon density andsoftware-driven platforms enabled efficient and economical implementation of digitally-based channelization algorithms. Such algorithm is the hierarchical multistage method(HMM), in which the input signal is consequently channelized to two channels in abinary-tree form [5]. Another is the frequency domain filtering (FDF) channelization,which performs, as its name suggests, filtering of the required channels in the frequencydomain, after the input signal is passed in FFT [6]. An improvement of the HMM isthe pipelined frequency transform (PFT) channelization algorithm that takes advantageof sample-rate differences among distinct stages in the binary-tree [7]. Another twoclosely related algorithms are the polyphase FFT filterbank channelizer [2] and theweight overlap-add (WOLA) [8]. These are based on enhancement of the per-channelapproach, which employs sample-rate conversion properties.

1.3 Research Question & Goals

Various studies of the channelization algorithms mentioned in the former section existand several refinements and application-specific approaches were published (e.g, [9–11]). However, these publications usually have a narrow scope and are meant for

1The term wide-band means ”of relatively big spectrum interval”. This term, however, depends uponapplication and is current-technology related. In order to be more specific we state here that we aimtowards channelizers of few hundreds to few thousands of channels.

1.4. METHODOLOGY 3

a particular field or specific implementation (e.g., a base-station for certain cellularcommunication standard), where normally channelization of only few tens to coupleof hundreds channels is required. There are, however, applications where variousconfigurations of channelization may be necessary. A few hundreds to few thousandsof channels could be required with various ranges of channel parameters. This work,therefore, will be concentrated in answering the following question:

• How to design a generic, scalable, and reconfigurable digital front-end architecturefor software defined radio wideband channelizer, which should form the basis ofa next-generation SDR platform?

In order to answer this question we form the following goals:

• Choose digital algorithm which is most appropriate for wideband channelizationin a reconfigurable environment.

• Determine the relationships and trade-offs between the various channelizer para-meters.

• Establish implementation architecture for the chosen algorithm.

• Demonstrate architecture feasibility on currently-available FPGAs for applicableparameters.

1.4 Methodology

This section describes the methodology chosen with the purpose of answering theresearch question and achieving the goals presented in Section 1.3. This work comprisesthe following three phases:

1. Examination of channelization algorithms: in this phase background literaturestudy is conveyed, and several prominent channelization algorithms are studied.This phase is concluded with a comparison between the surveyed algorithms, bywhich one is chosen for further investigation.

2. Parameter ranges survey: in this phase the chosen channelization algorithm isstudied in further details and modeled in software in order to indicate its scalabilityand reconfigurability, and with the aim of identifying critical items.

3. Test-case implementation in this phase a probable test-case is worked out based onthe parameter ranges survey, and critical items are implemented so as to validateconclusions.

1.5 Thesis Overview

The reminder of this paper is structured as follows:

4 CHAPTER 1. INTRODUCTION

• Chapter 2 introduces the SDR concept as a background for this work, highlightingadvantages and drawbacks of this concept.

• Chapter 3 describes three channelization algorithms, namely the per-channel al-gorithm, the pipelined frequency transform, and the polyphase FFT filterbankalgorithm. Thereafter, it presents a HW- cost and qualitative comparison. Basedon this comparison, the polyphase FFT filterbank algorithm is chosen for furtherinvestigation.

• Chapter 4 discusses in further details the architecture of the polyphase FFT filter-bank channelizer, focusing on the IQ-demodulator and the filterbank.

• Chapter 5 presents parameter ranges survey of the IQ-demodulator and the filter-bank modules, while introducing graphs that provide insight to design trade-offsof these two modules.

• Chapter 6 introduces our implementation architecture for the filterbank andpresents the results obtained from its implementation. This is done in orderto validate the results obtained in the parameter ranges survey.

• Chapter 7 presents the conclusions of this dissertation, its main contributions, andrecommendations for possible future continuation work.

Software Defined Radio 2The necessity for software defined radio (SDR) emerged from military applications

where communication between several different forces (i.e., air-force, ground force,navy, etc.) had to be facilitated while preventing interception by enemy forces. DARPA’sSPEAKeasy [12] and JTRS [13] projects are examples for development of SDR, wheremultiple air-interfaces with different signal processing techniques were integrated intoone platform. However, the necessity for SDR also exists in civil applications. Typicalexample is a cellular phone that is capable of operating within the different existingstandards (UMTS, GSM, DCS-1800, IS-95, JDC, and many more).

2.1 The SDR Concept

Figure 2.1 illustrates the structure of a typical superheterodyne radio receiver. In suchreceiver, the signal passes through many analog components (e.g., amplifiers, filters,and mixers) that have non-ideal performance and are subject to influence such as tem-perature differences and humidity. Therefore, the signal accumulates many distortionsalong its processing path.

LPF

AMP

RF stage

BPF LNA

LO

BPF AMP

VCO

LPF

AMP

~ 90°°°°

Digital Signal

Processing

IF stage BB stage

DAC

ADC

ADC

Figure 2.1: Typical superheterodyne radio receiver

An ideal SDR receiver should be capable of receiving (and transmitting) ultra-widebandwidth of RF signals (hundreds of Mhz to few GHz), interpreting many given air-interface radio standard using software. In order to do so, the ADC should be ”shifted”as close as possible to the receiver’s antenna as illustrated in Figure 2.2. Compared tothe traditional superheterodyne receiver in Figure 2.1, the ideal SDR receiver containsminimal quantity of analog components. Earlier conversion of the RF signal to digitalnot only allows more flexibility in signal processing but also provides higher signalfidelity as analogue components do not perform ideally and might significantly altertheir behavior due to external influence (i.e., temperature, humidity, etc.). Other ad-

5

6 CHAPTER 2. SOFTWARE DEFINED RADIO

vantages of digital components are small footprint, low power consumption, and fastdevelopment (time to market).

BB stage RF stage

BPF LNA

Digital Signal

Processing ADC

Figure 2.2: Ideal SDR receiver

However, some key issues still prevent a realization of an ideal SDR receiver. An-tenna that ideally receives and transmits wide band of frequency is not realizable withcurrently-available technology. Suppose the antenna problem is overcome, anotherproblem stems from the ADC bottleneck [14]. State of the art ADCs reach about 3Giga-samples per second (GSPS), and also this with a relatively low 8-bit resolution(e.g., National Semiconductor’s ADC08D1500). According to the Nyquist-Shannonsampling theorem, a periodic signal should be sampled in rate, which is at least twiceits frequency in order to be able to reconstruct it. A 2 GSPS ADC could therefore sam-ple periodic signals up to 1 GHz of frequency. Other fundamental limitations of ADCdue to its non-ideal nature are low resolution (quantization error), non-linear behavior,deviation from accurate sample timing intervals (jitter error) and noise, which limit itsperformance [4]. The third inherent problem in the ideal SDR results from the limitof nowadays computation power. Assuming that a perfect ADC exists, the amount ofdigital information (samples) to be processed by the digital signal processing unit(s)surpasses the computation capacity of presently available computing platforms andmight require Giga-FLOPS performance [15].

BPF LNA

LO

BPF AMP

Digital Signal

Processing

RF stage IF stage BB stage

Digital

Front End

ADC

Figure 2.3: Feasible SDR receiver

The limitations discussed above lead to the conclusion that a compromise should bedevised in order to facilitate the implementation of SDR receiver. Figure 2.3 depictspossible architecture for a feasible SDR receiver. Limiting the bandwidth (BW) of thereceiver makes it possible to devise a suitable antenna and to alleviate ADC sampling

2.2. CONCLUSION 7

rate limitation and computation load. Therefore, IF stage is introduced in order to dealwith ADC bandwidth limitations. Furthermore, a digital front-end stage is appendedin front of the digital signal-processing platform can take over computationally inten-sive tasks from the software-driven platform. These tasks may include sample rateconversion, channelization, filtering, and other tasks derived from the receiver’s targetapplication. The digital front-end is likely to be implemented in firmware (FPGAs) andflexible ASIC digitizers, which provide a trade-off between performance and flexibility.

Channelization can be realized in the digital front-end. However, it is not independentof the analog front-end. The properties of components in the analog front-end (e.g., ADCand LNA) should be taken into account when designing the digital front-end. Also,further processing in the digital processing platform should be taken into consideration.Some properties of the digital front-end can be imposed trough requirements from thedigital processing platform, such as channels spacing, sample rate conversion, etc.

2.2 Conclusion

In this chapter we introduced the SDR concept. We presented the ideal SDR receiverand showed its advantages above typical radio receivers, which are implementationflexibility and reconfigurability, improved accuracy, better robustness towards exter-nal environment influence, small footprint, low power consumption, and fast time-to-market. Subsequently, we explained the reasons for ideal SDR receiver unattainability.Consequently, we introduced a feasible SDR receiver with analog and digital front-ends, where the digital front-end takes over computationally intensive tasks that are toodemanding for the software-driven platform. Wideband channelization is such task,whereas studying, designing, and implementing it in a digital front-end for SDR is thefocus of this work.

8 CHAPTER 2. SOFTWARE DEFINED RADIO

Channelization AlgorithmsStudy 3Channelization is a process where single, few, or all channels from a certain fre-

quency band are separated for further processing. The separation of single channelis usually done by down-conversion followed by filtering and optional sample-rate con-version. Figure 3.1 illustrates a digital front-end containing a single-channel DDC basedon IQ Demodulation [16], followed by a sample-rate converter (also called decimator).

LPF

Digital Signal

Processing ADC

LPF

cos 2ππππf0t

sin 2ππππf0t

DDC

I

Q

SRC

SRC

Digital Front-End

Analog

Front-End

Figure 3.1: Single channel digital front-end channelizer

The channels of interest may be of equal or different bandwidths and may be uni-formly or non-uniformly, continuously or non-continuously distributed over the inputfrequency band. In military applications of our interest, many channels from the in-put frequency band have to be separated - usually all available channels. It is alsomostly common in such applications that the channels of interest are uniformly andcontinuously distributed over the input frequency band.

In the reminder of this chapter we introduce relevant SDR channelization algorithms.Thereafter, we compare the introduced algorithm in order to choose the one mostrelevant for the requirements of this project. Afterwards, conclude this chapter with anexplained choice of algorithm.

3.1 Channelization Algorithms

This section presents 3 channelization algorithms. Namely, The per-channel approach,The pipelined frequency transform, and the polyphase FFT algorithms.

9

10 CHAPTER 3. CHANNELIZATION ALGORITHMS STUDY

3.1.1 The per-channel Approach

A straightforward implementation, which is also the traditional implementation ofwideband channelizer, is to simply use a single-channel channelizer for each channelof interest, and connect them all to the input frequency band signal [9]. Figure 3.2illustrates such algorithm.

Digital Signal

Processing

ADC

SRC

Digital Front-End

Analog

Front-End

DDC

SRC DDC

SRC DDC

Ch 1

Ch 2

Ch K

Figure 3.2: Per-channel channelizer

This approach provides a great deal of flexibility in the choice of channels to beseparated. Each single-channel channelizer can be individually designed for BW andfrequency choice. Furthermore, the separated channels are not constrained to be ofthe same bandwidth or to be uniformly distributed over the frequency input band.However, once such channelizer is designed, it is very rigid for alteration. Adaptingthis channelizer algorithm to different air-interface might require replacement of someor all single-channel channelizers. When a change has to be done only in part of theinput frequency band, only the corresponding single-channel channelizers have to bealtered or replaced. Another weakness of this algorithm is that for wideband receivers,where many channels are to be separated, silicon costs and power consumption areextremely higher than in other, more advanced wideband channelization techniquesintroduced in the following sections [10, 17, 18] .

3.1.2 Pipelined Frequency Transform

The Pipelined Frequency Transform (PFT) algorithm [7] is based on a binary tree ofDDCs and SRCs (Figure 3.3) where units of DDC followed by SRC are used for dividingtheir input band into two half-bands with half sampling rate. This algorithm createsa binary tree that splits the input frequency in two half-bands and then splits eachhalf-band again into two half sub-bands and so on, until the last tree level produces therequired separated channels. The resulting structure is also called HMM (HierarchicalMultistage Method) [19] or QMF tree [20].

This algorithm for itself has no advantage over the algorithm presented in the previoussection and is actually much more expensive in terms of silicon use, since apart of a

3.1. CHANNELIZATION ALGORITHMS 11

DDC-SRC DDC-SRC

ADC

DDC-SRC DDC-SRC

DDC-SRC DDC-SRC

DDC-SRC DDC-SRC

DDC-SRC DDC-SRC

DDC-SRC DDC-SRC

Digital Signal

Processing Analog Front-End

SRC DDC

SRC DDC

fs

fs/4

fs/2

fs/8

DDC-SRC DDC-SRC

Figure 3.3: DDC-SRC tree

single-channel channelizer for each channel of interest (as in the per-channel algorithm)in the last stage of the tree, many more are needed in the other stages. Nevertheless, eachsingle-channel channelizer complexity can be reduced dramatically, taking advantageof half band filters symmetry and restricting the output sample rate to be quarter ofinput sample rate in each single node in the tree.

Observing that the components in each stage perform in half of the sampling rateof its former stage components, a considerable optimization can be performed. Theactual amount of operations-per-time performed in each level of the tree is equal whiledistributed over twice components than in its former tree level. Instead of using twocomponents for each component in the former tree level at half sampling rate, onecomponent that performs in the same sampling rate can be used in combination withinterleaver, which distributes the samples accordingly. This is done using complex (IQ)DDC and DUC as illustrated in Figure 3.4 (The DDCs and DUCs that are not in the 1stlevel are of a special interleaved version). The channels however are output serially, andtherefore some extra processing is required for distributing them in distinct outputs.

DDC

DUC

Interleaver

I

I

Q

Q

Q

I DDC

DUC

Interleaver

I

I

Q

Q

Q

I DDC

DUC

Interleaver

I

I

Q

Q

Q

I

fs 2fs 2fs 2fs I

Q

Figure 3.4: DDC-SRC tree

The PFT algorithm seems to be much more economical in terms of silicon use andpower consumption when compared to per-channel channelizers algorithm. Especiallywhen many channels are to be separated from the frequency input band [7]. However,it demonstrates less flexibility, as the separated channels must be of equal bandwidth


and uniformly distributed. The Tunable PFT algorithm is an adaptation of the PFTthat alleviates this inflexibility by introducing interleavers that provide intermediateoutputs from the PFT stages that may be used for fine tuning channelization [21]. Thisimprovement, however, leads to increasing HW costs and is not applicable for widebandchannelizers.

3.1.3 Polyphase FFT

This channelization algorithm is an improvement of FFT channelization using apolyphase filterbank in combination with FFT, taking advantage of the equivalencetheorem and noble identities [22] while posing acceptable restriction over the samplingrate.

LPF SRC

H(Z)

exp(-j �

k n)

M:1

x[n] yk(nM) yk(n)

(a)

BPF SRC

Hk(Z e -j � k)

exp(-j �

k n)

M:1

x[n] yk[nM] yk(n)

(b)

BPF SRC

exp(-j M �

k n)

M:1 Hk(Z e -j � k)

x[n]2f

yk[nM]

(c)

BPF SRC

M:1 Hk(Z e -j 2ππππ/M k)

x[n] yk[nM]

(d)

Figure 3.5: Modifications to the kth single channel channelizer

We consider the kth single (complex) channelizer from the per-channel channelizerin Figure 3.2 (shown in Figure 3.5(a)) and apply series of modifications to it [2]. Theexpression of the LPF output in Figure 3.5(a) is a multiplication of the input samplesx[n] with the complex heterodyne and a convolution with the filter coefficients h(n), andis given in Equation 3.1.

yk(n) = [x(n)e− jθkn] ∗ h(n)

=

N−1∑

r=1

x(n − r)e− jθk(n−r)h(r) (3.1)

Swapping between the complex multiplier and the prototype LPF alters the LPF to aBPF in accordance with the equivalency theorem [23] (Figure 3.5(b)). The correspondingmodification to Equation 3.1 is shown in Equation 3.2.

yk(n) =

N−1∑

r=1

x(n − r)e− jθk(n−r)h(r)

3.1. CHANNELIZATION ALGORITHMS 13

=

N−1∑

r=1

x(n − r)e− jnθkh(r)e jrθk

= e− jnθk

N−1∑

r=1

x(n − r)h(r)e jrθk (3.2)

Observing that only every Mth result of the complex multiplier in Figure 3.5(b) is keptafter of the SRC, we interchange these two elements while adapting the phase of thecomplex multiplier (multiply with M) as shown in Figure 3.5(c). Constraining the centerfrequency for the kth channel to be an integer multiple of the output sample rate so thatθk = 2πk

M results in aliasing to baseband, since the complex multiplier term becomese− j2πn = 1 + 0 j. Consequently, the complex multiplier becomes superfluous and can beremoved, as shown in Figure 3.5(d).

SRC

M:1 x[n] yk[nm]

Z-2

H2(ZM)

Z-1

H1(ZM)

H0(ZM)

Z-l

Hl(ZM)

2

2⋅− k

Mj

eπ

1

2⋅− k

Mj

eπ

0

2⋅− k

Mj

eπ

)

2lk

Mj

e⋅−

π

Figure 3.6: l branches in the filterbank decomposition of the kth single channelizer

Noting that as before, every Mth output of the BPF in Figure 3.5(d) is not used due tothe SRC, it would be sensible to ”shift” the SRC to the left of the BPF. In order to do so,we have to invoke the noble identity [22]. For this purpose we first have to decomposethe BPF in the kth single channelizer into a filterbank of l (=M) sub-filters. The filterbankdecomposition is described in Equation 3.3.

H(Ze− j( 2πM )k) =

M−1∑

r=0

Z−rHr(Z)e j( 2πM )rk (3.3)

The resulted l sub-filters in the filter bank are composed of delay element, sub-filter,and (time invariant) scaling multiplier (Figure 3.6). Moving the SRC through the scalingmultipliers and the l sub-filters we invoke the noble identity. The resulted filterbank isdepicted in Figure 3.7. The corresponding output function is shown in Equation 3.4.

yk(nM) =

M−1∑

r=0

y(r)(nM)e j( 2πM )rk (3.4)


SRC

M:1

x[n] yk[nm]

Z-2

H2(Z)

Z-1

H1(Z)

H0(Z)

Z-l

Hl(Z)

2

2⋅− k

Mj

eπ

1

2⋅− k

Mj

eπ

0

2⋅− k

Mj

eπ

)

2lk

Mj

e⋅−

π

SRC

SRC

SRC

Figure 3.7: Applying the noble identity in the kth filterbank

where y(r)(nM) is the nMth sample from the rth sub-filter.

x[n]

Filterbank 0

lkM

je

⋅−π2

Filterbank 1

Filterbank 2

Filterbank M-1

y0[nM]

y1[nM]

y2[nM]

yM-1[nM]

M

DFT

lk

Mj

e⋅−

π2

lk

Mj

e⋅−

π2

lk

Mj

e⋅−

π2

Figure 3.8: Discarding M-1 filterbanks

The delay elements, the SRCs and the sub-filters are similar for all the k filterbanksand therefore only one should be physically implemented as illustrated in Figure 3.8.Observing in Equation 3.4 that the multipliers and adders (Dashed-line rectangle inFigure 3.8) practically function as M-points DFT, they can be replaced with FFT forreducing complexity. The final result illustrated in Figure 3.9 (note that the delayelements are replaced by a chain of one unit delay elements) is known as the polyphaseFFT (PFFT) filterbank channelizer algorithm.

In comparison with the per-channel channelization algorithm formerly introduced,the PFFT algorithm is much more rigid to changes, and is subject to restrictions imposedover the sampling rate, the number of channels to be extracted, and the number oftaps in the prototype filter. however, it seems to show extremely lower silicon costs.

3.2. ALGORITHMS COMPARISON 15

SRC

M:1

x[n]

Z-1

H2(Z)

Z-1

H1(Z)

H0(Z)

Z-1

Hl(Z)

SRC

SRC

SRC

M points FFT

y0[nM]

y1[nM]

y2[nM]

yM-1[nM]

Figure 3.9: Polyphase FFT channelizer

Measured in terms of number of arithmetic operations per number of separated channels(computational complexity) [9, 24, 25], it seems that the PFFT outperforms the per-channel algorithm when separating more than 3 channels.

3.2 Algorithms Comparison

In the previous section, several channelization algorithm for wideband channelizerwere introduced. In this section, we present HW-complexity (cost) comparison and aqualitative comparison of these channelization algorithms with the aim to chose the onemost suitable for Eonic’s target applications.

3.2.1 Hardware Complexity Comparison

The following HW complexity comparison is based on data from [17], which is put herein plots. The first comparison is for LUT (Xilinx FPGAs basic block) utilization. Theright plot in Figure 3.10 show us that the per-channel algorithm (stacked) utilizes farmore LUTs than the PFT (binary) and PFFT algorithms and that its tendency is muchsteeper. The left plot in Figure 3.10 gives us a clearer comparison between the other twoalgorithms. We can see that for all given number of channels PFT more than twice LUTresources than the PFFT algorithm does.

The second comparison is of memory bits utilization. The right plot in Figure 3.11shows us that the per-channel algorithm employs much more memory resources thanthe PFT and PFFT algorithms for all number of channels. However, comparing the PFTand PFFT algorithms (left plot in Figure 3.11) we can see that the PFFT algorithm issuperior only when channelizing more than 300 channels. Another important propertyis that the PFT curve’s inclination is much steeper than the PFT curve.


Logic use comparison

0

200

400

600

800

1000

1200

1400

1600

256 512 1024

Number of channels

LUT

'sx

1000

StackedPFFTBinary

Logic use comparison

0

5

10

15

20

25

30

35

40

256 512 1024

Number of channels

LUT

'sx

1000

Figure 3.10: Comparison of LUT utilization

Memory use comparison

0200400600800

100012001400160018002000

256 512 1024

Number of channels

RA

M (

bit

s x

1000

)

StackedPFFTBinary

Memory use comparison

0

2

4

6

8

10

12

256 512 1024

Number of channels

RA

M (

bit

s x

1000

)

Figure 3.11: Comparison of memory bits employment

3.2.2 Qualitative Comparison

Comparison of different algorithms is not simple. The parameters ranges for comparisonare wide. Limitation to practical parameters may alleviate this difficulty. Most of newlyproposed channelization techniques in literature are compared to the traditional per-channel channelizer. The comparisons here are divided to three groups: Computationalcomplexity, size (”silicon costs”), and group delay and flexibility.

Computational complexity

A common comparison parameter is computational complexity, which is usually de-rived from simulations and software implementations. Such a comparison projects onsilicon costs but usually do not take into account memory requirements and controlcomplexity. Previous works of [6, 24, 26] show that when 3 or more channels are tobe channelized, the PFFT algorithm outperforms the per-channel algorithm. The workof [26] shows that an improvement in the filters of the per-channel algorithm raises thislimit to lay between 4 and 20 channels for some scenarios.

3.2. ALGORITHMS COMPARISON 17

Silicon cost

Comparison that is based on actual implementation in FPGA gives a good idea aboutthe HW complexity of the different algorithms. A drawback of such comparison is thatit is not platform independent. Different FPGAs contain some dedicated multipliers andbuilt-in memory blocks. Each configuration of distinct algorithm may have trade-offsin FPGA resources that is difficult to measure and compare. Such is the comparison ismade between the PFT, PFFT, and per-channel algorithm implementations presentedin Subsection 3.2.1. Based on this comparison, it seems that in terms of memory use,the PFT memory requirement is growing rapidly with the number of channels to beseparated. The conclusion drawn in [17] is that up to 256 channels, the HW complexityof PFT and PFFT is comparable and that above 256 channels PFFT outperforms the PFT.

Group delay

Generally, group delay is not a major consideration in the choice of channelizationalgorithm. It is usually of concern when designing ELINT receivers that deal withanalysis of short radar pulses. The work of [25] shows that the group delays of PFT andPFFT algorithms in different configurations are quite similar. Normally, PFFT groupdelay is better than in PFT algorithm, but more rigid implementation of the PFT (givingup intermediate outputs) may reach a comparable or better group delay than in thePFFT algorithm. Comparing the PFFT and per-channel algorithm, it seems that the laterhas a small, advantage due to the FFT stage in the PFFT algorithm. This advantageorder, however, is insignificant for the target implementations aimed to in this study.

Flexibility

As this study is aimed toward the mapping of selected algorithm on reconfigurabledigitizers, analysis of two flexibility aspects in the different algorithms is essential. Thefollowing discussion offers analysis of initial design flexibility and reconfigurability.

Initial design In this aspect, the per-channel approach is clearly the winner. Allthe separated channels are independent, may have different bandwidths and may benon-uniformly and non-continually distributed over the input frequency band. ThePFT and PFFT algorithms suffer from similar limitations. Namely, producing channelswith equal bandwidth that are uniformly and continually distributed over the inputfrequency band. The PFT suffers from another restriction however. The number ofthe separated channels has to be an integer power of 2. The PFFT in principle is moreflexible in the choice for number of channels to be separated. Nevertheless, the mosteconomical implementations of FFT have integer power of 2 bins, and that may alsoimpose restriction on the implementation of PFFT filterbank. An advantage of the PFTover the PFFT is its possibility to produce intermediate outputs of channels with half ofthe resolution and twice the bandwidth of the channels in the next level of the PFT tree.The PFFT has a constraint on the number of taps in the prototype filter, which must bean integer multiply of the number of channels.


Reconfiguration This is a key concern in the evaluation of the different channelizationalgorithms. Addition or removal of single or few channels is very easy to implementon the per-channel algorithm, while in most cases, for the PFT and the PFFT algorithmsit means a complete reconfiguration of the whole implementation (especially whena change in an integer power of 2 number of channels is required). Adaptation ofthe filtering performance (channels separation quality) requires modification to thenumber of taps and the weight for each tap in the filter. In the PFFT algorithm thefiltering is implemented in a logically separated block, and therefore its adaptationneed not have consequences for the rest of the algorithm implementation. In the PFTand the per-channel algorithms, however, the filters are distributed within differentlogical blocks, so that adaptation in their performance may have consequences to therest of the implementation.

Table 1 summarizes the qualitative comparison between the different channelizationalgorithms. Careful examination of the different comparison aspects with respect to thefocus of this study (presented in the 1st chapter) shows that the per-channel approachwins in many aspects. Conversely, its implementation for high number of channelsis infeasible, and that makes the PFFT algorithm the most suitable for SDR widebandchannelizer front-end implementation of our interest. Nevertheless, the differencesbetween the PFFT and FFT implementations for medium number of channels (few tensto few hundreds) is not well documented, and investigation in this direction might besubject for further research.

Aspect AlgorithmPer-Channel PFT PFFT

Computational Complexity forhigh number of channels

Poor Good Excellent

Silicon Cost Efficiency up to 3-20 up to 128-256 8-16 channelschannels channels and above

Group Delay Good Good Good

Initial Design

Independent Yes No Nochannels

Number of Selectable 2INT Preferablychannels 2INT

Flexibility Intermediate No Yes Nooutputs

Flexibility for

Addition / Excellent Poor Poorremoval ofchannels

Reconfiguration Filtering Poor Poor Goodindependence

Table 3.1: Qualitative Comparison

3.3. CONCLUSION 19

3.3 Conclusion

In this chapter we introduced three different channelization algorithms. Namely, theper-channel, the PFT, and the PFFT algorithms, explaining in details . Consequently, wepresented HW comparison between these algorithms for LUT and memory resourcesutilization. Based on this comparison, the PFFT algorithm appears to be superiorly costefficient when channelizing few hundreds or more communication channels.

Afterwards, we presented a qualitative comparison between these three algorithmsthat comprises also group delay, initial design flexibility, and reconfigurability. Basedon the performed comparisons, we came to the conclusion that despite the fact that theper-channel algorithm has better score in many comparison aspects, its implementationis critically HW inefficient and is infeasible for high number of channels, even on todayslargest available FPGAs. Therefore, we chose the PFFT algorithm, which is highlycost efficient and has the best computational for high number of channels, for ourimplementation of the front-end wideband channelizer.

Channelizer Architecture 4The polyphase FFT channelization algorithm was chosen for our study and was

explained in details in Chapter 3. In this chapter we present the implementationarchitecture of this algorithm. We first introduce decomposition to modules of thechannelizer architecture. Thereafter, we explain in details some of these modules,focusing on implementation choices.

4.1 Modules Decomposition

The architecture of the digital front-end channelizer comprises the digital signal process-ing done from the ADC output to the moment where each channel is available as separateoutput for further processing by software. The ADC output is in real digital signal for-mat, in contrast to complex format, also known as IQ (In-phase Quadrature) signal,which provides easier signal processing. Therefore, preprocessing of the ADC outputis necessary in order to convert its real output into a complex signal. This is done in theIQ-demodulator unit, which is placed between the ADC and the filterbank module.

The following components in the channelizer architecture are the filterbank moduleand the FFT processor, as described in the former report. An optional post-processingunit may be appended to the FFT processor’s output. The necessity of this moduledepends on implementation choices that are described in Section 4.5. The separatechannels outputs are then available for further digital signal processing. The layout ofthe channelizer architecture is depicted in Figure 4.1.

Figure 4.1: Channelizer architecture

In the following subsections, each of the architecture modules is described, focusingon implementation issues.

21

22 CHAPTER 4. CHANNELIZER ARCHITECTURE

4.2 IQ Demodulator

The task of the IQ demodulator is to convert real signal to complex one. There are,however, different possible implementation algorithms. These are described in thefollowing subsections.

4.2.1 Conventional IQ demodulator

The conventional IQ demodulator is implemented by down-conversion of the inputsignal, which is done by multiplication of the signal with sine and cosine components intwo different I and Q paths. Subsequently, a low-pass filter is applied on each path. Thesignal can afterward be decimated by a convenient rate, as long as the Nyquist criterionis kept. This processing sequence is depicted in Figure 4.2(a).

(a) Conventional (b) Wideband

Figure 4.2: IQ-demodulators

4.2.2 Wideband IQ Demodulator

The conventional IQ demodulator architecture is general in its nature and is usuallyapplied when a single channel is demodulated. In the case of wideband IQ demodu-lation, a better implementation is possible. Since in a wideband channelizer the wholeinput spectrum from the ADC has to be IQ-demodulated, the sample rate for the down-conversion is quarter of the IF signal sampling rate fs as produced in the ADC. In thiscase, the numerically controlled oscillator (NCO) can be replaced with a subsequentmultiplication of the I-path samples by +1, 0, -1, 0, and of the Q-path samples by 0, -1, 0,+1 [27]. The low-pass filter (LPF) is consequently strictly half-band low-pass filter (HBF),and since the output spectrum is half of the input spectrum, the optimal decimation ratein the sample rate converter (SRC) is 2:1. Since the input to the filterbank module has tobe between DC and half of the current Nyquist sampling rate, The complex signal hasto be up-converted back by a quarter of the current (decimated) sampling rate using acomplex digital up-converter (DUC) that includes 4 unit multipliers (selective comple-menters), adder, and subtracter. The structure of wideband IQ demodulator is broughtin Figure 4.2(b).

Another possible improvement is due to the unique HBF filter taps, where, exceptof the middle tap that equals 0.5, each 2nd tap equals zero [8] as shown in Figure

4.2. IQ DEMODULATOR 23

4.3(a). This allows us to invoke the noble identity and ”shift” the 2:1 SRC through theHBF in the I and the Q paths and also through the unit multipliers. This results in acomplex half-band filter (CHBF) where the real coefficients are the HBF’s odd taps andthe imaginary coefficients are the HBF’s even taps. Examining an impulse response ofexample CHBF (Figure 4.3(b)) we can see that one path is all zero coefficients, except ofthe HBF’s center tap, which has the value 0.5 that can be implemented as wired shift.

0 5 10 15 20 25 30 35 40 45

−0.1

0

0.1

0.2

0.3

0.4

0.5

Impulse Response − 47 taps

Tap number (Normalized time) [nT/T]

Am

plitu

de

−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5−120

−100

−80

−60

−40

−20

0

20Frequency Response

Frequency (normalized) [fs/2]

Log−

Mag

nitu

de [d

B]

(a) HBF

0 5 10 15 20

−0.1

0

0.1

0.2

0.3

0.4

0.5

Real Impulse Response − 24 taps

Normalized time nT/T

Am

plitu

de

0 5 10 15 20−0.2

−0.1

0

0.1

0.2

0.3

0.4

Imag. Impulse Response − 24 taps

Normalized time nT/TA

mpl

itude

(b) CHBF

Figure 4.3: HBF/CHBF Impulse and frequency response

4.2.3 Hilbert Transformed IQ Demodulator

In principle, the frequency down-conversion before the HBF filters is necessary in orderto shift the positive frequency spectrum to the filter’s pass band region (and the negativespectrum to the stop-band region), and the complex DUC is needed to move the filteredsignal back into within DC and half the sampling rate. Applying Hilbert transform onthe HBF results in a special half-band filter that passes the positive frequency spectrumand attenuates the negative one, having exactly the same characteristics of the HBF [28]as shown in Figure 4.4(a).

Using the Hilbert transformed HBF we can (and should) remove the unit multipliersand the complex DUC. As result, The Hilbert transformed IQ-demodulator architectureis simpler, while producing the same results as the standard wideband IQ demodulator(see Figure 4.5(a). Since this filter also has in every 2nd tap zero weight (except of themiddle tap), the noble identity can be applied here as well, as described in Subsection4.2.2. The resulted Hilbert transformed HBF impulse response plot is given in Figure4.4(b) and its architecture is depicted in Figure 4.5(b).

4.2.4 Chosen Implementation Algorithm

As conclusion, The Hilbert transformed IQ-demodulator algorithm is our choice forimplementation, since it achieves the same results as the conventional IQ demodulator


0 5 10 15 20 25 30 35 40 45 50−0.4

−0.2

0

0.2

0.4Real Impulse Response − 47 taps


Am

plitu

de

0 5 10 15 20 25 30 35 40 45 50−0.6

−0.4

−0.2

0

0.2Imag. Impulse Response − 47 taps


Am

plitu

de

−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5−120

−100

−80

−60

−40

−20

0

Hilbert transformed HB LPF − mode 1

Frequency (normalized)

Log−

Mag

nitu

de (

dB)

(a) Before applying the noble identity

0 5 10 15 20−0.4

−0.3

−0.2

−0.1

0

0.1

0.2

0.3

0.4Real Impulse Response − 24 taps


Am

plitu

de

0 5 10 15 20−0.6

−0.5

−0.4

−0.3

−0.2

−0.1

0

Imag. Impulse Response − 24 taps


Am

plitu

de

(b) After applying the noble identity

Figure 4.4: Hilbert transformed HBF Impulse and frequency response

(a) Before applying the noble identity (b) After applying the noble identity

Figure 4.5: Hilbert transformed IQ demodulators

and the wideband IQ demodulator, while requiring less HW resources for its imple-mentation.

4.3 Filterbank

Decomposing the prototype filter to filterbank is a firm procedure with no much designchoices to be done (see Section 3.1.3). The design of the prototype filter itself, however,has more liberty. The following subsection describes some design choices in the processof constructing a prototype filter.

4.3.1 Equiripple Prototype Filter

Designing the prototype filter is done using Matlab™ with the signal processing tool-box. The chosen filter design method is the iterative Parks-McClellan algorithm, whichproduces optimal FIR filter by minimization of the maximal error between the desiredand the resulted frequency response [29]. The resulted filter is called equiripple since it

4.4. FFT 25

has equal ripples in the pass and in the stop bands. Figure 4.6(a) depicts an equiripplefilter frequency response.

4.3.2 1/f Ripple Prototype Filter

If the first m − 1 derivatives of an impulse response function S( f ) are continuous andthe mth derivative of S( f ) has one or more finite amplitude discontinuities, then thestopband ripple decays as 1

f k+1 per octave [23, 30]. The stopband ripple decay rate in

equiripple filter is 1f 0 = 1. That implies discontinuity in the zeroth derivative i.e., S( f )

itself. An enhancement of the Parks-McClellan algorithm, suggested by [23], removesthe discontinuity from S( f ) and results in 1/ f stopband ripple decay rate per octave,while causing a negligible consequences for the filter performance. This improves theprototype filter design in two senses. It reduces spectral aliasing between adjacentchannels and it is more resistant to performance degradation due to quantization of thefilter coefficients. Figure 4.6 presents a comparison of equiripple and 1/f ripple designsand the truncation result on each of the designs.

−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5−120

−100

−80

−60

−40

−20

0

2016−bit truncation


Log−

Mag

nitu

de [d

B]

−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5−120

−100

−80

−60

−40

−20

0

20Frequency response prototype filter − 8 channels


Log−

Mag

nitu

de [d

B]

−0.4 −0.3 −0.2 −0.1

−90

−80

−70

−0.4 −0.3 −0.2 −0.1

−90

−80

−70

(a) Equiripple

−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5−120

−100

−80

−60

−40

−20

0

20Frequency response prototype filter − 8 channels


Log−

Mag

nitu

de [d

B]

−0.5 −0.4 −0.3 −0.2 −0.1

−90

−80

−70

−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5−120

−100

−80

−60

−40

−20

0

2016−bit truncation


Log−

Mag

nitu

de [d

B]

−0.5 −0.4 −0.3 −0.2 −0.1

−90

−80

−70

(b) 1/f ripple

Figure 4.6: Equiripple vs. 1/f ripple prototype filters

The stop-band of the prototype filter becomes narrower as the number of channelsNχ becomes greater, the influence the of 1/f ripple decay also becomes better. Figure 4.7illustrates four filter-response plots of various prototype filters with different number ofchannels. Therefore, and due to the improvements of 1/f ripple filter above equiripple,the former is our choice for design method of the prototype filter.

4.4 FFT

This channelizer’s module has a customary FFT functionality. FFT implementation is awide field for itself. Since this module is to be implemented using Eonic’s PowerFFT™processor [31], this module is left out of the focus for this study.


−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5−140

−120

−100

−80

−60

−40

−20

0

20Frequency response − 16 channels


Log−

Mag

nitu

de [d

B]

−0.5 −0.4 −0.3 −0.2 −0.1 0−140

−120

−100

−80

(a) 16 chhannels

−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5−140

−120

−100

−80

−60

−40

−20

0



Log−

Mag

nitu

de [d

B]

−0.5 −0.4 −0.3 −0.2 −0.1 0−140

−120

−100

−80

(b) 64 chhannels

−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5−140

−120

−100

−80

−60

−40

−20

0



Log−

Mag

nitu

de [d

B]

−0.5 −0.4 −0.3 −0.2 −0.1 0−140

−120

−100

−80

(c) 256 chhannels

−0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5−140

−120

−100

−80

−60

−40

−20

0



Log−

Mag

nitu

de [d

B]

−0.5 −0.4 −0.3 −0.2 −0.1 0−140

−120

−100

−80

(d) 1024 chhannels

Figure 4.7: 1/f ripple prototype filters

4.5 Post-Processing

When a WOLA (weight, overlap add) [8] implementation of the filterbank is applied,phase correction of the output signals is needed. This survey, however, is focused onthe critically sampled polyphase filterbank, where phase correction is not necessary.Therefore, it is left out of the focus of this study.

4.6 Conclusion

In this chapter we presented and explained the decomposition of the polyphase FFTchannelizer algorithm into IQ-demodulator, filterbank, FFT, and post-processing mod-ules. We gave a explanation about three different implementation algorithms ofthe IQ-demodulator, namely, conventional, wideband, and Hilbert transformed IQ-demodulators. We concluded that the Hilbert transformed IQ-demodulator algorithmis best choice for implementation since it provides the same results as the other twoalgorithms while requiring less HW resources.

Afterwards, we introduced two filter design techniques for the prototype filter, fromwhich the filterbank is derived, i.e., the Parks-McClellan equiripple filter design and theParks-McClellan 1/f ripple design. Comparing these two techniques we decided thatthe second one is most advantageous for the implementation of the filterbank. Since theFFT is to be implemented using Eonic’s PowerFFT™ processor, the modules chosen forthe parameter ranges survey (in Chapter 5) are the IQ-demodulator and the filterbank.

Parameter Ranges Survey 5In the previous chapter, The implementation architecture of the polyphase FFT chan-

nelizer was introduced. In order to explore various design spaces and trade-offs inthis architecture, a Matlab™ model of the digital front-end was constructed. In thischapter, we present a parameter ranges survey of the channelizer. However, in order toconvey an effective study, focus has to be maintained onto practical parameter ranges.Therefore we first explain the choices of parameters and ranges to be explored. After-ward, we bring some important results of this survey, and we end with conclusionsbased on the attained results.

5.1 Simulation setup

The most intensive computation tasks in the front-end are done by the IQ-demodulator’sfilter, by the filterbank and by the FFT. Since the FFT is to be implemented using Eonic’sPowerFFT™ processor, this parameter ranges study is focused on the design choices ofthese two special filters.

5.1.1 IQ demodulator Filter Design Parameters

The independent input parameters for low-pass FIR filter design using the Parks-McClellan algorithm are: stop-band attenuation (rSB), pass-band ripple (rPB) ,stop-bandwidth (wSB), and pass-band width (wPB). The word-length used for the taps coefficientsalso has influence on filter design and may restrict its stop-band attenuation.

One restriction on the input parameters occurs when the filter is designed to bestrictly half-band filter. In this case the stop-band and pass-band widths are alwaysequal: wSB = wPB, so we only have to control one these two parameters. In this modelwe quantify wPB in percents, where 100% means exactly half of the filter’s input band,which lies between DC and fs/4.

Another restriction is possible due to the unique HBF taps. This behavior, where eachsecond tap is zeroed, is achieved only when the filter is designed to have equal passbanddeviation δPB and stopband deviation δSB [23].

δ = δPB = δSB (5.1)

Traditionally, the deviation parameters are described as ripple in dB units. The stop-band ripple is defined as the difference between the nominal passband gain GPB and

27

28 CHAPTER 5. PARAMETER RANGES SURVEY

the maximal stopband deviation in dB (Equation 5.2), whereas the passband ripple isdefined as the difference between the maximal and the minimal deviations from thepassband gain in dB (Equation 5.3) [32].

rSB = 20 log10 (GPB) − 20 log (δSB) (5.2)rPB = 20 log10 (GPB + δPB) − 20 log (GPB − δPB) (5.3)

Applying Equation 5.1 and GSB = 1 (since the HBF has unit gain) on Equations 5.2and 5.3 results in Equations 5.4 and 5.5 respectively.

rSB = 20 log10 (1) − 20 log (δ) (5.4)rPB = 20 log10 (1 + δ) − 20 log (1 − δ) (5.5)

Isolating δ from Equation 5.4 yields:

δ = −10( rSB

20

)

which, when applied to Equation 5.5, results in the relation represented by Equation 5.6.

rPB = 20 log10

10

( rSB20

)+ 1

10( rSB

20

)− 1

(5.6)

Figure 5.1 depicts the relation of Equation (5.6) for some practical values of rSB. Wecan observe that even for low values of the stop-band attenuation the pass-band rippleis below 0.02 dB. This value is appropriate for many comm applications [23] and is,by far, suitable for a speech receiver that may utilize overall pass-band ripple of upto 3dB [33], and which is the application of interest for this study. Therefore, we mayrestrict the study of the IQ-demodulator filter design to its stop-band attenuation and toits pass-band width without being bothered by the implication on the passband ripplein the case of the IQ demodulator filter.

As result of this discussion we set the controlled parameters in the simulation modelof the IQ-demodulator’s filter to be the passband width wPB, the passband ripple rPB,and the stopband attenuation rSB.

5.1.2 Prototype Filter Design Parameters

The Input parameters for the Parks-McClellan algorithm when designing low-passfilter are the (normalized) frequency at the end of the passband fPB, the (normalized)frequency at the beginning of the stopband fSB, the passband ripple rPB, and the stopbandattenuation rSB. Minimal Values for rPB and rSB are dictated by a corresponding standard.For example, one of the relevant targets for this study is defined by ETSI (EuropeanTelecommunications Standards Institute) 300 086 standard [33], which deals with speechFM receivers specifications for 25 kHz channel spacing. In this case, the maximal value

5.1. SIMULATION SETUP 29

60 70 80 90 100 110 1200

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018pass−band ripple as function of stop−band attenuation in HBF

stop−band attenuation [db]

pass

−ba

nd r

ippl

e [d

b]

Figure 5.1: rPB as function of rSB in HBF

for rPB is defined to be 3 dB and the minimal value for rSB is defined to be 70 dB. Thesevalues, however, are defined for the whole receiver and therefore provide only upperand lower bounds for the corresponding filter design parameters.

Figure 5.2: Prototype filter design parameters choice for 2 and 4 channels

The values for fPB and fSB depend on the number of channels Nχ and the occupiedbandwidth percentage of one channel in the channel spacing (Bocc). Occupied bandwidth is the portion of a channel that contains 99% of the average power of the signal.


Figure 5.2 illustrates this dependency for 2 (upper part) and 4 (lower part) channels1.The Cut Frequency ( fcut) marks the middle of the transition band where it holds:

fcut =1

Nχ(5.7)

The length of the transition band Btr is twice the unoccupied bandwidth of one channelso it holds:

Btr =2(1 − Bocc)

Nχ(5.8)

Since fPB = fcut − 12 Btr and fSB = fcut + 1

2 Btr, applying Equations 5.7 and 5.8 results in:

fPB = fcut − Btr

2

=1

Nχ− 1 − Bocc

Nχ

=Bocc

Nχ(5.9)

fSB = fcut +Btr

2

=1

Nχ+

1 − Bocc

Nχ

=2 − Bocc

Nχ(5.10)

The target applications of interest for this study has occupied bandwidth percentageof Bocc ≈ 0.64 [33, 34]. This parameter, however, is set for overall system performance.Therefore, and since military applications often require stringent parameters, Bocc is setto 0.80, in accordance with available military system specifications. Consequently, weconclude that the independent parameters for the prototype filter design simulationare the passband ripple rPB, stopband ripple rSB, the stopband attenuation rSB, and thenumber of channels Nχ.

Figure 5.3 depicts two example plots, which demonstrate that the number of necessarytaps is a linear function of the number of channels when rPB and rSB have fixed values.This implies that the number of taps per channel is constant. Therefore, it is easierto measure HW complexity of the prototype filter in taps per channel Ntaps/Nχ. It isimportant to mention that due to the symmetric nature of the designed prototype filtertaps, the number of filter coefficients to be computed is half of the actual necessary filtertaps.

1Note that one channel is halved between the lowest and highest frequencies. This special positionmight limit the possibility to channelize it. However, since the HBF of the IQ-demodulator cannot be ideal,this channel is not part of the usable output channels anyway.

5.2. SIMULATION RESULTS 31

Number of channels vs. taps - 0.1 db

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

20000

0 128 256 384 512 640 768 896 1024

Channels

tap

s

(a) 0.1 dB

Number of channels vs. taps - 1.0 db

0

2000

4000

6000

8000

10000

12000

14000

16000

18000

20000

0 128 256 384 512 640 768 896 1024Channels

tap

s

12011010090807060

Stopband attenuation

[db]

(b) 1.0 dB

Figure 5.3: Number of channels vs. taps

5.2 Simulation Results

In this section we present important parameters behavior as simulated in Matlab. Sincethe design space is infinitely large, the actual ranges considered in the simulation areconstrained to slightly below and above practical ranges. This is done from two reasons.First, in order to provide better insight of the system behavior, and second, in order toprovide outlook for future implementations when technology enables it.

5.2.1 IQ Demodulator Filter Design Simulation Results

The parameters tested in this part of the simulation are described in Subsection 5.1.1.We bring first simulation with floating point coefficients and afterwards the influenceof taps coefficients quantization on the performance of the IQ-demodulator filter.

5.2.1.1 Floating-point coefficients

Figure 5.4 depicts the number of necessary taps Ntaps as function of the stopband atten-uation rSB for different values of passband width wPB. It is clear from this chart thatthis function is linear. That implies that the necessary number of taps grows linearlyalongside the stopband attenuation. This chart can be used when estimating the costfor improving the stopband attenuation for existing IQ demodulator filter design.

Rearranging the data and plotting it as the number of necessary taps Ntaps as functionof the passband width wPB for different values of stopband attenuation yields the plotin Figure 5.5. This plot becomes useful when designing for restricted HW resources. Itis easy then to explore the trade-off between passband width (the percentage of usefulchannels from the total output channels) and between the stopband attenuation forcertain number of taps (along horizontal lines). Alternatively, the trade-off between thenumber of necessary taps and between the different stopband attenuation values fordifferent passband width values can be explored along the horizontal lines.


Figure 5.4: Stopband Attenuation vs. number of taps

Figure 5.5: Passband width vs. number of taps

5.2.1.2 Fixed-point coefficients

The results of the floating-point simulation are theoretical since the word-length of thetaps coefficients is not taken into consideration. In the following discussion we bringsimulation results of a model with quantized (fixed-point) taps coefficients.

Figure 5.6 contains 3 plots of the minimal coefficient word-length as function ofstop-band attenuation for various passband width values. Figure 5.6(a) illustrates theword-length necessary in order to achieve near floating-point attenuation performance.Figures 5.6(b) and 5.6(c) demonstrate the word-length necessary in order to achieveattenuation that is worse in 5dB and 10dB (respectively) than in the ideal case. Inaverage, quantizing the coefficients word-length in 3-bits will cost 5dB in attenuationperformance, while quantization of 4-bits will cost about 10dB in the IQ-demodulator’sfilter attenuation.


(a) +1dB (b) +5dB (c) +10dB

Figure 5.6: Quantization limits

The plots in Figure 5.6 are useful for the choices of word-length dependent HW suchas ADC (resolution) and FPGA (bus-width) for the implementation of the channelizer’sdigital front-end.

5.2.2 Prototype Filter Design Simulation Results

The parameters tested in this part of the simulation are described in Subsection 5.1.2.We first bring results of simulation with floating point coefficients. Subsequently wepresent the influence of taps quantization on the performance of the prototype filter.

5.2.2.1 Floating-point coefficients

Figure 5.7 depicts the number of necessary taps per channel Ntaps/Nχ as function ofstopband attenuation for various passband ripple values. The staircase-like plots areresult of rounding up the necessary number of taps to the closest multiplication of thenumber of channels. However, when testing for non-rounded values, it appears thatthis function is linear. That implies that design for better attenuation trades-off constantNtaps/Nχ per dB. The behavior of this trade-off is shown in Figure 5.8, which depictsthe average number of Ntaps/Nχ necessary for each 10 dB attenuation improvement asfunction of passband ripple. This plot displays exponential increase in the necessarytaps per channel for each 10 dB attenuation improvement as the passband ripple valuesapproach zero.

The plots in Figures 5.7 and 5.8 are useful for approximation of HW complexity andtrade-offs when choosing the rSP and rPB parameters for the implementation of thechannelizer filterbank.

5.2.2.2 Fixed-point coefficients

The results in the former subsection does not take into account the influence of quan-tization due to limited word-size used for the taps coefficients. Each plot in Figure


Taps per channel vs. attenuation

8

12

16

20

24

28

60 70 80 90 100 110 120

db

tap

s

0.1 db

0.5 db

1.0 db

1.5 db

3 db

passband ripple

Figure 5.7: Taps per channel vs. stopband attenuation; various passband ripple values

(Ntaps/ch) per 10 db vs passband ripple

1.4

1.5

1.6

1.7

1.8

1.9

0123456

rPB

(tap

s/ch

ann

el)

per

10

db

Figure 5.8: Taps/channel per 10dB vs. passband ripple

5.9 depicts the minimal necessary coefficients word-length as function of Nχ for dif-ferent stopband attenuation values. Figures 5.9(a) and 5.9(b) depict the minimal nec-essary bits in order to achieve stopband attenuation which is 10 dB respectively 20dB worse than in the ideal (floating-point coefficients) case. It is remarkable thatwhen Nχ grows, the number of necessary bits slightly decreases. This phenomenonis due to the 1/f ripple design as explained in Section 4.3.2. These two figures arebrought as example. The same behavior, however, is observed for different combina-tions of rPB values (0.1dB, 0.5dB, 1.0dB, 1.5dB, 3.0dB) with various attenuation resolutions(+1dB,+5dB,+10dB,+20dB).

Inspection of the simulation results shows that the influence of passband ripple on thenecessary coefficients word-length is negligible. Figure 5.10 contains 5 plots of minimalnecessary coefficients word-length vs. stopband attenuation performance with +5dBresolution2. Each plot depicts different passband ripple value. Visual comparison of thedifferent plots exhibits similarity among them. Indeed, the standard deviation betweenthe word-length values with same parameters (Nχ, rSB) corresponding to different valuesof rPB shows value not greater than 0.55 (except of one outlier at 0.71). The standard

2stopband attenuation resolution of x dB means up to x dB worse than ideal (floating-point coefficients)stopband attenuation


(a) +10dB (b) +20dB

Figure 5.9: Quantization limit for 3dB passband ripple

deviation average is 0.287, which means that the difference in passband ripple has anaverage influence on the coefficients word-length that is, in average, less than 0.29 bit.Therefore we conclude that the passband ripple influence on the minimal necessarycoefficients word-length is minor.

(a) rPB = 0.1dB (b) rPB = 0.5dB (c) rPB = 1.0dB

(d) rPB = 1.5dB (e) rPB = 3.0dB

Figure 5.10: Minimal coefficients word-length vs. stopband attenuation performancefor different number of channels

Further examination of the prototype filter design simulation results shows that thetrade-off between the minimal coefficients word-length and between the stopband at-tenuation is linear and independent of Nχ and rPB. Inspection of all slope valuesfor all combinations of rPB = 0.1, 0.5, 1.0, 3.0 with stopband attenuation resolutions+1dB,+5dB,+10dB,+20dB shows values between 1.67 and 1.83 with average of 1.73.The meaning of it is that the average trade-off is 1.73 bits per 10dB attenuation or 5.78dB per bit.


5.3 Conclusion

In this chapter we presented a parameter ranges survey for the IQ-demodulator andfor the filterbank. We first presented the simulation setup, giving a comprehensiveexplanation of parameters dependency for the IQ-demodulator and for the filterbankmodules. Subsequently, we gave the simulation results for both full floating-pointprecision and fixed-point implications.

The parameter ranges survey gave us some important results necessary for under-standing the behavior and design trade-offs of the IQ-demodulator and the filterbank.The attained plots provide a tool for the choice of HW resources and for the process ofrequirements elicitation.

Validation 6In Chapter 5, a parameter ranges survey was presented for the IQ-demodulator and

the filterbank modules. In this chapter, we first present the filterbank implementation.Since the IQ-demodulator is a common used module, we choose to concentrate on HWimplementation of the filterbank. Afterwards, we present the results obtained by theimplementation.

6.1 Filterbank Implementation

The filterbank implementation is done using VHDL, where all parameters are declaredgeneric and are concentrated in one parameters package. This, in order to providedesign that can be scaled-up (or down) and easily reconfigured for various differenttarget implementations.

6.1.1 Test-Case

Although the implementation is of generic nature, we use in some places in this study aspecific test-case parameters, which are yielded from one of the target implementationsdesired by Eonic. This is done in order to enlighten some practical consequences toa choice of realistic parameters. For this test-case the following parameters are cho-sen: Number of channels, passband ripple, stopband attenuation, occupied bandwidthpercentage, taps per channel, and word-length.

Passband ripple, stopband attenuation, and occupied bandwidth percentage are de-vised from communication standards such as [33], and are 70dB, 3dB, and 0.64 (respec-tively). However, these are overall system requirements. Therefore, and since militaryapplications often require stringent parameters, these are tighten to 90dB, 1dB, and 0.80(respectively) in accordance with available military system specifications. The rest ofthe choices are explained in the following paragraphs.

Number of channels: The number of channels is chosen to be 1k (1024). This is thehighest number of channels that single PowerFFT processor can handle in its maximalfrequency performance. In principle even more channels can be channelized in realtime, while performing appropriate modification to the input of the FFT processor.

Taps per channel: In order to choose this parameter we can use the plot in Figure 5.8.Since the desired passband ripple is 1dB, using this plot we can see that about 1.56

37

38 CHAPTER 6. VALIDATION

Taps/Channel per 10dB are necessary. Given that our desired stopband attenuation is90dB we need d9 × 1.56e = d14.04e = 15 taps per channel.

Wordlength: In order to decide the minimal word-length for the test-case we can usethe plots in Figure 5.10. Since the passband ripple is 1dB, the sub-plot in Figure 5.10(c)shows us that the maximal required word-length is 13-bit. However, since 16-bit is amuch more common word-length, we choose 16-bit for this test-case.

Parameter ValueNumber of channels 1024 chStopband ripple 1 dBPassband attenuation 90 dBOccupied bandwidth percentage 0.80Taps per channel 15 taps/chWord-length 16 bit

Table 6.1: Test-case parameters

Table 6.1 summarizes the parameters chosen for the test-case.

6.1.2 Filterbank Implementation Approach

Nowadays industry trend is to provide FPGAs with built-in units such as memoryblocks and fitted multipliers. Built in blocks typically perform faster than functionalunits designed using LEs while requiring less space and less power consumption1.Therefore we employ memory blocks and built-in multipliers in this implementation.Nevertheless, the implementation is made highly modular so as to facilitate implemen-tation on different FPGA brands. For this purpose, the interface of a built-in unit entitymay be left unaltered, while necessitating modification of the product-specific VHDLcode only. The tap-coefficients are generated using a Matlab™ script that accepts asinput the required channelizer parameters (i.e., number of channels, channels spacing,word-length, stopband attenuation, and passband ripple) and outputs the appropriatescaled coefficient files in format that is compatible with the VHDL compiler.

6.1.3 Filterbank Architecture

A naive implementation of the filterbank would be to consider each sub-filter as anindependent filter where each tap is implemented as a register and multiplier, and allthe multiplier outputs are summed in a multi-operand adder. This approach, however,will require thousands to couple of ten-thousands of multipliers. Trying to solve this byusing multiply accumulate units will still require a couple of thousands of multipliersand will perform too slow.

1In fact, implementation of the test-case, for example, using only LEs will even not fit on the largestavailable FPGA.

6.1. FILTERBANK IMPLEMENTATION 39

The approach chosen for implementing the filterbank addresses the problems in thetwo former described implementations. In this approach we do not regard each sub-filteras an independent filter. Considering that in an M channels filterbank, each sub-filteroperates in 1

M of the input sample-rate, we take advantage of this property and sharethe multipliers and the multi-operand adder of one sub-filter among all the sub-filtersin the filterbank.

��

��

��

��

��

��

��

� �!�"

Figure 6.1: Filterbank implementation architecture for 4 channels with 5 taps per channel

Figure 6.1 depicts the architecture chosen for the filterbank implementation. Thefilterbank in this figure has 4 channels with 5 taps per channel. The registers of the tapsare implemented in a dual port memory blocks, where each memory block containssingle tap-register from each sub-filter. Each logical row of memory cells, therefore,comprises the tap-registers of a single sub-filter. This way, we avoid using huge andslow multiplexers for selecting the correct corresponding tap-register in each clock cycle.The counter controls the address for the memory inputs and output, choosing in eachclock cycle the consecutive sub-filter to perform. Each memory output, except of theleftmost memory block, is connected to the next memory block. Each memory outputis also connected to one multiplier input. The second multiplier input (broken lines) isfed by its corresponding tap-coefficient from the coefficients lookup table. The lookuptable can also be implemented as a ROM block. The correct lookup table entry is chosenby the channel-counter. Each tap-multiplier output feeds the multi-operand adder,which sums them up. The adder‘s output is also the data output of the filterbank, whichprovides all channels outputs in serial form. The channel-counter signal is also output toprovide indication for the current sample-data on the data output. The multipliers andthe multi-operand adder are pipelined. Four and five stages, respectively, are necessaryfor the test-case example. The channel-number output is therefore accordingly delayed(the delay elements are omitted from Figure 6.1). Only a single path, say the I-path,is depicted in Figure 6.1. The Q-path is similarly implemented where both paths aresharing the same counter and lookup table.


The design architecture depicted in Figure 6.1 provides a cost effective implementationof the filterbank, while keeping speed performance high. The test-case example can beimplemented using a total of only 30 16-bit multipliers (for the I and Q paths both) andtwo 15-operand adders. This configuration is not only feasible in terms of HW cost, butalso performs within the speed requirements, as shown in Section 6.2.

6.2 Results

In this section we present the results obtained from the filterbank implementation.First, we describe the functional verification setup. Subsequently, we show some resultsspecific to the test-case parameters, as appear in Table 6.1. We conclude presenting atable of HW-cost and speed performance results for various applicable parameters ofthe filterbank.

6.2.1 Functional Verification

The functionality of the design was tested in two steps. In the first step, VHDL simula-tion tool was used. Various input vectors were generated using Matlab. The inputs wereof normally distributed random samples and of sine samples, both scaled to full dynamicrange. afterwards, the VHDL simulation outputs were compared to the expected outputfrom the same Matlab model used for the parameter ranges survey. These tests resultedin identical output vectors achieved for several simulation of various parameters.

Figure 6.2: HW testbench configuration

6.2. RESULTS 41

In the second step, a HW testbench was produced for the target FPGA Altera StratixEP1S25F1020C7, which has 25,660 LEs, 1,944,576 built-in memory block bits, and 40 9-bitbuilt-in multipliers. The HW testbench configuration is illustrated in Figure 6.2. The test-vectors are loaded to the ROM, using Altera’s In-System Memory Content Editor - a toolthat can access built-in memory blocks trough the FPGA’s JTAG connectors and retrieveor edit their contents. The test-vectors are processed by the filterbank implementedon the FPGA, which passes its outputs to a RAM. The RAM contents are then readinto a file that is compared to the expected results generated by the Matlab model ofthe filterbank. During the functional verification filterbanks with diverse parameters(including the test-bench parameters from Table 6.1) were tested and yielded a perfectmatch to the output files generated by the fixed-point Matlab model of the filterbankwith identical parameters.

6.2.2 Test-Case Results

Implementation of the test-case on Stratix EP1S40F1508C5 requires 11,100 LEs, 737,280memory bits, and 60 built-in 9-bit multipliers. That is 27% , 22%, and 54% (respectively)of this FPGA resources. As a result, plenty of resources is left for implementing moremodules on the same FPGA (e.g., IQ-demodulator). This implementation achievesmaximal clock frequency of 220.41 MHz. Consequently, The maximal channel spacingthat can be handled using this filterbank implementation is of 107.6 KHz. Therefore,100 KHz, 50 KHz, 25 KHz, and 12.5 KHz, which are common values for practical targetsof interest and fit to this configuration.

Since the implementation is of generic nature, specific results are not obtainable as theydepend on the chosen implementation parameters such as word-length. Therefore, webring here specific results for the test-case alone. This is done by comparison of the test-case results which are for fixed-point word-length, which are compared to ideal resultsgenerated with the Matlab model of the filterbank using full floating-point precision(ANSI/IEEE Std 754-1985 double-precision).

Figure 6.3 contains example of the measures signal to noise ratio (SNR) per channel,where the average is 85.45 dB, and no channel has a lower SNR than 83 dB. Equation 6.1gives the theoretically ideal SNR (n ≥ 5) in decibels due to quantization noise [35], wheren is the word-length representation in bits. According to this equation the theoreticallyideal inherited SNR for 16-bit word-length is 98.1dB compared to the measured results,this implementation achieves dynamic range of 13.9-bit on average and 13.49-bit in theworst case.

SNR = n20 log(2) +12

20 log(1.5) (6.1)

6.2.3 General Results

In the former section we presented and explained specific results of the test-case imple-mentation. In this section we present HW-cost and performance results obtained for


0 100 200 300 400 500 600 700 800 900 10000

10

20

30

40

50

60

70

80

90

SNR per channel [dB]

0 100 200 300 400 500 600 700 800 900 100080

85

90

Figure 6.3: SNR

several applicable parameter choices. The results are summarized in Table 6.2.

Observing this table, we can see that various implementation schemes are feasible us-ing the architecture introduced in the previous chapter, while achieving channelizationof up to 4096 channels with a performance of 214.64 (complex) mega-sample per second(entry 8 in the table). Entries 3 and 6 illustrate the results for the test-case, implementedon two different FPGAs, where entry 6 achieves a performance of 308.07 mega-samplesper second.

6.2.4 Conclusion

In the first section of this chapter we introduced test-case parameters for the realizationof a practical filterbank. Afterward, we established approach by which the filterbankimplementation architecture is designed. Subsequently, we presented our implemen-tation architecture where multipliers are shared ”tap-wise” instead of ”subfilter-wise”.Thereafter, we gave a detailed explanation of the architecture we chose for implementingthe channelizer filterbank.

In the second section of this chapter we introduced the results of the HW implemen-tation. We first presented the HW setup used for a functional verification. Afterwards,we presented specific results of a test-case implementation scheme, providing HW-cost, speed performance, and SNR results, yielding the dynamic range of the filterbankoutput signals. Thereafter, we presented HW-cost and speed performance results forvarious applicable parameter configurations. Thereby, we proved that our implementa-tion architecture for the filterbank is efficient and feasible on currently-available FPGAs,and that it is consistent with the parameter ranges survey results.

6.2. RESULTS 43

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Conclusions &Recommendations 7In this dissertation we explained the software defined radio concept (Chapter 2), andwe introduced and compared three channelization algorithms, namely the per-channelalgorithm, the pipelined frequency transform algorithm, and the polyphase fast-Fouriertransform channelization algorithm, choosing the later for further investigation (Chap-ter 3). Consequently, we explained in details the PFFT architecture, focusing on theIQ-demodulator and the filterbank (Chapter 4). Afterward, we presented parameterranges survey of these two modules, introducing graphs that provide insight to designtrade-offs of these two modules(Chapter 5). Following, we presented our implementa-tion architecture for the filterbank and the implementation results (Chapter 6). Thereby,we proved that our implementation architecture for the filterbank is efficient and feasibleon currently-available FPGAs.

The reminder of this chapter is structured as follows. Section 7.1 presents the con-clusions from all previous chapters and in Section 7.3 we bring recommendations forfurther related investigation.

7.1 Conclusions

These are the conclusions attained in the preceding chapters.

• In Chapter 2 we introduced the SDR concept. We presented the ideal SDR receiverand showed its advantages above typical radio receivers, which are implementa-tion flexibility and reconfigurability, improved accuracy, better robustness towardsexternal environment influence, small footprint, low power consumption, and fasttime-to-market. Subsequently, we explained the reasons for ideal SDR receiverunattainability. Consequently, we introduced a feasible SDR receiver with analogand digital front-ends, where the digital front-end takes over computationally in-tensive tasks that are too demanding for the software-driven platform. Widebandchannelization is such task, whereas studying, designing, and implementing it ina digital front-end for SDR is the focus of this work.

• In Chapter 3 we introduced three different channelization algorithms. Namely,the per-channel, the PFT, and the PFFT algorithms, explaining in details . Con-sequently, we presented HW comparison between these algorithms for LUT andmemory resources utilization. Based on this comparison, the PFFT algorithmappears to be superiorly cost efficient when channelizing few hundreds or morecommunication channels.

45

46 CHAPTER 7. CONCLUSIONS & RECOMMENDATIONS

Afterwards, we presented a qualitative comparison between these three algo-rithms that comprises also group delay, initial design flexibility, and reconfig-urability. Based on the performed comparisons, we came to the conclusion thatdespite the fact that the per-channel algorithm has better score in many compar-ison aspects, its implementation is critically HW inefficient and is infeasible forhigh number of channels, even on todays largest available FPGAs. Therefore, wechose the PFFT algorithm, which is highly cost efficient and has the best com-putational for high number of channels, for our implementation of the front-endwideband channelizer.

• In Chapter 4 we presented and explained the decomposition of the polyphase FFTchannelizer algorithm into IQ-demodulator, filterbank, FFT, and post-processingmodules. We gave a explanation about three different implementation algorithmsof the IQ-demodulator, namely, conventional, wideband, and Hilbert transformedIQ-demodulators. We concluded that the Hilbert transformed IQ-demodulatoralgorithm is best choice for implementation since it provides the same results asthe other two algorithms while requiring less HW resources.

Afterwards, we introduced two filter design techniques for the prototype filter,from which the filterbank is derived, i.e., the Parks-McClellan equiripple filter de-sign and the Parks-McClellan 1/f ripple design. Comparing these two techniqueswe decided that the second one is most advantageous for the implementationof the filterbank. Since the FFT is to be implemented using Eonic’s PowerFFT™processor, the modules chosen for the parameter ranges survey (in Chapter 5) arethe IQ-demodulator and the filterbank.

• In Chapter 5 we presented a parameter ranges survey for the IQ-demodulator andfor the filterbank. We first presented the simulation setup, giving a comprehen-sive explanation of parameters dependency for the IQ-demodulator and for thefilterbank modules. Subsequently, we gave the simulation results for both fullfloating-point precision and fixed-point implications.

The parameter ranges survey gave us some important results necessary forunderstanding the behavior and design trade-offs of the IQ-demodulator and thefilterbank. The attained plots provide a tool for the choice of HW resources andfor the process of requirements elicitation.

• In Chapter 6 we we introduced test-case parameters for the realization of a practicalfilterbank. Afterward, we established approach by which the filterbank implemen-tation architecture is designed. Subsequently, we presented our implementationarchitecture where multipliers are shared ”tap-wise” instead of ”subfilter-wise”.Thereafter, we gave a detailed explanation of the architecture we chose for imple-menting the channelizer filterbank.

7.2. MAIN CONTRIBUTIONS 47

In the second section of this chapter we introduced the results of the HW im-plementation. We first presented the HW setup used for a functional verification.Afterwards, we presented specific results of a test-case implementation scheme,providing HW-cost, speed performance, and SNR results, yielding the dynamicrange of the filterbank output signals. Thereafter, we presented HW-cost and speedperformance results for various applicable parameter configurations. Thereby, weproved that our implementation architecture for the filterbank is efficient and fea-sible on currently-available FPGAs, and that it is consistent with the parameterranges survey results.

7.2 Main Contributions

In this section, highlights of the main contributions of our work are presented:

• We have shown that the polyphase FFT channelization algorithm is the mostappropriate for digital front-end SDR wideband channelizer.

• We have established the different relationships and trade-offs between the variouschannelizer parameters.

• We have devised implementation architecture for the polyphase FFT algorithm.

• We have demonstrated that the implementation architecture for applicable para-meters is feasible on state-of-the-art FPGAs.

7.3 Recommendations

In this section we provide few recommendations for possible directions in future relatedresearch.

• Oversampled version of the polyphase FFT algorithm (WOLA) could be studiedin detail following the same framework of this study.

• The implementation architecture devised in this study could be tested on differentFPGA brands and compared with the results obtained in our work.

• A complete channelizer front-end implementation based on this study could beexamined in detail.

• Dynamic reconfigurable architectures and implementation, based on this studycould be inspected.

48 CHAPTER 7. CONCLUSIONS & RECOMMENDATIONS

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Curriculum Vitae

Gil Savir was born in Afula, Israel on the 21st

of March 1976. In 1988 he started his secondaryeducation in the ”Ben-Gurion arts and sciencehigh-school”, where he graduated in 1994. InAugust 1994 he joined the Israeli Defense Forcesand served on the Israeli Navy Submarine ’Ra-hav’ as electronics technician and operator in thecombat information center (CIC) and navigationdepartment, on which he, later, also commanded.In 1997, he was assigned as instructor in the Is-raeli Submarines Naval Academy. In 1999, hewas released from duty with the rank of chiefpetty officer (CPO).

In September 2000, He enlisted as a studentat the Faculty of Computer Science, Delft Uni-versity of Technology (TU Delft) at The Nether-lands. In 2002 he spent one year in the Poly-technic University of Catalonia (UPC) at Spain aspart of students exchange program. He receivedhis BSc degree in Computer Science at the DelftUniversity of Technology in 2004. Currently, heis graduating his MSc studies in the Departmentof Computer Engineering at the Delft Universityof Technology.

scalable and reconfigurable digital front-end for sdr wideband

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