axel-x evaluation board hardware manual - fujitsu · 5.3.2 axel-x bottom view of evaluation...

AXEL-X Evaluation Board Hardware Manual

REVISION 1.1

This document contains confidential information which shall not be reproduced or transferred to other documents or disclosed to others or used for manufacturing or any other purpose without prior written permission from FUJITSU Ltd. All information contained in this document is subject to change without notice. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness.

Copyright © 2006 FUJITSU LTD. All rights reserved. - 2 -

Table of Contents1.0 ABOUT THIS MANUAL.......................................................................................... 3

1.1 DOCUMENT OVERVIEW ............................................................................................. 3 1.2 ACRONYMS ............................................................................................................... 3

2.0 HARDWARE OVERVIEW...................................................................................... 4 2.1 EVALUATION BOARD BLOCK DIAGRAM.................................................................... 5 2.2 POWER DIAGRAM...................................................................................................... 6 2.3 POWER MONITOR DIAGRAM...................................................................................... 6 2.4 CLOCK DIAGRAM ...................................................................................................... 7 2.5 RESET DIAGRAM ....................................................................................................... 7

3.0 AXEL-X CONNECTIONS ....................................................................................... 8 3.1 AXEL-X TO XFP CONNECTION ................................................................................ 8 3.2 AXEL-X TO CX4 CONNECTION................................................................................ 9 3.3 AXEL-X TO GMII/MII CONNECTION..................................................................... 10 3.4 AXEL-X TO CONFIGURATION DIP SWITCHES, STATUS AND IRQ........................... 10

4.0 AXEL-X EVALUATION BOARD SETTINGS.................................................... 11 4.1 AXEL-X EVALUATION BOARD HEADERS............................................................... 11 4.2 AXEL-X EVALUATION BOARD JUMPERS................................................................ 13 4.3 AXEL-X EVALUATION BOARD DIP SWITCHES ....................................................... 14

5.0 PHYSICAL OVERVIEW ....................................................................................... 19 5.1 HSIO INTERFACE .................................................................................................... 19 5.2 LAYER STACK-UP ................................................................................................... 20 5.3 AXEL-X PHYSICAL BOARD VIEW .......................................................................... 21

5.3.1 AXEL-X Top View of Evaluation Board ........................................................ 21 5.3.2 AXEL-X Bottom View of Evaluation Board................................................... 22



1.0 About This Manual This document describes the Fujitsu AXEL-X 10 Gigabit Ethernet evaluation board.

1.1 Document Overview The documents includes a description of the following:

• Hardware Block Diagram • Hardware References • Signal Timing • Register Description • Board Layout

1.2 Acronyms GBE Gigabit Ethernet GMII Gigabit Medium Independent Interface HSIO High Speed Input/Output LVDS Low Voltage Differential Signal MDIO Management Data Input/Output MDII Medium Independent Interface PHY Physical Layer Device XAUI 10 Gigabit Attachment Unit Interface XGP 10 Gigabit Ethernet Pluggable Transceiver



2.0 Hardware Overview The AXEL-X chip contains the following:

1. Power Supply • 1.2V • 2.5V

2. Reference Clock • 156.25 MHz LVDS • 6 Clock Inputs

3. Package • FCBGPA1156 (1 mm, 35mm x 35mm)

4. Total Power Consumption • 15W to 20W Typical

5. Interface • 20 HSIO Interfaces • 2 GMII Interfaces • 2 I2C Interfaces • 2 MDIO Interface

2.1 Evaluation Board Block Diagram The evaluation board consists of the following blocks:

• 2 GMII/MII PHYs • Headers and Test Points • AXEL-X Reset Switch • I2C Interface • I2C Switch • 156.25 Crystal Oscillator • AXEL-X Ethernet Switch • EEPROM • 16 CX4 Interfaces • 4 XFP Interfaces

AXEL-X

CX4PORT

1

CX4PORT

3

XFPPORT

1

CX4PORT

16

CX4PORT

2

16 XAUI

4 X 10GBE

SERIALLANES

XFPPORT

2

XFPPORT

3

XFPPORT

4

I2C Switch

I2C

EEPROM

I2C

CLOCK BUFFER

156.25 MHz

x 6CLOCKS

GBEPHY

GBEPHY

RESET

HEADER

0.80V 1.2V 2.5VVOLTAGEMONITOR



2.2 Power Diagram

DC to DCConverter

DC to DCConverter

DC to DCConverter

12 Volts

VoltageRegulator

5V_INT

VoltageRegulator

VoltageRegulator

VoltageRegulator

VoltageRegulator

3.3V

1.2V

2.5V_VDE

1.8V

2.5V_VDP

2.5V

VoltageRegulator

1.2V_VDD

1.2V_VDN

5V

1.2V_AVD

1V_REF

2.3 Power Monitor Diagram

1V_REF

1V_REF

1V_REF

1V_REF

2.5V_VDE

2.5V_VDP

1.2V_VDD

1.2V_VDN

POWER GOOD MONITOR



2.4 Clock Diagram

2.5V

CLOCK LVDSREPEATER

6 LVDS 156.25MHz Signals that

go to AXEL156.25 MHzSignals

2.5 Reset Diagram

2.5V

POWER GOOD MONITOR

LOW PASS FILTERWITH 100us delay

RESET AXEL PLL

RESET AXEL

RESET I2C SWITCH

RESET GBE PHY



3.0 AXEL-X Connections This sections describes the AXEL-X connections to the following:

• AXEL-X connections to XFP modules • AXEL-X connections to CX4 connectors • AXEL-X connections to GMII/MII PHYs.

3.1 AXEL-X to XFP Connection

AXEL-X

VCC5

5V

VCC5 VCC3VCC3 VCC2VCC2

XO_Pnn_TXx[0]

XO_Pnn_TXx[3]

XO_Pnn_TXx[0]

XO_Pnn_TXx[3]

XI_Pnn_TXx[0]

XI_Pnn_TXx[0]

5V_XFP

3.3V 3.3V_XFP

1.8V_XFP 1.8V

XFPTD+

TD-

REFCLK+

REFCLK-

RD+

RD-

P_DOWN/RST

TX_DIS

MOD_DESEL

INTERRUPT

RX_LOS

MOD_NR

MOD_ABS

SCL

SDA

DIP SW (GND)

DIP SW (GND)

DIP SW (GND)

RED (L) LED (3.3V PULL UP)

RED (H) LED (3.3V PULL UP)



I2C SWITCH (3.3V PULL UP)

I2C SWITCH (3.3V PULL UP)

Polarity can be swapped. 161 MHz reference can go on any layer



3.2 AXEL-X to CX4 Connection

AXEL-X

RX0+

RX3-

RX3+

RX2-

RX2+

RX1-

RX1+

RX0-

CX4 Connector

S01

S07

S06

S05

S04

S03

S02

S08

TX0-

TX3+

TX2+

TX2-

TX1+

TX1-

TX0+

TX3-

S16

S15

S14

S13

S12

S11

S10

S09

Note: Both Tx and Rx polarity lanes can be swapped. Note: DC Blocking caps for RX lanes are required.



3.3 AXEL-X to GMII/MII Connection

PHY

3.3V 1.2V2.5V 1.2V_PHY

XO_GTK_CLK1

XO_TXD1[7:0]

XO_TX_EN1

XO_TX_ER1

XI_RX_CLK1

XI_RX_D1[7:0]

XI_RX_DV1

XI_RX_ER1

XI_TX_CLK1

XI_COL1

XI_CRS1CRS

COL

RXER

RXDV

RXD[0:7]

RXCLK

TXER

TXEN

TXD[0-7]

GTXCLK

TXCLK

RJ45CONNECTORTXVxx

CMODE[7:0]

RESET

TXDIS

USER SPECIFIED

NEED RESET SEQ

XTALK1/225 MHz

CLKOUTMICRO

MODDEF0

MODDEF1

MODDEF2

MDINT

EECLK

EEDAT

LED[4:0]

AXEL-X

PULL DOWN

NO CONNECT

PULL DOWN

HEADER

HEADER

2.5V PULL UP

DIP SW

LEDs

3.4 AXEL-X to Configuration DIP Switches, Status and IRQ

AXEL-X

DIP SWITCHESXI_CONFIG[7:0]

XO_IRQ_N[2:0]

2.5V_VDE

TO HEADERAND LEDs

XO_STS_OUT[8:0]CYCLE STATUSGENERATION

LOGICLEDs

HEADER



4.0 AXEL-X Evaluation Board Settings The AXEL-X evaluation boards is equipped with a number of different headers, jumpers, potentiometers and dip switches used to monitor, configure and vary different voltages. This section describes these components and their uses.

4.1 AXEL-X Evaluation Board Headers





Headers Description J34 CLK00_STS[5:0] J35 JTAG PHY1 J36 AXEL_STS[8:0] J37 CLK01_STS[5:0] J38 I2C #1 HEADER FOR DEBUG J39 I2C #2 HEADER FOR EEPROM J40 CLK10_STS[5:0] J41 MDIO #1 J42 MDIO #2 J43 JTAG PHY2 J44 CLK11_STS[5:0] J45 AXEL_TEST_HEADER J46 JTAG AXEL-X HEADER J47 AXEL INTERRUPT HEADER J49 1.2V_VDD J51 1.2V_VDD J53 GND J54 1.2V_VDN J55 1.2V_VDN J57 GND J71 3.3V AND 2.5V_VDE JX1 I2C #1 HEADER FOR DEBUG JX2 I2C #2 HEADER FOR EEPROM JY1 MDIO #1 JY2 MDIO #2

4.2 AXEL-X Evaluation Board Jumpers

Headers Description J5 If high (on) EEPROM write is disabled J8 SMA connector used for external clock input J9 If low (off) 156.25 MHz XTAL is disable J10 SMA connector used to measure clock J50 If low 1.2V_VDD is disabled J52 If low 5V_INT is disabled. J56 If low 1.2V_VDN is disabled. J58 Jumper for 0.80V_VDR J59 Jumper for 0.80V_VDR J63 Jumper for external 2.5V_VDE J64 Jumper for external 2.5V_VDE J65 If low 2.5V_VDE is disabled J66 Jumper for external 2.5V_VDP J67 Jumper for external 2.5V_VDP J68 If low 2.5V_VDP is disabled



4.3 AXEL-X Evaluation Board Dip Switches





SW1

Dip

Switch Description

1 XI_CONFIG0 Reserverd

2 XI_CONFIG1 EEPROM Presence

1: EEPROM Present 0: EEPROM not present

3 XI_CONFIG2 I2C Bus Speed

1: 400KHz 0: 100KHz

4 XI_CONFIG3 Buffer Configuration 1: For Management

0: Default 5 6 7

XI_CONFIG[6:4] Lower 3 bits of slave address. Valid configuration 3’b001-3’b111

8 XI_CONFIG7

1: Disable Chatter Filter 0: Enable Chatter Filter

SW2

Dip

Switch Description

1 Power down XFP Port 1 2 Disable Tx XFP Port 1 3 MOD_DESEL XFP Port 1 6 Power down XFP Port 5 7 Disable Tx XFP Port 5 8 MOD_DESEL XFP Port 5



SW3

Dip Switch

Description

1 Power down XFP Port 6 2 Disable Tx XFP Port 6 3 MOD_DESEL XFP Port 6 6 Power down XFP Port 2 7 Disable Tx XFP Port 2 8 MOD_DESEL XFP Port 2



SW4

Dip Switch

Description

1 HTMODE HSIO Test Mode Select

1: Test Mode 0: Normal

2 HTSCK HSIO Test Clock

3 HTXRST HSIO Test Register

Active Low 4 SCK

Auxiliary Clock Input for test mode. 5 PLLBP

PLL Bypass Mode Input 1: Bypass 0: Normal

6 VPD1 IDDQ test control input

1: Test mode 0: Normal

7 VPD2 IDDQ Test control input

1: Test mode 0: Normal



SW5

Dip

Switch Description

1 Stop RTC task for I2C Port-2 test. RTC can be restarted by hardware reset.

2 Disable host-port isolation upon Sync. (so that the eval board can be used as a private-LAN component)

3 Port-21 Mode. 0=1000BaseT FDX, 1=100/10BaseT FDX. (this bit is checked after reset)

4 Port-23 Mode. 0=1000BaseT FDX, 1=100/10BaseT FDX. (this bit is checked after reset)

5 Port-21 Isolation. 1=Port-21 is excluded from the default VLAN membership.

6 Port-23 Isolation. 1=Port-23 is excluded from the default VLAN membership.

7 Flow Control Enable. 1=PAUSE Flow Control enabled. (Note: this bit can be change at any time)

8 Port Initialization Control. 1=stop port initialization after reset. 1->0: restart port initialization

5.0 Physical Overview This section will describe the following:

• HSIO Interface • Trace Length • Layer Stack-up • Top and Bottom View of AXEL-X Evaluation Board

5.1 HSIO Interface The AXEL-X evaluation board is configured to use 16 CX4 interfaces and 4 XFP interfaces.

11

10

14

18

9

15

8

9

13

17

16

12

7 403

6 512

CX4 CX4

CX4

CX4

CX4

CX4

CX4CX4

CX4

CX4

CX4

CX4

CX4

CX4

CX4

CX4

XFP

XFP

XFP

XFP

AXEL TOPVIEW





5.2 Layer Stack-Up The evaluation board is 14 layers. The layer stack up is as follows:

Layers Type 1 Signal 2 Ground 3 Signal 4 Ground 5 Power 6 Ground 7 Power 8 Ground 9 Power 10 Power 11 Ground 12 Signal 13 Ground 14 Signal

5.3 AXEL-X Physical Board View This section shows the top and bottom view of the AXEL-X evaluation board. 5.3.1 AXEL-X Top View of Evaluation Board



5.3.2 AXEL-X Bottom View of Evaluation Board



axel-x evaluation board hardware manual - fujitsu · 5.3.2 axel-x bottom view of evaluation...

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