bab19 - engineering applications

8/9/2019 BAB19 - Engineering Applications

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Introduction to Simulink with Engineering Applications 19−1Copyright © Orchard Publications

Chapter 19

Engineering Applications

his chapter is devoted to engineering applications using appropriate Simulink blocks toillustrate the application of the blocks in the libraries which we described in Chapters 2through 18. Most of these applications may be considered components or subsystems of

large systems such as the demos provided by Simulink. Some of these applications describe someof the new blocks added to the latest Simulink revision.

19.1 Analog−to−Digital Conversion

One of the recently added Simulink blocks is the Idealized ADC Quantizer. Figure 19.1 shows

how this block can be used to discretize a continuous−

time signal such as a clock. The FunctionBlock Parameters dialog box provides a detailed description for this block.

Figure 19.1. Model for Analog−

to−

Digital conversion

The settings specified for the Idealized ADC Quantizer are noted in Figure 19.1. The output datatypes for the Clock and the Idealized ADC Quantizer blocks are specified as double. The inputand output waveforms are shown in Figure 19.2.

Figure 19.2. Input and output waveforms for the model of Figure 19.1


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Chapter 19 Engineering Applications

19−2 Introduction to Simulink with Engineering Applications Copyright © Orchard Publications

19.2 The Zero−Order Hold and First−Order Hold as Reconstructors

Suppose that a continuous−time signal is bandlimited with bandwidth , and its Fourier

transform is zero for . The Sampling Theorem states that if the sampling frequency

is equal or greater than , the signal can be recover entirely from the sampled signal

by applying to an ideal lowpass filter with bandwidth . Another method for recover-

ing the continuous−time signal from the sampled signal is to use a holding circuit that

holds the value of the sampled signal at time until it receives the next value at time . A

Zero−Order Hold circuit behaves like a low-pass filter and thus can be used as a holding circuit to

recover the continuous−time signal from the sampled signal .

The model of Figure 19.3 shows the output of a Zero−Order Hold block specified at a low sam-pling frequency, and Figure 19.4 shows the input and output waveforms.

Figure 19.3. Model producing a piecewise constant waveform when the sampling frequency is low


Whereas the Zero−Order Hold circuit generates a continuous input signal by holding each

sample value constant over one sample period, a First−Order Hold circuit uses linear inter-

polation between samples as shown by the model of Figure 19.5 and the waveforms in Figure 19.6.

x t( ) B

X ω( ) ω B>

ωS 2B x t( )

xS t( ) xS t( ) B

x t( ) xS t( )

nT nT T+

x t( ) xS t( )

u t( )

u k [ ]


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The Zero−Order Hold and First−Order Hold as Reconstructors

Figure 19.5. The model of Figure 19.2 with a First−Order Hold block


A comparison of the outputs produced by a Zero-Order Hold block and a First-Order Hold blockwith the same input, is shown in the model of Figure 19.7. The outputs are shown in Figure 19.8.

Figure 19.7. Model for comparison of a Zero-Order Hold and a First-Order Hold blocks with same input


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Figure 19.8. Waveforms for the model of Figure 19.7

19.3 Digital Filter Realization Forms

A given transfer function of a digital filter can be realized in several forms, the most com-

mon being the Direct Form I, Direct Form II, Cascade (Series), and Parallel. These aredescribed in Subsections 19.3.1 through 19.3.4 below. Similar demo models can be displayed asindicated in these subsections.

19.3.1 The Direct Form I Realization of a Digital Filter

The Direct Form I Realization of a second−order digital filter is shown in Figure 19.9.

Figure 19.9. Direct Form I Realization of a second−order digital filter

At the summing junction of Figure 19.9 we obtain

H z( )

+

y n[ ]

a1

a0

a2

b– 2

b– 1

x n[ ] z 1–

z 1– z

1–z

1–

a0X z( ) a1z 1–

X z( ) a2z 2–

X z( ) b1–( )z 1–

Y z( ) b2–( )z 1–

Y z( )+ + + + Y z( )=


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Digital Filter Realization Forms

and thus the transfer function of the Direct Form I Realization of the second−order digital filter of Figure 19.9 is

(19.1)

A disadvantage of a Direct Form I Realization digital filter is that it requires registers where

represents the order of the filter. We observe that the second−order ( ) digital filter of Figure

11.9 requires 4 delay (register) elements denoted as . However, this form of realization has the

advantage that there is no possibility of internal filter overflow.*

19.3.2 The Direct Form II Realization of a Digital Filter

Figure 19.10 shows the Direct Form-II† Realization of a second−order digital filter. The Sim-ulink Transfer Fcn Direct Form II block implements the transfer function of this filter.

Figure 19.10. Direct Form-II Realization of a second-order digital filter

The transfer function for the Direct Form−II second−order digital filter of Figure 19.10 is the sameas for a Direct Form−I second−order digital filter of Figure 19.9, that is,

(19.2)

A comparison of Figures 19.9 and 19.10 shows that whereas a Direct Form−I second−order digitalfilter is requires registers, where represents the order of the filter, a Direct Form−II second−

order digital filter requires only register elements denoted as . This is because the register

* For a detailed discussion on overflow conditions please refer to Digital Circuit Analysis and Design with anIntroduction to CPLDs and FPGAs, ISBN 0-9744239-6-3, Section 10.5, Chapter 10, Page 10−6.

† The Direct Form-II is also known as the Canonical Form.

X z( ) a0 a1z 1–

a2z 2–

+ +( ) Y z( ) 1 b1z 1–

b2z 2–

+ +( )=

H z( ) Y z( )X z( )------------ a0 a1z

1–

a2z

2–

+ +1 b1z

1– b2z

2–+ +

-----------------------------------------= =

2k k

k 2=

z 1–

x n[ ]

b2

y n[ ]

++

++

z 1–

z 1–

a1–

a2–

b1

b0

H z( ) a0 a1z

1–a2z

2–+ +

1 b1z 1–

b2z 2–

+ +-----------------------------------------=

2k k

k z 1–


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( ) elements in a Direct Form−II realization are shared between the zero section and the pole

section.

Example 19.1

Figure 19.11 shows a Direct Form−II second−order digital filter whose transfer function is

(19.3)

The input and output waveforms are shown in Figure 19.12.

Figure 19.11. Model for Example 19.1


z 1–

H z( ) 1 1.5z

1–1.02z

2–+ +

1 0.25 z 1–

– 0.75z 2–

+--------------------------------------------------=


7/32



A demo model using fixed−point Simulink blocks can be displayed by typing

fxpdemo_direct_form2

in MATLAB’s Command Window. This demo is an implementation of the third−order transferfunction

19.3.3 The Series Form Realization of a Digital Filter

For the Series* Form Realization, the transfer function is expressed as a product of first−order andsecond-order transfer functions as shown in relation (19.4) below.

(19.4)

Relation (19.4) is implemented as the cascaded blocks shown in Figure 19.13.

Figure 19.13. Series Form Realization

Figure 19.14 shows the Series−Form Realization of a second−order digital filter.

Figure 19.14. Series Form Realization of a second-order digital filter

The transfer function for the Series Form second−order digital filter of Figure 19.14 is

(19.5)

* The Series Form Realization is also known as the Cascade Form Realization

H z( ) 1 2.2z 1– 1.85z

2– 0.5z

3–+ + +

1 0.5– z 1–

0.84z 2–

0.09z 3–

+ +---------------------------------------------------------------------=

H z( ) H1 z( ) H2 z( )… HR z( )( )⋅=

X z( ) HR z( )H2 z( )H1 z( ) Y z( )

z 1–

z 1–

a1

a2

b– 1

b– 2

+ + y[n]x[n]

H z( ) 1 a1 z

1–a2z

2–+ +

1 b1 z 1–

b2 z 2–

+ +----------------------------------------=


8/32



Example 19.2

The transfer function of the Series Form Realization of a certain second−order digital filter is

To implement this filter, we factor the numerator and denominator polynomials as

* (19.6)

The model is shown in Figure 19.15, and the input and output waveforms are shown in Figure19.16.


* The combination of the of factors in parentheses is immaterial. For instance, we can group the factors as

and or as and

H z( ) 0.5 1 0.36– z

2–( )

1 0.1z 1–

0.72– z 2–

+---------------------------------------------=

H z( ) 0.5 1 0.6 z

1–+( ) 1 0.6z

1––( )

1 0.9z 1–

+( ) 1 0.8z 1–

–( )-----------------------------------------------------------------=

1 0.6 z 1–

+( )

1 0.9 z 1–

+( )-----------------------------

1 0.6 z 1–

–( )

1 0.8 z 1–

–( )-----------------------------

1 0.6z 1–

+( )

1 0.8 z 1–

–( )-----------------------------

1 0.6 z 1–

–( )

1 0.9z 1–

+( )-----------------------------


9/32


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Figure 19.17. Parallel Form Realization

As with the Series Form Realization, the ordering of the individual filters in Figure 19.17 is imma-

terial. But because of the presence of the constant , we can simplify the transfer function

expression by performing partial fraction expansion after we express the transfer function in the

form .

Figure 19.18 shows the Parallel Form Realization of a second−order digital filter. The transferfunction for the Parallel Form second−order digital filter of Figure 19.18 is

(19.8)

Figure 19.18. Parallel Form Realization of a second-order digital filter

X z( )

HR

z( )

H2

z( ) Y z( )

K

H1

z( )

K

H z( ) z ⁄

H z( ) a1 a2z

2–+

1 b1 z

1–

b2 z

2–

+ +

----------------------------------------=

z 1–

z 1–

a1

a2

b– 1

b– 2

+ + y[n]x[n]


11/32



Example 19.3

The transfer function of the Parallel Form Realization of a certain second−order digital filter is

To implement this filter, we first express the transfer function as

Next, we perform partial fraction expansion.

Therefore,

(19.9)

The model is shown in Figure 19.19, and the input and output waveforms are shown in Figure19.20.

H z( ) 0.5 1 0.36– z

2–( )

1 0.1z 1–

0.72– z 2–

+---------------------------------------------=

H z( )

z------------

0.5 z 0.6+( ) z 0.6–( )

z z 0.9+( ) z 0.8–( )--------------------------------------------------=

0.5 z 0.6+( ) z 0.6–( )

z z 0.9+( ) z 0.8–( )--------------------------------------------------

r 1

z----

r 2

z 0.9+( )---------------------

r 3

z 0.8–( )---------------------+ +=

r 10.5 z 0.6+( ) z 0.6–( )

z 0.9+( ) z 0.8–( )--------------------------------------------------z 0=

0.25= =

r 20.5 z 0.6+( ) z 0.6–( )

z z 0.8–( )--------------------------------------------------

z 0.9–=

0.147= =

r 30.5 z 0.6+( ) z 0.6–( )

z z 0.9+( )--------------------------------------------------

z 0.8=

0.103= =

H z( )

z------------

0.25

z----------

0.147

z 0.9+----------------

0.103

z 0.8–----------------

+ +=

H z( ) 0.25 0.147z

z 0.9+----------------

0.103z

z 0.8–----------------+ +=

H z( ) 0.25 0.147

1 0.9z 1–

+------------------------

0.103

z 0.8z 1–

–-----------------------+ +=


12/32





A demo model using fixed-point Simulink blocks can be displayed by typing

fxpdemo_parallel_form

in MATLAB’s Command Window. This demo is an implementation of the third−order transferfunction


13/32


Models for Binary Counters

19.4 Models for Binary Counters

In this section we will draw two models for binary counters.* Subsection 19.4.1 presents a 3−bit up/ down counter, and Subsection 19.4.2 presents a 4−bit Johnson counter.

19.4.1 Model for a 3− bit Up / Down Counter

A model for the operation of a 3−bit counter with three D Flip-Flop blocks, six NAND gateblocks, a NOT gate (Inverter) block, and a Clock block is shown in Figure 19.21. The D Flip −Flop and Clock blocks are in the Simulink Extras Toolbox, Flip−Flops library, and the NANDand NOT gates are in the Logic and Bit Operations Library. The D Flip−Flop CLK (clock)inputs are Negative Edge Triggered. The Clock waveform and the D Flip−Flops output waveforms

when the Manual Switch block is the Count up position, are shown in Figure 19.22.

Figure 19.21. Model for a 3−bit Up / Down binary counter

* For a detailed discussion on the analysis and design of binary counters, please refer to Digital Circuit Analysisand Design with an Introduction to CPLDs and FPGAs, ISBN 0-9744239-6-3.

H z( ) 5.5556 3.4639

1 0.1z 1–

+( )----------------------------–

1.0916– 3.0086z 1–

+

1 0.6z 1–

– 0.9z 2–

+

---------------------------------------------------+=


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19.4.2 Model for a 4− bit Ring Counter

The model of Figure 19.23 implements a 4−bit binary counter known as Johnson counter. The DFlip−Flop and Clock blocks are in the Simulink Extras Toolbox, Flip−Flops library. The wave-forms for this model are shown in Figure 11.24.

Figure 19.23. Model for a 4−bit Johnson counter


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Models for Mechanical Systems


19.5 Models for Mechanical Systems

In this section we will draw three models for mechanical systems. Subsection 19.5.1 presents aBlock−Spring−Dashpot system, Subsection 19.5.2 presents a system with two mass blocks and twosprings, and Subsection 19.5.3 is a simple mechanical accelerometer system

19.5.1 Model for a Mass−Spring−Dashpot

Figure 19.25 shows a system consisting of a block, a dashpot, and a spring. It is shown in feedbackand control systems textbooks that this system is described by the second-order differential equa-tion

(19.10)

where represents the mass of the block, is a positive constant of proportionality of the force

that the dashpot exerts on the block, and is also a positive constant of proportionality of the

force that the spring exerts on the block, known as Hooke’s law.

Figure 19.25. Mechanical system with a block, spring and dashpot

m d

2

dt2

-------x t( ) p d

dt-----x t( ) kx t( )+ + F t( )=

m p

k

F

Dashpot

Spring

Block

Mass m

x


16/32



The mass of the dashpot and the mass of the spring are small and are neglected. Friction is also

neglected. For the system of Figure 19.25, the input is the applied force and the output is the

change in distance .

Let us express the differential equation of (19.10) with numerical coefficients as

(19.11)

where is the unit step function, and the initial conditions are , and .

For convenience, we denote these are denoted as and respectively.

For the solution of (19.11) we will use the State−Space block found in the Continuous Library,and thus our model is as shown in Figure 19.26.

Figure 19.26. Model for Figure 19.25

The state equations are defined as

(19.12)

and

(19.13)

Then,

(19.14)

From (19.11), (19.13), and (19.14) we obtain the system of state equations

(19.15)

and in matrix form,

(19.16)

F

x

d2

dt2

------- x t( ) 2 d

dt----- x t( ) 3x t( )+ + 20 tsin( )u0 t( )=

u0 t( ) x 0( ) 4= dx dt ⁄ 0=

x10 x20

x1 t( ) x t( )=

x2 t( ) ddt----- x1 t( )=

d

dt-----x2 t( )

d2

dt2

------- x1 t( ) d

2

dt2

------- x t( )= =

d

dt----- x1 t( ) x2 t( )=

ddt----- x2 t( ) 3x1 t( ) 2x 2 t( )–– 20 tsin( )u0 t( )+=

d

dt-----x1 t( )

d

dt-----x2 t( )

0 1

3– 2–

x1 t( )

x2 t( )

0

20 tsin

u0 t( )+=


17/32



The output state equation is

or

Therefore, for the model of Figure 19.26, the coefficients , , , and are

(19.17)

The initial conditions and are denoted by the matrix

(19.18)

The values in (19.17) and (19.18) are entered in the Block parameters dialog box for the State-Space block, and after the simulation command is issued, the Scope block displays the waveformof Figure 19.27.

Figure 19.27. Waveform for the model of Figure 19.26

19.5.2 Model for a Cascaded Mass−Spring System

Figure 19.28 shows a a cascaded mass-spring system where is the applied force, is the mass, is the spring constant, is the friction, and is the displacement. It is shown in feedback and

control systems textbooks that the transfer function is

(19.19)

y Cx Du+=

y t( ) 1 0x1 t( )

x2 t( )

=

A B C D

A 0 1

3– 2–= B

0

5= C 1 0= D 0=

x10 x20

x10

x20

4

0=

F Mk f X

G s( ) X1 F ⁄ =

G s( ) k 1

M1s2

f + 1s k 1+( ) M2s2

f + 2s k 1 k 2+ +( ) k 12

–----------------------------------------------------------------------------------------------------------=


18/32



Figure 19.28. Cascaded mass−spring system

For simplicity, let us assume that the constants and conditions are such that after substitution into(19.19), this relation reduces to

(19.20)

and the force applied at . The model under those conditions is shown in Figure 19.29, and

the input and output waveforms are shown in Figure 19.30.

Figure 19.29. Model for the system of Figure 19.28


k 1 k 2

X1 X2

M1f 1 f 2

M2 F

G s( ) 12

s4

10s3

36s2

56s 32+ + + +------------------------------------------------------------------=

50 tsin


19/32



19.5.3 Model for a Mechanical Accelerometer

A simple mechanical accelerometer system consisting of a block, a dashpot, and a spring is con-nected as shown in Figure 19.31.

Figure 19.31. A simple mechanical accelerometer

It is shown in feedback and control systems textbooks that the transfer function is

(19.21)

For simplicity, let us assume that the constants and conditions are such that after substitution into(19.21), this relation reduces to

(19.22)

and the force applied is where is the unit step function. The model under those

conditions is shown in Figure 19.32, and the input and output waveforms are shown in Figure19.33.

Figure 19.32. Model for the system of Figure 19.31

x

Spring

Block

Mass

Dashpot

D

k

M

A cc el er at io n a=

G s( ) x a ⁄ =

G s( ) 1

s2

D M ⁄ ( )+ s k M ⁄ +--------------------------------------------------=

G s( ) 1

s2

0.1s 0.2+ +----------------------------------=

0.8u0 t( ) u0 t( )


20/32


21/32


Feedback Control Systems

Figure 19.35. Simplified representation for the system of Figure 19.33

To find the overall transfer function , observe that

or

Dividing both sides by we obtain

and thus

Therefore, the block diagram of Figure 19.34can be replaced with only one block in an open−loop

form as shown in Figure 19.36.

Figure 19.36. The system of Figure 19.33 in an open−loop form

A feedback control system in the form of the feedback path shown as in Figure 19.37 is referred to

as a feedback control system in canonical form. For the system of Figure 19.37, the ratio is

(19.23)

Figure 19.37. Canonical form of a feedback control system

X Y1

s a+( ) s b+( )---------------------------------

E

−+

G s( ) Y X ⁄ =

Y 1

s a+( ) s b+( )-------------------------------E

1

s a+( ) s b+( )------------------------------- X Y–[ ]= =

Y 1

s a+( ) s b+( )-------------------------------Y+

1

s a+( ) s b+( )-------------------------------X=

Y s a+( ) s b+( )

s a+( )

s b+( )

------------------------------- 1

s a+( )

s b+( )

-------------------------------Y+ 1

s a+( )

s b+( )

-------------------------------X=

s a+( ) s b+( )

s a+( ) s b+( )Y Y+ X=

s a+( ) s b+( ) 1+[ ]Y X=

G s( ) Y

X----

1

s a+( ) s b+( ) 1+----------------------------------------= =

1

s a+( ) s b+( ) 1+-------------------------------------------X Y

Y X ⁄

Y

X

---- G

1 GH±

------------------=

X

H

Y

R

EG+

+−


22/32



More complicated block diagrams can be reduced by methods described in Feedback and ControlSystems textbooks. For instance, the block diagram of Figure 19.38 below,

Figure 19.38. Feedback control system to be simplified to an open−loop system

can be replaced with the open−loop system of Figure 19.39.

Figure 19.39. Open-loop equivalent control system for the closed−loop system of Figure 19.38

We can prove that the systems of Figures 19.37 and 19.38 are equivalent with Simulink blocks.The system of Figure 19.38 is represented by the model in Figure 19.40 and there is no need torepresent it as an open−loop equivalent. Instead, we can represent it as the subsystem shown inFigure 19.41.

Figure 19.40. A complicated feedback control system

1

s 1+-----------

3s 5+

s3

15+

-----------------

4

s 2+-----------

7

s2

3+

--------------

2s 1+

s2

3s 2+ +

--------------------------

12s

+ + ++ +

+

−

+ −

X Y

G1

G2 G3

G4

H2

H1

0.5

s4

4+

-------------

G1

G2

G3

G4

G1

G2

G4

H1

– G2

G4

H1

G2

G3

G4

H2

+ + +

1 G1

G2

H1

– G2

H1

G2

G3

H2

+ +

-----------------------------------------------------------------------------------------------------------------------X Y


23/32


Models for Electrical Systems

Figure 19.41. The model of Figure 19.40 replaced by a Subsystem block

19.7 Models for Electrical Systems

In this section we will draw two models for mechanical systems. Subsection 19.7.1 presents anelectric circuit whose output voltage is determined by application of Thevenin’s theorem, andSubsection 19.7.2 presents an electric circuit to be analyzed by application of the SuperpositionPrinciple.

19.7.1 Model for an Electric Circuit in Phasor* Form

By application of Thevenin’s theorem, the electric circuit of Figure 19.42 can be simplified† to

that shown in Figure 19.43.

Figure 19.42. Electric circuit to be replaced by its Thevenin equivalent

Figure 19.43. The circuit of Figure 19.42 replaced by its Thevenin equivalent

* A phasor is a rotating vector. Phasors are used extensively in the analysis of AC electric circuits. For a thoroughdiscussion on phasors, please refer to Circuit Analysis I with MATLAB Applications, ISBN 0-9709511-2-4.

† For a step-by-step procedure, please see same reference.

170 0° V∠

85 Ω

50 Ω

100 Ω

j200 Ω

IX

j100– Ω

VTH = 110− j6.87 V

100 Ω

j10.6 ΩX

Y

112 Ω


24/32



Next, we let , , , and . Application of the volt-

age division expression yields

(19.24)

Now, we use the model of Figure 19.44 to convert all quantities from the rectangular to the polarform, perform the addition and multiplication operations, display the output voltage in both polarand rectangular forms, and show the output voltage on a Scope block in Figure 19.45. The Sim-ulink blocks used for the conversions are in the Math Operations library.

Figure 19.44. Model for the computation and display of the output voltage for the circuit of Figure 19.43

Figure 19.45. Waveform for the output voltage of model of Figure 19.44

VIN VTH= VOU T VX Y= Z1 112 j 10+= Z2 100=

VOU TZ2

Z1 Z2+------------------VIN=


25/32


Models for Electrical Systems

19.7.2 Model for the Application of the Superposition Principle

We will create a model to illustrate the superposition principle by computing the phasor voltage

across capacitor in the circuit of Figure 19.46.

Figure 19.46. Electric circuit to illustrate the superposition principle

Let the phasor voltage across due to the current source acting alone be denoted as

, and that due to the current source as . Then, by the superposition principle,

With the current source acting alone, the circuit reduces to that shown in Figure 19.47.

Figure 19.47. Circuit of Figure 7.45 with the current source acting alone

By application of the current division expression, the current through is

The voltage across with the current source acting alone is

Next, with the current source acting alone, the circuit reduces to that shown in Figure

19.48.

C2

10 0° A∠5 0° A∠4 Ω

j– 6 Ω

2 Ω

8 Ω

j3 Ω

j– 3 Ω C2C1

LR 2

R 1R 3

C2 5 0° A∠

V'C2 10 0° A∠

V''C2

VC2 V 'C2 V ''C2+=

5 0° A∠

V 'C2

5 0° A∠4 Ω

j– 6 Ω

R 1

C1

R 2

2 Ω

L

j3 Ω

8 Ω R 3

j– 3 ΩC2

5 0° A∠

I 'C2 C2

I 'C24 j6–

4 j6– 2 j3 8 j3–+ + +-------------------------------------------------------5 0°∠

7.211 56.3°–∠

15.232 23.2°–∠------------------------------------- 5 0°∠ 2.367 33.1°–∠= = =

C2 5 0°∠

V 'C2 j3–( ) 2.367 33.1°–∠( ) 3 90°–∠( ) 2.367 33.1°–∠( )= =

7.102 123.1°–∠ 3.878– j5.949–==

10 0° A∠


26/32



Figure 19.48. Circuit with the current source acting alone

and by application of the current division expression, the current through is

The voltage across with the current source acting alone is

Addition of (7.13) with (7.14) yields

or

The models for the computation of and are shown in Figures 19.49 and 19.50 respec-

tively.

Figure 19.49. Model for the computation of

10 0° A∠4 Ω

j– 6 Ω

2 Ω

8 Ω

j3 Ω

j– 3 Ω

C2

V ''C2C1

L

R 3R 1

R 2

10 0° A∠

I ''C2 C2

I ''C24 j6– 2 j3+ +

4 j6– 2 j3 8 j3–+ + +------------------------------------------------------- 10– 0°∠( )=

6.708 26.6°–∠

15.232 23.2°–∠------------------------------------- 10 180°∠ 4.404 176.6°∠==

C2 10 0°∠

V ''C2 j3–( ) 4.404 176.6°∠( ) 3 90°–∠( ) 4.404 176.6°∠( )= =

13.213 86.6∠ 0.784 j13.189+=( )=

VC2 V 'C2 V ''C2+ 3.878– j5.949– 0.784 j13.189+ += =

VC2

3.094– j7.240+ 7.873 113.1°∠= =

V 'C2 V ''C2

V'C2


27/32


Transformations

Figure 19.50. Model for the computation of

The final step is to add with . This addition is performed by the model of Figure 19.51

where the models of Figures 19.49 and 19.50 have been converted to Subsystems 1 and 2 respec-tively.

Figure 19.51. Model for the addition of with

The model of Figure 19.51 can now be used with the circuit of Figure 19.46 for any values of the

impedances .

19.8 Transformations

The conversions from complex to magnitude−angle and magnitude−angle to complex used in theprevious section, can also be performed with the Cartesian to Polar and Polar to Cartesian blocks.Examples are presented in the model of Figure 19.52 where transformations from Cartesian toSpherical and Spherical to Cartesian are shown. The equations used in these transformations areshown in the Block Parameters dialog box for each block.

V''C2

V 'C2 V ''C2

V'C2

V''C2

Z


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Figure 19.52. Transformation examples

Other transformation blocks include Fahrenheit to Celsius, Celsius to Fahrenheit, Degrees toRadians, and Radians to Degrees.

19.9 Another S− Function Example

An S−Function example is presented in Subsection 11.18, Chapter 11, Page 11−44. In this sec-tion, we will present another example.

For semiconductor diodes, the empirical equations describing the temperature coefficient

in as a function of forward current in are

where, for this example,

We begin with the user−defined m−file below which we type in the Editor Window and we save itas diode.m

function dx=diode(t,x,Ifv)%% Model for gold-doped and non-gold-doped diodes% Vf1 = x(1); % Gold-doped diode forward voltage, volts Vf2 = x(2); % Non-gold-doped diode forward voltage, volts

dVF dT ⁄ mV °C ⁄ IF mA

dVF1

dT------------ 0.6 10 Iff ( ) 1.92–log= for gold doped diodes

dVF1

dT------------ 0.33 10 Iff Ifv–( ) 1.66–log= for non g– old doped diodes

Iff final value of forward current=

Ifv variable value of forward current=


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Another S− Function Example

Iff = 100; % Iff = final value in of forward current in mA dVf1 = 0.6*log10(Iff)-1.92;dVf2 = 0.33*log10(Iff-Ifv)-1.66; % Ifv = variable value of forward current in mA dx = [dVf1;dVf2];

To test this function for correctness, on MATLAB’s Command Window we type and execute thecommand

[t,x,Ifw]=ode45(@diode, [0 10], [1;10],[ ], 50)

where the vector [0 10] specifies the start and the end of the simulation time, the vector [1;10]specifies an initial value column vector, the null vector [ ] can be used for other options, and theinput value is set to 50.

Next, using the Editor Window we write the m−file below and we save it as diode_sfcn.m

function [sys,x0,str,ts]=...

diode_sfcn(t,x,u,flag,Vf1init,Vf2init) switch flag

case 0 % Initialize

str = []; ts = [0 0];

s = simsizes;

s.NumContStates = 2; s.NumDiscStates = 0; s.NumOutputs = 2;

s.NumInputs = 1; s.DirFeedthrough = 0; s.NumSampleTimes = 1;

sys =simsizes(s);

x0 = [Vf1init,Vf2init];

case 1 % Derivatives

Ifw = u

sys = diode(t,x,Ifw);

case 3 % Output

sys = x;

case {2 4 9} % 2:discrete

% 3:calcTimeHit % 9:termination sys = [];

otherwise


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error(['unhandled flag =',num2str(flag)]);

end

The syntax for the diode_sfcn.m file above is the same as that of Example 11.14, Chapter 11,Page 11−44.

Next, we open a new model window, from the User−

Defined Functions Library we drag an S−

Function block into it, we double−click this block, in the Function Block Parameters dialog boxwe name it diode_sfcn, and we add and interconnect the other blocks shown in Figure 19.53.

Figure 19.53. Another example illustrating the construction of an S−Function block

The waveforms displayed by the Scope 1 and Scope 2 blocks are shown in Figures 19.54 and 19.55respectively.

Figure 19.54. Waveform displayed by the Scope 1 block in the model of Figure 19.53


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Concluding Remarks

Figure 19.55. Waveform displayed by the Scope 2 block in the model of Figure 19.53

19.10 Concluding Remarks

This text, as its title indicates, is an introduction to Simulink. In Chapters 2 through 18 we havedescribed all blocks of all Simulink Libraries and provided examples to illustrate their application.Chapter 1 and this chapter provided additional examples. This text is not a substitute for the Sim-ulink User’s Manual which provides much more information on MATLAB and Simulink, andshould be treated as a supplement. Moreover, the demos provided with Simulink are real−worldexamples and should be studied in thoroughly after reading this text. Undoubtedly, new MAT-LAB and Simulink releases will include new functions and new blocks.


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19.11 Summary

• An analog−to−digital conversion (ADC) application with an Idealized ADC Quantizer blockwas presented in Section 19.1.

• Examples of using Zero−Order Hold and First−Order Hold blocks as reconstructors for digital-

to-analog conversion were presented in Section 19.2.

• The four forms of digital filter realization forms were presented in Section 19.3.

• Models for binary counters were presented in Section 19.4.

• Three models for mechanical systems were presented in Section 19.5.

• A brief review of feedback control systems was provided in Section 19.6.

• Two models for AC electric circuit analysis were presented in Section 19.7.

• Four transformations blocks were introduced in Section 19.8.• An S−Function example was presented in Section 11.18, Chapter 11. Another example was

given in Section 19.9, this chapter.

bab19 - engineering applications

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