USN 06ELN15/25

uFig.Q3(c)

B) feedback resistor C) base resistor D) none oftheseindependent of temperature variation or variation in transistor

E

I

-^t

.9.\

"ob

'.o

,,:

E=

z

oE

Basic ElectronicsTime: 3 hrs- Max. Marks:100

Note: 1. Answer any FIW full queslions, choosing at least two from each part.2. Answer all objective type questions only in OMR sheet page 5 of the answer booklet.3. Answer to objective 4)pe questions on sheels other than OMR will not be valued

PART _ AI a. Choose the corect answers for the following : (01 Mark)

i) Forward cut-in voltage ofSilicon diode is

A) 0.3 V B) 0.2 V c) 0.6 v D) 0.8 Vii) A Zener diode can be used as

A) regulator B) rectifier C) amplifier D) oscillatoriii) The ripple factor of half wave rectifier is _. A) 0.48 B) 0,64 C) 0.81 D) l.2liv) A semiconductor has _ temperature coefficient ofresistance.

A) positive B) negative C) neutral D) none ofthese(0,1Markr)(06 Mark)

Load current 11 : 20 mA;(06 Mark)

(01Nlark)D) fourD) zero

D) none ofthese

DC input voltage V; : 20 V ; DC output voltage V" : l0 V;

A) not biased B) revetse biased C) forward biasediv) Common collector arrangement can be used for _ application.

A) high liequency B; audio frequency C) irnpedance matching D) none oftheseb. Explain the input, output and curent gain characteristics of common base configuration and also explain the

concept of punch through. (08 Mark)c. Define Q-point and DC load line. For the circuit sho\4'n in Fig.Q2(c), draw DC loadline and Mark Q-point.

Assume p : 100, neglect VsE. (08 Mark)

First/Second Semester B.E. Degree Examination, June/July 2013

b. Explain the V-l characteristics ofa Silicon diode.c. Explain the circuit of full wave rectifier and show that ripple factor is 0.48.d. Design a Zener diode voltage regulator to meet the following specifications:

Minimum Zener current l,n,i": l0mA; Maximum Zener cunent 1,,"* = l00mA

2 a. Choose the correct answers for the following:i) A transistor has PNjunctions. A)one B)tuo C) three

ii) The value of'cr' is equal to A). 1 B) > I C) I

iii) ln the active region ofCE amplifier th6base emitterjunction is

V". : j o1/ ^ - V..= ,.4 Y

?, :5rr lSaKtL )9.1

3 a. Choose the correct answers for the following : . - i.. (04 Marks)

i) The most commonly used transistor configuration is circuit.A) CB B) CC C) CE ,.D)

BC

Fig.Q2(c)

ii) The best method oftransistor bras rs

A) selfbiasiii) Stabilization means making

parameters.A) knee point

b.

c-

B) operating point C) threshold point D) none oftheseiv) tfthe operating point changes it results in

A) thennal runway B) unfaithful amplification C) faithful amplification D) punch throughState the need for biasing and explain different t)?es ofbiasing with relevant diagrams and equations.(08 Mark)Determine Is, Vs. V6 and V6E for the circuit shown in Fig.Q3(c). and assume Vee = 0.7 V.

1of2

(08 Mark) .

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4a.

d.

8a.

A) 360" B) e0"

B) increases

A) (324)8

ii) UJT has junctions. A) one B) two C) three D) fouriii) The anode ofthe SCR is always maintained at potential with respect to cathode.

Choose the correct answers for the following :

i) FET is controlled device. A) current

A) zero B) negative C) positiveiv) JFET is transistor.

A) bipolar B) unipolar C) tripolarExplain the basic principle ofoperation of SCR taking ofthe two transistor analogy.Explain UJT as rela\ation oscillator.Explain the drain and transfer characteristics ofn-channel JFET.

PART _ BChoose the correct answers for the lollowing :

.i) The input and output voltages ofsingle stage CE transistor amplifier are

06ELN15/25(04 MArk)

B) voltage C) bandwidth D) power

D) none ofthese

D) none ofthese(04 Mark)(0t Mark)(08 Marks)

(0{ Mark)

c) r 80"out ofphase.

D) 4s"

b.

c.

d.

b.c.

d.

ii) .The negative voltage leedback

-

the gain of an amplifier.A) decreases C) remains same as D) none

iii) ln phase shift oscillator, generally _ RC stages are used.

A) one B) two C) three D) four

C) both +ve and -ve D) none oftheseiv) Oscillator employs _ feedback.

A) negative B) positiveExplain two stage RC coupled amplifier with i1s iiequency response. (08 Marks)

Derive an equation for inpu! and output impedance ofvoltage series negative feedback amplifier. (06 }turks)

In RC phase sh ift oscillator R = 5 kQ and C : 0. I trtF. Calculate frequency of oscillation. (02 Marks)

Choose the correct answers lor the follor.ring ;

i) The CMRR of an ideal OP-AMP is A) finite B) infinite C) zero

ii) Slew rate of an OPAMP is given bydV

B) ______rr. dI.

iii) An ideal OP-AMP charactqistics do not change withA) pressure B) power C) liequency

iii) (283)ro:(?)8

c) 8l.lB) (64)10 C) (90)roB) (433)8 C) (4s6)s

D) temperature

(0:t Markr)(06 Markt)(06 Marks)

(0,, Mark)

D) 95.sD) (53)roD) (402)8

(02 Marks)

(06 \'lark!)

(04 Marks)

C) A D)A+BD)A

D) A+ D

D) NOR gate

(01 Mark!)D) none ofthese

dID) ------L

clV

(0,1 Mark)(06 Marks)

(06 Mflrks)

dIo, ;,dVc) ------gdr

b.

c.

d.

b.

c.

iv) The heart ofCRO is A) CRT B) electron gun C) deflecting plates D) screen

List the ideal characteristics ofan OP-AMP.Draw the circuit ofOPAMP as summff and derive an expression for output voltage.Explain the block diagram ofCRO.

Choose the corect answers for the following :

i) lfm = l, the sidebands carry % ofAM wave power.B) 46.6A) 33.3

ii) (1l0l0l), = ( ? ),0 A) (34),0

iv) 2's complement ofbinary number 101I is-. A) ll00 Bl 0l0l C)0110 Dll0l0Derive an expression for the instantaneous value ofan AM signal in terms ofcarrier and sjdeband frequencies.

(08 Mark)A l5 kHz audio signal is used to frequency modulate a 100 MHz carrier causing a carier deviation of75 kHz.Determine modulation index.i) Convert ( 1024.625)10 = ( ? )z ii) Convert (ABCD) 16 = ( ? ).:( ? )tiii) Subtract (l I l0l)2 tom ( I l0l0), using 2's complement method.

Choose the correct answers for the following :

i) Absorption property states that A + AB = B) B+AA) A+Bii) ldempotent property states that A.A A) A B) I

iii) AB+ABC+ABD:_. A)ABC B)A+B C)iv) The output is high, when all the inputs are high, such gate is called

A) NOT gate _ _B) AND gate

Prove that ABC + ABC + ABC = AB + AC .

C) NAND gate

Realize full adder circuit using logic gates and write its truth table.

Simplif the following expression and implement using NAND gates only.

A=(A+(BCXA+B+axA +B)

c)0AB

b.c.

d.

2 of 2

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