EECL 309B VHDL

Behavioral Modeling

Spring 2014 Semester

VHDL Design Styles

Components andinterconnects

structural

VHDL Design Styles

dataflow

Concurrent statements

behavioral

• Registers• Shift registers• Counters• State machines

Sequential statements

synthesizable

Behavioral Design/Modelling

• Functional performance is the goal of behavioral modeling• Timing optionally included in the model• Software engineering practices should be used to develop

behavioral models• Sequential, inside a process• Just like a sequential program• The main character is ‘process(sensitivity

list)’

3

Anatomy of a Process

• The process statement is a concurrent statement , which delineates a part of an architecture where sequential statements are executed.

• Syntax [label:] process [(sensitivity list )] declarations begin sequential statements end process [label];

PROCESS with a SENSITIVITY LIST

• List of signals to which the process is sensitive.

• Whenever there is an event on any of the signals in the sensitivity list, the process fires.

• Every time the process fires, it will run in its entirety.

• WAIT statements are NOT ALLOWED in a processes with SENSITIVITY LIST.

label: process (sensitivity list) declaration part begin

statement part end process;

Concurrent VS sequential

• Every statement inside the architecture body is executed concurrently, except statements enclosed by a process.

• Process– Statements within a process are executed sequentially.

Result is known when the whole process is complete.– You may treat a process as one concurrent statement in

the architecture body.– Process(sensitivity list): when one or more signals in the

sensitivity list change state, the process executes once.– Process should either have sensitivity list or an explicit

wait statement. Both should not be present in the same process statement.

6

Process contd..

• The order of execution of statements is the order in which the statements appear in the process

• All the statements in the process are executed continuously in a loop .

• The simulator runs a process when any one of the signals in the sensitivity list changes.

• For a wait statement, the simulator executes the process after the wait is over.

Example of Process with/without wait

process (clk,reset)begin if (reset = ‘1’) then A <= ‘0’; elsif (clk’event and clk = ‘1’) then A <= ‘B’; end if;end process;

processbegin if (reset = ‘1’) then A <= ‘0’ ; elsif (clk’event and clk = ‘1’) then A <= ‘B’; end if; wait on reset, clk;end process;

Let’s Write a VHDL Model of Full Adder using Behavioral Modeling

ENTITY full_adder ISPORT ( A, B, Cin : IN BIT; Sum, Cout : OUT BIT );

END full_adder;

ENTITY full_adder ISPORT ( A, B, Cin : IN BIT; Sum, Cout : OUT BIT );

END full_adder;

A

B

Cin

Sum

Cout

Full Adder Architecture

A B Cin Sum Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

for Sum:Cin (I.e. Carry In):

A B 0 10 0 0 10 1 1 01 1 0 11 0 1 0

for Cout (I.e. Carry Out):Cin (I.e. Carry In)

A B 0 10 0 0 00 1 0 11 1 1 11 0 0 1

Two Full Adder Processes

A

B

Cin

Sum

Cout

Summation:PROCESS( A, B, Cin)BEGIN Sum <= A XOR B XOR Cin;END PROCESS Summation;

Summation:PROCESS( A, B, Cin)BEGIN Sum <= A XOR B XOR Cin;END PROCESS Summation;

Carry:PROCESS( A, B, Cin)BEGIN Cout <= (A AND B) OR (A AND Cin) OR (B AND Cin);END PROCESS Carry;

Carry:PROCESS( A, B, Cin)BEGIN Cout <= (A AND B) OR (A AND Cin) OR (B AND Cin);END PROCESS Carry;

Complete ArchitectureARCHITECTURE example OF full_adder IS -- Nothing needed in declarative block...BEGIN

Summation: PROCESS( A, B, Cin) BEGIN Sum <= A XOR B XOR Cin; END PROCESS Summation;

Carry: PROCESS( A, B, Cin) BEGIN Cout <= (A AND B) OR (A AND Cin) OR (B AND Cin); END PROCESS Carry;

END example;

ARCHITECTURE example OF full_adder IS -- Nothing needed in declarative block...BEGIN

Summation: PROCESS( A, B, Cin) BEGIN Sum <= A XOR B XOR Cin; END PROCESS Summation;

Carry: PROCESS( A, B, Cin) BEGIN Cout <= (A AND B) OR (A AND Cin) OR (B AND Cin); END PROCESS Carry;

END example;

VHDL Sequential Statements• Assignments executed sequentially in processes• Sequential statements

– {Signal, variable} assignments– Flow control

• IF <condition> THEN <statements> [ELSIF <statements] [ELSE <statements>] END IF;

• FOR <range> LOOP <statements> END LOOP;• WHILE <condition> LOOP <statements> END LOOP;• CASE <condition> IS WHEN <value> => <statements>

{WHEN <value> => <statements>}[WHEN others => <statements>]

END CASE;– WAIT [ON <signal>] [UNTIL <expression>] [FOR <time>] ;– ASSERT <condition> [REPORT <string>] [SEVERITY <level>] ;

• Syntax

if condition1 then statements [elsif condition2 then statements] [else statements] end if;• An if statement selects one or none of a sequence of

events to execute . The choice depends on one or more conditions.

Priority

The if statement

• If statements can be nested.

if sel = ‘1’ then c <= a;else c <= b;end if;

if (sel = “00”) then o <= a;elsif sel = “01” then x <= b;elsif (color = red) then y <= c;else o <= d;end if;

The if statement contd.

• If statement generates a priority structure

• If corresponds to when else concurrent statement.

Alternate Carry Process

Carry: PROCESS( A, B, Cin) BEGIN

IF ( A = ‘1’ AND B = ‘1’ ) THEN Cout <= ‘1’; ELSIF ( A = ‘1’ AND Cin = ‘1’ ) THEN Cout < = ‘1’; ELSIF ( B = ‘1’ AND Cin = ‘1’ ) THEN Cout <= ‘1’; ELSE Cout <= ‘0’; END IF; END PROCESS Carry;

Carry: PROCESS( A, B, Cin) BEGIN

IF ( A = ‘1’ AND B = ‘1’ ) THEN Cout <= ‘1’; ELSIF ( A = ‘1’ AND Cin = ‘1’ ) THEN Cout < = ‘1’; ELSIF ( B = ‘1’ AND Cin = ‘1’ ) THEN Cout <= ‘1’; ELSE Cout <= ‘0’; END IF; END PROCESS Carry;

Priority Encoder

• All signals which appear on the left of signal assignment statement (<=) are outputs e.g. y, z

• All signals which appear on the right of signal assignment statement (<=) or in logic expressions are inputs e.g. w, a, b, c

• All signals which appear in the sensitivity list are inputs e.g. clk

• Note that not all inputs need to be included in the sensitivity list

priority: PROCESS (clk)BEGIN

IF w(3) = '1' THENy <= "11" ;

ELSIF w(2) = '1' THEN y <= "10" ;

ELSIF w(1) = c THENy <= a and b;

ELSEz <= "00" ;

END IF ;END PROCESS ;

wa

y

zpriorit

ybc

clk

BEHAVIORAL ( Processes using signals)

Sig2 = 1

Sig1 = 2 + 3 = 5

Sig3 = 2

Sum = 1 + 2 + 3 = 6

BEHAVIORAL ( Processes using Variables)

var1 = 2 + 3 = 5

var2 = 5

var3 = 5

Sum = 5 + 5 + 5 = 15

Loop, While & For Statement

Syntax

[label:] loop{sequential_statement}end loop [label]; Syntax

[label:] while condition loop{sequential_statement}end loop [label]; Syntax

[label:] for identifier in discrete_range loop

{sequential_statement}end loop [label];

For Loops

Add Function

WHILE LOOP :

Syntax :loop_label: while condition loop<sequence of statements>end loop loop_label

Statements are executed continuously as long as condition is true.

Has a Boolean Iteration Scheme. Condition is evaluated before execution.

Example: A square wave generation

The case statement - syntax

case expression is when choice 1 => statements when choice 3 to 5 => statements when choice 8 downto 6 => statements when choice 9 | 13 | 17 => statements when others => statementsend case;

The case statement

• The case statement selects, for execution one of a number of alternative sequences of statements .

• Corresponds to with select in concurrent statements .

• Case statement does not result in prioritized logic structure unlike the if statement.

process(sel, a, b, c, d)begin case sel is when “00” => dout <= a; when “01” => dout <= b; when “10” => dout <= c; when “11” => dout <= d; when others => null; end case;end process;

process (count)begin case count is when 0 => dout <= “00”; when 1 to 15 => dout <= “01”; when 16 to 255 => dout <= “10”; when others => null; end case;end process;

The case statement contd.

Think Hardware! (Mutually exclusive conditions)

This priority is useful for timings.

myif_pro: process (s, c, d, e, f) begin if s = "00" then pout <= c; elsif s = "01" then pout <= d; elsif s = "10" then pout <= e; else pout <= f; end if;end process myif_pro;

Think Hardware! Use a case for mutually exclusive things

mycase_pro: process (s, c, d, e, f) begin case s is when "00" => pout <= c; when "01" => pout <= d; when "10" => pout <= e; when others => pout <= f; end if; end process mycase_pro;

C

D

E

F

S

POUT

There is no priority with case.

Use of others All the choices in case statement must be enumerated The choices must not overlap If the case expression contains many values, the others is usable

entity case_ex1 is port (a: in integer range 0 to 30; q: out integer range 0 to 6);end;architecture bhv of case_ex1 isbegin p1: process(a) begin case a is when 0 => q<=3; when 1 | 2 => q<=2; when others => q<=0; end case; end process;end;

Multiple assignment - examples architecture rtl of case_ex8 is

begin p1: process (a) begin case a is when “00” => q1<=“1”; q2<=‘0’;

q3<=‘0’; when “10” => q1<=“0”; q2<=‘1’;

q3<=‘1’; when others => q1<=“0”; q2<=‘0’;

q3<=‘1’; end case; end process;end;

architecture rtl of case_ex9 isbegin p1: process (a) begin q1<=“0”; q2<=‘0’; q3<=‘0’; case a is when “00” =>q1<=“1”; when “10” =>q2<=‘1’;

q3<=‘1’; when others =>q3<=‘1’; end case; end process;end;

Null statement

null_statement::=[ label : ] null ;

The null - statement explicitly prevents any action from being carried out. This statement means “do nothing”. This command can, for example, be used if default signal assignments have

been used in a process and an alternative in the case statement must not change that value.

Null statement - example

architecture rtl of ex isbegin p1: process (a) begin q1<=“0”; q2<=‘0’; q3<=‘0’; case a is when “00” => q1<=“1”; when “10” => q2<=‘1’;

q3<=‘1’; when others => null; end case; end process;end;

Wait statement wait_statement::=

     [ label : ] wait [ sensitivity_clause ]    [ condition_clause ]    [ timeout_clause ] ;

Examples: wait ; The process is permanently interrupted. wait for 5 ns ; The process is interrupted for 5 ns. wait on sig_1, sig_2 ; The process is interrupted until the value of one of the

two signals changes. wait until clock = '1' ; The process is interrupted until the value of clock is 1.

Wait statement in a process There are three ways of describing a wait statement in a process:

process (a,b)wait until a=1wait on a,b;wait for 10 ns;

The first and the third are identical, if wait on a,b; is placed at the end of the process:

p0: process (a, b)

begin

if a>b then

q<=‘1’;else q<=‘0’;end if;

end process;

p1: process

begin

if a>b then

q<=‘1’;else q<=‘0’;end if;

wait on a,b;

end process;

Features of the wait statement

In the first example the process will be triggered each time that signal a or b changes value (a’event or b’event)

Wait on a,b; has to be placed at the end of the second example to be identical with the first example because all processes are executed at stat-up until they reach their first wait statement.

That process also executed at least once, which has sensitivity list and there is no changes in the values of the list members

If a wait on is placed anywhere else, the output signal’s value will be different when simulation is started.

If a sensitivity list is used in a process, it is not permissible to use a wait command in the process.

It is permissible, however, to have several wait commands in the same process.

Details of the wait’s types Wait until a=‘1’; means that, for the wait condition to be satisfied and

execution of the code to continue, it is necessary for signal a to have an event, i.e. change value, and the new value to be ‘1’, i.e. a rising edge for signal a.

Wait on a,b; is satisfied when either signal a or b has an event (changes value). Wait for 10 ns; means that the simulator will wait for 10 ns before continuing

execution of the process. The starting time point of the waiting is important and not the actual changes of any

signal value. It is also permissible to use the wait for command as follows:

constant period:time:=10 ns;wait for 2*period;

The wait alternatives can be combined into: wait on a until b=‘1’ for 10 ns;, but the process sensitivity list must never be combined with the wait alternatives

Example: wait until a=‘1’ for 10 ns;The wait condition is satisfied when a changes value or after a wait of 10 ns (regarded as an or condition).

Examples of wait statement

Example 1process (a)begin c1<= not a;end process;

type a: in bit; c1, c2, c3, c4, c5, c6, c7: out bit;

Example 2processbegin c2<= not a; wait on a;end process;

Example 3processbegin wait on a; c3<= not a;end process;

Example 4processbegin wait until a=‘1’; c4<= not a;end process;

Example 5processbegin c5<= not a; wait until a=‘1’;end process;

Example 6processbegin c5<= not a; wait for 10 ns;end process;

Example 7processbegin c5<= not a; wait until a=‘1’ for 10 ns;end process;

Simulation results

10 20 30 40 6050 time [ns]

A

C1

C2

C3

C4

C6

10 ns 20 ns

C7

C5

Wait statement in synthesis tools

Synthesis tools do not support use of wait for 10 ns;. This description method produces an error in the synthesis.

The majority of synthesis tools only accept a sensitivity list being used for combinational processes, i.e. example 1, but not example 2, can be synthesized.

But some advanced systems accept example 2, while example 3 is not permitted in synthesis.

Example 4 is a clocked process and results in a D-type flip-flop after synthesis. Examples 3 and 5 can only be used for simulation, and not for design. The wait command is a sequential command, it is not permissible to use wait

in functions, but it can be used in procedures and processes.

Behavioral Description of a 3-to-8 Decoder

Except for different syntax, approach is not all that different from the dataflow version

Attributes

• Value kind—A simple value is returned.• Function kind—A function call is performed to

return a value.• Signal kind—A new signal is created whose value is

derived from another signal.• Type kind—A type mark is returned.• Range kind—A range value is returned.

Array Attributes

A can be either an array name or an array type.

Array attributes work with signals, variables, and constants.

Signal Attributes

Attributes associated with signals that return a value

A’event – true if a change in S has just occurred

A’active – true if A has just been reevaluated, even if A does not change

Review: Signal Attributes (cont’d)

Attributes that create a signal

Example of D flip flop using s’EVENT

1. LIBRARY IEEE;

2. USE IEEE.std_logic_1164.ALL;

3. ENTITY dff IS

4. PORT( d, clk : IN std_logic;

5. PORT( q : OUT std_logic);

6. END dff;

7. ARCHITECTURE dff OF dff IS

8. BEGIN

9. PROCESS(clk)

10. BEGIN

11. IF ( clk = ’1’) AND ( clk’EVENT ) THEN

12. q <= d;

13. END IF;

14. END PROCESS;

15. END dff;

Timing Model

• VHDL uses the following simulation cycle to model the stimulus and response nature of digital hardware

Delay

Start Simulation

Update Signals Execute Processes

End Simulation

Delay Types

• All VHDL signal assignment statements prescribe an amount of time that must transpire before the signal assumes its new value

• This prescribed delay can be in one of three forms: Transport -- prescribes propagation delay only Inertial -- prescribes propagation delay and minimum input pulse width Delta -- the default if no delay time is explicitly specified

Inputdelay

Output

Transport Delay

• Transport delay must be explicitly specified I.e. keyword “TRANSPORT” must be used

• Signal will assume its new value after specified delay

Input Output

0 5 10 15 20 25 30 35

Input

Output

-- TRANSPORT delay exampleOutput <= TRANSPORT NOT Input AFTER 10 ns;

Inertial Delay

• Provides for specification propagation delay and input pulse width, i.e. ‘inertia’ of output:

• Inertial delay is default and REJECT is optional:

Input

Output

0 5 10 15 20 25 30 35

Input Output

target <= [REJECT time_expression] INERTIAL waveform;

Output <= NOT Input AFTER 10 ns;-- Propagation delay and minimum pulse width are 10ns

Inertial Delay (cont.)

• Example of gate with ‘inertia’ smaller than propagation delay e.g. Inverter with propagation delay of 10ns which suppresses

pulses shorter than 5ns

• Note: the REJECT feature is new to VHDL 1076-1993

Input

Output

0 5 10 15 20 25 30 35

Output <= REJECT 5ns INERTIAL NOT Input AFTER 10ns;

Delta Delay

• Default signal assignment propagation delay if no delay is explicitly prescribed VHDL signal assignments do not take place immediately Delta is an infinitesimal VHDL time unit so that all signal

assignments can result in signals assuming their values at a future time

E.g.

• Supports a model of concurrent VHDL process execution Order in which processes are executed by simulator does not

affect simulation output

Output <= NOT Input;-- Output assumes new value in one delta cycle

Transport and Inertial Delay

Simulation Example

D f/f WITH PRESET AND CLEAR1. ENTITY dtype IS

2. PORT(clk, d, clr, pre : IN std_logic;

3. q, n_q : OUT std_logic);

4. END dtype;

5. ARCHITECTURE behav OF dtype IS

6. SIGNAL temp_q : std_logic; -- internal signal

7. BEGIN

8. PROCESS (clk, clr, pre)

9. BEGIN

10. IF clr = ‘1’ THEN -- clear operation

11. temp_q <= ‘0’;

12. ELSIF pre = ‘1’ THEN -- preset operation

13. temp_q <= ‘1’;

14. ELSIF clk’EVENT AND clk = ‘1’ THEN -- clock

15. temp_q <= d;

16. END IF;

17. END PROCESS;

18. q <= temp_q;

19. n_q <= NOT temp_q;

20. END behav;