RTL Synthesis Based on Hardware Description Languages

Franco Franco FummiFummiDipartimentoDipartimento di di InformaticaInformatica

UniversitàUniversità di Veronadi Veronafranco.fummi@univr.itfranco.fummi@univr.it

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Course overview

�� IntroductionIntroduction�� VLSI designVLSI design�� Modeling aspectsModeling aspects�� Design elementsDesign elements

�� VHDL syntaxVHDL syntax�� Main characteristicsMain characteristics�� Advanced featuresAdvanced features

�� SpecificationSpecification�� OrganizationOrganization�� VerificationVerification

�� Complex exampleComplex example�� PartitioningPartitioning

�� DesignDesign

�� SimulationSimulation�� Time modelTime model

�� ComparisonsComparisons

�� SynthesisSynthesis�� Combinational blocksCombinational blocks

�� Sequential blocksSequential blocks

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VLSI Design

�� VLSI increasing complexityVLSI increasing complexity

�� “Time to market”“Time to market”

Structural DesignStructural Design

Algorithmic DesignAlgorithmic Design

Hardware Description LanguagesHardware Description Languages44

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Software versus Hardware Design

AlgorithmAlgorithm

TT

MBMB

MHMHzz

GateGate

ArchitectureArchitecture

AlgorithmAlgorithm

PrePre--defined defined Virtual MachineVirtual Machine

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Example: GCD modeled in C

#i ncl ude <st di o. h>

i nt gcd( i nt x i , i nt y i ){

i nt x, y, t emp;

x = xi ;y = yi ;whi l e ( x > 0) {

i f ( x <= y) {t emp = y;y = x ;x = t emp;

}x = x - y;

}r et ur n( y) ;

}

mai n( ){

i nt x i , y i , ou;

scanf ( " %d %d" , &x i , &yi ) ;ou = gcd( xi , y i ) ;pr i nt f ( " %d\ n" , ou) ;

}

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Hardware requirements (1)

�� Input /OutputInput /OutputSS pr i nt fpr i nt f , , scanfscanf . . .. . .

HH component interface must be definedcomponent interface must be defined

�� TimingTimingSS CPU instructions are executed at the CPU clock CPU instructions are executed at the CPU clock

speedspeed

HH one or more explicit CLOCK signals must be one or more explicit CLOCK signals must be defineddefined

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Hardware requirements (2)

�� Variables sizeVariables sizeSS hidden implicit definition (integer 4bytes, char hidden implicit definition (integer 4bytes, char

1byte, …)1byte, …)

HH all preall pre--defined and userdefined and user--defined types must be defined types must be translated into bit vectorstranslated into bit vectors

�� Relationships operands/operatorsRelationships operands/operatorsSS allall operators in the C libraries are acceptedoperators in the C libraries are accepted

HH explicit mapping of operands on operatorsexplicit mapping of operands on operators

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Hardware requirements (3)

�� Memory elements identificationMemory elements identificationSS the optimization module of the compiler the optimization module of the compiler

transparently maps variables onto CPU transparently maps variables onto CPU registers and memory elementsregisters and memory elements

HH the synthesis tool identifies memory elements the synthesis tool identifies memory elements by analyzing the algorithmic semanticsby analyzing the algorithmic semantics

�� Modules synchronizationModules synchronizationSS sequential execution of instructionssequential execution of instructions

HH inherently parallel execution of all componentsinherently parallel execution of all components

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Entity/Architecture

GCDGCDYIYI

XIXIOUOU

CLOCKCLOCK RESETRESET

ENTI TY gcd I SPORT ( c l ock, r eset : I N bi t ;

x i , y i : I N unsi gned ( s i ze- 1 DOWNTO 0) ;ou : OUT unsi gned ( si ze- 1 DOWNTO 0)

) ;END gcd;

variable sizevariable size1010

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Example: GCD modeled in VHDL

ARCHI TECTURE behavi or al OF gcd I SBEGI N

PROCESSVARI ABLE x, y, t emp : unsi gned ( si ze- 1 DOWNTO 0) ;

BEGI NWAI T UNTI L c l ock = ' 1' ;x : = xi ;y : = yi ;WHI LE ( x > 0) LOOP

I F ( x <= y) THENt emp: =y;y : = x;x: =t emp;

END I F;x : = x - y;

END LOOP;ou <= y;END PROCESS;

END behavi or al ;

timingtiming

memoriesmemories

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�� Identification of a Identification of a targettarget architecturearchitecture�� FSM + DataFSM + Data--Path (FSMD)Path (FSMD)

�� Identification of time instants for each Identification of time instants for each operation:operation:�� time ordertime order�� time lengthtime length

�� Identification of operators:Identification of operators:�� data sizedata size�� time performancestime performances

Algorithmic (Behavioral) Synthesis

schedulingscheduling

allocationallocation

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FSMD Model

PRIMARY INPUTS

CLOCK

CONTROLUNIT(FSM)

ELABORATIONUNIT

(Data-path)

RESET

PRIMARY OUTPUTS

CONTROL SIGNALS

CONDITION SIGNALS

FSMD

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Scheduling (FSM)

ARCHI TECTURE behavi or al OF gcd I SBEGI N

PROCESSVARI ABLE x, y , t emp : unsi gned ( s i ze- 1 DOWNTO 0) ;

BEGI NWAI T UNTI L c l ock = ' 1' ;x : = x i ;y : = y i ;WHI LE ( x > 0) LOOP

I F ( x <= y) THENt emp: =y;y : = x;x: =t emp;

END I F;x : = x - y ;

END LOOP;ou <= y;END PROCESS;

END behavi or al ;

S1S1

S0S0

S2S2

S3S3

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Allocation (Data-Path)

ARCHI TECTURE behavi or al OF gcd I SBEGI N

PROCESSVARI ABLE x, y , t emp : unsi gned ( s i ze- 1 DOWNTO 0) ;

BEGI NWAI T UNTI L c l ock = ' 1' ;x : = x i ;y : = y i ;WHI LE ( x > 0) LOOP

I F ( x <= y) THENt emp: =y;y : = x;x: =t emp;

END I F;x : = x - y ;

END LOOP;ou <= y;END PROCESS;

END behavi or al ;

CLOCK

nD

nQ

reg

S

n n

nO

muxm

A1 2mA

. . .0...0 1...1

A

B nOn

n+

A

B

On

n>

A

B

On

n<=

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Register Transfer Level (RTL)

�� Interconnection of FSM + DataInterconnection of FSM + Data--pathpath�� control/condition signals are identifiedcontrol/condition signals are identified

�� FSM is represented by states and transitionsFSM is represented by states and transitions

�� DataData--path is represented by registers, path is represented by registers, multiplexers and operatorsmultiplexers and operators

�� Automatic translation into a set of registers Automatic translation into a set of registers and library components (RTL)and library components (RTL)

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Logic Synthesis

�� Each RTL module is optimized by means of:Each RTL module is optimized by means of:�� areaarea�� delaydelay�� powerpower

�� Efficient synthesis algorithms exist for:Efficient synthesis algorithms exist for:�� twotwo--level synthesislevel synthesis�� multiplemultiple--level synthesislevel synthesis

�� A logic representation of each RTL module A logic representation of each RTL module is generated and optimizedis generated and optimized

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General synthesis flow

Behavioral VHDLBehavioral VHDL

VHDL RTLVHDL RTL

VHDL GateVHDL Gate

HighHigh--level synthesislevel synthesis

Logic synthesisLogic synthesis

Physical synthesisPhysical synthesistesting

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VHDL and Modeling Aspects

�� The elements of the TOPThe elements of the TOP--DOWN design DOWN design methodology can be identified asmethodology can be identified as

�� ABSTRACTION ABSTRACTION

�� HIERARCHY HIERARCHY

�� MODULARITY MODULARITY

�� REUSABILITY REUSABILITY

�� EFFICIENCYEFFICIENCY

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VHDL Modeling Aspects

�� ABSTRACTIONABSTRACTION�� Today Top Down Design refers to the practice Today Top Down Design refers to the practice

of using a Hardware Description Language to of using a Hardware Description Language to capturecapture the functionality of a design at an the functionality of a design at an abstract level.abstract level.

�� An abstraction will group details (in a module) An abstraction will group details (in a module) that describe the function of design unit but that describe the function of design unit but does not describe how the design unit is does not describe how the design unit is implemented.implemented.

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VHDL Modeling Aspects

�� ABSTRACTIONABSTRACTION�� The primary abstraction level of a VHDL The primary abstraction level of a VHDL

hardware model is the design entity, which can hardware model is the design entity, which can represent a cell, a chip, a board, or subsystems.represent a cell, a chip, a board, or subsystems.�� Entity Entity

�� Architecture Architecture

�� Design description methods: Design description methods: �� Behavioral Behavioral �� highhigh--abstraction level abstraction level

�� Data flow and Structural Data flow and Structural �� lower abstraction levels.lower abstraction levels.

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VHDL Modeling Aspects

Design Entity

structural

data flow

behavioral

Architecture Body

Entity Declaration This term is used with This term is used with different meaningsdifferent meanings

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VHDL Modeling Aspects

�� ABSTRACTIONABSTRACTION�� Design Description Methods: behavioralDesign Description Methods: behavioral

�� Functional behavior of an hardware design in terms Functional behavior of an hardware design in terms of signals and responses to various stimuli. of signals and responses to various stimuli.

�� Algorithmic description with no underlying Algorithmic description with no underlying structure.structure.

�� Constructs:Constructs:�� PROCESS PROCESS

�� PROCEDUREPROCEDURE VARIABLE VARIABLE

�� FUNCTIONFUNCTION

behavioral

Architecture Body

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VHDL Modeling Aspects

�� ABSTRACTIONABSTRACTION�� Design description methods: data flowDesign description methods: data flow

�� Definition of the design functionality through the Definition of the design functionality through the information flow from inputs to outputs by means of information flow from inputs to outputs by means of arithmetic and logical relations. arithmetic and logical relations.

�� Concurrent execution of the defined relations.Concurrent execution of the defined relations.

�� Constructs:Constructs:�� BLOCK BLOCK

�� PROCEDUREPROCEDURE SIGNAL SIGNAL

�� FUNCTIONFUNCTION

Data-flow

Architecture Body

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VHDL Modeling Aspects

�� ABSTRACTIONABSTRACTION�� Design description methods: structuralDesign description methods: structural

�� Topological description of the interconnection of Topological description of the interconnection of components for realizing the circuit functionality components for realizing the circuit functionality completely detached from the components' completely detached from the components' functionality.functionality.

�� Constructs:Constructs:�� COMPONENT declaration COMPONENT declaration

�� COMPONENT instantiation COMPONENT instantiation

�� CONFIGURATIONCONFIGURATION

Structural

Architecture Body

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VHDL Modeling Aspects

�� ABSTRACTION (behavioral example)ABSTRACTION (behavioral example)ENTI TY ex_adder I S

PORT( op1, op2, car r y i n: I N bi t ; out put , car r yout : OUT bi t ) ;

END ex_adder ;ARCHI TECTURE beh_ar c OF ex_adder I SBEGI N

PROCESS ( op1, op2, car r y i n)var i abl e r esul t : i nt eger r ange 0 t o 3 : = 0;

BEGI Nr esul t : = bi t _t o_i nt eger ( op1) + bi t _t o_i nt eger ( op2)

+ bi t _t o_i nt eger ( car r y i n) ;out put <= bool ean_t o_bi t ( ( r esul t mod 2) =1) ;car r yout <= bool ean_t o_bi t ( r esul t > 1) ;

END PROCESS ;END beh_ar c ;

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VHDL Modeling Aspects

�� ABSTRACTION (dataABSTRACTION (data--flow example)flow example)

ARCHI TECTURE s t r _dat af l ow OF ex_adder I S

SI GNAL t mp1, t mp2, t mp3: bi t ;

BEGI N

t mp1 <= op1 XOR op2;

out put <= t mp1 XOR car r y i n af t er 1ns ;

t mp2 <= op1 AND op2;

t mp3 <= t mp1 AND car r y i n af t er 1ns ;

car r yout <= t mp2 OR t mp3 af t er 2ns ;

END st r _ar c ;

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VHDL Modeling Aspects

�� ABSTRACTION (structural example)ABSTRACTION (structural example)ARCHI TECTURE s t r _ar c OF ex_adder I S

COMPONENT hal f _add I SPORT( i n1, i n2: I N bi t ;

out , car r y: OUT bi t ) ;END COMPONENT ;COMPONENT or _gat e I S

PORT( a, b: I N bi t ;o: OUT bi t ) ;

END COMPONENT ;SI GNAL t mp1, t mp2, t mp3: bi t ;

BEGI NI 1: hal f _add PORT MAP ( op1, op2, t mp1, t mp2) ;I 2: hal f _add PORT MAP ( t mp2, car r y i n, t mp3, out put ) ;I 3: or _gat e PORT MAP ( t mp1, t mp3, car r yout ) ;

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VHDL Modeling Aspects

�� ABSTRACTIONABSTRACTION�� Example:Example:

�� A A Read Only MemoryRead Only Memory device is described at a high device is described at a high

level as a series of address locations with level as a series of address locations with

corresponding data bytes stored in each location corresponding data bytes stored in each location

�� no care about address lines, data lines, or control linesno care about address lines, data lines, or control lines

�� focus on the data byte assignments to selected addresses focus on the data byte assignments to selected addresses

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VHDL Modeling Aspects

�� ABSTRACTIONABSTRACTION�� In the lowerIn the lower--level module, it is possible to level module, it is possible to

describe how each signal on the ROM pins describe how each signal on the ROM pins must be configured to read or program each must be configured to read or program each data storage locationdata storage location�� To change the data stored in a given location go to To change the data stored in a given location go to

the higherthe higher--level module and modify the hex value level module and modify the hex value associated with an address rather than redefine the associated with an address rather than redefine the states of many data linesstates of many data lines

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VHDL Modeling Aspects

�� ABSTRACTION (ABSTRACTION (ROM exampleROM example))

Description of Address, Data, and

Control Signals

Description of Addressable Bytesof Storage

Lower AbstractionLevels

Higher AbstractionLevels

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VHDL Modeling Aspects

�� ABSTRACTIONABSTRACTION

�� Information HidingInformation Hiding

�� Complements abstraction Complements abstraction

�� Focuses the attention of the designer on relevant Focuses the attention of the designer on relevant

information information

�� the extracting of the functional details from a given the extracting of the functional details from a given

module and masking of the implementation detailsmodule and masking of the implementation details

�� Protects proprietary informationProtects proprietary information

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VHDL Modeling Aspects

�� HIERARCHYHIERARCHY�� Approach of Approach of splittingsplitting an initial, complex an initial, complex

problem into simpler, more manageable subproblem into simpler, more manageable sub--problems that can be worked out separately to problems that can be worked out separately to achieve a solution to the initial problem.achieve a solution to the initial problem.

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VHDL Modeling Aspects

�� HIERARCHYHIERARCHY�� Design PartitioningDesign Partitioning

�� Related to the problem of defining a hierarchy to handle the Related to the problem of defining a hierarchy to handle the design process within the methodologydesign process within the methodology

�� Starting point:Starting point: behavioral description of the behavioral description of the entire deviceentire device

�� Target:Target: description identifying elements, which description identifying elements, which properly connected perform the same global properly connected perform the same global functionalityfunctionality�� Concurrent decomposition Concurrent decomposition �� Sequential decompositionSequential decomposition

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VHDL Modeling Aspects

�� HIERARCHY HIERARCHY -- PARTITIONINGPARTITIONING�� How to do the partitioning ? How to do the partitioning ?

�� There is no defined methodologyThere is no defined methodology�� Designer experienceDesigner experience

�� HintsHints: : �� Identification of operations to be performedIdentification of operations to be performed

�� control path & data path control path & data path

�� Behavioral SpecificationBehavioral Specification

�� Simulation Simulation

�� Synthesis to get an idea of used elementsSynthesis to get an idea of used elements

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VHDL Modeling Aspects

�� HIERARCHY HIERARCHY -- PARTITIONINGPARTITIONING

�� Subprograms Subprograms -- functions and proceduresfunctions and procedures

�� A subprogram allows the user to decompose the A subprogram allows the user to decompose the

hardware description into behavioral descriptions or hardware description into behavioral descriptions or

operations using algorithms for computing values.operations using algorithms for computing values.

�� In a TOPIn a TOP--DOWN approach it is possible to DOWN approach it is possible to

decompose the solution into its primary functions:decompose the solution into its primary functions:

�� highhigh--levellevel: "what happens": "what happens"

�� lowlow--levellevel: "how it happens": "how it happens"

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VHDL Modeling Aspects

�� HIERARCHY HIERARCHY -- PARTITIONINGPARTITIONING

�� SimulationSimulation�� synchronization among elements synchronization among elements

�� data exchange among elementsdata exchange among elements

�� SynthesisSynthesis�� the process may autonomously create a partitioning the process may autonomously create a partitioning

and a hierarchy while processing a VHDL and a hierarchy while processing a VHDL descriptiondescription

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VHDL Modeling Aspects

�� REUSABILITYREUSABILITY

�� The complexity of designed electronic devices The complexity of designed electronic devices

underlines the need to adopt effective methods underlines the need to adopt effective methods

to cut the design timeto cut the design time

�� definition of definition of librarieslibraries of standard cellsof standard cells

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VHDL Modeling Aspects

�� EFFICIENCYEFFICIENCY�� The complexity of developed models results in The complexity of developed models results in

an increased an increased CPU timeCPU time consumed to simulate consumed to simulate themthem

�� This raises the issue of efficiency of VHDL This raises the issue of efficiency of VHDL concepts used for modeling:concepts used for modeling:�� use variable instead of signals whenever possibleuse variable instead of signals whenever possible�� use signal attribute returning a value rather than a use signal attribute returning a value rather than a

signalsignal�� efficient process statementefficient process statement

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VHDL Modeling Aspects

�� DOCUMENTATIONDOCUMENTATION�� VHDL may be used to document a design. VHDL may be used to document a design.

Communication medium Communication medium �� manman--toto--tool tool

�� manman--toto--man man

�� tooltool--toto--tooltool

�� VHDL is used as a VHDL is used as a formatformat

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VHDL Modeling Aspects

�� DOCUMENTATIONDOCUMENTATION�� There is a need for a common representation There is a need for a common representation

format that can be used to represent: format that can be used to represent: �� system specificationsystem specification

�� partial design data generated by various synthesis tools partial design data generated by various synthesis tools

�� synthesis results produced by those cosynthesis results produced by those co--operating toolsoperating tools

�� Format serves as a common foundation Format serves as a common foundation constituting a synthesis environmentconstituting a synthesis environment

An input design specification written in VHDL may be mapped on this foundation, and similarly, the synthesis results may be mapped onto VHDL

from this foundation

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VHDL Description Styles

�� A comparison (1)A comparison (1)�� The behavioral description more generally The behavioral description more generally

constitutes the starting point for the specification of constitutes the starting point for the specification of systems of a relevant complexitysystems of a relevant complexity�� Adopted in the TopAdopted in the Top--Down design methodology Down design methodology

�� Apt for the immediacy of describing in an almost algorithmic Apt for the immediacy of describing in an almost algorithmic way, complex devices, independent of the final implementationway, complex devices, independent of the final implementation

�� High abstraction level High abstraction level

�� Used for validating the correctness of the VHDL description Used for validating the correctness of the VHDL description with respect to the specificationswith respect to the specifications

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VHDL Description Styles

�� A comparison (2)A comparison (2)�� The data flow description requires the knowledge The data flow description requires the knowledge

of the input/output relations, in terms of of the input/output relations, in terms of arithmetical and logical data manipulationarithmetical and logical data manipulation�� The specification provides hints of what the final realization The specification provides hints of what the final realization

will look likewill look like�� Apt for describing DataApt for describing Data--path path

�� The structural description defines the topology of The structural description defines the topology of the circuit in terms of the components constituting the circuit in terms of the components constituting it and of their interconnectionsit and of their interconnections�� Component functionality is not required at this level of Component functionality is not required at this level of

descriptiondescription

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VHDL Description Styles

�� A comparison (3)A comparison (3)�� The adopted description style depends on The adopted description style depends on

several factors, among which: several factors, among which: �� specific knowledge of the device functionality and specific knowledge of the device functionality and

possible (desired) implementation possible (desired) implementation

�� target of the VHDL description target of the VHDL description �� evaluation of alternatives evaluation of alternatives

�� determination of a sound implementation determination of a sound implementation

�� ……

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Structural VHDL

�� Structural style is similar to a Structural style is similar to a netlistingnetlistinglanguage in other CAD systems.language in other CAD systems.

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Components -1

�� Component declaration and instantiation Component declaration and instantiation allow the structural kind of VHDL allow the structural kind of VHDL description.description.

�� Components must be Components must be declareddeclared, , specifiedspecifiedand and instantiatedinstantiated for their use.for their use.

component_declarationcomponent_declaration

componentcomponent component _namecomponent _name

por tpor t ( { names: di r ect i on t ype[ : = expr ess i on] } )( { names: di r ect i on t ype[ : = expr ess i on] } )

end componentend component ;

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Components -2

�� Example:Example:ent i t y ent i t y r sf l opr sf l op i si s

por t ( set , r eset : i n bi t ;por t ( set , r eset : i n bi t ;

q, qbarq, qbar : : i nouti nout bi t ) ;bi t ) ;

end end r sf l opr sf l op;;

ar chi t ect ur e ar chi t ect ur e net l i s tnet l i s t of of r sf l opr sf l op i si s

component nor 2component nor 2

gener i c ( del ay: t i me) ;gener i c ( del ay: t i me) ;

por t ( a, b: i n bi t ; c: out bi t ) ;por t ( a, b: i n bi t ; c: out bi t ) ;

end component ;end component ;

… … … … … …

begi nbegi n

… … … … … …

end end net l i s tnet l i s t ;;

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Components -3

�� The component configuration statement allows the The component configuration statement allows the specification of the selected architecture related to specification of the selected architecture related to the declared component.the declared component.

�� If no architecture is specified, the If no architecture is specified, the defaultdefaultarchitecture is selected.architecture is selected.

configuration_specificationconfiguration_specification

f or f or names: comp_name names: comp_name use ent i t yuse ent i t y ent _name( ar ch_nameent _name( ar ch_name) ;) ;

�� Local names after the Local names after the FORFOR statement specify the statement specify the number of instantiated components.number of instantiated components.

�� Example:Example:f or u1, u2: nor 2 use ent i t y f or u1, u2: nor 2 use ent i t y nor _gat e( dat af l ownor _gat e( dat af l ow) ;) ;

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Components -4

component_instantiationcomponent_instantiation

l abell abel : : component _name component _name por t mappor t map( [ named| posi t i onal ] ) ;( [ named| posi t i onal ] ) ;

�� Example:Example:U1: nor 2 gener i c map ( 10. 2 ns)U1: nor 2 gener i c map ( 10. 2 ns)

por t map( r eset , por t map( r eset , qbar _i nt , q_i ntqbar _i nt , q_i nt ) ;) ;

por t map( b => por t map( b => qbar _i ntqbar _i nt , c => , c => q_i ntq_i nt , a => r eset ) ;, a => r eset ) ;

�� The local port names (reset, The local port names (reset, qbar_intqbar_int, , q_intq_int) are ) are put in relation with the formal names (a, b, c).put in relation with the formal names (a, b, c).

�� The generic value 10.2 ns overrides the default The generic value 10.2 ns overrides the default value 5.0 ns.value 5.0 ns.

positionalpositional

namednamed

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Components -5

�� Example:Example:ar chi t ect ur e ar chi t ect ur e net l i s tnet l i s t of of r sf l opr sf l op i si s

… … … … … …

f or u1, u2: nor 2 use ent i t y f or u1, u2: nor 2 use ent i t y nor _gat e( dat af l ownor _gat e( dat af l ow) ;) ;

s i gnal s i gnal q_i ntq_i nt , , qbar _i ntqbar _i nt : bi t ;: bi t ;

begi nbegi n

U1: nor 2 U1: nor 2

gener i c map ( 10. 2 ns)gener i c map ( 10. 2 ns)

por t map( r eset , por t map( r eset , qbar _i nt , q_i ntqbar _i nt , q_i nt ) ;) ;

U2: nor 2U2: nor 2

gener i c map ( 10. 3 ns)gener i c map ( 10. 3 ns)

por t por t map( q_i ntmap( q_i nt , set , , set , qbar _i ntqbar _i nt ) ;) ;

q <= q <= q_i ntq_i nt ;;

qbarqbar <= <= qbar _i ntqbar _i nt ;;

end end net l i s tnet l i s t ;;

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Dataflow VHDL

�� A set of VHDL statements is concurrently A set of VHDL statements is concurrently executed whenever they are placed into an executed whenever they are placed into an architecture body.architecture body.

�� There are different versions of the same statement There are different versions of the same statement if it is executed concurrently or sequentially.if it is executed concurrently or sequentially.

�� Concurrent statements are:Concurrent statements are:�� Signal assignmentSignal assignment

�� Conditional signal assignmentConditional signal assignment

�� Selected signal assignmentSelected signal assignment

�� Instantiation statementInstantiation statement

�� Block statementBlock statement

�� Procedure callProcedure call

�� Assertion statementAssertion statement

�� Process statementProcess statement

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Signal Assignment -1

signal_assignmentsignal_assignment

si gnal _namesi gnal _name <= val ue;<= val ue;

�� Examples:Examples:ar chi t ect ur e pr obe of ar chi t ect ur e pr obe of hal f adderhal f adder i si s

begi nbegi n

sum <= a sum <= a xorxor b;b;

car r y <= a and b;car r y <= a and b;

end pr obe;end pr obe;

�� Array values assignment:Array values assignment:bus_out ( 4) <= dat a( 5) ;bus_out ( 4) <= dat a( 5) ;

r ot at e_si g( 7: 0) : = s i g( 0: 7) ;r ot at e_si g( 7: 0) : = s i g( 0: 7) ;

sum <= a sum <= a xorxor b af t er 5 ns;b af t er 5 ns;

car r y <= a and b af t er 10 ns ;car r y <= a and b af t er 10 ns ;

Wi t h or wi t hout del ays :Wi t h or wi t hout del ays :

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Signal Assignment -2

�� AggregationAggregation�� Positional association:Positional association:

SI GNAL z_bus : bi t _vec t or ( 3 DOWNTO 0) ;SI GNAL z_bus : bi t _vec t or ( 3 DOWNTO 0) ;

SI GNAL a_bi t , b_bi t , c_bi t , d_bi t : bi t ;SI GNAL a_bi t , b_bi t , c_bi t , d_bi t : bi t ;

… … … … … …

z_bus <= ( a_bi t , b_bi t , c_bi t , d_bi t ) ;z_bus <= ( a_bi t , b_bi t , c_bi t , d_bi t ) ;

�� Named association:Named association:z_bus <= ( 2 => b_bi t , 1 => c_bi t , 0 => d_bi t ; 3 => a_bi t ) ;z_bus <= ( 2 => b_bi t , 1 => c_bi t , 0 => d_bi t ; 3 => a_bi t ) ;

�� Others keyword:Others keyword:z_bus <= ( 3 DOWNTO 2 => ' 1' , OTHERS => ' 0' ) ;z_bus <= ( 3 DOWNTO 2 => ' 1' , OTHERS => ' 0' ) ;

z_bus <= ( OTHERS => ' 1' ) ;z_bus <= ( OTHERS => ' 1' ) ;

z_bus <= ( 2 => b_bi t , 1 => c_bi t , 0 => d_bi t ; 3 => a_bi t ) ;z_bus <= ( 2 => b_bi t , 1 => c_bi t , 0 => d_bi t ; 3 => a_bi t ) ;

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Conditional Signal Assignment-1

conditional_assignmentconditional_assignment

si gnal _name <= expr ess i on_1 WHEN condi t i on_1 ELSEsi gnal _name <= expr ess i on_1 WHEN condi t i on_1 ELSE

expr essi on_2 WHEN condi t i on_2 ELSEexpr essi on_2 WHEN condi t i on_2 ELSE

… … … … … …

expr essi on_N;expr essi on_N;

�� equivalent to equivalent to IF / THEN / ELSE / END IFIF / THEN / ELSE / END IF�� Each condition is a Each condition is a booleanboolean expression.expression.�� The expression of the The expression of the firstfirst TRUE condition is assigned.TRUE condition is assigned.�� There must be There must be alwaysalways an ELSE expression,an ELSE expression,�� The expression may be delayed.The expression may be delayed.

a <= ' 1' AFTER 2 ns WHEN b = ' 0' ELSEa <= ' 1' AFTER 2 ns WHEN b = ' 0' ELSE

' 0' AFTER 3 ns;' 0' AFTER 3 ns;

5454

Fummi

Conditional Signal Assignment-2

�� Example:Example:

ENTI TY t r i _s t at e I SENTI TY t r i _s t at e I S

PORT( bi t _1, en_1, en_2: I N s t d_l ogi c;PORT( bi t _1, en_1, en_2: I N s t d_l ogi c;

bus_1: I N st d_l ogi c_vect or ( 0 TO 7) ;bus_1: I N st d_l ogi c_vect or ( 0 TO 7) ;

t r i _bi t : OUT st d_l ogi c ;t r i _bi t : OUT st d_l ogi c ;

t r i _bus : OUT st d_l ogi c_vect or ( 0 TO 7) ) ;t r i _bus : OUT st d_l ogi c_vect or ( 0 TO 7) ) ;

END t r i _st at e;END t r i _st at e;

ARCHI TECTURE condi t i on OF t r i _st at e I SARCHI TECTURE condi t i on OF t r i _st at e I S

BEGI NBEGI N

t r i _bi t <=t r i _bi t <= bi t _1 WHEN en_1 = ' 1' ELSE ' Z' ;bi t _1 WHEN en_1 = ' 1' ELSE ' Z' ;

t r i _bus <= t r i _bus <= bus_1 WHEN en_2 = ' 1' ELSE ( OTHERS => ' Z' ) ;bus_1 WHEN en_2 = ' 1' ELSE ( OTHERS => ' Z' ) ;

END condi t i on;END condi t i on;

5555

Fummi

Behavioral VHDL

�� Describe an architecture in a programDescribe an architecture in a program--like style.like style.

�� Process statementProcess statement

�� A set of VHDL statements is sequentially A set of VHDL statements is sequentially executed whenever they are placed into process.executed whenever they are placed into process.

�� Signal assignmentSignal assignment

�� Variable assignmentVariable assignment

�� WaitWait

�� Procedure callProcedure call

�� Function callFunction call

�� BranchesBranches

�� Control flowControl flow

�� Assertion writes messagesAssertion writes messages

NOTE: underlined statements are also concurrent statements.NOTE: underlined statements are also concurrent statements.5656

Fummi

Variable Declaration

variable_declarationvariable_declaration

var i abl evar i abl e names: t ype[names: t ype[ range_constraintrange_constraint] [ : = expr essi on] ;] [ : = expr essi on] ;

var i abl evar i abl e names: ar r ay_t ype[ (names: ar r ay_t ype[ ( index_constraintindex_constraint) ] [ : =expr essi on] ;) ] [ : =expr essi on] ;

�� Declaration examples:Declaration examples:var i abl e sum : r eal ;var i abl e sum : r eal ;

var i abl e vol t age : i nt eger : = 0;var i abl e vol t age : i nt eger : = 0;

var i abl e c l ock : bi t : = ’ 1’ ;var i abl e c l ock : bi t : = ’ 1’ ;

var i abl e dat a : var i abl e dat a : s t d_ul ogi cs t d_ul ogi c ; ;

�� Arrays:Arrays:var i abl e dat a_bus : bi t _vect or ( 0 t o 7) : = " 11111111" ;var i abl e dat a_bus : bi t _vect or ( 0 t o 7) : = " 11111111" ;

var i abl e i nput s : var i abl e i nput s : st d_ul ogi c_vect orst d_ul ogi c_vect or ( 15 ( 15 downt odownt o 0) ;0) ;

initial value?initial value?

ScalarScalar

ArrayArray

5757

Fummi

Signals and Variables -1

�� Declaration place:Declaration place:

�� Signals can be declared only between the Signals can be declared only between the ARCHITECTUREARCHITECTURE statement and its statement and its BEGINBEGIN(declarative part of the architecture).(declarative part of the architecture).

�� Variables can be declared only between the Variables can be declared only between the PROCESSPROCESS statement and its statement and its BEGINBEGIN(declarative part of the process).(declarative part of the process).

�� Default value:Default value:

�� Both objects assume the leftBoth objects assume the left--most or minimum most or minimum value of the corresponding type.value of the corresponding type.

5858

Fummi

Signal vs.VariableAssignment-1

�� Signal and variable assignments are performed by Signal and variable assignments are performed by using different symbols to emphasize the different using different symbols to emphasize the different meaning of the two objects.meaning of the two objects.

variable_assignmentvariable_assignment

var i abl e_name : = val ue;var i abl e_name : = val ue;

signal_assignmentsignal_assignment

si gnal _name : = val ue;si gnal _name : = val ue;

�� Note that the assignment of the initial value to a Note that the assignment of the initial value to a

signal uses the same symbol of variable signal uses the same symbol of variable

assignment.assignment.

5959

Fummi

Signal vs.VariableAssignment-2

�� The main difference is the nature of the The main difference is the nature of the assignment:assignment:�� Signal assignment Signal assignment → concurrent statementconcurrent statement�� Variable assignment Variable assignment → sequential statementsequential statement

�� Such a difference implies some other differences:Such a difference implies some other differences:�� Variables can be assigned only in the sequential part of Variables can be assigned only in the sequential part of

a VHDL description (into a process statement)a VHDL description (into a process statement)�� Signals can be assigned in the sequential or concurrent Signals can be assigned in the sequential or concurrent

part.part.

�� A variable assignment takes effect A variable assignment takes effect immediatelyimmediately!!�� A signal assignment may depend on a A signal assignment may depend on a delaydelay..

6060

Fummi

Signal vs.VariableAssignment-3

var _exvar _ex : PROCESS: PROCESS

VARI ABLE VARI ABLE num, sum: I NTEGERnum, sum: I NTEGER: =0;: =0;

BEGI NBEGI N

WAI T FOR 20 ns;WAI T FOR 20 ns;

num : = num + 1;num : = num + 1;

sum : = sum + num;sum : = sum + num;

END PROCESS END PROCESS var _exvar _ex ;;

SI GNAL num, sum: I NTEGER: =0;SI GNAL num, sum: I NTEGER: =0;

si g_exsi g_ex : PROCESS: PROCESS

BEGI NBEGI N

WAI T FOR 20 ns;WAI T FOR 20 ns;

num <= num <= numnum + 1;+ 1;

sum <= sum + num;sum <= sum + num;

END PROCESS END PROCESS si g_exsi g_ex ;;

• The two processes are apparently equal, but …• Do they produce the same result?

• NO! Signals and variables are updated at different times.

6161

Fummi

Process -1

�� It is a concurrent statement that delineates a It is a concurrent statement that delineates a set of sequentially executed statements.set of sequentially executed statements.

process_statementprocess_statement

[ l abel : ] [ l abel : ] pr ocesspr ocess [ ( sensi t i v i t y_l i st ) ][ ( sensi t i v i t y_l i st ) ]

[ decl ar at i ons][ decl ar at i ons]

begi nbegi n

sequent i al _s t at ement ssequent i al _s t at ement s

end pr ocessend pr ocess [ l abel ] ;[ l abel ] ;

6262

Fummi

Process -2

�� The The sensitivity listsensitivity list is a list of signals. The is a list of signals. The change of one or more of such signals change of one or more of such signals causes the process to be activated.causes the process to be activated.

�� Alternatively the WAIT statement may Alternatively the WAIT statement may control the execution of a process.control the execution of a process.

�� The The sensitivity listsensitivity list and the and the WAITWAIT statement statement are mutually exclusive.are mutually exclusive.

6363

Fummi

Process -3

�� Both processes show the same behavior.Both processes show the same behavior.

�� Signals in the sensitivity list help the reader to understand Signals in the sensitivity list help the reader to understand the behavior of the process.the behavior of the process.

�� Multiple WAIT statements may represent a more complex Multiple WAIT statements may represent a more complex behavior.behavior.

wai t _st y l e_pr ocwai t _st y l e_pr oc : PROCESS: PROCESS

I F (I F ( al ar m_tal ar m_t = = cur r ent _tcur r ent _t ) ) THENTHEN

sound <= ' 1' ;sound <= ' 1' ;

ELSEELSE

sound <= ' 0' ;sound <= ' 0' ;

WAI T on WAI T on al ar m_tal ar m_t , , cur r ent _tcur r ent _t ;;

END PROCESS END PROCESS wai t _st y l e_pr ocwai t _st y l e_pr oc

�� ComparisonComparisonsens_l i st _st y l e_pr ocsens_l i st _st y l e_pr oc ::PROCESS (PROCESS ( al ar m_tal ar m_t , , cur r ent _tcur r ent _t ))

I F (I F ( al ar m_tal ar m_t = = cur r ent _tcur r ent _t ) ) THENTHEN

sound <= ' 1' ;sound <= ' 1' ;ELSEELSE

sound <= ' 0' ;sound <= ' 0' ;END PROCESS;END PROCESS;

6464

Fummi

Process -3

�� Execution:Execution:

�� Every process is executed once in the Every process is executed once in the initialization phase.initialization phase.�� a process based on the sensitivity list runs until its a process based on the sensitivity list runs until its

last instruction;last instruction;

�� a process based on the wait keyword runs until the a process based on the wait keyword runs until the first wait.first wait.

�� A process is restarted when a signal in the A process is restarted when a signal in the sensitivity list or in the wait statement changes.sensitivity list or in the wait statement changes.

6565

Fummi

Process -4

�� A process is considered as a A process is considered as a UNIQUEUNIQUEconcurrent operation.concurrent operation.

�� Signals of a process are all updated at the Signals of a process are all updated at the end of the process execution.end of the process execution.

�� All internal operations are sequentially All internal operations are sequentially executed, thus only sequential operators can executed, thus only sequential operators can be used.be used.

6666

Fummi

Wait -1

�� Provides the control of the process execution.Provides the control of the process execution.wai twai t ;;

�� suspends a process indefinitely (useful in test benches).suspends a process indefinitely (useful in test benches).wai t f orwai t f or t i me;t i me;

�� suspends a process for time units (useful in test benches suspends a process for time units (useful in test benches and behavioral models).and behavioral models).

wai t onwai t on si gnal _l i st ;s i gnal _l i st ;

�� suspends a process until a change occurs on one or more of suspends a process until a change occurs on one or more of the signals in the list (it is equivalent to the sensitivity listhe signals in the list (it is equivalent to the sensitivity list).t).

wai t unt i lwai t unt i l condi t i on;condi t i on;

�� suspends a process until a change occurs on one or more of suspends a process until a change occurs on one or more of the signals in the condition and it evaluates to TRUE.the signals in the condition and it evaluates to TRUE.

6767

Fummi

Wait -2

�� Examples:Examples:d_f f _1 : pr ocessd_f f _1 : pr ocessbegi nbegi n

wai t unt i lwai t unt i l cl k ' eventcl k ' event and and c l kc l k=' 1' ;=' 1' ;q <= d;q <= d;

end pr ocess d_f f _1 ;end pr ocess d_f f _1 ;

d_f f _2 : pr ocess begi nd_f f _2 : pr ocess begi ni f i f c l kcl k=' 1' t hen=' 1' t hen

q <= d;q <= d;end i f ;end i f ;wai t onwai t on cl kcl k ;;

end pr ocess d_f f _2 ;end pr ocess d_f f _2 ;

st i mul i : pr ocessst i mul i : pr ocessbegi nbegi n

en_1 <= ' 0' ;en_1 <= ' 0' ;en_2 <= ' 1' ;en_2 <= ' 1' ;wai t f orwai t f or 10 ns;10 ns;en_1 <= ' 1' ;en_1 <= ' 1' ;en_2 <= ' 0' ;en_2 <= ' 0' ;wai t f orwai t f or 10 ns;10 ns;en_1 <= ' 0' ;en_1 <= ' 0' ;wai twai t ;;

end pr ocess st i mul i ;end pr ocess st i mul i ;

semantically equivalent to:semantically equivalent to:wait untilwait until clkclk='1';='1';

6868

Fummi

Branches -1

if_statementif_statementi fi f condi t i on condi t i on t hent hen sequent i al _st at ement ssequent i al _st at ement s{{ el si fel s i f condi t i on condi t i on t hent hen sequent i al _st at ement s}sequent i al _st at ement s}[[ el seel se sequent i al _st at ement s]sequent i al _st at ement s]end i fend i f ;;

�� Example:Example:count er : pr ocess (count er : pr ocess ( c l kcl k , r eset ), r eset )begi nbegi n

i f r eset = ' 1' t heni f r eset = ' 1' t hencount <= ' 0' ;count <= ' 0' ;

el s i fel s i f c l k ' eventc l k ' event and and cl kcl k = ' 1' t hen= ' 1' t heni f count >= 9 t heni f count >= 9 t hen

count <= ' 0' ;count <= ' 0' ;el seel se

count <= count + 1;count <= count + 1;end i f ;end i f ;

end i f ;end i f ;end pr ocess count er ;end pr ocess count er ;

6969

Fummi

Branches -2

case_statementcase_statementcasecase expr ess i on expr ess i on i si s

whenwhen choi cechoi ce-- 1 => sequent i al _st at ement s1 => sequent i al _st at ement s… … … … … … whenwhen choi cechoi ce-- n => sequent i al _st at ement sn => sequent i al _st at ement s

end caseend case;;

�� Equivalent to Equivalent to WITH /SELECTWITH /SELECT

�� ALLALL possible choices must be included, possible choices must be included, RANGERANGE is allowed.is allowed.

�� Choices cannot overlapChoices cannot overlap

�� Example:Example:CASE CASE i nt _ai nt _a I SI S

WHEN 0 => z <= a;WHEN 0 => z <= a;WHEN 1 TO 3 => z <= b;WHEN 1 TO 3 => z <= b;WHEN 2 | 6 | 8 => z <= c;WHEN 2 | 6 | 8 => z <= c;WHEN OTHERS => z <= ' X' ;WHEN OTHERS => z <= ' X' ;

END CASE ;END CASE ;

error !error !

7070

Fummi

Loops

for_statementfor_statement[ l abel : ] [ l abel : ] f orf or i ndex i ndex i ni n r ange r ange l oopl oop

sequent i al _s t at ement ssequent i al _s t at ement send l oopend l oop [ l abel ] ;[ l abel ] ;

�� indexindex is automatically declared as integer and is automatically declared as integer and cannot be modified within the loop.cannot be modified within the loop.

�� rangerange may be an enumerative type.may be an enumerative type.loop_statementloop_statement[ l abel : ] [[ l abel : ] [ whi l ewhi l e condi t i on] condi t i on] l oopl oop

sequent i al _s t at ement ssequent i al _s t at ement send l oopend l oop [ l abel ] ;[ l abel ] ;

�� conditioncondition is tested before each iteration.is tested before each iteration.

7171

Fummi

Control Flow

exit_statementexit_statement

exi texi t [ l abel : ] [[ l abel : ] [ whenwhen condi t i on] ;condi t i on] ;

�� terminates the execution of a while, for, loop.terminates the execution of a while, for, loop.�� exit may be conditioned and it allows the exit from any exit may be conditioned and it allows the exit from any

loop even if it is not the innermost one.loop even if it is not the innermost one.l 1: FOR i I N 0 TO 7 LOOPl 1: FOR i I N 0 TO 7 LOOP

l 2: FOR j I N 0 TO 7 LOOPl 2: FOR j I N 0 TO 7 LOOPEXI T l 1 WHEN qui t _bot h_l oops = ' 1'EXI T l 1 WHEN qui t _bot h_l oops = ' 1'

next_statementnext_statementnextnext [ l abel : ] [[ l abel : ] [ whenwhen condi t i on] ;condi t i on] ;

�� terminates of the current iteration of a while, for, loop.terminates of the current iteration of a while, for, loop.�� it may be conditioned and it allows the termination of an it may be conditioned and it allows the termination of an

iteration of any loop.iteration of any loop.

7272

Fummi

RTL Description Style

�� Useful for:Useful for:�� automatic synthesisautomatic synthesis

�� complete control of the synthesis resultscomplete control of the synthesis results

�� acceptable estimation of structural propertiesacceptable estimation of structural properties

�� test bench generation and reusetest bench generation and reuse

�� DrawbacksDrawbacks�� modeling of details concerning the chosen modeling of details concerning the chosen

architecturearchitecture�� e.g. states of the FSMe.g. states of the FSM

7373

Fummi

RTL GCD Exemplification

ARCHI TECTURE behavi or al OF gcd I SBEGI N

PROCESSVARI ABLE x, y , t emp : unsi gned ( s i ze- 1 DOWNTO 0) ;

BEGI NWAI T UNTI L c l ock = ' 1' ;x : = x i ;y : = y i ;WHI LE ( x > 0) LOOP

I F ( x <= y) THENt emp: =y;y : = x;x: =t emp;

END I F;x : = x - y ;

END LOOP;ou <= y;END PROCESS;

END behavi or al ;

S1S1

S0S0

S2S2

S3S3

7474

Fummi

Finite State Machine Description

�� Characteristics:Characteristics:�� an explicit finite set of states is identifiedan explicit finite set of states is identified

�� at each clock cycle a new state is selectedat each clock cycle a new state is selected

�� at each clock cycle outputs are evaluatedat each clock cycle outputs are evaluated

�� a reset signal put the FSM in the reset statea reset signal put the FSM in the reset state

�� VHDL consideration:VHDL consideration:�� a sequence of operations required a a sequence of operations required a sequential sequential

description styledescription style (e.g. a process)(e.g. a process)

7575

Fummi

Finite State Machine Description

�� Synthesis tool considerations:Synthesis tool considerations:�� there are some templates to describe there are some templates to describe FSMsFSMs

which are recognized by synthesis toolswhich are recognized by synthesis tools

�� each template produces different gateeach template produces different gate--level level implementationsimplementations

�� FSM versus FSMD:FSM versus FSMD:�� complex operations can be inserted into each complex operations can be inserted into each

transition instead of direct input/output transition instead of direct input/output mappingmapping

7676

Fummi

RTL GCD Exemplification

�� Clock synchronization:Clock synchronization:�� behavioral style:behavioral style:PROCESS

VARI ABLE x, y, t emp : I NTEGER;BEGI N

WAI T UNTI L c l ock = ' 1' ;

�� RTL style:RTL style:PROCESS( cl ock, r eset )

VARI ABLE x, y, t emp : UNSI GNED ( SI ZE- 1 DOWNTO 0) ;BEGI N

I F ( c l ock' EVENT AND cl ock = ' 1' ) THENI F ( r eset = ' 1' ) THEN

reset stateELSE

next-state evolutionEND I F;

END I F;END PROCESS;

7777

Fummi

RTL GCD Exemplification

�� States enumeration:States enumeration:PACKAGE gcd_pack I S

CONSTANT SI ZE : I NTEGER : = 8;TYPE st at e_code I S ( S0, S1, S2, S3) ;

END gcd_pack ;. . .PROCESS( cl ock, r eset )

VARI ABLE x, y, t emp : UNSI GNED ( SI ZE- 1 DOWNTO 0) ;VARI ABLE st at e : st at e_code;

BEGI NI F ( c l ock' EVENT AND cl ock = ' 1' ) THEN

I F ( r eset = ' 1' ) THENst at e : = S0;

�� Symbolic states or coded states?Symbolic states or coded states?

7878

Fummi

RTL GCD Exemplification

�� States evolution:States evolution:I F ( c l ock' EVENT AND cl ock = ' 1' ) THEN

I F ( r eset = ' 1' ) THENst at e : = S0;

ELSECASE st at e I SWHEN S0 =>

st at e : = S1;WHEN S1 =>

I F ( condition) THENst at e : = S2;

ELSEst at e : = S3;

END I F;WHEN S2 =>

st at e : = S1;WHEN S3 =>

. . .END CASE;

END I F;END I F;

Equivalent to behavioral Equivalent to behavioral ( WHI LE x > 0) LOOP( WHI LE x > 0) LOOP

behavioral behavioral LOOP exi tLOOP exi t

7979

Fummi

RTL GCD Exemplification

�� Behavioral condition:Behavioral condition:WHI LE ( x > 0) LOOP

�� RTL condition:RTL condition:Integer valuesInteger values

I F ( x > 0) THEN WrongWrong comparison comparison UNSIGNED / integerUNSIGNED / integer

I F ( x > conv_unsi gned( 0, SI ZE) ) THEN

Converts integer to a Converts integer to a vector of vector of st d_l ogi cst d_l ogi cvalues of size values of size SI ZESI ZE

Defined in package Defined in package st d_l ogi c_ar i t h

8080

Fummi

RTL GCD Exemplification

�� Signal initialization:Signal initialization:�� Behavioral levelBehavioral level

�� OUOU is initialized to the default levelis initialized to the default level

�� RTL levelRTL level�� signals initialization implies or not memory signals initialization implies or not memory

elements (elements (see synthesis lecturesee synthesis lecture))

I F ( r eset = ' 1' ) THENst at e : = S0;ou <= ( ot her s => ’ 0’ ) ;

ELSE

Independent on signal sizeIndependent on signal size

8181

Fummi

RTL Simulation

�� Output generation required some clock Output generation required some clock cyclescycles

8282

Fummi

Synthesis Annotation

�� FSMD model is difficult to be automatically FSMD model is difficult to be automatically synthesized:synthesized:

�� synthesis tool does not automatically isolate the synthesis tool does not automatically isolate the

FSM from the dataFSM from the data--pathpath

�� “Ad“Ad--hoc” synthesis algorithms for hoc” synthesis algorithms for FSMsFSMs

cannot be applied cannot be applied �� low optimization levellow optimization level

�� manual separation of FSM from Datamanual separation of FSM from Data--pathpath

8383

Fummi

Synthesis Annotation

�� Identification of control/condition signalsIdentification of control/condition signals

�� Instantiation of two components (FSM + DataInstantiation of two components (FSM + Data--Path)Path)

PRIMARY INPUTS

CLOCK

CONTROLUNIT(FSM)

ELABORATIONUNIT

(Data-path)

RESET

PRIMARY OUTPUTS

CONTROL SIGNALS

CONDITION SIGNALS

FSMD

8484

Fummi

Condition signals

. . .CASE st at e I S

. . .WHEN S1 =>

I F ( x > conv_unsi gned( 0, SI ZE) ) ) THENst at e : = S2;

ELSEst at e : = S3;

END I F;

. . .WHEN S1 =>

I F ( x_cond = ’ 1’ ) THENst at e : = S2;

ELSEst at e : = S3;

END I F;

FSMDFSMDconditioncondition(some bits)(some bits)

FSMFSMcondition condition (1 bit size)(1 bit size)

8585

Fummi

Control signals

. . .CASE st at e I S

. . .WHEN S2 =>

x : = x - y;

. . .WHEN S2 =>

sub_cont r ol <= ’ 1’ ;

FSMDFSMDoperationoperation(some bits)(some bits)

FSMFSMcontrolcontrol(1 bit size)(1 bit size)

�� control signals must be asserted only in such states control signals must be asserted only in such states where the operation must be executedwhere the operation must be executed

�� control signal must be set to ’0’ in all other statescontrol signal must be set to ’0’ in all other states

8686

Fummi

Mixed Level Verification

�� Verification of the RT level descriptionVerification of the RT level description

�� Comparison specification/implementationComparison specification/implementation

�� Hypotheses:Hypotheses:

�� behavioral level specification is correctbehavioral level specification is correct

�� timing aspects are not consideredtiming aspects are not considered

�� an an acceptableacceptable amount of input vectors amount of input vectors

guarantee the correctness of the implementationguarantee the correctness of the implementation

8787

Fummi

Mixed Level Verification

�� Strategy:Strategy:

ENTI TY compar e I S

BEGI N END;

ARCHI TECTURE t est OF compar e

BEGI N

Inputs generationInputs generation

Outputs comparisonOutputs comparison

ENTI TY gcd I S. . .BEGI N END;ARCHI TECTURE r t l OF gcdBEGI N. . .

ENTI TY gcd I S. . .BEGI N END;ARCHI TECTURE behavi or al OF gcdBEGI N. . .

8888

Fummi

Mixed Level Verification

�� Inputs generation:Inputs generation:

�� a process without sensitivity list with one or a process without sensitivity list with one or more more wai twai t statements for each test vectorstatements for each test vector

vect or s_gener at or : PROCESS

BEGI Nr eset <= ’ 0’ ;x i _r t l <= conv_unsi gned( 5, SI ZE) ) ;x i _beh <= conv_unsi gned( 5, SI ZE) ) ;y i _r t l <= conv_unsi gned( 1, SI ZE) ) ;y i _beh <= conv_unsi gned( 1, SI ZE) ) ;wai t f or 1000 ns;. . .

Assumption: RTL module has completed the computationAssumption: RTL module has completed the computation

8989

Fummi

Mixed Level Verification

�� Inputs generation:Inputs generation:

�� the clock signal can be generated by using an the clock signal can be generated by using an “ad“ad--hoc” processhoc” process

ARCHI TECTURE t est OF compar e

SI GNAL cl ock : STD_LOGI C;

BEGI N

. . .c l ock_gener at or : PROCESSBEGI N

cl ock <= ’ 0’ ;wai t f or 25 ns;c l ock <= ’ 1’ ;wai t f or 25 ns;

END PROCESS;. . .

9090

Fummi

Mixed Level Verification

�� Outputs comparison:Outputs comparison:

�� the the correctcorrect specification output is compared to specification output is compared to the possibly wrong implementation outputthe possibly wrong implementation output

vect or s_gener at or : PROCESS

VARI ABLE o_r t l , o_beh: UNSI GNED ( SI ZE- 1 DOWNTO 0) ;

BEGI N. . .wai t f or 1000 ns;o_r t l : = ou_r t l ;o_beh : = ou_beh;ASSERT o_r t l = o_beh

REPORT ” out put s mi smat ch . . . "SEVERI TY er r or ;

. . .

simulation endssimulation ends

9191

Fummi

Mixed Level Verification

�� Multiple test vectors application:Multiple test vectors application:

�� build a textual file with pairs of inputs (build a textual file with pairs of inputs (e.g., 5 1e.g., 5 1))

�� read pairs of inputs and apply themread pairs of inputs and apply themvect or s_gener at or : PROCESS

VARI ABLE i n_l i ne : LI NE;VARI ABLE x1, x2 : I NTEGER;

BEGI Nr eset <= ’ 0’ ;WHI LE NOT ( endf i l e( dat a_i n) ) LOOP

READLI NE ( dat a_i n, i n_l i ne) ;READ ( i n_l i ne, x1) ; READ ( i n_l i ne, x2) ; x i _r t l <= conv_unsi gned( x1, SI ZE) ) ;x i _beh <= conv_unsi gned( x1, SI ZE) ) ;y i _r t l <= conv_unsi gned( x2, SI ZE) ) ;y i _beh <= conv_unsi gned( x2, SI ZE) ) ;. . . 9292

Fummi

Process styles

�� Four styles of processes are envisioned:Four styles of processes are envisioned:�� Processes with a sensitivity list including all read Processes with a sensitivity list including all read

signals and assigning all signals and variables in all signals and assigning all signals and variables in all conditional branches.conditional branches.

�� Processes with a sensitivity list including all read Processes with a sensitivity list including all read signals and assigning all variables in all conditional signals and assigning all variables in all conditional branches.branches.

�� Processes with a wait statement for detecting clock Processes with a wait statement for detecting clock edges.edges.

�� Processes with a sensitivity list including a clock Processes with a sensitivity list including a clock signal and optionally an asynchronous reset signal.signal and optionally an asynchronous reset signal.

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Process “style 1”

�� Processes with a sensitivity list including all read Processes with a sensitivity list including all read signals and assigning all signals and variables in signals and assigning all signals and variables in all conditional branches.all conditional branches.

�� The sensitivity list will contain all the The sensitivity list will contain all the intermediate signalsintermediate signals

�� It models pure combinational logicIt models pure combinational logic

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Process “style 1”

ENTI TY ao I Spor t ( i 0, i 1, i 2: I N BI T;

out 0: OUT BI T) ;END ao;

ARCHI TECTURE r t l OF ao I SSI GNAL r esul t : BI T;

BEGI NPROCESS( i 0, i 1, i 2, r esul t )BEGI N

r esul t <= i 0 AND i 1;out 0 <= r esul t OR i 2;

END PROCESS;END r t l ; Intermediate signalIntermediate signal

If result is not insertedin the sensitivity list thesynthesis would provide(when the tool providesa synthesis) a complex

asynchronous sequentialcircuit with an

event-triggered flip-flop.

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Process “style 1”

�� Signal assignments are updated at the end of the Signal assignments are updated at the end of the process execution.process execution.

�� Therefore Therefore resultresult and and out0out0 are updated at the same are updated at the same time, time, out0out0 accessing the old value of accessing the old value of resultresult..

�� To access the correct value of To access the correct value of resultresult, the process , the process must be remust be re--executed following an update of executed following an update of resultresultto update to update out0out0 to the correct value.to the correct value.This is done by placing the intermediate signal in This is done by placing the intermediate signal in the process sensitivity list.the process sensitivity list.

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Process “style 1”

�� Use of variables would resolve the problem Use of variables would resolve the problem of inserting in the sensitivity list of inserting in the sensitivity list intermediate signals.intermediate signals.

�� Intermediate signals with no other specific Intermediate signals with no other specific functionality are inefficient.functionality are inefficient.

. . .PROCESS( i 0, i 1, i 2)

VARI ABLE r esul t : BI TBEGI N

r esul t : = i 0 AND i 1;out 0 <= r esul t OR i 2;

. . .

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Process “style 2”

�� Processes with a sensitivity list including all Processes with a sensitivity list including all read signals and assigning all variables in read signals and assigning all variables in all conditional branches.all conditional branches.

Model a mixture of pure combinational logic Model a mixture of pure combinational logic and asynchronous latches.and asynchronous latches.

�� Latches are inferred when signals are Latches are inferred when signals are not assigned in a conditional branch.not assigned in a conditional branch.

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Process “style 2”

ent i t y ANDGATE i spor t ( i n1, i n2: i n st d_l ogi c;

out p: out st d_l ogi c) ;end ANDGATE;ar chi t ec t ur e cor r ect of ANDGATE i sbegi n

pr ocess( i n1, i n2)var i abl e x: st d_l ogi c;

begi ni f ( i n1=' 1' ) t hen

x: =i n2;el se

x : = ' 0' ;end i f ;out p <= x;

end pr ocess;end cor r ect ;

AND gate!AND gate!

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Process “style 2”

ent i t y ANDGATE i spor t ( i n1, i n2: i n st d_l ogi c;

out p: out st d_l ogi c) ;end ANDGATE;ar chi t ec t ur e i ncor r ect of ANDGATE i sbegi n

pr ocess( i n1, i n2)var i abl e x: st d_l ogi c;

begi ni f ( i n1=' 1' ) t hen

x: =i n2;end i f ;out p <= x;

end pr ocess;end cor r ect ;

A levelA level--sensitivesensitivelatchlatch

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Process “style 3”

�� Processes with a WAIT statement as the Processes with a WAIT statement as the first statement of a process.first statement of a process.

�� It is a clocked circuit (synchronous It is a clocked circuit (synchronous sequential machine)sequential machine)�� Finite State Machine (FSM) Finite State Machine (FSM)

�� Moore & MealyMoore & Mealy

WAI T UNTI L cl k ’ EVENT and cl k = ‘ 1’

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Process “style 4”

�� Processes with a sensitivity list including a clock Processes with a sensitivity list including a clock signal, and eventually an asynchronous reset signal, and eventually an asynchronous reset signal. An if statement constitutes the process, signal. An if statement constitutes the process, sensitive to the clock (and reset) events.sensitive to the clock (and reset) events.

Pr ocess ( ck_name [ , r eset _name] )begi n

[ i f ( r eset _name = val ue) t hen… r eset behavi or

el s] i f ( ck_name = val ue and ck_name' event ) t hen… cl ocked behavi or

end i f ;end pr ocess;

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Specifying FSMs

�� Selection of:Selection of:�� Moore or Mealy styleMoore or Mealy style

�� Reset or notReset or not

�� Synchronous/asynchronous resetSynchronous/asynchronous reset

�� Buffers positionBuffers position

�� Data type definition for State elementsData type definition for State elements

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FSMs in VHDL - Recognizer - 1

aa bb cc

dd0/1

0/1

1/0

1/0

1/01/0

0/0

0/0

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FSMs in VHDL - Recognizer - 2

PACKAGE RecognPack I St ype Rst at e i s ( a, b, c, d) ;

END RecognPack ;

ENTI TY Recogni zer i sPORT( cl k : i n bi t ;

PI : i n bi t ;Z: out bi t )

END Recogni zer ;

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FSMs in VHDL - Recognizer - 3

ARCHI TECTURE Thr eePr oc OF Recogni zer I Ssi gnal pst at e, nst at e: Rst at e : = a;

BEGI N Next St at e: PROCESSBEGI N

WAI T UNTI L c l k = ‘ 1’ AND cl k ’ EVENTCASE pst at e I S

WHEN a => I F PI = ‘ 1’ THENnst at e <= b;

ELSEnst at e <= a;

END I F;WHEN b => I F PI = ‘ 1’ THEN

nst at e <= c;ELSE

nst at e <= a;END I F;

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FSMs in VHDL - Recognizer - 4

WHEN c => I F PI = ‘ 1’ THEN

nst at e <= d;

ELSE

nst at e <= a;

END I F;

WHEN d => I F PI = ‘ 1’ THEN

nst at e <= c;

ELSE

nst at e <= a;

END I F;

WHEN OTHERS => nst at e <= a;

END CASE;

END PROCESS Next St at e;

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FSMs in VHDL - Recognizer - 5

Out put : PROCESS( pst at e, PI )BEGI N

CASE pst at e I SWHEN a => Z <= ‘ 0’ ;WHEN b => Z <= ‘ 0’ ;WHEN c => I F PI = ‘ 1’ THEN

Z <= ‘ 0’ ;ELSE

Z <= ‘ 1’ ;END I F;

WHEN d => I F PI = ‘ 1’ THENZ <= ‘ 0’ ;

ELSEZ <= ‘ 1’ ;

END I F;WHEN OTHERS => Z <= ‘ 0’ ;

END CASE;END PROCESS;

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FSMs in VHDL - Recognizer - 6

St at eEvol : Pr ocessbegi n

WAI T UNTI L cl k ' EVENT and c l k = ' 1' ;pst at e <= nst at e;

end pr ocess;end Thr eePr oc;

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FSMs in VHDL - Recognizer - 7

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Fummi

FSMs in VHDL - Recognizer - 8

111111

Fummi

FSMs in VHDL - Recognizer - 9