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EEM 334 Digital Systems II

Outline

•  Overview on VHDL •  Lexical Elements •  Basic VHDL Program •  STD_LOGIC •  Modeling Wires and Buses

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Overview on VHDL

Traditional Programming Language

•  Can we use C or Java as HDL? •  Modeled after a sequential process

– Operations performed in a sequential order – Help human's thinking process to develop an

algorithm step by step – Resemble the operation of a basic computer

model

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HDL

•  Characteristics of digital hardware – Connections of parts – Concurrent operations – Concept of propagation delay and timing

•  Characteristics cannot be captured by traditional PLs

•  Require new languages: HDL

Modern HDL

•  Capture characteristics of a digital circuit: – entity –  connectivity –  concurrency –  timing

•  Cover description –  In gate level and RT level –  In structural view and behavioral view

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Two HDLs Used Today •  VHDL and Verilog •  Syntax and ``appearance'' of the two

languages are very different •  Capabilities and scopes are quite similar •  Both are industrial standards and are

supported by most software tools

VHDL

•  VHDL: VHSIC (Very High Speed Integrated Circuit) HDL

•  Initially sponsored by DoD as a hardware documentation standard in early 80s

•  Transferred to IEEE and ratified it as IEEE standard 1176 in 1987 (known as VHDL-87)

•  Major modification in ’93 (known as VHDL-93)

•  Revised continuously

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IEEE Extensions •  IEEE standard 1076.1 Analog and Mixed Signal

Extensions (VHDL-AMS) •  IEEE standard 1076.2 VHDL Mathematical Packages •  IEEE standard 1076.3 Synthesis Packages •  IEEE standard 1076.4 VHDL Initiative Towards ASIC

Libraries (VITAL) •  IEEE standard 1076.6 VHDL Register Transfer Level

(RTL) Synthesis •  IEEE standard 1164 Multivalue Logic System for

VHDL Model Interoperability •  IEEE standard 1029 VHDL Waveform and Vector

Exchange to Support Design and Test Verification (WAVES)

Lexical Elements

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Lexical Elements

•  Lexical element: – Basic syntactical units in a VHDL program

•  Types of Lexical elements: – Comments –  Identifiers – Reserved words – Numbers – Characters – Strings

Comments

•  Comments in VHDL are indicated with a “double dash”, i.e., “--” – Comment indicator can be placed anywhere in

the line – Any text that follows in the same line is treated

as a comment – Carriage return terminates a comment – No method for commenting a block extending

over a couple of lines

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Comments

Identifiers

•  All names should start with an alphabet character (a-z or A-Z)

•  Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)

•  Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -, etc.)

•  Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid)

•  All names and labels in a given entity and architecture must be unique

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Valid or Invalid?

7segment_display A87372477424 Adder/Subtractor /reset And_or_gate AND__OR__NOT Kogge-Stone-Adder Ripple&Carry_Adder My adder

Identifiers

•  VHDL is case insensitive •  Names or labels

databus

Databus

DataBus DATABUS

are all equivalent

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Reserved Words

Numbers

•  Integer: 0, 1234, 98E7 (E: exponent) •  Real: 0.0,1.23456, 9.87E6 •  Other number bases are possible

– 45 = 2#101101# – 45 = 16#2D#

•  Underscore for readability – 12_3456 = 123456 – 2#0011_1010_1101# = 2#001110101101#

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Characters and Strings

•  Character –  ‘A’, ‘Z’ and ‘3’ – 1 and ‘1’ are different!

•  String: a sequence of characters –  “Hello” and “1000111” – 2#10110010# and 10110010 are different –  “10100010” and “1011_0010” are different

Free Format

•  VHDL is a “free format” language •  No formatting conventions, such as

spacing or indentation, imposed by VHDL compilers.

•  Space and carriage return treated the same way.

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Free Format

A Good Header

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Basic VHDL Program

Even Parity Detector

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Language Organization

Entity

Architecture

Library

Library

•  Library is a collection of commonly used pieces of code, grouped for reuse.

TYPES CONSTANTS FUNCTIONS

PROCEDURES COMPONENTS

TYPES CONSTANTS FUNCTIONS

PROCEDURES COMPONENTS

LIBRARY

PACKAGE 1 PACKAGE 2

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Library Declaration Library

declaration

Use all definitions from

package std_logic_1164

Library Declaration - Syntax

LIBRARY library_name;

USE library_name.package_name.package_parts;

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Commonly Used Libraries •  ieee

– Specifies multi-level logic system including STD_LOGIC and STD_LOGIC_VECTOR data types

– Needs to be explicitly declared •  std

– Specifies pre-defined data types (BIT, BOOLEAN, INTEGER, REAL, SIGNED, UNSIGNED, etc.), arithmetic operations, basic type conversion functions, basic text i/o functions, etc.

– Visible by default •  work

– User-created designs after compilation – Visible by default

Design Entity

•  Most basic building block of a design

•  Represent arbitrarily complex systems

•  One entity – many different architectures

entity declaration

architecture 1

architecture 2

architecture 3

design entity

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Design Entity

•  VHDL design entity has two main parts: –  Interface (Entity)

• Specification – What a design does • Boundary (Inputs and outputs) between

system and its environment – Body (Architecture)

• Implementation – How a design implements • Describes how the outputs responds to

inputs

Entity

•  Name of the circuit: even_detector •  One input port – a

– Three element array: a(2), a(1), a(0) •  One output port – even

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Entity Declaration

•  entity_name: any legal identifier •  No semicolon after the last port •  File extension for a VHDL file is .vhd •  Name of the file should be the same as

the entity name (even_detector.vhd) – Place each entity in a different file

Port Declaration

•  port name: any legal identifier •  mode:

–  in, out, inout, buffer •  data type: a set of legal values for the port

–  std_logic, std_logic_vector, integer, signed, etc.

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a

Entity Port signal

Driver resides outside the entity

Port Mode IN

Entity

Port signal

Driver resides inside the entity

Output cannot be read within the entity

z

c <= z

c

Port Mode OUT

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Port signal

Entity

Driver resides inside the entity

Signal x can be read inside the entity

x

c

z

z <= x c <= x

Port Mode OUT (with extra signal)

Entity

Port signal

Driver resides inside the entity

Port signal Z can be read inside the entity

c

z

c <= z

Port Mode BUFFER

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Signal can be read inside the entity

Entity Port signal

Driver may reside both inside and outside of the entity

a

Port Mode INOUT

Port Modes: Summary •  The Port Mode of the interface describes the direction in which

data travels with respect to the component –  In: Data comes in this port and can only be read within

the entity. It can appear only on the right side of a signal or variable assignment.

–  Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment.

–  Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment.

–  Buffer: Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement the signal can appear on the left and right sides of the <= operator

INOUT AND BUFFER NOT USED IN EEM334

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Architecture

•  sop_arc is an realization of even_detector •  signal – wires that connect internal parts •  begin, end – architecture description

Declarations

Architectural Description

Architecture Declaration

•  arch_name: any legal identifier •  entity_name: always linked to an entity •  declarations: optional •  concurrent statement: operation

performed by the circuit

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STD_LOGIC

BIT versus STD_LOGIC

•  BIT type can only have a value of ‘0’ or ‘1’ •  STD_LOGIC can have nine values

–  'U',‘0’,’1’,’X’,’Z’,’W’,’L’,’H’,’-’ – Useful mainly for simulation –  ‘0’,’1’, and ‘Z’ are synthesizable

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STD_LOGIC Type

Value Meaning

'U' Uninitialized

‘X’ Forcing (Strong driven) Unknown

‘0’ Forcing (Strong driven) 0

‘1’ Forcing (Strong driven) 1

‘Z’ High Impedance

‘W’ Weak (Weakly driven) Unknown

‘L’ Weak (Weakly driven) 0. Models a pull down.

‘H’ Weak (Weakly driven) 1. Models a pull up.

‘-’ Don't Care

More on STD_LOGIC Meanings (1)

‘1’

‘0’

‘X’

Contention on the bus

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More on STD_LOGIC Meanings (2)

‘0’

VDD

‘H’

‘0’

‘1’

‘L’

VDD

More on STD_LOGIC Meanings (3)

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More on STD_LOGIC Meanings (4)

•  ‘-’: do not care •  Can be assigned to outputs for the case of

invalid inputs (may produce significant improvements in resource utilization after synthesis)

•  Use with caution –  ‘1’=‘-’ gives FALSE

Resolving Logic Levels

U X 0 1 Z W L H - U U U U U U U U U U X U X X X X X X X X 0 U X 0 X 0 0 0 0 X 1 U X X 1 1 1 1 1 X Z U X 0 1 Z W L H X W U X 0 1 W W W W X L U X 0 1 L W L W X H U X 0 1 H W W H X - U X X X X X X X X

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STD_LOGIC Rules

•  In EEM 334, use std_logic or std_logic_vector for all entity input or output ports – Do not use integer, unsigned, signed, bit for ports – Can use other types inside an architecture if

desired – Can use other types in generics

•  Instead use std_logic_vector and a conversion function inside your architecture

MODELING WIRES AND BUSES

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Single Wire Versus Bus

wire

a

bus

b

1

8

SIGNAL a : STD_LOGIC;

SIGNAL b : STD_LOGIC_VECTOR(7 downto 0);

Standard Logic Vectors

SIGNAL a: STD_LOGIC; SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL f: STD_LOGIC_VECTOR(8 DOWNTO 0); ………. a <= '1'; b <= "0000"; -- Binary base assumed by default c <= B"0000"; -- Binary base explicitly specified d <= "0110_0111"; -- You can use '_' to increase readability e <= X"AF67"; -- Hexadecimal base f <= O"723"; -- Octal bas

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Single versus Double Quote

•  Use single quote to hold a single bit signal – a <= '0', a <='Z'

•  Use double quote to hold a multi-bit signal – b <= "00", b <= "11"

Vectors and Concatenation

SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0); a <= "0000"; b <= "1111"; c <= a & b; -- c = "00001111" d <= '0' & "0001111"; -- d <= "00001111" e <= '0' & '0' & '0' & '0' & '1' & '1' & '1' & '1'; -- e <= "00001111"

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STD_LOGIC versus STD_ULOGIC

•  STD_LOGIC resolves types which conflict via the conflict resolution table

•  STD_ULOGIC does not allow for conflicts on buses and will not resolve multiple sources for a signal

•  We only use STD_LOGIC in this course