3/2/12

1

EEM 334 Digital Systems II

Outline

•  VHDL Design Styles – Concurrent – Structural – Behavioral

•  Test-bench •  VHDL in Development Flow

3/2/12

2

VHDL Design Styles

VHDL Design Styles (Architecture)

STRUCTURAL

components and interconnects

VHDL Design Styles

DATAFLOW

“concurrent” statements

•  State machines •  Registers

“sequential” statements

VHDL subset most suitable for synthesis

NON- SYNTHESIZABLE SYTHESIZABLE

BEHAVIORAL

•  Test Benches •  Modeling IP

3/2/12

3

Even Parity Detector

VHDL Listing

3/2/12

4

Concurrent Signal Description

Concurrent Signal Description

3/2/12

5

Concurrent Signal Description

•  Concurrent statement: A circuit part –  Left-hand-side signal: output –  Right-hand-side signals: inputs –  Right-hand-side: Operation performed by this circuit

•  Concurrent statements are linked through signals •  They are independent,

–  their order does not matter –  they can be activated in parallel

Conceptual Interpretation

3/2/12

6

Structural Description

Structural Description

•  Assume that there is a library with predesigned parts: – xor2 – not1

3/2/12

7

VHDL Listing

Component Declaration

•  Declare components first •  Component declaration is similar to entity

declaration

3/2/12

8

Component Instantiation

•  unit1 –  label: a unique id for this part

•  xor2 –  Initiated component

•  port map – How each component instance is connected to

the rest of the system – Which signals are connected to which

component ports

Component Instantiation

•  Component instantiations: Concurrent statements – Order does not matter

•  Connections between components are through the same signal names

3/2/12

9

Structural Description

•  Structural description ≡ component concept •  Closest to schematic/block diagram

– What types of parts are used – How these parts are connected

•  Hierarchical design of complex systems – Several smaller subsystems: each is a

component – Each subsystem can be further divided

•  Allow using predesigned circuits, IP cores or specialized library cells –  Instantiate in the description – Treat as a black box

Sequential Signal Description

3/2/12

10

Sequential Signal Description

Sequential Signal Description

3/2/12

11

Sequential Signal Description

•  sensitivity_list – a set of signals – When a signal in this list changes, the process is

activated •  begin-end

– process body – Sequential statements as usual

Sequential Signal Description

•  Sequential signal description ≡ process concept •  Sequential execution similar to the traditional

languages inside process •  Focus on the system operation rather than its

construction –  Initially, time-consuming and very complex to

implement a system •  Variable, loop: No hardware counterparts

3/2/12

12

Test-benches

Test-benches

•  Simulation – A major use of a VHDL program –  Study the operation of a circuit –  Verify its correctness

•  Similar to doing an experiment with a physical circuit –  Connect the inputs to the stimulus (function generator)

•  Test vector generation in VHDL –  Physical circuit

•  VHDL code –  Observe the output (logic analyzer)

•  Collect output responses in VHDL

3/2/12

13

A Simple Test-bench

Library Declaration

Entity Declaration

Architecture Declaration

Circuit to be tested

A Simple Test-bench

3/2/12

14

A Simple Test-bench

Configuration •  Multiple architecture bodies can be

associated with an entity declaration – Like IC chips and sockets

•  VHDL configuration specifies the binding

3/2/12

15

VHDL in Development Flow

•  The course focuses on hardware, not VHDL (i.e., the “H”, not “L” of HDL)

•  Emphasis on coding for synthesis: – Code accurately describing the underlying

hardware structure – Code providing adequate info to guide

synthesis software to generate efficient implementation

Coding for Synthesis

3/2/12

16

Algorithmic level

Register Transfer Level

Logic (gate) level

Circuit (transistor) level

Physical (layout) level

Level of description most suitable for

synthesis

Levels of Design Description

… Combinational Logic

Combinational Logic

Registers

Register Transfer Logic (RTL) Design Description

3/2/12

17

Scope of VHDL

Execution of VHDL Codes

•  Simulation – Design “realized” in a virtual environment

(simulation software) – All language constructs can be “realized” –  “realized” by a single CPU

3/2/12

18

•  Synthesis – Design realized by hardware components – Many VHDL constructs cannot be synthesized

(e,g, file operation, floating-point data type, division)

– Only small subset can be used – Syntactically correct code ≠ Synthesizable code – Synthesizable code ≠ Efficient code

• Synthesis software only performs transformation and local optimization

Execution of VHDL Codes