benvenuto su ams tesi di dottorato - almadl...

Alma Mater Studiorum · Universita di Bologna

ARCES - Advanced Research Center on Electronic Systems forInformation and Communication Technologies E. De Castro

European doctorate program in Information Technology (EDITH)

Cycle XXI - ING-INF/01

Characterization and Modelingof Low-Frequency Noise

in Mosfets

Nicola Zanolla

Ph.D. Thesis

Tutor Coordinator

Prof. Claudio Fiegna Prof. Claudio Fiegna

January 2006 - December 2008

To Wibke

Contents

1 Introduction 11.1 Motivation of this work . . . . . . . . . . . . . . . . . . . . . . 21.2 Scope of this thesis . . . . . . . . . . . . . . . . . . . . . . . . 3

2 MOSFETs: device physics 52.1 MOS capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1.1 Energy band diagram . . . . . . . . . . . . . . . . . . . 62.1.2 Classical model . . . . . . . . . . . . . . . . . . . . . . 82.1.3 Quantum mechanical effects . . . . . . . . . . . . . . . 9

2.2 Fundamental of MOSFETs . . . . . . . . . . . . . . . . . . . . 132.2.1 MOSFET I-V characteristic . . . . . . . . . . . . . . . 132.2.2 Carrier mobility . . . . . . . . . . . . . . . . . . . . . . 16

3 Basic electrical characterization of MOS devices 193.1 I-V characterization . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1.1 Threshold voltage extraction . . . . . . . . . . . . . . . 203.1.2 Mobility extraction . . . . . . . . . . . . . . . . . . . . 21

3.2 C-V characterization . . . . . . . . . . . . . . . . . . . . . . . 233.3 Charge-pumping measurement . . . . . . . . . . . . . . . . . . 253.4 Results of charge-pumping and mobility measurements . .. . . 27

4 Low-frequency noise in MOSFETs 334.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344.2 Noise sources . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.2.1 Thermal noise . . . . . . . . . . . . . . . . . . . . . . . 384.2.2 Shot noise . . . . . . . . . . . . . . . . . . . . . . . . . 394.2.3 Generation-recombination noise . . . . . . . . . . . . . 394.2.4 Flicker or1/f noise . . . . . . . . . . . . . . . . . . . 39

ii Contents

4.3 MOSFETs 1/f noise model . . . . . . . . . . . . . . . . . . . . 404.3.1 ∆N model . . . . . . . . . . . . . . . . . . . . . . . . 404.3.2 ∆µ model . . . . . . . . . . . . . . . . . . . . . . . . . 434.3.3 Unified∆N and∆µ model . . . . . . . . . . . . . . . 44

4.4 Flicker noise under switched bias conditions . . . . . . . . .. . 454.5 Background of Random Telegraph Signal . . . . . . . . . . . . 46

4.5.1 Statistical properties of RTS . . . . . . . . . . . . . . . 464.5.2 PSD of RTS: Lorentzian spectrum . . . . . . . . . . . . 48

4.6 RTS noise in MOSFETs . . . . . . . . . . . . . . . . . . . . . 504.6.1 RTS under constant bias conditions . . . . . . . . . . . 524.6.2 RTS under switched bias conditions . . . . . . . . . . . 52

4.7 Monte Carlo simulation of RTS and 1/f noise . . . . . . . . . . 544.7.1 MC under constant bias conditions . . . . . . . . . . . . 554.7.2 MC under switched bias conditions . . . . . . . . . . . 564.7.3 Validation . . . . . . . . . . . . . . . . . . . . . . . . . 584.7.4 Simulation of RTS noise under CB and SB conditions . 594.7.5 Simulation of flicker noise . . . . . . . . . . . . . . . . 62

5 Modeling of RTS under constant bias conditions 655.1 Traps and RTS noise . . . . . . . . . . . . . . . . . . . . . . . 665.2 Modeling of RTS . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.2.1 SRH theory . . . . . . . . . . . . . . . . . . . . . . . . 685.2.2 VGS dependence ofτc . . . . . . . . . . . . . . . . . . . 705.2.3 VGS dependence ofτe . . . . . . . . . . . . . . . . . . . 715.2.4 Trap position inside the oxide . . . . . . . . . . . . . . 715.2.5 Tunneling mechanisms . . . . . . . . . . . . . . . . . . 745.2.6 Capture cross-section . . . . . . . . . . . . . . . . . . . 74

5.3 Comparison of RTS models with experimental data . . . . . . .755.3.1 Experimental details . . . . . . . . . . . . . . . . . . . 755.3.2 Modeling approaches . . . . . . . . . . . . . . . . . . . 765.3.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . 785.3.4 Discussion . . . . . . . . . . . . . . . . . . . . . . . . 845.3.5 Extension for pMOSFETs . . . . . . . . . . . . . . . . 84

6 Measurement of flicker and RTS noise under switched bias condi-tions 896.1 Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . 90

Contents iii

6.2 Flicker noise measurements . . . . . . . . . . . . . . . . . . . . 916.2.1 Measurement condition . . . . . . . . . . . . . . . . . . 916.2.2 Measurement results . . . . . . . . . . . . . . . . . . . 926.2.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . 1006.2.4 Measurement on a 45 nm technology . . . . . . . . . . 101

6.3 RTS noise measurement . . . . . . . . . . . . . . . . . . . . . 1046.3.1 Measurement condition . . . . . . . . . . . . . . . . . . 1046.3.2 Measurement results . . . . . . . . . . . . . . . . . . . 1056.3.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . 112

7 Conclusions 115

Acknowledgments 117

Bibliography 119

iv Contents

List of Figures

1.1 TypicalfT for nMOSFETs vs. technology node in CMOS process 2

2.1 Schematic cross section of a MOS capacitor . . . . . . . . . . . 62.2 Energy band diagram of a MOS capacitor biased (a) Flatband,

(b) Accumulation, (c) Depletion, (d) Inversion. . . . . . . . . . 72.3 Band structure of a p-type MOS capacitor in inversion. . .. . . 92.4 Constant energy ellipsoids for silicon along (100) surface. . . . . 112.5 Band structure of a p-type MOS capacitor in inversion showing

the energy subbands due to quantization effects. . . . . . . . . .122.6 Schematic cross section of a standard 4-terminal MOSFET. . . 142.7 IDS vs. VGS characteristic in logarithmic scale. . . . . . . . . . 152.8 Carriers mobility in an inversion layer of a MOSFET as a func-

tion of the effective electric field. . . . . . . . . . . . . . . . . . 17

3.1 Schematic of a Kelvin measurement. . . . . . . . . . . . . . . . 203.2 TypicalIDS/g

1/2m characteristic for an nMOS used to extract the

threshold voltage. . . . . . . . . . . . . . . . . . . . . . . . . . 213.3 Measurement configurations for the gate-to-channel capacitance

(a)CGC and the gate-to-substrate capacitance (b)CGB. . . . . . 243.4 CGC , CGB characteristics for an nMOSFET. . . . . . . . . . . . 243.5 Charge-pumping measurements . . . . . . . . . . . . . . . . . 253.6 Energy band diagram of a nMOSFET commutating between in-

version and accumulation and the relative CP current. . . . . .. 273.7 Charge-pumping currents for nMOSFETs with DGox WF and

WOF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.8 Mobility measurements: nMOS with SGox with and without the

fluorine doping step. . . . . . . . . . . . . . . . . . . . . . . . 303.9 Mobility measurements: nMOS with DGox with and without flu-

orine doping step. . . . . . . . . . . . . . . . . . . . . . . . . . 30

vi List of Figures

4.1 Representation of a stochastic process (e.g.. noise) asa functionof time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.2 Schematic illustration of trapping/detrapping of electron in/fromtraps for a nMOSFET. . . . . . . . . . . . . . . . . . . . . . . . 41

4.3 The superposition of 4 Lorentzians gives a total power spectraldensity roughly proportional to1/f over several decades of fre-quency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.4 nMOSFET cycled between an ON-state (VGS ON ) and an OFF-state (VGS OFF ). . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.5 A Random Telegraph Signal (RTS). . . . . . . . . . . . . . . . 474.6 Power spectral density of RTS noise withτ1=10 ms and different

values ofτ0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.7 Power of RTS noise withτ1=10 ms and different values ofτ0. . 514.8 RTS noise under constant bias and switched bias conditions. RTS

is sampled during the ON-states and joining the sampled valuestogether the RTS under SB conditions is obtained. . . . . . . . . 53

4.9 Monte Carlo simulation and analytical model of the autocorrela-tion of an RTS under CB. . . . . . . . . . . . . . . . . . . . . . 57

4.10 Monte Carlo simulation and analytical model of the PSD of anRTS under CB. . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.11 Monte Carlo simulation and analytical model of the PSD of anRTS under SB. . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.12 Monte Carlo simulated PSD of an RTS under CB and SB condi-tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.13 Occupation probability simulated with MC under SB conditionswith two different switching frequencies: quasi-staticfsw=10 Hzand very largefsw=10 kHz. . . . . . . . . . . . . . . . . . . . 61

4.14 Monte Carlo simulation of flicker noise under CB and SB condi-tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.1 Different types of charges present at the Si-SiO2 interface and inthe bulk of the oxide. . . . . . . . . . . . . . . . . . . . . . . . 67

5.2 The basic processes involved in recombination by trapping: a)electron capture, b) electron emission, c) hole capture, d)holeemission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.3 Band bending of a nMOSFET. . . . . . . . . . . . . . . . . . . 705.4 The energy band diagram in the channel at the trap position. . . 72

List of Figures vii

5.5 ”Tunneling and Capture” (dotted arrows) and ”Capture and Tun-neling” (solid arrows) mechanisms for the capture and emissionprocess for a trap locate at a distancext inside the oxide. . . . . 73

5.6 Experimental and simulatedτc andτe as a function ofVGS (SCHRapproach). Estimatedxt=0.79 nm. . . . . . . . . . . . . . . . . 78

5.7 Experimental and simulatedτc andτe as a function ofVGS (SRGapproach). Estimatedxt=0.76 nm. . . . . . . . . . . . . . . . . 79



5.10 Experimental and simulatedτc andτe as a function ofVGS (SRGapproach). The model assumes an empirical adjustment ofσ0.Estimatedxt=0.82 nm. . . . . . . . . . . . . . . . . . . . . . . 81

5.11 Experimental and simulatedτc andτe as a function ofVGS (SRGapproach). The model assumes an empirical adjustment ofσ0.Estimatedxt=1.13 nm. . . . . . . . . . . . . . . . . . . . . . . 83

5.12 Experimental and simulatedτc andτe as a function ofVGS (SRGapproach). The model accounts for the Coulomb blockade effect.Estimatedxt=1.13 nm. . . . . . . . . . . . . . . . . . . . . . . 83

5.13 Experimental and simulatedτc andτe for a pMOSFET as a func-tion of |VGS| (SRG approach). Estimatedxt=0.32 nm.. . . . . . 85

5.14 Experimental and simulatedτc andτe for a pMOSFET as a func-tion of |VGS| (SRG approach). The model assumes an empiricaladjustment ofσ0. Estimatedxt=0.33 nm. . . . . . . . . . . . . 86

6.1 Schematic setup for measurement of flicker and RTS noise underconstant and switched gate and substrate bias conditions. .. . . 90

6.2 Timing scheme for 1/f noise measurement with in-phase (IP) and180 out-of-phase (OP) switched substrate bias (VBS) with re-spect to the gate voltage (VGS) timing. . . . . . . . . . . . . . . 91

6.3 Normalized noise power densitySid/Id for nMOSFET under CBand SB conditions with ZSB and FSB vs. frequency. . . . . . . 93

6.4 Normalized noise power densitySid/Id for pMOSFET under CBand SB conditions with ZSB and FSB vs. frequency. . . . . . . 93

6.5 Sid/Id @ 1 Hz under CB and SB vs. substrate biasVBS fornMOSFETs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

viii List of Figures

6.6 Sid/Id @ 1 Hz under CB and SB vs. substrate biasVBS forpMOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

6.7 Sid/Id vs. frequency for a single nMOS device under SB condi-tions with ZSB, IP and OP substrate bias switching with respectto the gate pulse timing. . . . . . . . . . . . . . . . . . . . . . . 95

6.8 Sid/Id @ 1 Hz vs. pulsed gate OFF-voltageVGS OFF for a zerovolt substrate bias for nMOSFETs. . . . . . . . . . . . . . . . . 97

6.9 Sid/Id @ 1 Hz vs. pulsed gate OFF-voltageVGS OFF for a zerovolt substrate bias for pMOSFETs. . . . . . . . . . . . . . . . . 97

6.10 Sid/Id @ 1 Hz vs. substrate biasVBS for nMOSFETs. . . . . . . 986.11 Sid/Id @ 1 Hz vs. substrate biasVBS for pMOSFETs. . . . . . . 986.12 NormalizedSid/Id @ 1 Hz under SB conditions for nMOS de-

vices with different oxide thicknesses. . . . . . . . . . . . . . . 1006.13 NormalizedSid/Id @ 1 Hz under SB conditions for pMOS de-

vices with different oxide thicknesses. . . . . . . . . . . . . . . 1006.14 Sid/Id @ 1 Hz vs. pulsed gate OFF-voltageVGS OFF for a zero

volt substrate bias for nMOSFETs. . . . . . . . . . . . . . . . . 1026.15 Sid/Id @ 1 Hz vs. substrate biasVBS for nMOSFETs under CB

and SB conditions. . . . . . . . . . . . . . . . . . . . . . . . . 1026.16 Sid/Id @ 1 Hz vs. pulsed gate OFF-voltageVGS OFF for a zero

volt substrate bias for pMOSFETs. . . . . . . . . . . . . . . . . 1036.17 Sid/Id @ 1 Hz vs. substrate biasVBS for pMOSFETs under CB

and SB conditions. . . . . . . . . . . . . . . . . . . . . . . . . 1036.18 RTS PSD for: CB; SB; gate- and substrate-SB (OP). . . . . . .1056.19 RTS PSD for: CB; gate and substrate SB (IP); gate SB and con-

stant FSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066.20 RTS PSD under gate- and substrate-SB (OP case) for different

values of the substrate biasVBS OFF applied in the OFF-state. . 1076.21 τc, τe and RTS-noise power P under gate and substrate SB (OP

case) as a function of substrate biasVBS OFF applied during theOFF-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

6.22 RTS PSD for: CB; SB; gate- and substrate-SB (OP). . . . . . .1096.23 RTS PSD under gate- and substrate-SB (OP case) for different

values of the substrate biasVBS OFF applied in the OFF-state. . 1106.24 τc, τe and RTS-noise power P under gate and substrate SB (OP

case) as a function of substrate biasVBS OFF applied during theOFF-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

List of Figures ix

6.25 RTS PSD under gate SB for different values of the gate OFF-voltageVGS OFF . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6.26 τc, τe and RTS-noise power P under gate SB as a function of gateOFF-voltageVGS OFF . . . . . . . . . . . . . . . . . . . . . . . 112

x List of Figures

List of Tables

3.1 Interface state densityDit for nMOS devices with different oxidethicknesses and process steps. . . . . . . . . . . . . . . . . . . 29

3.2 Interface state densityDit for pMOS devices with different oxidethicknesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1 τe andτc for the four different traps simulated to generate flickernoise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.1 Extracted physical model parameters for 4 different traps in 4different nMOS devices. . . . . . . . . . . . . . . . . . . . . . 80

5.2 Extracted physical model parameters for 4 different traps in 4different nMOS devices. Due to the largeVGS dependence ofτc,an empirical adjustment ofσ0 is necessary. . . . . . . . . . . . . 82

5.3 Extracted physical model parameters for 3 different traps in 3different pMOS devices. . . . . . . . . . . . . . . . . . . . . . 86

5.4 Extracted physical model parameters for 5 different traps in 5different pMOS devices. Due to the largeVGS dependence ofτc,an empirical adjustment ofσ0 is necessary. . . . . . . . . . . . . 87

xii List of Tables

List of Symbols and Acronyms

Symbol

b Variation parameter in electron wavefunction (m−1)

CD Depletion layer capacitance (Fm−2)

CGB Gate-to-channel capacitance (Fm−2)

CGC Gate-to-channel capacitance (Fm−2)

Cox Gate oxide capacitance (Fm−2)

Dit Interface trap density (m−2)

∆E Coulomb blockade energy (eV)

ECS Conduction band energy at Si-SiO2 interface (eV)

EF Fermi energy level (eV)

ET0 Trap energy level at flatband (eV)

ET Trap energy level (eV)

FS Electric field normal to the surface (Vm−1)

f Frequency (Hz)

fsw Switching frequency (Hz)

gd Drain conductance (S)

gm Transconductance (S)

~ Reduced Plank’s constant (Js)

∆I RTS amplitude (A)

ICP Charge-pumping current (A)

IDS Drain current (A)

k Boltzmann’s constant (JK−1)

xiv List of Symbols and Acronyms

L MOSFET channel length (m)

m0 Electron mass (Kg)

m∗ Effective electron mass (Kg)

ml Longitudinal effective mass (Kg)

mt Transverse effective mass (Kg)

n Electron concentration (m−3)

n2D Electron concentration in 2D (m−2)

NA Substrate doping concentration (m−3)

NC Conduction band effective density of states (m−3)

NC(2D) Conduction band effective density of states in 2D (m−2)

NP Polysilicon doping concentration (m−3)

P Noise power (A2)

p(z) Probability function (m−1)

q Electronic charge (C)

QB MOSFET bulk charge (Cm−2)

Qinv MOSFET inversion charge (Cm−2)

Sid/Id Normalized noise power spectral density of drain current (AHz−1)

SS Subthreshold slope (V/decade)

T Temperature (K)

tox Gate oxide thickness (m)

Tsw Switching period (s)

VBS Substrate-to-source voltage (V)

VDS Drain-to-source voltage (V)

VFB Flatband voltage (V)

VGS Gate-to-source voltage (V)

VTH Threshold voltage (V)

vth Electron thermal velocity (ms−1)

W MOSFET channel width (m)

List of Symbols and Acronyms xv

xt Trap position in the oxide with respect to the Si-SiO2 inter-face (m)

z Charge centroid location of the inversion layer (m)

αH Hooge’s empirical factor

ε0 Permittivity of free space (F/m)

εox Oxide relative dielectric constant

εsi Silicon relative dielectric constant

λt Attenuation wave function coefficient (m)

µ0 Low field mobility (m2V−1s−1)

µc Mobility limited by Coulomb scattering (m2V−1s−1)

µeff Effective mobility (m2V−1s−1)

µfe Field effect mobility (m2V−1s−1)

µph Mobility limited by surface acoustic phonon (m2V−1s−1)

µsr Mobility limited by surface roughness (m2V−1s−1)

φF Fermi potential (V)

φp Voltage drop across poly-depletion region (V)

φs Surface potential (V)

σ Capture cross-section (m2)

σ0 Capture cross-section prefactor (m2)

τ0 Mean time spent in the ”low” state of the RTS (s)

τ1 Mean time spent in the ”high” state of the RTS (s)

τc Mean capture time of the RTS (s)

τe Mean emission time of the RTS (s)

Acronym

AC Alternating current

C-V Capacitance-voltage

CB Constant bias

CMOS Complementary metal oxide semiconductor

DC Direct current

xvi List of Symbols and Acronyms

DUT Device under test

FSB Forward substrate bias

FT Fourier transform

I-V Current-voltage

IC Integrated circuit

IFT Inverse Fourier transform

IP In-phase with respect to the gate voltage

LNA Low noise amplifier

MC Monte Carlo

nMOSFET n-channel Metal oxide semiconductor field effect transistor

pMOSFET p-channel Metal oxide semiconductor field effect transistor

OP Out-of-phase with respect to the gate voltage

PSD Power spectral density

RF Radio frequency

RSB Reverse substrate bias

RTS Random telegraph signal

SB Switched bias

Si Silicon

SiO2 Silicon dioxide

SMU Source-measure unit

SRH Shockley-Read-Hall

WKB Wentzel-Kramers-Brillouin

ZSB Zero substrate bias

Chapter 1

Introduction

Semiconductor technology started to be developed more thanfive decades ago.The first step was made when the bipolar junction transistor was invented inthe late 1940s. After deep research in the field, it was possible to create goodquality gate oxides in the 1960s-opening the way to the development of metal-semiconductor-oxide field effect transistor (MOSFET). Theera of integrated cir-cuits (ICs) was born. The progress of device integration hasproceeded for morethan forty years following the well-known Moore’s law. Gordon Moore, in 1965,made his famous prediction that the number of transistors inan integrated cir-cuit would double every year [1]. Moore’s law has been updated in 1975 with aprospected density doubling rate of two years.

The ICs are divided into two main groups: digital and analog/RF. The drivingforce of digital logic and memory ICs has been the scaling of device size. In thisframe, CMOS has been the technology of choice for the digitalICs. Analog andRF circuits for wireless and mobile communication application must meet manyother performance specifications. The relationships between device feature sizeand performance figures of merit are more complex for RF and analog IC ap-plications. RF and analog IC technologies depend on many different materialsand device structures to provide optimal solutions. For many years, RF and ana-log ICs have been mainly developed using bipolar and compound semiconductortechnologies due to their better performance.

In the last years, the advance made in CMOS technology allowed analog andRF circuits to be built with such a technology. Performance improvement, costadvantage and ease of integration have been the driving force to use CMOS tech-nology for analog and RF applications. In Fig. 1.1 the transition frequency (fT )of nMOSFETs for different technology nodes in a CMOS processis reported.

2 Introduction

250 nm

180 nm

130 nm90 nm

65 nm45 nm

Technology node

0

50

100

150

200

250

300

Tra

nsiti

on fr

eque

ncy

f T [G

Hz]

nMOSFET

Figure 1.1: Typical fT for nMOSFETs vs. technology node in CMOS process(source: www.fujitsu.com).

This is one of the figures of merit that qualifies the transistor for application inanalog/RF circuits. ThefT is strongly improved by technology scaling.

The integration of digital, RF and analog circuits in the same chip has givenbirth to the so called system-on-chip (SoC). The new scenario further increasesthe interest for analog and RF applications of MOSFET technology.

A field in which the integration of digital and analog/RF circuits has beensuccessful is that of wireless communications. Wireless communications startedto grow rapidly ten years ago. The driving force has been the development of dig-ital coding and digital signal processing. As for all digital applications, CMOStechnology has been the technology of choice due to its high performance, lowcost, and integration capability. The next step was to develop the front-end partof a wireless system in the same technology. CMOS devices forRF and analogapplications are developed in order to fulfill the needs of wireless communicationsystem.

1.1 Motivation of this work

Advances in MOSFET technology have definitely paved the way to the integra-tion of different circuits in the same chip, but its use in RF application instead of

1.2 Scope of this thesis 3

bipolar technology has also brought more issues in terms of noise.

The noise cannot be completely eliminated and will therefore ultimately limitthe accuracy of measurements and set a lower limit on how small signals can bedetected and processed in an electronic circuit. One kind ofnoise which affectsMOS transistors much more than bipolar ones is the low-frequency noise. InMOSFETs, low-frequency noise is mainly of two kinds: flickeror 1/f noise andrandom telegraph signal noise (RTS).

Flicker noise is the excess noise at low frequencies whose power spectraldensity (PSD) approximately depends inversely on the frequency. The1/f noiseof MOS transistors is a severe obstacle in analog and RF circuits [2]. The1/f

noise is, for example, up-converted to undesired phase noise in voltage controlledoscillator (VCO) circuits, which can limit the informationcapacity of communi-cation systems [2].

The downscaling of the device dimensions not only entails a downscaling ofthe voltage levels, but made RTS noise more and more prominent. RTS noiseis caused by traps or defects at the silicon-oxide interfaceor in the oxide andin small-area MOSFETs a single RTS signal can be isolated. RTS noise is alsoassumed to be the origin of flicker noise in large-area devices [3]. In particular,the superposition of the RTS noise from many traps could leadto a 1/f spec-trum. In the last years, the direct influence of random telegraph signal noise incircuits has been shown. In [4] the erratic behavior in SRAM due to RTS noiseis demonstrated. RTS noise can also be a limiting factor in CMOS image sensorswhere it affects the pixel read noise floor [5].

In 1991, it was noted for the first time [6] that low-frequencynoise couldbe reduced by cycling a MOSFET between strong inversion and accumulation.That means that, turning ”OFF” the device for a certain time before turning it”ON” again, reduces the noise measured when it is always ”ON”. This effect isrelated to the fact that the noise not only depends on the present bias but also onthe bias history of the device. Soon afterwards this effect was associated withthe emptying of traps that cause RTS noise [7]. The reductionof flicker noise inswitched bias CMOS circuits has been studied in [8].

1.2 Scope of this thesis

As we have seen from the above section, low-frequency noise in MOSFETs hasa strong influence in modern CMOS circuits. Low-frequency noise can be found

4 Introduction

in many applications and it can be influenced under switched bias conditions.This kind of noise appears both as flicker and RTS noise.

The objective of this thesis is to characterize and to model the low-frequencynoise by studying RTS and flicker noise under both constant bias and switchedbias conditions. Different biasing schemes have been investigated both for RTSand flicker noise in time and in frequency domain.

In chapter 2the basic working principles of the MOS capacitor are discussed,and the importance of quantum mechanical effects is analyzed. The fundamen-tal basis of the MOS transistor is also presented.Chapter 3describes the ba-sic electrical characterization by means of current-voltage (I-V), capacitance-voltage (C-V), and charge-pumping measurements. Two methods to extract boththe interface trap density and the mobility have been adopted in order to ana-lyze MOSFETs having a different process option. Inchapter 4, after the reviewof stochastic signals, a Monte Carlo simulator able to simulate both RTS andflicker noise under constant and switched bias conditions ispresented.Chapter5, after a brief introduction on different kind of traps present in the silicon ox-ide, describes the Shockley-Read-Hall (SRH) theory for trapping and detrappingof electrons in traps located at the silicon oxide interfaceor inside the oxide.Measurements and simulation of the gate bias dependence of RTS emission andcapture time constants in n and pMOS transistors are presented. In chapter 6measurements of flicker and RTS noise under constant and switched bias con-ditions are proposed. The effect of a forward substrate biasis deeply analyzed.The final conclusions of this thesis are presented inchapter 7.

Chapter 2

MOSFETs: device physics

The metal-oxide-semiconductor field effect transistor (MOSFET) is the funda-mental component for digital circuits such as microprocessor and memories. Inthe last years CMOS technology replaced the bipolar one in analog, RF andpower applications in which the bipolar technology has beenfor many years thepreferred choice. The CMOS technology has the great advantage of combininglow-cost, high performance, high yield, low standby power,and larger integra-tion of functions. The ability to reduce the dimensions of MOS transistors andthe consequent higher integration lead to faster and smaller chips. This chap-ter is organized as follows: in the first part the basic working principles of theMOS capacitor are discussed and the importance of quantum mechanical effectsis analyzed. In the second part of the chapter the fundamental basis of the MOStransistor are presented.

2.1 MOS capacitor

In order to understand the working principle of a MOS transistor it is useful firstto analyze its basic part: the MOS capacitor. The MOS capacitor consists ofa metal-oxide-semiconductor structure as illustrated by Fig. 2.1. A thin oxidelayer usually SiO2 separates the metal and the semiconductor (silicon) regions.The metal is referred as gate and the semiconductor as bulk orsubstrate. Thebulk can be p- or n-type depending on the adopted doping. In this section wealways refer to a p-type substrate.

6 MOSFETs: device physics

METAL

OXIDE

SEMICONDUCTOR

GATE

BULK

Figure 2.1: Schematic cross section of a MOS capacitor

2.1.1 Energy band diagram

To understand the basic operation of a MOS capacitor it is useful to refer to itsenergy band diagram. The energy band diagram represents thedifferent energylevels of the three materials metal-oxide-semiconductor.Depending on the ap-plied voltage at the gate terminal the energy levels in the structure can bend giv-ing rise to four different operation modes (Fig. 2.2). For simplicity, we assumethat the metal work function is the same as the silicon work function.

Flatband When no voltage is applied to the gate terminal, the Fermi level ofthe semiconductor and the metal line up and the bands both in the silicon andin the oxide are flat. This condition is calledflatbandcondition and is shown inFig. 2.2(a)

Accumulation When a negative voltage is applied to the gate terminal, it re-sults in a rise of the Fermi level of the metal with reference to the Fermi levelof the semiconductor as shown in Fig. 2.2(b). This creates anelectric field inthe oxide. This field accelerates negative charges towards the silicon substrate.A field is also induced at the silicon surface in the same direction as the oxidefield. The bands bend upward toward the oxide interface. The Fermi level of thesemiconductor is flat since there is no net flow of conduction current. This re-sults in a hole concentration much higher at the surface thanthe equilibrium hole

2.1 MOS capacitor 7

EC

Ei

EF

EV

EC

Ei

EF

EV

EC

Ei

EF

EV

2Si0

EFm

EFm

EC

Ei

EF

EV

VG < 0

EFm

EFm

VG > 0

VG = 0

Gate p−type substrate

VG > 0

Depletion

Inversion

Flatband

(a)

(b)

(c)

(d)

Accumulation

Figure 2.2: Energy band diagram of a MOS capacitor biased (a) Flatband,(b)Accumulation, (c) Depletion, (d) Inversion.


concentration in the bulk. Since excess holes are accumulated at the surface, thisis referred to as theaccumulationcondition.

Depletion When a positive voltage is applied to the gate of the capacitor, theFermi level of the metal move downward and creates an oxide field in the oxideand in the silicon surface which causes the bands to bend downward towardthe surface, as shown in Fig. 2.2(c). In this case, the holes are repelled fromthe interface side of the semiconductor, resulting in the formation of immobilenegative ions layer near the interface and a depletion charge QB is associated tothis layer. This condition is calleddepletion.

Inversion When the applied voltage to the gate is increased, the band bendingincreases and the depletion region becomes wider. This process will continueand reach the state where the intrinsic level of the semiconductorEi is equal tothe Fermi levelEF making it intrinsic. A further increase in the gate voltagecreates no further depletion and, at the interface side of the semiconductor, alayer of electrons is formed. An inversion chargeQinv is associated to this layer.This is referred to as theinversioncondition.

The inversion condition is the most important because is theone that allowsthe flowing of a current in a MOS transistor.

2.1.2 Classical model

In this section we introduce the basic notion necessary to characterize the inver-sion layer of a MOS device using the classical approach.

For the classical semiconductor theory the electrons in theconduction bandare free to move in any direction forming a three-dimensional gas. The electronconcentration it is assumed maximum at the interface and, under some simplifi-cations, the electron concentration at the interface between the substrate and theoxide is [9]:

n = NCexp

(

EF − ECS

kT

)

(2.1)

whereECS is the conduction band energy level at the Si-SiO2 interface, andEF

the Fermi level (Fig. 2.3).

2.1 MOS capacitor 9

2Si0

EC

EFm

EV

Ei

EF

ECS

EVS

φF

φs


qq

Figure 2.3: Band structure of a p-type MOS capacitor in inversion.

NC is the effective density of states in the conduction band andcan be ex-pressed as:

NC = 2

(

m∗kT

2π~2

)3

2

(2.2)

wherem∗ is the effective electron mass,k is the Boltzmann’s constant,T is thetemperature and~ is the reduced Planck’s constant.

A 3D approach is acceptable only for lightly doped semiconductor in whichthe electric field at the surface is relative small. When the semiconductor ishighly doped, like in modern devices, quantization effectsare present and a 2Dapproach is more appropriate. A brief introduction on quantization effects isgiven in the next section.

2.1.3 Quantum mechanical effects

Electrons in the inversion layer of a MOS are confined in a potential well closeto the Si-SiO2 interface. This potential well is formed by the silicon conduction


band, that is bent under the effect of the electric field, and the silicon-oxide bar-rier. To ensure a good control of the gate on the channel in small size devices, itis necessary to reduce the gate oxide thickness and to increase the substrate dop-ing concentration. This results in a very high surface electric field. The higherthe electric field the higher is the confinement of electrons in the potential well.The width of the potential well in the z direction, the direction perpendicular tothe interface, is small compared to the wavelengths of the carriers. The quan-tum mechanics demonstrated that the energy of confined carriers is discretized.Each discrete level corresponds to asubbandof the electron gas. To each sub-band is then associated a discrete value of energy for the motion of the carriersperpendicular to the interface (z direction), and a continuum of energies for themotion in the plane parallel to the interface. The total number of electrons in theconduction band is therefore the sum of the electrons present in each subband.

Inversion layer electrons on a<100> surface are known to be composed oftwo kinds of subbands (Fig. 2.4). One is the 2-fold valleys along the z direction.These valleys respond to the external electric field with their longitudinal effec-tive massml=0.916m0. The other 4-fold valleys respond with the transverseeffective massmt=0.19m0. Each set of subbands can be visualized as a ladder.Thus, two different ladders will be obtained for the 2-fold (unprimed ladder)and the 4-fold (primed ladder) valleys. In Fig. 2.5 the first four sets of subbandsare illustrated. The levelsE0, E1 andE2 are due to the doubly degenerate en-ergy ellipsoids, while theE

′

0 level is the ground state for the 4-fold degenerateellipsoids [10]. It is interesting to notice that the unprimed ladder has a largereffective mass, so the energies of the subband associated tothe unprimed ladderare relatively smaller than the energies of the subbands associated to the primedladder.

Another difference with respect to the classical approach is that only a smallamount of the electron density is located at the Si-SiO2 interface but has a peakat a certain distancez called charge centroid and a total distribution defined bythe probability functionp(z), see Fig. 2.5.

Comparing the quantum mechanics approach with the classical one two mainkey effects can be underlined.

The first effect is an increase of the threshold voltage. The threshold volt-age is approximately the gate voltage for which the conduction band goes belowthe Fermi level. However, due to the energy quantization, the lowest level thatelectrons occupy is not the bottom of conduction band, rather it is the first en-ergy levelE0, which is little higher than the conduction band at the interface

2.1 MOS capacitor 11

Kx

Ky

Kz

Figure 2.4: Constant energy ellipsoids for silicon along (100) surface.

ECS. Hence, to bend this band below the Fermi level, a little moregate voltageis needed. This is reflected to a higher threshold voltage compared to the onecalculated by the classical theory.

The second effect comes from the spatial distribution of inversion charge thatfollows the probability functionp(z). While the classical distribution shows apeak at the oxide semiconductor interface, the quantum mechanical distributionshows a peak inside the substrate with an average distancez. The average car-riers distance produces an increase of the effective oxide thickness. Therefore,the quantum mechanical calculation predicts a larger effective oxide thickness,which means a lower gate capacitance. Thus, for a certain gate voltage, theamount of inversion charge will be somewhat smaller than that predicted by theclassical analysis. This is more important as the oxide thickness becomes smallerwith each technology generation.

In our work, in order to analyze experimental results, we usea first order ap-proximation of quantization effects taking into account only the lowest subbandE0 in which the most of electrons resides. An exhaustive discussion of this ap-proach is presented in [11]. Here we report only the basic notion needed in ourwork.

The effective density of states for electron in the 2D case is:


2Si0

EC

EFm

ECS

EVS

EV

EF

Ei

E0

E1

E2E0

’


p(z)

z

Figure 2.5: Band structure of a p-type MOS capacitor in inversion showing theenergy subbands due to quantization effects.

NC(2D) =2kTmt

~2π(2.3)

wheremt is the electron transverse effective mass.The electron concentration is expressed by:

n2D = NC(2D)exp

(

EF − (ECS + ∆E0)

kT

)

(2.4)

where∆E0 = E0 − ECS and it is given by:

∆E0 ≈(

~2

2ml

)1

3

(

9πq

8FS

)2

3

(2.5)

whereml is the electron longitudinal effective mass, andFS is the electric fieldnormal to the interface.

The probability function of finding electrons along the z direction can beexpressed as:

p(z) =(

b3/2)z2exp(−bz))

(2.6)

2.2 Fundamental of MOSFETs 13

with:

b =

[

12qml

~2ε0εsi

(

QB +11

32Qinv

)]1

3

(2.7)

whereε0 is the permittivity of free space, andεsi is the silicon relative dielectricconstant.

The charge centroid of the inversion layer is calculated as:

z =3

b(2.8)

Eq. 2.8 gives an estimation of the average distance of carriers from the interface.

2.2 Fundamental of MOSFETs

The MOS transistor is basically a MOS capacitor to which two more regionscalled source and drain are added. A cross section of a MOS transistor is shownin Fig. 2.6.

The gate terminal controls the formation of the channel and the flowing ofthe current between the source and the drain terminals. The substrate terminal isusually connected to ground, even if in some applications a positive o negativevoltage could be applied. The well forming the substrate is n- or p-doped for ap- or n-channel MOSFET, respectively. The source and the drain regions presenta large concentration of dopants of opposite type of the substrate. In Fig. 2.6the schematic cross section of a n-type MOS is shown. The gateelectrode isusually made of poly-silicon or metal and it is separated from the Si substrate byan insulator with a thicknesstox. The typical material of the insulator is SiO2 ornitrided SiO2.

2.2.1 MOSFET I-V characteristic

The operation of a MOSFET can be separated into three different modes, de-pending on the voltages applied to the terminals. For a n-channel MOSFET themodes are:

• Cutoff or subthreshold mode: whenVGS < VTH , whereVGS is the gate-to-source voltage andVTH is the threshold voltage of the device. Thetransistor is turned OFF, and there is no conduction betweendrain and


toxOXIDE

GATE

DRAINSOURCE

BULK

n diffusionn diffusion

p substrate

Gate Length L

poly

Figure 2.6: Schematic cross section of a standard 4-terminal MOSFET

source. While the current between drain and source should ideally be zero,there is a weak-inversion current orsubthreshold leakage.

• Triode or linear region: whenVGS > VTH andVDS < VGS − VTH , whereVDS is the drain-to-source voltage. The transistor is turned ON, and achannel has been created which allows current to flow betweenthe drainand the source. The MOSFET operates like a resistor controlled by thegate voltage. The current from drain to source can be expressed as:

IDS =W

LCoxµeff

(

(VGS − VTH)VDS − 1

2V 2

DS

)

(2.9)

whereL is the channel length,W is the channel width,Cox = ε0εox/tox

is the oxide capacitance,µeff is the effective mobility,NA is the substratedoping concentration.

• Saturation: whenVGS > VTH andVDS > VGS − VTH . The transistor isturned on, and a channel has been created which allows current to flow be-tween the drain and source. Since the drain voltage is higherthan the gatevoltage, a portion of the channel is turned off. The oneset ofthis regionis also know as pinch-off. The drain current is now relatively independent


0 0.5 1 1.5V

GS [V]

10-9

10-8

10-7

10-6

10-5

10-4

I DS [

A]

SS-1

Figure 2.7: IDS vs. VGS characteristic in logarithmic scale.

of the drain voltage (in a first-order approximation) and thecurrent is onlycontrolled by the gate voltage:

IDS =W

2LCoxµeff(VGS − VTH)2 (2.10)

The threshold voltage can be expressed as:

VTH = VFB + 2φF +

√4ε0εsiqNAφF

Cox+

√2ε0εsiqNA

Cox(√

VSB + 2φF −√

2φF )

(2.11)whereVFB is the flatband voltage,VSB is the source-to-substrate voltage, andφF

is the Fermi potential.The simple expressions for the drain current (Eqs. 2.9 and 2.10) can be ob-

tained from hand-calculation under many approximations. The most importantone is theGradual Channel Approximation[12] which assumes that the electricfield in the direction normal to the Si-SiO2 interface is much larger than the oneparallel to the transport direction.

The ability to turn OFF a transistor is described by the subthreshold slope(Fig. 2.7):

SS =∂VGS

∂log10IDS

=kT

qln(10)

(

1 +CD

Cox

)

(2.12)


whereCD is the depletion layer capacitance.A steep subthreshold slope is desired since the current drops faster with de-

creasing the gate voltage, therefore, the device is easier to turn OFF. This allowsa lower threshold voltage and as a consequence a higher ON-current. In MOS-FETs the value of the substhreshold slope is usually between60-100 mV/dec. SSis sensitive to the presence of traps at the Si-SiO2 interface. This fact depends onthe capacitance associated with the interface states whichwill be parallel withthe depletion layer capacitanceCD (Eq. 2.12) and will therefore increase thesubthreshold slope.

The characteristic which has made MOSFETs so interesting isthe scalability.Already from Eqs. 2.9 and 2.10, it is possible to evaluate thedependence of thecurrent on the different geometry parameters and applied voltages. For example,a decrease of the gate lengthL leads to an increase of the drain currentIDS.Shrinking the device dimensions is not a straightforward task, and especiallyin the short-channel regime, many second-order effects become more and morerelevant such as quantization effects previously reported.

2.2.2 Carrier mobility

In a semiconductor under thermal equilibrium and no appliedelectric field thecarriers move rapidly with the thermal velocity∼ 107 cm/s in random directionsand no net current flows. The motion of the carriers is perturbated by the semi-conductor lattice (phonon) and impurities (dopants and defects). These perturba-tions are called scattering events. The application of an electric field acceleratesthe carriers between two collisions and the carrier mobility is defined as the ratioof the carrier velocity and the electric field. The carrier mobility in an inversionlayer of a MOSFET is much lower than in the bulk since the carriers are confinedin a narrow layer below the Si-SiO2 interface suffering therefore from scatteringat the surface (roughness and surface phonons). If the different scattering mech-anisms are assumed to be mutually independent and to have thesame energydependence, the effective mobilityµeff in the inversion layer can be calculatedusing the Matthiessen’s rule according to [10, 13]:

1

µeff=

1

µph+

1

µsr+

1

µc(2.13)

whereµph is the mobility limited by surface acoustic phonon scattering, µsr isthe mobility due to surface roughness scattering andµc is the mobility limited by


Figure 2.8: Carriers mobility in an inversion layer of a MOSFET as a functionof the effective electric field. The dependence on the main scattering sources andon temperature is shown. Picture is taken from [13].

Coulomb scattering mainly due to ionized atoms of dopants and fixed/trappedcharge in the gate oxide. The conditions for using the Matthiessen’s rule areonly seldom fulfilled in practice, however Eq. 2.13 is usefulto analyze the de-pendence of the effective mobility on the scattering events. Both the surfaceroughness scattering due to the micro roughness at the Si-SiO2 interface and theCoulomb scattering are sensitive to technology factors such as doping concen-tration, surface cleaning and the gate oxidation process. On the other hand, thephonon scattering has only a weak dependence on technology for a semiconduc-tor material of good crystalline quality.

The impact of different scattering mechanisms is describedin Fig. 2.8. It isinteresting to notice the strong impact of surface roughness at large effective fieldthat is required by MOSFETs with large substrate doping concentration in orderto operate in strong inversion. Indeed, phonon scattering and Coulomb scatteringare both strongly temperature dependent, whereas surface roughness scatteringhas a weaker dependence on temperature.

Chapter 3

Basic electrical characterization ofMOS devices

Device-level electrical characterization is a fundamental tool used to study andto verify the basic characteristics of a device. Electricalcharacterization is alsoimportant in the modeling in order to calibrate the models. In the first part of thischapter we introduce the basic electrical characterization of MOS transistors bymeans of current-voltage (I-V), capacitance-voltage (C-V), and charge-pumpingmeasurements. In the second part the proposed methods are then performed inorder to evaluate the interface state density and the mobility of MOSFETs havinga different process option.

3.1 I-V characterization

I-V characterization is usually the first step to evaluate a device measuring thecurrents at the terminals versus the applied voltages. The instrument that allowsthis kind of measurements is the parameter analyzer. In our measurement weused the HP 4156C. It provides several Source-Measure Units(SMUs) in orderto apply and to measure currents and voltages. SMUs perform Kelvin measure-ments to avoid the effects of parasitic series resistance. This measurement pro-cedure, also know as the four-wire method, consists of a stimulating line (force)with a second one in parallel (sense) (Fig. 3.1). Ohmic losses on the force lineare eliminated by the operational amplifier (op-amp) in voltage follower mode.This means that the op-amp output will exhibit a somewhat higher voltage thanthe desired test voltage at the device under test (DUT) to compensate the ohmic

20 Basic electrical characterization of MOS devices

Rs

SMUDesiredVoltage

x1

Buffer

Force

Sense

DUT

Shield

10kΩ

Figure 3.1: Schematic of a Kelvin measurement.

losses along the force line due to the flowing of the test current. The sense line,connected to the inverting input of the op-amp, guarantees that the DUT is ex-actly biased with the desired test voltage.

While this method eliminates DC errors, it does not avoid dynamic measure-ment problems such as electromagnetic influences. To solve these problems, anextra inner shielding (guard) is applied between the internal signal wire and theexternal cable shielding (triax cables). The guard is connected to a separate sec-ond op-amp which follows exactly the value of the desired test voltage. Thisauxiliary op-amp supplies the charging current for the testcables while the mainop-amp can measure the current from the DUT independently ofthis chargingproblem.

Many properties and parameters of a device can be extrapolated from the I-Vcharacterization such as the effective channel lengthLeff , the parasitic sourceand drain series resistanceRSD [14, 15], the effective mobilityµeff , the fieldeffect mobilityµfe, and the threshold voltageVTH . For the purpose of our workwe are interested in measuring the threshold voltage and thefield effect mobility.

3.1.1 Threshold voltage extraction

Many different methods have been proposed in order to extract the thresholdvoltage of MOS transistors [16]. A powerful and easy method used in this workhas been proposed by Ghibaudo [17]. This method uses the intercept of theIDS/g

1/2m function with the x-axis (Fig. 3.2), wheregm is the transconductance

and is defined as:

3.1 I-V characterization 21

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6V

GS [V]

0

1×10-3

2×10-3

3×10-3

4×10-3

I DS/g

m

1/2 [(

AV

)1/2]

VTH

Figure 3.2: Typical IDS/g1/2m characteristic for an nMOS used to extract the

threshold voltage.

gm =∂IDS

∂VGS

∣

∣

∣

∣

VDS

(3.1)

The transconductancegm is a very important parameter for analog circuit de-signers and can be extracted fromIDS−VGS curves. Indeed, see section 3.1.2,the low field transconductance, measured therefore at low VDS, is also useful inorder to estimate the carrier mobility.

3.1.2 Mobility extraction

The mobility can be extracted in different ways. In particular, depending onthe method two different mobilities for electrons in the inversion layer can beextracted: the effective and the field effect mobility.

The effective mobility can be obtained from I-V measurements in the linearregime at small VDS rearranging Eq. 2.9:

µeff = gdL

WCox(VGS − VTH)(3.2)

wheregd is the drain conductance and is defined as:


gd =∂IDS

∂VDS

∣

∣

∣

∣

VGS

(3.3)

This method is not accurate for bias conditions close to threshold voltage. Thisis mainly due for two reasons: first because the threshold voltage is not well de-fined, second because Eq. 3.2, based on the approximationQinv = Cox(VGS −VTH), is not correct close to the threshold and well above threshold where polysil-icon depletion and the inversion layer capacitance reduce the gate capacitance.However, this method is quite easy to apply.

A more accurate method is the split-CV technique [18, 19] that uses both acapacitance and a current measurement in order to extract the effective mobility.In the split-CV method the inversion charge is calculated bya C-V measurement:

Qinv(VGS) =

∫ VGS

VGSacc

CGC(V )dV (3.4)

whereVGSaccis a voltage chosen in strong accumulation, andCGC is the gate-to-

channel capacitance. The effective mobility is then extracted by:

µeff =L

W

IDS

QinvVDS(3.5)

Even if the split-CV method is the most accurate, it is also the most difficultto perform and some advanced test structures should be used [20].

Another possibility is to extract the field effect mobilityµfe [18, 21]. In thiscase Eq. 2.9 is rearranged taking its partial derivative with respect to theVGS:

µfe = gmL

WCoxVDS

(3.6)

where the transconductancegm is defined by Eq. 3.1.Both the effective mobilityµeff from Eq. 3.2 and the field effect mobility

from Eq. 3.6 are deduced by I-V characterization and simple analytical models.Specifically, the effective mobility is extracted from the drain conductancegd

while the field effect mobility from the transconductancegm. The field effectivemobility is generally lower than the effective mobility dueto a differentVGS

dependence. This fact can be easily explained explicating theVGS dependenceof the effective mobility in Eq. 2.9 [17]:

µeff =µ0

1 + θ(1 + VGS − VTH)(3.7)

3.2 C-V characterization 23

whereµ0 is the low field mobility andθ is the mobility attenuation factor.In Eq. 3.6 the field effect mobility is:

µfe =µ0

[1 + θ(1 + VGS − VTH)]2(3.8)

The quadratic dependence of the field effect mobility on theVGS explains thelower values ofµfe compared toµeff .

In our work, in order to evaluate the mobility, we use Eq. 3.6 therefore weevaluate the field effect mobility.

3.2 C-V characterization

C-V testing is widely used to determine semiconductor parameters, particularlyin MOS capacitor and MOSFET structures. C-V measurements can reveal ox-ide thickness, oxide charges, contamination from mobile ions, and interface trapdensity [22, 23]. These measurements can be used also duringthe wafer pro-cesses after each process step such as lithography, etching, cleaning dielectric,polysilicon deposition, and metalization. In this frame C-V measurements arequite useful to analyze the quality of each process step. Also reliability issuescan be investigated by the C-V characterization.

The C-V measurement consists in applying a small AC signal ontop of theDC bias across the structure and sensing the AC current at thesame frequency.Commonly, AC signals with frequencies from about1 kHz to10 MHz and peak-to-peak voltages between10 and50 mV are used. This is typically performedusing an LCR meter which measures the phase and modulus of theimpedance.In our work we used an HP 4284A.

The aim of C-V measurement in our work has been the extractionof the gateoxide capacitance by measuring both the gate-to-channel capacitance and thegate-to-substrate capacitance versus the bias applied to the gate terminal. Themeasurement configurations are reported in Fig. 3.3 and examples of measure-ment results in Fig. 3.4. In the gate-to-channel configuration (Fig. 3.3(a)) thegate, drain and source are connected to the LCR meter while the bulk is tiedto ground. This configuration measures the change in inversion charge with theapplied voltage:

CGC =dQinv

dVGS(3.9)


(a) C GC (b) C GB

SOURCE DRAIN

SUBSTRATE

GATE

BULK

SOURCE DRAIN

SUBSTRATE

GATE

BULK

Figure 3.3: Measurement configurations for the gate-to-channel capacitance (a)CGC and the gate-to-substrate capacitance (b)CGB.

-1.5 -1 -0.5 0 0.5 1 1.5Gate Voltage [V]

0.0

5.0×10-11

1.0×10-10

1.5×10-10

2.0×10-10

2.5×10-10

3.0×10-10

Cap

acita

nce

[F]

CGB

CGC

Figure 3.4: CGC , CGB characteristics for an nMOSFET.

3.3 Charge-pumping measurement 25

ICP

A

V

SOURCE DRAIN

SUBSTRATE

GATE

(a) Setup

FBV

VTH

(b) Waveform of gate voltage

Figure 3.5: Charge-pumping measurements

In strong inversionCGC=WLCox eff , whereasCGC approaches zero belowthreshold asQinv decreases exponentially. Poly-depletion and inversion layerquantization effects concur to reduce the effective oxide capacitance:

1

Cox eff

=1

Cox

+z

ε0εsi

+Wpoly

ε0εsi

(3.10)

thereforeCox eff < Cox = ε0εox/tox.

The second term of Eq. 3.10 is due to the quantization effectsthat move theinversion layer away from the interface on an average distancez (see Chapter 2),while the last term is the capacitance of a depletion layer with a widthWpoly inthe polysilicon gate. Scaling more and more the oxide thickness is becomingan important problem due to the limitations caused by the quantization and thepoly-depletion effects.

The gate-to-substrate capacitanceCGB is measured with the source and thedrain terminals grounded (Fig. 3.3(b)) and approachesCox in accumulation andthe series combination ofCox andCD = ε0εsi/WD in depletion.

3.3 Charge-pumping measurement

The Si-SiO2 interface contains electronic states with energies withinthe forbid-den bandgap. These interface states act as carrier traps anddegrade the sub-threshold slope and the mobility through Coulomb scattering.


Charge-pumping measurements are widely used to characterize interface statedensities in MOSFET devices [24].

The basic charge-pumping technique involves measuring thesubstrate cur-rent while applying voltage pulses of fixed rise time, fall time, and frequency tothe gate of the transistor, with the source and drain tied to ground (Fig. 3.5(a),(b)).When the transistor is pulsed into inversion, the surface becomes deeply depletedand electrons will flow from the source and drain regions intothe channel wheresome of them will be captured by the surface states. When the gate pulse isdriving the surface back into accumulation, the mobile charge drifts back to thesource and drain, but the charges trapped in the surface states will recombinewith the majority carriers from the substrate and give rise to a net flow of negativecharge into the substrate. This is the so-called charge-pumping effect (Fig. 3.6).

The gate pulse can be applied with a fixed amplitude, sweepingthe base levelor with a fixed base level, sweeping the amplitude. In a voltage base sweep, theamplitude and the period of the pulse are fixed while sweepingthe pulse basevoltage (Fig. 3.5(b)). At each base voltage, the substrate current can be mea-sured and plotted against the base voltage. In an amplitude sweep, the base levelis fixed while sweeping the amplitude of the pulse. In both these approaches,the basic idea is to reach the condition in which the maximum charge-pumpingcurrent can be measured. This condition is reached when the transistor is pulsedbetween accumulation and inversion, therefore from valuesbelow the flatbandvoltage to values above threshold voltage.

The interface trap density (Dit) can be extracted with the following equation:

Dit =ICP

qAf(3.11)

whereICP [A] is the measured charge-pumping current,A [cm2] is the area ofthe device, andf [Hz] is the frequency of the applied voltage pulses.

Eq. 3.11 give us the interface trap density in [cm−2]. A more appropriate wayis to calculate the effective energy levels reached by the gate pulse and to expressthe interface state density in [cm−2eV−1] [25].

For the purpose of our work we use Eq. 3.11.

3.4 Results of charge-pumping and mobility measurements 27

2

3

inversion

e− from source/drain to traps

e− in traps to substrate4

1

accumulation

ramp up

ramp down

ICP=qADitf

Figure 3.6: Energy band diagram of a nMOSFET commutating between inver-sion and accumulation and the relative CP current.

3.4 Results of charge-pumping and mobility mea-surements

In this section we present the results of both charge-pumping and mobility mea-surements to compare devices with a process split that introduces an additionalfluorine doping step to the standard process. Measured MOSFET devices weremanufactured in a0.13 µm technology [26] with a nitrided gate oxide with twothickness:tox=2.2 nm (SGox) andtox=5.4 nm (DGox). The effect of the fluorinedoping step is reported only for n-type MOSFETs. When we compare deviceswith and without the fluorine doping step we will use the symbol WF and WOF,respectively. C-V measurements on large area MOSFETs have shown that WFdevices have a lower gate oxide capacitance, therefore the fluorine doping stepcould influence the oxide dielectric constant and/or the oxide thickness. This factimplies also that the threshold voltage of the WF devices is higher than the oneof WOF devices.

Charge-pumping results

Charge-pumping measurements are done with the base voltagesweep method.


-3 -2.5 -2 -1.5 -1 -0.5 0Base voltage V

B [V]

0.0

0.2

0.4

0.6

0.8

1.0

1.2

Cha

rge-

pum

ping

cur

rent

I

CP [n

A]

nMOS DGOX

WOF

WF

Max ICP

Figure 3.7: Charge-pumping currents for nMOSFETs with DGox WF and WOF.

The switching frequency of the gate pulse is set tofsw=1 MHz with rising andfalling times tr=tf=10 ns. Charge-pumping current measured when the gatevoltage is pulsed from values belowVFB and aboveVTH is used in Eq. 3.11 toextract the interface state density. The gate voltage amplitude is set to1.6 Vand1.7 V for SGox and DGox, respectively. For each analyzed device type,Dit

is the average of interface state densities measured in six different transistors indifferent dies inside the wafer. The following devices havebeen analyzed:

• nMOS SGox WOF, Area=18.72 um2

• nMOS SGox WF, Area=18.72 um2

• nMOS DGox WOF, Area=62.4 um2

• nMOS DGox WF, Area = 62.4 um2

• pMOS SGox WOF, Area = 54.72 um2

• pMOS DGox WF, Area = 182.4 um2

Typical charge-pumping currents are shown in Fig. 3.7 whereICP as a func-tion of the voltage base for nMOSFETs with DGox with (WF) and without(WOF) the fluorine doping step is reported.


SGox WOF SGox WF DGox WOF DGox WFDit [cm−2] 1.02x1010 4.23x109 1.07x1010 2.97x109

Table 3.1: Interface state densityDit for nMOS devices with different oxidethicknesses and process steps.

SGox DGox

Dit [cm−2] 4.93x1010 1.63x1010

Table 3.2: Interface state densityDit for pMOS devices with different oxidethicknesses.

Results of charge-pumping measurements for nMOS transistors are shown inTable 3.1.

Comparing the interface state density of devices WF and WOF it is interest-ing to notice that for both the oxide thicknesses SGox, and DGox the fluorinateddevices (WF) show a lower value, so lower interface states density. This canbe explained supposing that the fluorine doping step contributes to decrease thedefect density of Si-SiO2 interface.

Table 3.2 reports the interface state density for pMOS devices with two dif-ferent oxide thicknesses showing that the DGox devices have a better Si-SiO2

interface.

Mobility results

To analyze the effect of the fluorine doping step on the carriers mobility we per-formed mobility measurement with thegm method described in section 3.1.2,thus measuring the field effect mobility. Thegm has been measured in nMOS-FETs with SGox and DGox WF and WOF having long channel (L=10 µm) andlarge width (W=10 µm). The drain-to-source voltage VDS is set to 50 mV toensure the linear regime.

In order to compare transistors with and without the fluorinedoping stephaving different threshold voltages and gate oxide capacitance, we report thetransconductancegm overCox versus the gate voltage overdriveVGS − VTH .

In Figs. 3.8 and 3.9 the transconductancegm has been reported for transis-tors with different oxide thicknesses with and without the fluorine doping step.For both the oxide thicknesses the mobility is higher in the case of devices withthe fluorine doping step. From the considerations made in section 2.2.2 and the


0 0.5 1 1.5V

GS-V

TH [V]

0.0

2.5×10-4

5.0×10-4

7.5×10-4

1.0×10-3

1.2×10-3

1.5×10-3

1.8×10-3

2.0×10-3

g m /

Cox

[S

m2 /

F] WOF

WF

nMOS SGox

Figure 3.8: Mobility measurements: nMOS with SGox with and without thefluorine doping step.

-0.5 0 0.5 1 1.5 2 2.5 3V

GS-V

TH [V]

0.0

2.5×10-4

5.0×10-4

7.5×10-4

1.0×10-3

1.2×10-3

1.5×10-3

1.8×10-3

2.0×10-3

g m /

Cox

[S

m2 /

F] WOF

WF

nMOS DGox

Figure 3.9: Mobility measurements: nMOS with DGox with and without fluo-rine doping step.


results of charge-pumping measurements, the higher mobility in fluorinated de-vices could be related to less Coulomb scattering events dueto a lower density ofinterface states. Coulomb scattering increases when a larger number of trappedcharge is present at the interface or inside the oxide. The fluorine doping step,lowering the number of interface states, reduces also the Coulomb scattering andincreases carriers mobility. Indeed, the fluorine doping step may also have aninfluence on the surface scattering reducing the micro roughness at the Si-SiO2interface.

Chapter 4

Low-frequency noise in MOSFETs

Noise in electronic circuits is generally associated to therandom fluctuationsaffecting currents and voltages. Noise cannot be completely eliminated and itsets the lower limit of the signal being processed by a circuit without significantdeterioration in the signal quality. In electronics and telecommunications animportant quantity is the signal to noise ratio (SNR). SNR represents a measureof the signal strength relative to the background noise. In acircuit the goal isto maximize the SNR paying attention on the power consumption. In moderncircuits, due to the decreasing dimensions of the devices, the signals levels arebecoming very low therefore decreasing the SNR. The study ofnoise becomesmore and more important as it aims, at the same time, to understand its basicprinciple and to find methods to reduce it. The chapter beginswith the reviewof stochastic signals and their statistical analysis. Thisbackground informationis necessary to analyze the noise in the following chapters.The second partof the chapter discusses the fundamental noise mechanisms in semiconductors:thermal noise, shot noise, generation and recombination noise, random telegraphsignal noise (RTS), and flicker noise (1/f ). In the third part of the chapter1/fnoise in MOSFETs is presented; the existing models are reviewed and the effecton flicker noise of switching the transistor between an ON- and an OFF-stateis discussed. Finally, a detailed analysis of RTS noise is reported and a MonteCarlo simulator of RTS and1/f noise under both constant and switched biasconditions is presented.

34 Low-frequency noise in MOSFETs

4.1 Background

The value of a stochastic signal at a particular time cannot be predicted due to itsrandom origin. A stochastic signal can be described by its statistical properties.In this section a brief introduction to stochastic signals and to the techniques fortheir time and frequency domain analysis is reported.

Stochastic signals

A stochastic signal is the counterpart to a deterministic signal. Each value of adeterministic signal is fixed and can be determined by a mathematical expression,rule, or table. Because of this, future values of any deterministic signal can becalculated from past values. For this reason, these signalsare relatively easy toanalyze as they are predictable, and we can make accurate assumptions abouttheir past and future behavior.

Unlike deterministic signals, stochastic signals, or random signals, cannot becharacterized by a simple, well-defined mathematical equation and their futurevalues cannot be predicted. Rather, we must use probabilityand statistics toanalyze their behavior.

A collection of stochastic signals rather than just one instance of that signalis called a stochastic process (Fig. 4.1). At each time the value assumed by theprocess is unknown. The value of the process at a certain timet1 is completelyrandom, therefore, i(t1) is a random variable.

Describing stochastic signals

The expected valueof a stochastic signalx(t) is its time average and it is alsocalledmean valuemx(t). It is given by:

E[x(t)] ≡ mx(t) = limT→∞

1

T

∫ +T/2

−T/2

x(t)dt (4.1)

The expected value ofx(t) represents also thefirst momentof the stochasticsignal. Thenth moment of a stochastic signal is the expected value ofx(t)n andit is given by:

E[x(t)n] = limT→∞

1

T

∫ +T/2

−T/2

x(t)ndt (4.2)

4.1 Background 35

i1(t)

i (t)2

i (t)3

t=t

i(t ) is a random variable1

1

t

t

t

Figure 4.1: Representation of a stochastic process (e.g.. noise) as a function oftime.

The2nd moment of[x(t)−mx(t)] is the variance (σ2) of the stochastic signal:

σ2 ≡ E[(x(t)−mx(t))2] = lim

T→∞

1

T

∫ +T/2

−T/2

(x(t)−mx(t))(x(t)−mx(t))dt (4.3)

The autocorrelation function of a stochastic signalx(t) is:

Rxx(t, t + τ) = E[x(t)x(t + τ)]

= limT→∞

1

T

∫ +T/2

−T/2

x(t)x(t + τ)dt (4.4)

while the autocovariance is defined as:

Cxx(t, t + τ) = E[(x(t) − mx(t))(x(t + τ) − mx(t + τ))]

= limT→∞

1

T

∫ +T/2

−T/2

(x(t) − mx(t))x((t + τ) − mx(t + τ))dt(4.5)

The only difference between the autocorrelation and the autocovariance isthat in the autocovariance the mean is subtracted from the input data. If the


mean of a stochastic signal is zero the two functions are identical. Therefore, theautocorrelation is more complete and, in general, the autocovariance functionshould be only used in the specific case where the intent is to disregard the meanof a non-zero mean stochastic signal.

When one considers electric circuits, it is possible to relate the moments of astochastic signalx(t) to characteristic quantities:

• The1st moment ofx(t), mx(t), is theDC component.

• The2nd moment ofx(t) is thetotal power.

• The2nd moment of [x(t) − mx(t)], σ2, is theAC power.

Stationary, ergodic and cyclostationary stochastic signals

A stochastic signal isstationaryif the moments of the signal are not a functionof time. In particular, if this is true for the moments of any order the signal isstrictly stationary. In case this is satisfied for all moments up to and includingthe second one, the signal iswide-sense stationary. If the signal is wide-sensestationary, the autocorrelation function defined in Eq. 4.4will be a function ofthe time differenceτ only and no longer of the absolute timet:

Rxx(t, t + τ) = Rxx(τ) (4.6)

A stochastic signal isergodic if the ensemble average (average of instanta-neous values over a number of realizations) is equal to the time average of onerealization of the signal. A signal is ergodic in the strict sense if all its momentare ergodic; it is wide-sense ergodic if the first and second moments are ergodic.Stationarity is a necessary condition for a signal to be ergodic, on the other hand,stationary signals are not necessarily ergodic.

A signal whose moments of any order are periodic inT is said to bestrictlycyclostationaryin T . A cyclostationary signal is defined wide-sense cyclosta-tionary if its mean and its autocorrelation function are periodic in T [27, 28]:

mx(t) = mx(t + T )

Rxx(t, t + τ) = Rxx(t + T, t + T + τ)(4.7)

4.1 Background 37

Power and energy of a stochastic signal

The power of a stationary stochastic signalx(t) is expressed as:

P = limT→∞

1

T

∫ +T/2

−T/2

x2(t)dt (4.8)

while the total energy is:

limT→∞

TP =

∫ +∞

−∞

x2(t)dt (4.9)

PSD and the Wiener-Khinchin theorem

In the frequency domain analysis the basic mathematical tool is the Fourier trans-form. The Fourier transform allows the analysis of signals both in the frequencyand in the time domain. The Fourier transform (FT) and its inverse (IFT) of astochastic signalx(t) are defined by:

X(f) =

∫ +∞

−∞

x(t)e−2jπftdt (4.10)

x(t) =

∫ +∞

−∞

X(f)e2jπftdf (4.11)

The power spectral density (PSD) of a signal is a plot of the power per unit ofbandwith as a function of the frequency. The Wiener-Khinchin theorem relatesthe autocorrelation function to the PSD of the stochastic signal [29]:

S(f) = FT (Rxx(t, t + τ)) (4.12)

The power (P ) of the signal can be expressed in the time domain and in thefrequency domain as:

∫ +∞

−∞

S(f)df = limT→∞

1

T

∫ +T/2

−T/2

x2(t)dt (4.13)

Another way to calculate the PSD, without first calculating the autocorrela-tion function, is:


S(f) = limT→∞

|X(f)|2T

(4.14)

The PSD contains less information than the signal in the timedomain. Whilecomputing the PSD with Eq. 4.12, we should consider that different time domainsignals may have the same autocorrelation function, hence,the same PSD. Bycomputing the PSD with Eq. 4.14, we discards phase information by taking themagnitude ofX(f). However, the PSD of a stochastic signal is very useful,keeping in mind that for some particular needs, a time domaindescription ismandatory.

4.2 Noise sources

The current flowing in a device under DC conditions can be written asI(t) =

IDC + in(t), whereIDC is the wanted current due to the chosen bias point, whilein(t) is a random fluctuating current related to the noise. This latter current canbe caused by external noise sources and by fundamental physical processes. Ex-ternal sources are for example cross-talk between adjacentcircuits, electrostaticand electromagnetic coupling from AC power lines, vibration etc. These dis-turbances can often be eliminated by shielding, filtering, and change of layout.Fundamental physical sources cannot be eliminated, but it is however possibleto reduce them by proper design of the devices and circuits. In this work we areinterested only in these latter sources. A brief introduction on fundamental noisesources is reported below.

4.2.1 Thermal noise

Thermal noise, also called Nyquist or Johnson noise, is the noise associated withthe thermal random motion of charge carriers. The direct current has no influ-ence on the thermal noise since the electron drift velocity is much less than theelectron thermal velocity. Considering a piece of materialwith a resistanceRat a temperatureT , thermal noise can be represented by a current generator (i2)parallel toR or a voltage generator (v2) in series toR:

i2 = 4kT1

R∆f ; v2 = 4kTR∆f (4.15)

wherek is the Boltzmann’s constant and∆f is the bandwidth in Hertz. Eq. 4.15shows that thermal noise is proportional to the absolute temperature and it ap-

4.2 Noise sources 39

proaches zero if the temperature approaches zero. The PSD ofthermal noise isalso independent of frequency. All noise sources which are independent of fre-quency are calledwhite noisesources. This is because all different frequenciesare present with the same strength.

4.2.2 Shot noise

Shot noise is associated to the direct current flowing acrossa potential barrierlike a pn-junction. Shot noise is caused by the random fluctuation of the electriccurrent due to the discrete nature of the electronic charge (electrons). The noiseincreases proportionally to the flowing current crossing the potential barrier. Themean square value of the current associated to the shot noiseis:

i2 = 2qI∆f (4.16)

whereq is the electronic charge. Shot noise is independent of frequency andit should be distinguished from the current fluctuations at equilibrium, whichare present without any applied voltage or without any average current flowingthrough the device.

4.2.3 Generation-recombination noise

Generation-recombination (g-r) noise in semiconductors stems from traps thatrandomly capture and emit carriers acting as generation-recombination centers.These events cause fluctuation in the number of carriers available for currenttransport. The trapped charge can also induce fluctuations in the mobility, elec-tric field, barrier height etc. Traps involved in g-r noise are located in the forbid-den bandgap and they exist due to the presence of various defects or impurities inthe semiconductor or at its surfaces. The power spectral density of g-r noise is aLorentzian [30]. A single trapping/detrapping process leads to random telegraphsignal (RTS) noise.

4.2.4 Flicker or 1/f noise

Flicker noise is present in active as well passive devices and may be due to sev-eral mechanisms as it will be discussed in the next section. Flicker noise isassociated with the flow of a direct current and the mean square value of thecurrent affected by this kind of noise is:


i2 = KIβ

fγ∆f (4.17)

whereK is a constant associated with the device,I is the direct current,β is thecurrent exponent with a value between 0.5 and 2, andγ is a parameter with avalue close to 1. Consideringγ = 1 in Eq. 4.17, the noise spectral density is pro-portional to1/f and for this reason flicker noise is also called ’1/f ’ noise. In thecase the parameterγ has values outside the range 0.9-1.1, the noise is referred as1/f -like noise. Flicker noise is most significant at low frequencies while it dis-appears under thermal noise at higher frequencies. However, in devices showinga high level of1/f it can dominate also in the MHz range. Flicker noise is alsocalledpink noisebecause of the frequency dependence of the spectral density.1/f noise occurs in many different systems and sometimes the suggestive adjec-tive ’ubiquitous’ is associated to this noise. It is possible to find1/f noise, inbiology, astronomy, fluid dynamics, optical systems and economics.

4.3 MOSFETs 1/f noise model

MOSFETs are particularly affected by low-frequency noise having a spectraldensity inversely proportional to the frequency (1/f or 1/f -like noise). 1/f

noise in MOSFETs has been under investigation since more than forty years [31].Despite the efforts to identify the origins of this noise, there is still not a uniqueaccepted theory and therefore a model to simulate flicker noise. Two differenttheories have been proposed to explain the physical originsof 1/f noise: num-ber fluctuation and mobility fluctuation. These two theoriesare based on thefluctuation of the conductivity of MOS transistors that is:

σ = µnq (4.18)

whereµ andn are the mobility and the concentration of the carriers, respectively.Hence, from Eq. 4.18 it is clear that a fluctuation of the conductivity is inducedeither by a fluctuation of the number of carriers (∆N) or a fluctuation in thechannel mobility (∆µ).

4.3.1 ∆N model

The carrier number fluctuation theory [32, 33, 34, 35], originally proposed byMcWhorter [36], attributes the origin of flicker noise to therandom trapping and

4.3 MOSFETs 1/f noise model 41

SUBSTRATE p−type

GATE

GATE OXIDE

SOURCE DRAIN

n+n+

Figure 4.2: Schematic illustration of trapping/detrapping of electron in/fromtraps for a nMOSFET.

detrapping of charge carriers into or from traps located inside the oxide. Trap-ping/detrapping process from a single trap leads to an RTS. Each trap is charac-terized by a relaxation timeτ that depends on the mean time needed for the trap-ping process and the mean one needed for detrapping. The trapping/detrappingprocess occurs through the tunneling of charge carriers from the channel intotraps located inside the oxide and vice versa. A schematic illustration is repre-sented in Fig. 4.2.

For a given trap characterized by the relaxation timeτ , the occupation func-tion N(t) is defined as:N=1 when the trap is occupied,N=0 when the trap isempty. The power spectral density ofN(t) is given by:

SN(τ) = (∆N)2 4τ

1 + (2πf)2τ 2(4.19)

When several traps are present with time constantsτ distributed as:

g(τ) =

K/τ if τ1 < τ < τ2

0 otherwise(4.20)

The superposition of RTS signals due to each traps gives a1/f noise with PSDgiven by:


100

101

102

103

104

Frequency [Hz]

10-6

10-5

10-4

10-3

10-2

10-1

S [a

rbitr

ary

units

]

1/f

Figure 4.3: The superposition of 4 Lorentzians gives a total power spectraldensity roughly proportional to1/f over several decades of frequency.

S(f) =

∫ ∞

0

g(τ)SN(τ) dτ

=

∫ ∞

0

K

τ(∆N)2 4τ

1 + (2πf)2τ 2dτ

=4K(∆N)2

2πf[arctan(2πfτ)]τ2τ1

S(f) ≈ K

f(∆N)2 for 1/2πτ2 << f << 1/2πτ1

(4.21)

An example is given in Fig. 4.3 where the superposition of theeffects of fourindividual traps with different relaxation times roughly gives a1/f spectrum. Inorder to extend the1/f spectrum over ten decades, the spread in time constantsmust cover many order of magnitude. In MOSFETs the tunnelingin the oxidemay account for relaxation times between 10−5 s and 10+8 s. McWhorter showedas a uniform spatial distribution of oxide traps can give rise to a distribution oftime constants giving the1/f spectrum typical of MOS transistors [36]. Even ifthe number fluctuation model is supported by many experiments [34, 37, 38, 39,40], some remarks are necessary. First, it is assumed that the RTS noise of eachsingle trap can be simply added. This is true only if traps areisolated and do

4.3 MOSFETs 1/f noise model 43

not interact with each other. Secondly, each trap should be coupled to the outputcurrent in the same way (same values forK in Eq. 4.20 for all traps).

4.3.2 ∆µ model

A second mechanism that can give a1/f noise is the mobility fluctuation. Thenoise of homogeneous layers can be described by Hooge’s empirical formula[41, 42, 43]:

SI

I2=

αH

fN(4.22)

whereI is the current flowing through the sample,SI is the spectral density ofthe noise affecting the current,N is the number of free carriers, andαH is theHooge’s parameter that usually can assume values between10−6 and10−4 [44].

The step now is to determine whether the conductivity fluctuates becauseof fluctuations in the number of carriers or in their mobility. While numberfluctuation can be a reason to explain the conductivity fluctuation in MOSFETs,obviously this cannot be the case in metals.

The only way to separate the∆N and∆µ is to measure an effect that doesnot involve annµ product. Such effects are the Hall effect, hot electron effects,etc. [44, 45]. An experimental example of the Hall effect in GaAs is presentedin [46], where the noise measured across the Hall contacts follows the mobilityfluctuations (∆µ).

The mobility is determined by the scattering of free carriers. A scatteringmechanism that is always present is caused by the acoustic lattice vibrations.However, other scattering mechanisms might be present in a MOSFET: impurityscattering by charged or neutral centers, surface scattering against the crystalboundaries, and carrier scattering by other carriers. The study of 1/f noise isof special interest when at least two different scattering mechanisms are present.Considering therefore the case of a varying amount of impurity scattering, to-gether with the always present lattice scattering, the contribution of the twomechanisms to the resulting mobility can be expressed with the Matthiessen’srule:

1

µ=

1

µlatt+

1

µimp(4.23)

The observed noise is plotted aslogαH versuslogµ [47]. TheαH −µ depen-dence experimentally found can only be explained by assuming 1/f noise in the


lattice scattering while the other mechanisms are noise free. From Eqs. 4.22 and4.23 following [44, 45, 46] we get:

1

µ

(

∆µ

µ

)

=1

µlatt

(

∆µlatt

µlatt

)

+ 0 (4.24)

αH =

(

µ

µlatt

)2

αlatt (4.25)

Measuring the noise in the intensity of scattered light provides an indepen-dent way of proving that the intensity of acoustic lattice modes fluctuates with a1/f spectrum [44].

4.3.3 Unified∆N and ∆µ model

Both ∆N and∆µ theories try to explain and to find correlation between exper-iments and arguments to support one or the other theory. In MOSFETs, wherethe charge transport is at the interface, the number fluctuation model apparentlyprovides a better explanation of the origin of1/f noise. Some measurementson devices fabricated with different CMOS processes featuring different oxidethicknesses suggest that flicker noise in nMOS transistors behaves as predictedby the number fluctuation model [48]. In the same study, however, pMOS tran-sistors show a lower1/f noise which is well explained by the mobility fluctua-tion model.

An extensive analysis of flicker noise in MOSFETs gives a morecompli-cated bias dependence on the gate bias and on the oxide thickness that cannot bepredictable by only the number fluctuation or only mobility fluctuation modelsalone. Hung [49, 50] proposed a unified model that assumes correlated mobil-ity and number fluctuations. The surface mobility fluctuations are attributed tothe remote Coulomb scattering due to oxide charges. As mobility and numberfluctuations have the same source of origin they are correlated. It is importantto remark that the correlated mobility fluctuations in the Hung’s unified modelare different from the mobility fluctuation previously discussed in the∆µ modelwhose origin is due to phonon scattering. The unified model isthe most usedone among those adopted to simulate flicker noise in circuit design tools. It isable to explain most of the experimental data; when this is not true [51], it usesnon-physical fitting parameters. The model unifies the number fluctuation modelwhich dominates at low bias and the mobility model which is mostly effective athigh bias.

4.4 Flicker noise under switched bias conditions 45

V

VGS_OFF

VGS_ON

IDS + inoise

TH

Figure 4.4: nMOSFET cycled between an ON-state (VGS ON ) and an OFF-state(VGS OFF ).

4.4 Flicker noise under switched bias conditions

Flicker noise has a large influence in circuits using MOSFET transistors. There-fore, in the last years a lot of circuit techniques have been proposed in order toreduce its impact [52, 53, 54, 55, 56]. These techniques are anyway unable toreduce the intrinsic1/f noise in MOSFETs.

Bloom and Nemirovsky [6], for the first time, showed that by cycling aMOSFET between strong inversion and accumulation a reduction of the low-frequency noise occurs. Indeed, [7] reported that also RTS noise generated bya single trap is strongly reduced when the MOSFET is cycled between inver-sion and accumulation. The effect was again observed in ringoscillator phasenoise [8] fabricated with a CMOS process.

In Fig. 4.4 the basic principle of cycling a nMOSFET between an ON-stateand an OFF-state is illustrated. The input voltage applied to the gate terminal isswitched between an ON- and an OFF-state with a pulse signal with 50% dutycycle. Such a bias it is usually called switched bias (SB), the counterpart to afixed constant bias (CB). The high level (VGS ON ) is higher than the thresholdvoltage in order to bias the transistor in inversion, while the low level (VGS OFF )is set below the threshold voltage.VGS OFF can be set to have the transistor inmoderate inversion, weak inversion or in accumulation. In this configuration anintrinsic reduction of the low-frequency noise, compared to constant bias condi-


tions, is due to the fact that the device is OFF for half a period. This translatesin an intrinsic reduction by a factor of 4 in the resulting PSDof the noise [57]due to the mixing effect of low frequencies to higher frequencies. Hence, in theanalysis presented in this work, the PSD in the case of constant bias is usuallydivided by a factor of 4 in order to be compared to the PSD underswitched biasconditions.

In the last years new progresses in this field have been made. Anew mea-surement approach that allows the observation of1/f noise spectra in MOSFETsunder switched bias conditions in a wide frequency band (10 Hz - 100 kHz) hasbeen reported in [57]. They investigated in particular the dependence of flickernoise on the switching frequency and on the voltage applied in the OFF-state.

4.5 Background of Random Telegraph Signal

In this section we provide the necessary background of RTS noise in order toexplain and to analyze experimental results.

4.5.1 Statistical properties of RTS

RTS is a random sequence of pulses that switch between two levels: a high and alow state (Fig. 4.5). In our work, we are interested in the RTSnoise superimposedto the drain current of small-area MOSFETs. We can associatethe state 1 to thehigh level, and the state 0 to the low level. We assume that theprobability ofa transition from the state 1 to the state 0 (i.e. from up to down) is given by1/τ1, the probability of a transition from 0 to 1 is1/τ0. We also assume thatthe transitions are instantaneous. Under these assumptions, we show that therandom variables representing the times spent in states ”high” and ”low” areexponentially distributed and therefore RTS is a Poisson process.

Let us assumep1(t)dt the probability that no transition occurs from the state1 during the time intervalt and then a transition happens betweent andt + dt.If P (t) is the probability of remaining in the ”high” state without making anytransition during the time interval t, we get:

p1(t) = P (t)/τ1 (4.26)

remembering the assumption that1/τ1 is the probability of making a transitionfrom state 1 to state 0.

4.5 Background of Random Telegraph Signal 47

time

high (1)

low (0)

stat

e

Figure 4.5: A Random Telegraph Signal (RTS).

We have also that:

P (t + dt) = P (t)(1 − dt/τ1) (4.27)

that means that the probability of not making a transition attime t + dt is equalto the product of the probability of not having made a transition at timet andthe probability of not making a transition during the interval from t to t + dt.Rearranging Eq. 4.27 we obtain:

dP (t)

dt= −P (t)

τ1(4.28)

Now we need to integrate Eq. 4.28 and we get:

P (t) = exp(−t/τ1) (4.29)

With P (0) = 1 we get:

p1(t) =1

τ1exp(−t/τ1) (4.30)

and

∫ ∞

0

p1(t)dt = 1 (4.31)

Following the same procedure for the state ”low” we obtain:

p0(t) =1

τ0

exp(−t/τ0) (4.32)

From this analysis, starting with the assumption that the transitions betweenthe high/low and the low/high states are described by singlerates, we can showthat the times spent in the high/low states are exponentially distributed. Themean time spent in the state ”high” is:


∫ ∞

0

tp1(t)dt = τ1 (4.33)

and the standard deviation is:

σ ≡[∫ ∞

0

t2p1(t)dt − τ 21

]

= τ1 (4.34)

To conclude we can say that an RTS signal is characterized by switchingbetween two states, high and low, and that the time spent in both states is expo-nentially distributed. This shows that RTS is a Poisson process. To each state it ispossible to associate a mean timeτ1 andτ0. We have also seen that the standarddeviation is equal to the mean time spent in either state of the RTS and this isnormal for a Poisson process.

4.5.2 PSD of RTS: Lorentzian spectrum

Here we derive the power spectral density of an RTS signal as proposed byMachlup [30]. We need first to evaluate the autocorrelation function of the RTS.In order to do that we suppose that the RTS can be in two states,0 (low) and 1(high), and that the amplitude of the signal is∆I. We assume also that all thestatistical properties are independent of the time origin.We know that the meantime spent in the state 1 isτ1 while the mean time spent in the state 0 isτ0. Theprobability that the RTS is in the state 1 is thereforeτ1/(τ0 + τ1), for the state 0is τ0/(τ0 + τ1).

The autocorrelation function of such an RTS process is:

Rxx(t) =< x(s)x(s + t) >

=∑

i

∑

j

xixj × Prob. thatx(s) = xi

× Prob. thatx(s + t) = xj , givenx(s) = xi

(4.35)

Since the low state of the RTS is chosen to be 0 and the RTS amplitude is∆I, the autocorrelation function is:

Rxx(t) = (∆I)2 τ1

τ0 + τ1P11(t) (4.36)

whereP11(t) is the probability of an even number of transitions during the timeinterval t, starting from state 1. Defining in a similar wayP10(t) the probabilityof an odd number of transitions in time interval t, starting from state 1 we have:

4.5 Background of Random Telegraph Signal 49

P11(t) + P10(t) = 1 (4.37)

The probability of an even number of transitions in timet + dt is given by thesum of two mutually exclusive events. The first is the probability of an oddnumber of transitions during the time interval t and one transition during dt; thesecond is the probability of an even number of transitions intime interval t andno transition during dt:

P11(t + dt) = P10(t)dt

τ0+ P11(t)

(

1 − dt

τ1

)

(4.38)

By lettingdt → 0 and substituting Eq. 4.37 into Eq. 4.38, we obtain the followingdifferential equation forP11(t):

dP11(t)

dt+ P11(t)

(

1

τ0+

1

τ1

)

=1

τ0(4.39)

Eq. 4.39 can be solved by usingexp[∫

(1/τ0 + 1/τ1)dt] as an integrating factor:

P11(t) =τ1

τ0 + τ1

+τ0

τ0 + τ1

exp

[

−(

1

τ0

+1

τ1

)

t

]

(4.40)

The power spectral density can be calculated from Eqs. 4.36 and 4.40 applyingthe Wiener-Khinchin theorem:

S(f) = 4

∫ ∞

0

Rxx(t)cos(2πfτ)dτ

=4(∆I)2

(τ0 + τ1)[(1/τ0 + 1/τ1)2 + (2πf)2]

(4.41)

where the DC term, a delta function atf=0, has been ignored.In the case of RTS with equal mean times in the high and in the low state,

τ0=τ1=τ , Eq. 4.41 becomes:

S(f) =2(∆I)2τ

4 + (2πfτ)2(4.42)

The total average power is obtained by integratingS(f) over all frequencies:

P =

∫ ∞

0

S(f)df =(∆I)2

(τ0 + τ1)(1/τ0 + 1/τ1)(4.43)


100

101

102

103

104

Frequency [Hz]

10-21

10-20

10-19

10-18

10-17

10-16

10-15

PS

D [

A2 /Hz]

τ0=10ms

τ0=1ms

τ0=0.1ms

τ0=0.1s τ0=1s

1/f 2

τ1=10ms

Figure 4.6: Power spectral density of RTS noise withτ1=10 ms and differentvalues ofτ0. The PSD is a typical Lorentzian, flat at low frequencies and aroll-off of 1/f 2 at high frequencies.

In Fig. 4.6 the PSD from Eq. 4.41 is reported for∆I=200 nA, τ1=10 mswhile τ0 is varied. RTS features a typical Lorentzian PSD characterized by aconstant plateau at low frequencies and a1/f 2 roll-off above a characteristiccut-off frequencyft=1/2π(1/τ0 + 1/τ1).

Fig. 4.7 reports the power associated to the RTS from Eq. 4.43. The am-plitude of the RTS is∆I=200 nA andτ1=10 ms. τ0 is varied between0.1 msand1 s. The power shows a maximum whenτ0 is equal toτ1. In this work,the relation between RTS time constants and the noise power is quite important,especially when we analyze RTS noise under switched bias conditions.

4.6 RTS noise in MOSFETs

As already stated, in this thesis we are interested in the RTSnoise that affectsthe drain current of small-area MOS transistors. In MOSFETs, RTS noise iscaused by the trapping/detrapping of charge carriers into/from traps that can belocated at the Si-SiO2 interface or in the bulk of the gate oxide. In this scenarioit is possible to associate the mean time spent by the currentin the high or in the

4.6 RTS noise in MOSFETs 51

10-4

10-3

10-2

10-1

100

τ0 [s]

10-16

10-15

10-14

P [

A2 /H

z] τ0=τ1

τ0<τ1 τ0>τ1

τ1=10ms

Figure 4.7: Power of RTS noise withτ1 =10 ms and different values ofτ0. ThePSD shows a maximum forτ0 = τ1.

low state with the mean emission or capture timesτe andτc. To associateτe andτc to the state of the current some considerations must be done and this will bediscussed in the next chapter. For the purpose of the next part of this chapter itis enough to know that the emission and capture time constants are associated tocapture and emission of charge carriers by a trap.

As for flicker noise, also RTS noise can be measured and modeled under bothconstant bias (CB) and switched bias (SB) conditions. In particular, in the lastyears, some important steps have been done in the modeling and in the character-ization of RTS noise under SB conditions. In [58] measurements and simulationof RTS noise in nMOSFETs under switched gate bias conditionshave been pro-posed. They have shown that the simple model of a stationary noise generatingprocess whose output is modulated by the bias voltage is not sufficient to ex-plain the switched bias measurement results. This is due to the fact that a simplemodulation should give a noise reduction of a factor of 4, while experimentalresults showed devices where the noise reduction could be both higher or lowerthan this factor. Therefore, they proposed a model based on cyclostationary RTSnoise generation. A new physical model, reproducing the transient behavior andpredicting the RTS noise under switched bias conditions hasbeen proposed in[59].


4.6.1 RTS under constant bias conditions

The expressions for the autocorrelation function and the power spectral densityreported in the previous section following the Machlup’s [30] approach can beused to model the RTS noise of MOSFETs operating under constant bias condi-tions.

The autocorrelation function can be rewritten as:

Rxx ∝ γ(1 − γ)e(−|t|/τ) (4.44)

while the PSD as:

PSD ∝ γ(1 − γ)τ

1 + (2πfτ)2(4.45)

where:

τ =τeτc

τe + τc

(4.46)

γ =τe

τe + τc(4.47)

1 − γ =τc

τe + τc(4.48)

It is important to notice thatγ represents the occupation probability of a trapunder constant bias conditions.

4.6.2 RTS under switched bias conditions

As we have seen in section 4.4, a transistor may be switched between an ON-and an OFF-state. To do that it is necessary to apply to the gate terminal a puls-ing waveform that biases the transistor between strong inversion and subthresh-old/accumulation. Under this operating condition, the emission and the capturetime constants of the RTS noise are modulated. Even if obvious, it is importantto remark that, when the transistor is in the OFF-state, no current flows and sothe emission and the capture times are not directly measurable.

Kolhatkar in [60] proposes an experimental method to measure the emissionand capture time constants under SB conditions. This method, represented inFig. 4.8, consists in sampling the RTS during the ON-states and then, joiningthe sampled values together, the RTS under SB conditions is obtained. This

4.6 RTS noise in MOSFETs 53

Figure 4.8: RTS noise under constant bias and switched bias conditions. RTS issampled during the ON-states and joining the sampled valuestogether the RTSunder SB conditions is obtained. The ON-state is indicated by the shaded partand the OFF-state by the white part (source [60]).

method will be used in this work in Chapter 6. The expressionsof the emissionand capture time constants under SB are now derived following the approachproposed by Kolhatkar in [60].

Let’s consider a pulse waveform applied to the gate switching between anON- and an OFF-state with a switching periodTsw, beingTon andToff the timespent in the ON- and in the OFF-state, respectively. Kolhatkar associates to theON- and to the OFF-state different time constants:τe on andτc on to the ON-state,andτe off andτc off to the OFF-state.

The effective time constants in the ON- and in the OFF-state are expressedin a similar way as in Eq. 4.46 as:

τeff on =τc onτe on

τc on + τe on

(4.49)

τeff off =τc offτe off

τc off + τe off(4.50)

The effective emission and capture time constants are givenby:

1

τe eff=

Ton

Tsw

1

τe on+

Toff

Tsw

1

τe off(4.51)


1

τc eff=

Ton

Tsw

1

τc on+

Toff

Tsw

1

τc off(4.52)

Therefore, from expressions above we can express the effective τ as:

τeff =τe effτc eff

τe eff + τc eff(4.53)

The autocorrelation function and the PSD under switched bias conditionsbecome:

Rxx ∝ γ(1 − γ)e(−|t|/τeff ) (4.54)

PSD ∝ γ(1 − γ)τeff

1 + (2πfτeff)2(4.55)

where:

γ =τe eff

τe eff + τc eff

(4.56)

1 − γ =τc eff

τe eff + τc eff

(4.57)

γ represents also the effective occupation probability of a trap (Peff ) underswitched bias conditions.

We can still write the occupation probability in the ON-state as:

Pon =τe on

τe on + τc on(4.58)

and in the OFF-state as:

Poff =τe off

τe off + τc off

(4.59)

4.7 Monte Carlo simulation of RTS and 1/f noise

As we have seen in section 4.5.1, the emission and capture times of an RTS areexponentially distributed and RTS is therefore a Poisson process. The MonteCarlo (MC) simulation technique is ideally suited to simulate Poisson processes.

Supposing that the mean time associated with a Poisson process isτ0, we cangenerate a Poisson stochastic time between two distinct events of the process as[61]:

4.7 Monte Carlo simulation of RTS and 1/f noise 55

tr = −τ0ln(1 − r) (4.60)

wherer is a random number uniformly distributed between 0 and 1. However,sincer is uniformly distributed between0 and1, so also is(1−r), and in practice,in place of Eq. 4.60 we can use:

tr = −τ0ln(r) (4.61)

An RTS process is characterized by two possible states: empty trap and oc-cupied trap. Two characteristic times,τc andτe, are associated to such states:τc

is the mean time for an empty trap to capture a charge carrier,τe is the meantime for the trap to emit a charge carrier. Therefore each occurrence, trappingand detrapping, is conditioned by the other one. For example, a trapping event ispossible only if before a detrapping event occurred. Dealing with a process withtwo characteristic time constants, we need to substitute inEq. 4.61 the appropri-ate one according to the current state of the trap. Simulating an RTS process weuseτe if the trap is occupied and, hence, the next occurrence is a detrapping,τc

otherwise.

4.7.1 MC under constant bias conditions

Under constant bias conditions a fixed bias is applied to the gate of the transis-tor. In small-area MOSFETs, a single trap affects the drain current leading tothe switching of the current between a high and a low value. This is due to thetrapping and detrapping of charge carriers into or from the trap. The core of thesimulation of RTS noise is therefore the evaluation of the occupation state ofa trap as a function of the time. The simulation of the occupation state of thetrap is performed as follows: initially a check on the state of the trap is done:free or occupied; then the state of the trap is changed after a certain time in-terval tr according to Eq. 4.61 in which the appropriate time constantis used.When the occupation state of a trap changes, it contributes to the noise superim-posed to the drain current. The amount of this contribution depends on severalfactors, among them the position of the trap inside the gate oxide. A way totake into account this fact in the simulation, is to ”weight”the contribution ofthe occurrence (trapping/detrapping) to the current. In other words it means toreflect the trapping/detrapping process to a certain variation of the drain current(∆I). What we then obtain is a time domain RTS signal reproducingthe effect of


trapping/detrapping process on the drain current. This signal switches thereforebetween two different states with mean times given byτe andτc and amplitude∆I. In a second part of the simulation the autocorrelation function of the RTSsignal and the Fourier transform of the autocorrelation arecalculated in order toget the power spectral density of the simulated RTS.

4.7.2 MC under switched bias conditions

Under switched bias conditions a pulse waveform is applied to the gate of thetransistor biasing the transistor between inversion and subthreshold/accumula-tion conditions, therefore between an ON- and an OFF-state.As described insection 4.6.2, we can model the effect of a switching bias by assuming differenttime constants during the ON- and the OFF-state. Adopting this approach wecan therefore associate an emission time constant to the ON-and to the OFF-state,τe on andτe off , respectively, and a capture time constant to the ON- andto the OFF-state,τc on andτc off , respectively. We have therefore to deal withfour different time constants. A quasi stationary assumption is done for mod-eling the emission and capture time constants:τe on and τc on are assumed tobe the emission and capture time constants corresponding tothe CB case withVGS=VGS ON . While τe on andτc on are measurable because the transistor is ONand a net drain current is flowing, this is not possible when the transistor is inthe OFF-state and no current flows. In order to model the time constants in theOFF-state we use the approach proposed in [58] where the relationships betweenthe time constants in the ON- and in the OFF-state are assumedas:

τe off = τe on/m

τc off = τc on × m(4.62)

where the parameterm is a positive number. The characteristic of this approachby taking the capture time constant in the OFF-state as the one in the ON-statemultiplied by the constantm is physically supported by considering that thecapture of a carrier is unlikely in the OFF-state of the device since no carriers arepresent in the channel.

Under these assumptions, the simulation differs only slightly compared to theone under constant bias conditions. In particular, under switched bias conditionsit is necessary to know at each simulation time, not only the state of the trap, butalso the state of the bias, ON or OFF. According to this two variables, state of


0 1 2 3 4 5Time [s]

0

0.2

0.4

0.6

0.8

1A

utoc

orre

latio

n

MC simulatione

-|t|/τ

τ=0.5s

τe=1s, τ

c=1s

Figure 4.9: Monte Carlo simulation and analytical model of the autocorrelationof an RTS under CB withτe=τc=1 s.

the trap and state of the bias, the appropriate time constantmust be chosen inEq. 4.61. Indeed, under SB the drain current of the device is switched and, whenthe gate bias is OFF, no current flows in the transistor. That means that the RTSnoise under SB is modulated by a square wave. Therefore, the drain current ofthe device can be considered as the product of two signals: the contribution ofthe trap giving the RTS and the square wave applied to the gate. It is important toreamark, see Fig. 4.8, that RTS continues to exist even when it cannot be directlyobserved because no current is flowing in the device. The square wave appliedto the gate with a certain switching frequencyfsw contributes in the frequencydomain with a series ofδ functions at0 Hz,±fsw, ±3fsw, ±5fsw, ....

From Eqs. 4.51, 4.52, 4.62 we obtain:

τe eff =2

m + 1τe on

τc eff =2m

m + 1τc on

(4.63)

Analyzing Eqs. 4.62 and 4.63 we can see as a change inτc off is not as impor-tant as a change inτe off . In the limit case of takingm → ∞, τc eff becomestwice τc on. On the other hand,τe eff can change by several orders of magnitude


10-2

10-1

100

101

102

103

Frequency [Hz]10

-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

PS

D [a

.u.]

MC simulationanalytical model

τe=1s, τ

c=1s

CB

Figure 4.10: Monte Carlo simulation and analytical model of the PSD of anRTS under CB withτe=τc=1 s.

compared toτe on. Further details on this approach are discussed in [58].

4.7.3 Validation

In order to validate the MC simulator, simulations under CB and SB conditionsare performed and compared to the analytical models. Under CB we simulateboth the autocorrelation function and the power spectral density of an RTS withemission and capture time constantsτe=τc=1 s. Results for the autocorrelationfunction obtained by both the MC simulator and the analytical model of Eq. 4.44are reported in Fig. 4.9. Results for the power spectral density are plotted inFig. 4.10 where the analytical model of Eq. 4.45 is used. Fromthese results wecan see as MC simulations under CB are in good agreement with the analyticalmodels.

Fig. 4.11 reports the comparison between the MC simulation of RTS underSB conditions and the analytical model provided by Eq. 4.55.The RTS is mod-ulated by a square wave featuring a duty cycle of 50% and a switching periodTsw=1 ms, thereforefsw=1 kHz. The emission and capture time constants in theON- and in the OFF-state are:τe on=τc on=1 s,τe off=τe on/m, τc off=τc on×m

with m=10. Results from Fig. 4.11 confirm the validity of the simulation ap-


10-2

10-1

100

101

102

103

Frequency [Hz]10

-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

PS

D [a

.u.]

MC simulationanalytical model

m=10

τe_ON

=1s, τc_ON

=1s

τe_OFF

= τe_ON

/ m, τc_OFF

= τc_ON

x m

SB: Tsw

=1ms

Figure 4.11: Monte Carlo simulation and analytical model of the PSD of anRTS under SB withTsw=1 ms,50% duty cycle,τe on=τc on=1 s,τe off=τe on/m,τc off=τc on × m.

proach using the Monte Carlo technique also under SB conditions. We couldnotice that the PSD simulated by the MC shows the effect of themodulatingsquare wave applied to the gate with a peak atfsw. This is not the case for thePSD obtained by the analytical model.

4.7.4 Simulation of RTS noise under CB and SB conditions

In this section a comparison of the power spectral density ofRTS noise underconstant bias and switched bias conditions is performed by means of the MCsimulator presented earlier. A simulation of the occupation probability of trapsunder SB is also reported. In particular, the variation of the occupation probabil-ity as a function of the time for different switching frequencies is discussed.

PSD under CB and SB

In Fig. 4.12 the power spectral densities simulated by the MCsimulator underCB and SB conditions are reported. Under CB we simulate an RTSwith emissionand capture time constantsτe=τc=5 ms. As we have seen in section 4.5.2, the


100

101

102

103

104

Frequency [Hz]

10-5

10-4

10-3

10-2

10-1

100

101

PS

D [a

.u.]

CB SB (m=1)

SB (m=10)

τc_ON

= τe_ON

= 5 ms

Figure 4.12: Monte Carlo simulated PSD of an RTS under: CB withτe=τe on=5 ms andτc=τc on=5 ms; SB (fsw=10 kHz) with fixedτe off=τe on/m,τc off=τc on × m (m=1); SB (fsw=10 kHz) with modulatedτe off=τe on/10,τc off=τc on × 10 (m=10).

condition in which the emission and capture times are equal gives the maximumpower associated to the RTS. In this case we can also observe the maximum valueof the low-frequency plateau of the PSD. Under SB we apply to the gate of thedevice a square wave with a switching frequencyfsw=10 kHz and a 50% dutycycle. The emission and the capture time constants in the ON-state are set as inthe CB case while the time constants in the OFF-state are obtained by Eq. 4.62with two different values of the parameterm: m=1 andm=10. In the first casethere is no modulation of the time constants between the ON- and the OFF-state,on the other hand, assumingm=10 the emission time constant in the OFF-stateis ten times faster than in the ON-state, while the capture time constant is tentimes slower. As a result of this modulation, the effective emission and capturetime constants become (from Eq. 4.63):

τe eff ≃ 0.9 ms

τc eff ≃ 9 ms(4.64)

As clear from Fig. 4.12, the PSD under SB without modulation of the time


0 0.05 0.1 0.15 0.2Time [s]

0

0.1

0.2

0.3

0.4

0.5

Occ

upat

ion

Pro

babi

lity

fsw

= 10 kHz

fsw

= 10 Hz

m=10

Figure 4.13: Occupation probability simulated with MC under SB conditionswith two different switching frequencies: quasi-staticfsw=10 Hz and very largefsw=10 kHz. Emission and capture time constants in the ON-state aretakenequalτe on=τc on=5 ms. In the OFF-state are modulated with am=10.

constants (m=1) shows a6 dB reduction due the fact that for half a period thetransistor is in the OFF-state [57] and no current is flowing.On the other hand,a modulation of the time constants (m=10), further reduces the noise. Noisereduction can be explained with the help of Fig. 4.7. A trap gives the maximumnoise contribution when the emission and capture time constants associated tothat trap are the same, i.e.τe=τc. Under SB conditions withm=10 the unbalancebetween the emission and the capture time constants (Eq. 4.64) gives the noisereduction as shown in Fig. 4.12.

Occupation probability under SB

The MC simulator is also able to simulate the occupation probability of a trap asa function of the time. To do that the simulation must be carried out for a largenumber of traps featuring the same time constants. At each simulation time thetrap-occupancy is calculated by averaging the state (free or occupied) of eachtrap over the total number of simulated traps.

In Fig. 4.13 MC simulation of the occupation probability of atrap under


SB condition is reported. The trap features emission and capture time constantsin the ON-stateτe on=τc on=5 ms and modulatedτe off andτc off with m=10

in the OFF-state. The simulation is performed for two different switching fre-quencies: a quasi-staticfsw=10 Hz and a very largefsw=10 kHz. In the caseof fsw=10 Hz, the occupation probability varies between two different values.The values assumed in the ON- and in the OFF-state,Pon andPoff , are well de-scribed by Eq. 4.58 and Eq. 4.59, respectively. In particular, the trap-occupancyincreases exponentially fromPoff toPon, and decrease exponentially fromPon toPoff , in a cyclic manner. For the analyzed trap we havePoff → 0 andPon=0.5.On the other hand, for a very largefsw=10 kHz, the occupation probability ofthe trap cannot follow the switching frequency and assumes aconstant value(Peff ) well described by Eq. 4.56, hence, in this casePeff ≃ 0.09. Intuitively,it happens because slow traps cannot adapt quick enough to fast changes in thebiasing.

The study of the occupation probability of a trap under SB conditions is an-other way to explain the effect of the noise reduction shown in Fig. 4.12. Inparticular, we have seen as the trap-occupancy under SB conditions with largeswitching frequency is much lower than expected under quasi-static (i.e. CBconditions) due to the effect of the switching bias on the time constants associ-ated to the trap. As a result, the trap is almost always empty producing thereforea lower RTS noise superimposed to the drain current of MOS transistors.

4.7.5 Simulation of flicker noise

As we have seen in section 4.3, flicker noise can be caused by the superpositionof the RTS noise generated by traps featuring different timeconstants. In theprevious sections we have presented a MC simulator able to evaluate the effectof RTS noise on the drain current of a transistor due the presence of a trap in theoxide. Simulations can be performed under both constant bias and switched biasconditions. RTS noise simulation is performed in the time domain generating aprocess characterized by two time constants distributed with a Poisson statistic.The time constants are the mean time needed by a trap to capture a charge carrierand the mean time to emit it. In this frame, by simulating a certain number ofRTS processes with different time constants and then summing the contributionto the drain current of each of these processes leads to a timedomain signalfeaturing a1/f spectrum. The frequency range in which the spectrum shows a1/f slope depends on the distribution of the time constants of the elemental RTS


10-1

100

101

102

103

104

Frequency [Hz]

10-6

10-5

10-4

10-3

10-2

10-1

100

101

PS

D [a

.u.]

1/f

fsw

=10 kHz

CB

SB

Figure 4.14: Monte Carlo simulation of flicker noise under CB and SB condi-tions withfsw=10 kHz.

processes as discussed in section 4.3.1.

Simulations of flicker noise can be performed under both CB and SB condi-tions.

In Fig. 4.14 the MC simulation of the PSD of flicker noise underCB and SBconditions obtained by the superposition of different RTS are reported. UnderCB, simulation of four different traps having time constants reported in Table 4.1have been performed.

Under SB conditions the time constants are modulated duringthe ON- and theOFF-state. In the simulation, the values of emission and capture time constantsin the ON-state for each trap are assumed the same as under CB conditions (Ta-

Trap τe τc

1 100 ms 100 ms2 10 ms 10 ms3 1 ms 1 ms4 0.1 ms 0.1 ms

Table 4.1:τe andτc for the four different traps simulated to generate flicker noise


ble 4.1); while in the OFF-state the time constants are modulated according toEq. 4.62 withm=10.

From Fig. 4.14 we can notice that, under CB, the effect of fourtraps featuringdifferent time constants roughly gives a1/f spectrum over several decades offrequency. Under SB conditions a noise reduction is observed for frequenciesbelowfsw due to the modulation of the time constants during the ON- andtheOFF-state.

Results of MC simulation reported in Fig. 4.14 show that, as for RTS noise,also flicker noise can be reduced under SB conditions. This reduction can beexplained as the effect of the modulation of the time constants on the occupationprobability of the traps whose superposition causes the1/f noise.

Chapter 5

Modeling of RTS under constantbias conditions

RTS is becoming more and more a limiting factor in CMOS circuits adoptingsmall-area devices [4, 5]. A good modeling of RTS is then a major issue. Animportant aspect is the gate bias dependence of RTS noise. Inparticular, we haveseen that the noise power associated to the RTS assumes its maximum when theemission and capture time constants assume the same value. Every event thatproduces a departure from this condition will reduce the noise associated to thetrap producing RTS noise. Therefore, the gate bias dependence of the RTS timeconstants is of crucial importance to estimate the noise affecting the drain currentof small-area MOSFETs. By means of a frequency domain analysis we canextrapolate the characteristic time constantτ of the RTS process by inspectionof the cut-off frequency of the PSD associated to the RTS.τ is the compositionof both the emission and the capture time constants,τe andτc. In order to be ableto extract separately the values ofτe andτc a time domain analysis is mandatory.This chapter is organized as follows: after a brief introduction on different kindof traps present in the silicon dioxide, the basis of the Shockley-Read-Hall (SRH)theory for trapping and detrapping of electrons in traps located at the siliconoxide interface or inside the oxide is given. Finally, measurement and simulationof the gate voltage dependence of RTS emission and capture time constants underconstant bias conditions for n and pMOS transistors are presented.

66 Modeling of RTS under constant bias conditions

5.1 Traps and RTS noise

The most important step toward the success of CMOS technology has been thedevelopment of the high quality silicon dioxide (SiO2). SiO2 is a good insula-tor and forms an almost perfect electrical interface with the silicon substrate ofa MOS transistor. Even if the silicon dioxide has been part ofthe success ofCMOS technology, it presents some defects that influence theworking of MOS-FETs [62] (Fig. 5.1):

• The interface traps (Qit), which are located at the Si-SiO2 interface withenergy states in the silicon band gap. They can be produced byexcesssilicon, excess oxygen, metal impurities, and from different kinds of bondbreaking processes such as hot carrier stress and radiation.

• Fixed oxide charges (Qf ), which are located at or near the interface. Dif-ferent factors influence the density of these charges: oxidation tempera-ture, silicon orientation, and cooling conditions. They are not influencedby an applied electric field and they are fixed.

• Oxide trapped charges (Qot), these traps can be created, for example, byhot electron injections, by Fowler-Nordheim tunneling, byionizing radia-tion, and may be positive or negative due to trapping of holesor electrons.They are distributed inside the oxide and can influence the characteristicof the transistors changing the threshold voltage.

• Mobile ionic charges (Qm), such as sodium or potassium ions, that can beintroduced by an external contamination during the process. These mobilecharges, under the effect of an electric field applied acrossthe oxide, canmove from one end of the oxide to the other one.

Interface and oxide trapped charges can exchange charge with the bulk regionof the transistor while that does not happen for fixed oxide charges and mobileionic charges. Depending on the surface potential, interface and oxide trappedcharges can be filled or emptied by electrons or holes. Two different kinds oftraps have been recognized, acceptor-type and donor-type.Assuming electronsas charge carriers, the acceptor-type traps are neutral when empty and negativelycharged when filled. The donor-type traps are neutral when filled and positivelycharged when empty. RTS noise can be originated by both kindsof traps.

5.2 Modeling of RTS 67

Na+

+K

Si substrateinterface trapped charge (Q )

it

fixed oxide charge (Q )f

mobile oxide charge (Q )m

oxide trapped charge (Q )ot

SiO

SiO

2

x

Figure 5.1: Different types of charges present at the Si-SiO2 interface and in thebulk of the oxide.

In the previous chapter RTS noise was defined as the switchingof the currentbetween a high and a low level. Its origin is due to such defects or traps locatednear the Si-SiO2 interface or in the bulk of the oxide. In particular, a singleRTS is caused by an individual trap. The trapping/detrapping process affectsthe conductivity of the channel leading to the characteristic switching between ahigh and a low level in the drain current. More details on the experiments neededto distinguish between acceptor and donor traps are given issection 5.2.2.

5.2 Modeling of RTS

The influence of a trap on the noise is mainly determined by itsoccupation proba-bility and by the influence of the occupation state of the trapon the drain current.Trapping and detrapping processes are usually modeled by the Shockley-Read-Hall (SRH) theory [63, 64]. SRH theory was originally developed for traps lo-cated in the bulk of silicon or at the Si-SiO2 interface. Therefore, it has to bemodified in order to account for tunneling into/from traps located in the oxide.


Ec

EvEle

ctr

on

en

erg

y

ba dc

Figure 5.2: The basic processes involved in recombination by trapping: a) elec-tron capture, b) electron emission, c) hole capture, d) holeemission.

5.2.1 SRH theory

In this section the standard SRH theory is presented. We describe the behav-ior for a nMOS device, operating in inversion condition, in which the chargeexchange happens mainly between the conduction band and thetrap. Some as-sumptions must be made:

• A trap can capture only one charge carrier and therefore can change itscharge by the unit chargeq. An acceptor trap can assume charge states 0and−q while a donor trap 0 and+q.

• No exchange of charges between different traps occurs.

• Trapping and detrapping processes are instantaneous.

• The energy of a trapET is independent of its occupancy.

Trapping and detrapping processes between interface trapsand the conduc-tion and valence band are shown in Fig. 5.2. A trap in the neutral state cancapture an electron from the conduction band (a) or capture an electron fromthe valence band (d) leaving therefore an hole in the valenceband. Process (b)represents the emission of an electron and (c) the capture ofan hole.

The capture rate of an electron from the conduction band is given by:

cn = nvthσ(1 − ft) (5.1)


wheren is the electron concentration,vth is the electron thermal velocity,σ isthe capture cross-section and1 − ft is the probability that the trap is empty andso in the condition to capture an electron.

The emission rate of an electron to the conduction band is given by:

en = n1vthσft (5.2)

whereft is the probability that the trap is occupied andn1 is the electron con-centration in the conduction band when the Fermi level fallsatET (trap energy)and is expressed as:

n1 = NCexp

(

ET − ECS

kT

)

(5.3)

The electron concentration is given by Eq. 2.1 and it is here reported:

n = NCexp

(

EF − ECS

kT

)

(5.4)

At equilibrium the trapping/detrapping process follows the Fermi-Dirac statis-tic [63], hence the probability occupation of a trap is:

ft = 1/[1 + exp(ET − EF )/kT ] (5.5)

In this analysis the trap and the electrons in the conductionband are supposedto be in thermal equilibrium so, they have the same Fermi level.

The capture and emission time constants are given by:

τc =1

nσvth(5.6)

and

τe =1

n1σvth=

exp[(EF − ET )/kT ]

nσvth(5.7)

The capture and emission rates can be written as:

cn =1 − ft

τc; en =

ft

τe(5.8)

Under constant bias conditions the detail balance principle requires the cap-ture rate to be equal to the emission rate. From Eqs. 5.6 and 5.7 we get:


2Si0

EC

EV

EF

ET

ET’

∆VGS

∆φs


Figure 5.3: Band bending of a nMOSFET. An increase of the gate voltage∆VGS

correspond to a change in the band bending (dotted lines).∆φs is the changein the surface potential.ET and E

′

T denote the trap energy before and afterchanging the gate voltage.

τc

τe= exp

(

ET − EF

kT

)

(5.9)

Eq. 5.9 gives us an important result: emission and capture time constants assumethe same value when the trap energyET is equal to the Fermi levelEF .

5.2.2 VGS dependence ofτc

If we consider an increase of theVGS, the band bending (Fig. 5.3) and the elec-tron concentrationn (Eq. 5.4) will increase. Analyzing now the expression forthe capture time constant (Eq. 5.6), we can notice thatτc will decrease. Thisdependence allows to distinguish from experimental data ifthe trap producingan RTS signal is an acceptor or a donor one [65]. An acceptor trap is negatively


charged when occupied by an electron and neutral when empty.A donor trap, onthe other hand, is neutral when filled by an electron and positively charged whenempty [66, 67]. As we have seen in Chapter 4 an RTS signal switches betweena high and a low state corresponding in MOSFETs to a high and a low draincurrent level. For both acceptor and donor traps the high level corresponds toa neutral trap due to a lower threshold voltage. Therefore, for an acceptor trap,the time spent by the current in the high level corresponds tothe time neededby the trap to capture an electron. If the mean time spent by the current in thehigh state decreases with increasingVGS it corresponds toτc, on the other hand,the mean time spent in the low state corresponds toτe. In our experiments, onlyacceptor traps have been found. Normally donors traps are observed only atlow-temperatures below 70K [66].

5.2.3 VGS dependence ofτe

The emission time constantτe depends on the trap energyET . According toEq. 5.7,τe seems to be independent of the applied gate voltage becauseET isindependent of VGS. That holds only for traps located exactly at the Si-SiO2

interface. The energy of a trap inside the oxide depends on the oxide electricfield and is given by [68, 69]:

ET = ET0 − qφs − qxt

tox(VGS − VFB − φs − φp) (5.10)

wherext is the trap position inside the oxide,ET0 is the trap energy at flatbandcondition,q is the electronic charge,φs is the surface potential, andφp is the volt-age drop across the gate electrode accounting for poly-depletion. The referenceenergy level is the intrinsic Fermi level in the bulk silicon.

From Eq. 5.10 it is clear that for a trap located at the interface (xt=0 nm),ET

does not depend on the applied gate voltage. On the other hand, a trap locatedinside the oxide shows a decrease of the energy withVGS, hence, from Eq. 5.7,an increase ofτe.

5.2.4 Trap position inside the oxide

Eq. 5.9 can be rewritten following the notation in Fig. 5.4 as:


2Si0

EC

EV

Ei

EF

φF

xt

ECox −ET

φ0

φsq

φq p

EFm

qVGS


q

Figure 5.4: The energy band diagram in the channel at the trap position.

lnτc

τe= − 1

kT

[

(ECox − ET ) − (EC − EF ) − φ0

+ qφs + qxt

tox(VGS − VFB − φs − φp)

] (5.11)

whereECox is the bottom of the conduction band of the oxide,EC is the bottomof the conduction band in the bulk of the silicon,φ0 is the difference betweenthe electron affinity of the Si and the SiO2, φs is the surface potential,φp is thevoltage drop across the gate electrode,xt is the trap position inside the oxide,andtox is the oxide thickness.

According to [70], the trap position inside the oxidext is then calculatedbased on the gate voltage dependence of theτc/τe ratio by using Eq. 5.11:


EC

EVxt

2Si0

trap

p−type substrate

Figure 5.5: ”Tunneling and Capture” (dotted arrows) and ”Capture and Tunnel-ing” (solid arrows) mechanisms for the capture and emissionprocesses for a traplocate at a distancext inside the oxide. The arrows indicate electron transitions.

dln

(

τc

τe

)

dVGS= − q

kT

[

dφs

dVGS+

xt

tox

(

1 − dφp

dVGS− dφs

dVGS

)]

(5.12)

The extraction procedure requires the evaluation of the slope of the line thatprovides a linear fitting of the gate bias dependence ofln(τc/τe). The slopecorresponds to the left-hand side of Eq. 5.12. It is indeed necessary to know theoxide thicknesstox and the dependence onVGS of the surface potentialφs and ofthe voltage drop across the gate electrodeφp.


5.2.5 Tunneling mechanisms

To explain the capture and emission processes of electrons in traps located insidethe oxide, two different models have been proposed. According to the ”Tunnel-ing and Capture” model [71], electrons from the conduction band first tunnelinto the oxide at the distance of the traps, and then are captured by traps (dot-ted arrows in Fig. 5.5). The validity of this model has been later questioned,since measurement data did not support energy dissipation in the oxide [72].The ”Capture and Tunneling” model [34] states that electrons first get trappedby fast defects centers at the interface, and then tunnel into the traps inside theoxide (solid arrows in Fig. 5.5). In this latter model electrons do not dissipateenergy in the oxide. A continuous trap energy distribution over the bandgap atthe interface is required for this process; the presence of such a distribution isgenerally accepted for the Si-SiO2 interface. It is important to notice that for atrap featuring an energy level higher than the conduction band energy at the in-terface, the ”Capture and Tunneling” model has no anymore meaning and directtunneling of electrons in traps should be effective.

5.2.6 Capture cross-section

The capture cross-section (σ) of an electron trap is an effective area within whichan electron is captured by the trap. The larger the cross-section is, the higher isthe probability for an electron to be captured and thus the smaller isτc (Eq. 5.6).

As we have seen in the previous section, in order to be captured by a traplocated in the oxide an electron needs to tunnel to it. Tunneling is a quantummechanical process and to analyze such a process for the electron/trap system,the knowledge of the structure of the trap would be necessaryat the atom level.Unluckily this information is unavailable.

What normally can be done is to model the capture cross-section including inits equation simply the tunneling probability of an electron through the potentialbarrier given by the difference between the oxide barrier height and the energy ofthe electrons that tunnel into the trap. The tunneling depends also on the distancethat an electron must tunnel to be captured in a trap. The tunneling probabilityreduces exponentially with the distance. The capture cross-section is then givenby [73]:

σ(xt) = σ0exp(−xt/λt) (5.13)

5.3 Comparison of RTS models with experimental data 75

whereσ0 is the capture cross-section prefactor,xt is the trap distance into theoxide, andλt is the attenuation wave function coefficient.

5.3 Comparison of RTS models with experimentaldata

In the first part of this section we report the results of measurements and simula-tion of emission (τe) and capture (τc) time constants as a function of gate voltagefor eight individual traps [74] in nMOS transistors. In the second part, resultsare reported for pMOS devices.

5.3.1 Experimental details

RTS noise has been measured in nMOSFETs manufactured in a0.13 µm tech-nology [26] with nitrided gate oxide and physical oxide thicknesstox=2.2 nm.Small-area devices with physical poly gate width W and gate length L productWxL= 0.16x0.1 µm2, 0.4x0.1 µm2, 0.75x0.1 µm2 have been investigated in or-der to detect the effect of single traps. Drain current fluctuations have been mea-sured and recorded using a low noise amplifier and a digital oscilloscope. Theexperiments have been carried out in the linear mode of operation (VDS=50 mV).For each device, the gate bias is varied in order to detect thesignature of a singletrap, i.e. a clear RTS switch superimposed to the DC drain current. Once the trapwas found, the gate voltage was swept over a200 mV range with50 mV steps.For each gate voltage a long time frame of the drain current (up to2 minutes) isrecorded by the digital oscilloscope. For accurately extracting the emission andcapture time constants, the time domain waveform contains at least200 tran-sitions between the high and the low state. Indeed, in order to not miss anytransition, the sampling frequency of the oscilloscope is set at least100 timeshigher than the RTS corner frequency.

Each recorded waveform of drain current has been post-processed in order toestimateτe andτc. This is done by means of a simple software routine that filtersthe high-frequency noise and discriminates between the high and the low stateby a level-crossing algorithm.

All the measured traps are acceptor traps so the high currentlevel corre-sponds to the capture time and the low current level to the emission time.


5.3.2 Modeling approaches

To model the gate bias dependence ofτc andτe we used the SRH model (Eqs. 5.6,5.7) and a modified version proposed by Schulz in [75] by introducing an ad-ditional Coulomb energy accounting for the Coulomb blockade effect. For anacceptor-type trap the expression ofτc is modified including the Coulomb en-ergy∆E, while τe remains the same:

τc =exp(∆E/kT )

nσ(xt)vth

; τe =exp[(EF − ET )/kT ]

nσ(xt)vth

(5.14)

When a trap captures an electron, electrostatic charges in the substrate, channeland gate are modified. This charge variation expends the energy called Coulombenergy∆E, which must be provided and which reduces the capture probabilityaccording to Eq. 5.14.

Quantization effects

The equations 5.6, 5.7, 5.14 forτc andτe are valid for a 3D electron gas. As wehave seen in Chapter 2, in a MOSFET biased in inversion condition, the profileof the conduction band in the vicinity of the Si−SiO2 interface forms a triangularpotential well that induces substantial quantization effects. Due to the confine-ment introduced by this potential well, the energy component associated to themotion in the direction normal to the silicon-dielectric interface is quantized,leading to the formation of subbands. Therefore, a description in terms of a 2Delectron gas is more appropriate.

Following [76, 77], quantization effects in the equation ofτc andτe are takeninto account by means of a first order approximation (see Chapter 2) where onlythe first subband is modeled. The equivalent volume concentration is obtainedby Eqs. 2.4 and 2.6 as:

n = n2D

∫ z

0

p(z)

zdz (5.15)

wheren2D is the electron concentration of the 2D electron gas formingthe in-version layer,p(z) is the probability function of finding electrons at depthz andz is the distance of the inversion charge centroid from the Si−SiO2 interface.

The capture and emission time constants (Eqs. 5.6 and 5.7) are now given by:

τc =1

n2D

∫ z

0p(z)

zdzσ(xt)vth

; τe =exp[(EF − ET )/kT ]

n2D

∫ z

0p(z)

zdzσ(xt)vth

(5.16)


Tunneling mechanism and trap position

In order to model the tunneling we used the ”Tunneling and Capture” modelearlier discussed supposing that electrons tunnel from theenergy of the first sub-bandE0. For all the traps analyzed in this work, the energy level of the firstsubbandE0 is always close to the energy level of the trapET , therefore thisapproach seems reasonable. The capture cross-section is modeled as functionof the distance of the trap inside the oxide given by Eq. 5.13 and the parameterλt is evaluated by the WKB method taking into account the bias dependence ofthe energy barrier [78]. The capture cross-section prefactor σ0 is a model pa-rameter and for some traps has been used as a fitting parameterin order to fitexperimental data.

The trap position inside the oxide has been calculated usingEq. 5.12.

MOSFET electrostatic

In order to calculate the volume concentration of channel electronsn, the surfacepotentialφs and the voltage drop across the gate electrodeφp , we used twodifferent approaches.

The first approach (SCHR) consists in the numerical solutionof the Poissonand Schrodinger equations in a 1-D MOS structure using the SCHRED 2.0 solver[79]. The simulation are performed directly on the websitewww.nanohub.org.

In the second one (SRG) we used a modified version of the model proposedby Siergiej in [76]. In the frame of the SRG approach, the effect of polysilicondepletion is taken into account by an analytical approximation, leading to thefollowing non-linear system of coupled equations:

φs = VGS − VFB − tox

εox

(QB + Qinv) − φp (5.17)

Qinv =2kTmtq

π~2exp

[

−(

Eg

2+ qφF − qφs + ∆E0

)

/kT

]

(5.18)

QB =√

(2εsqNAφs) (5.19)

φp =(QB + Qinv)

2

2qεsNP(5.20)

where∆E0 (Eq. 2.5) is the energy distance betweenE0 (energy level of the firstsubband) and the conduction band energy at the Si−SiO2 interface (ECS), mt


0.7 0.75 0.8 0.85 0.9V

GS [V]

10-3

10-2

10-1

τc,

τ e [s

]

τc- SCHR

τe- SCHR

τc- Exper.

τe- Exper.

xt = 0.79 nm

Trap_1

(a)

Figure 5.6: Experimental and simulatedτc andτe as a function ofVGS (SCHRapproach). Estimatedxt=0.79 nm.

andml are the transverse and longitudinal effective mass of electrons, respec-tively, QB is the MOSFET bulk charge,Qinv is the inversion charge,Eg is theforbidden band gap,φF=(kT/q)ln(NA/ni), ni is the intrinsic electron concen-tration. The flatband volgateVFB, the substrate doping concentrationNA and thepolysilicon doping concentrationNP are treated as known technological parame-ters. The system of Eqs. 5.17-5.20 is solved through Newton-Raphson iterations.

5.3.3 Results

Modeling of τe andτc requires the preliminary extraction of values for the trapenergy at flatbandET0 and cross-section prefactorσ0. For all the consideredtraps, these parameters are set in order to fit experiments for VGS correspondingto 50% trap occupation probability, thus (see Eq. 4.47) for the case in whichτc=τe.

Figs. 5.6 and 5.7 report experimental and simulatedτc andτe by the standardSRH model (5.16) using both the SCHR and SRG approaches for Trap 1. Exper-imentalτc andτe are represented by symbols while simulated data by lines. Thegate voltage is swept between0.7 and0.9 V with 50 mV steps, thus the device isin inversion condition. As reported before, theVDS is always set to50 mV assur-


0.7 0.75 0.8 0.85 0.9V

GS [V]

10-3

10-2

10-1

τc,

τ e [s

]τ

c- SRG

τe- SRG

τc- Exper.

τe- Exper.

xt=0.76nm

Trap_1

(b)

Figure 5.7: Experimental and simulatedτc andτe as a function ofVGS (SRGapproach). Estimatedxt=0.76 nm.

ing the linear operation mode. The capture time constant shows a decrease withthe gate voltage due to an increase of the electron concentration n (Eq. 5.6). Thetwo approaches (SCHR and SRG) provide almost the same results; the estimatedtrap position isxt=0.79 nm andxt=0.76 nm with the SCHR and SRG approach,respectively, and the simulated gate bias dependence ofτc andτe are pretty simi-lar. This is valid for all the traps we have analyzed in this work and therefore wewill report results obtained by the simpler and more efficient SRG approach. Infact, while the electrostatic of the MOSFET in the SRG approach is calculatingsolving the system of Eqs. 5.17-5.20 that takes into accountonly the first sub-band, the SCHR approach require to solve numerically, by means of simulationby the SCHRED 2.0 simulator, the Poisson and Schrodinger equations.

Fig. 5.8 reports the gate voltage dependence of experimental and simulatedemission and capture time constants for a trap (Trap2) with xt=1.12 nm. Thegate voltage is swept between0.65 and0.85 V. Also in this case the standardSRH model is able to provide a reasonable description of experimental data.We obtained similar results also for two more traps (Trap3 and Trap4), notreported in figures, featuring different positions inside the oxide and energies.The relevant parameters of these traps are reported in Table5.1. Also for Trap3and Trap4 the emission and capture time constants are measured and simulated


0.65 0.7 0.75 0.8 0.85V

GS [V]

10-4

10-3

10-2

τc,

τ e [s

]

τc- SRG

τe- SRG

τc- Exper.

τe- Exper.

xt=1.12nm

Trap_2


xt ET0 − ECS σ0

[nm] [eV] [cm2]

Trap 1SCHR 0.79 0.30 5.9x10−21

SRG 0.76 0.31 5.5x10−21

Trap 2 SRG 1.12 0.39 4.0x10−18

Trap 3 SRG 0.61 0.25 1.4x10−20

Trap 4 SRG 0.71 0.24 1.3x10−20

Table 5.1: Extracted physical model parameters for 4 different traps in 4 dif-ferent nMOS devices. For these traps the SRH model well reproduces theVGS

dependence ofτe andτc. ET0 is the trap energy at flatband voltage andECS isthe conduction band energy at the Si-SiO2 interface.

for a gate voltage swept over a200 mV range in inversion condition. Similarresults were shown in [60] where the standard SRH model is reported to fit welltheVGS dependence of three traps.

Fig. 5.9 reports results for an additional trap (Trap5) located at an estimateddistancext=0.82 nm. The gate voltage is swept between0.8 and1 V. It can benoticed that for this specific trap the dependence ofτc on VGS is much largercompared to the cases shown in Figs. 5.7 and 5.8. As a consequence, the stan-


0.8 0.85 0.9 0.95 1V

GS [V]

10-4

10-3

10-2

10-1

τc,

τ e [s

]τ

c- SRG

τe- SRG

τc- Exper.

τe- Exper.

xt=0.82nm

Trap_5


0.8 0.85 0.9 0.95 1V

GS [V]

10-5

10-4

10-3

10-2

10-1

τc,

τ e [s

]

τc- SRG

τe- SRG

τc- Exper.

τe- Exper.

0.8 0.85 0.9 0.95 1V

GS [V]

02468

10

σ 0 [a

.u.]

xt=0.82nm

Trap_5

σ0

Figure 5.10: Experimental and simulatedτc andτe as a function ofVGS (SRGapproach). The model assumes an empirical adjustment ofσ0. Estimatedxt=0.82 nm. In the inset the normalized values ofσ0 are reported as a func-tion of VGS.


xt ET0 − ECS σ0 (τc=τe)[nm] [eV] [cm2]

Trap 5 SRG 0.82 0.36 2.2x10−20

Trap 6 SRG 1.13 0.43 7.4x10−18

Trap 7 SRG 0.92 0.34 5.2x10−20

Trap 8 SRG 0.98 0.31 1.1x10−18

Table 5.2: Extracted physical model parameters for 4 different traps in 4 differentnMOS devices. Due to the largeVGS dependence ofτc, an empirical adjustmentof σ0 is necessary.ET0 is the trap energy at flatband voltage andECS is theconduction band energy at the Si-SiO2 interface.

dard SRH model provides a much lower gate bias dependence ofτc compared toexperiments. Also the simulated emission time constant does not provide a goodfitting of the experimentalτe. Similar results were obtained in [77, 80] where, inorder to fit the experiments, an empiricalVGS dependence of the capture cross-section [77] or a modification of the trap energy due to the Coulomb blockadeeffect [80] were introduced.

In order to recover a better agreement between the experimental and the sim-ulated data of Trap5, we tried the approach discussed in [77, 81] empiricallyvarying the capture cross-section prefactorσ0. Results for Trap5 are shown inFig. 5.10 where both experimental emission and capture timeconstants are wellreproduced by the model.σ0 must be increased withVGS and this behavior isalso reported in [81]. The normalized values of the capture cross-section pref-actor are reported in the inset of Fig. 5.10. In this particular case the capturecross-section prefactor must be increased about of a factorof 10 for the exploredgate voltage.

Similar results are shown in Fig. 5.11 for another trap (Trap6) featuring adistance inside the oxidext=1.13 nm. Also for this trap an empirical variation ofσ0 with the gate voltage is necessary in order to reproduce the strong dependenceof the capture time constant onVGS.

We have measured four different traps for which an empiricaladjustment ofthe capture cross-section prefactor has been necessary to reproduce the gate biasdependence of emission and capture time constants. The relevant parameters ofthese traps are reported in Table 5.2. The value reported forthe capture cross-section prefactor is the extracted one at theVGS that givesτc=τe.

Trying to recover a good fitting with experiments for Trap6, we tried also


0.75 0.8 0.85 0.9 0.95V

GS [V]

10-6

10-5

10-4

10-3

10-2

τc,

τ e [s

]τ

c- SRG

τe- SRG

τc- Exper.

τe- Exper.

0.75 0.8 0.85 0.9 0.95V

GS [V]

02468

10121416

σ 0 [a

.u.]

xt=1.13nm

Trap_6

σ0

Figure 5.11: Experimental and simulatedτc andτe as a function ofVGS (SRGapproach). The model assumes an empirical adjustment ofσ0. Estimatedxt=1.13 nm. In the inset the normalized values ofσ0 are reported as a func-tion of VGS.

0.75 0.8 0.85 0.9 0.95V

GS [V]

10-6

10-5

10-4

10-3

10-2

τc,

τ e [s

]

τc- SRG

τe- SRG

τc- Exper.

τe- Exper.

0.75 0.8 0.85 0.9 0.95V

GS [V]

020406080

∆E [m

eV]

xt=1.13nm

Trap_6

Figure 5.12: Experimental and simulatedτc andτe as a function ofVGS (SRGapproach). The model accounts for the Coulomb blockade effect. Estimatedxt=1.13 nm. In the inset the values of the Coulomb blockade∆E are reportedas a function ofVGS.


the approach proposed in [80] by accounting for the Coulomb blockade effect.Capture and emission time constants are modeled as reportedin Eq. 5.14 takinginto account quantization effects. The trap energy at flatband voltageET0 andthe cross-section prefactorσ0 are set to fit experiments for theVGS correspondingto τc=τe. σ0 is kept constant for each gate voltage. The Coulomb energy∆E istreated as a fitting parameter in order to reproduce the gate voltage dependenceof τc. Results of this approach are reported in Fig. 5.12. While the experimentalτc is perfectly reproduced, the model predicts an excessive dependence ofτe onVGS. The values of the Coulomb energy are reported in the inset ofFig. 5.12showing a variation between 60 and 0 mV; these values are comparable to theones reported in [80].

5.3.4 Discussion

From results previously reported it is interesting to notice that it is not possibleto reproduce with a single model the gate bias dependence of emission and cap-ture time constants. In particular, some traps show a quite strong dependenceof the capture time constant as a function of the bias appliedto the gate. Forsuch traps, the standard SRH model is not able to reproduce experiments, but anempirical variation of the capture cross-section it is necessary to recover a goodfitting of experimentalτc andτe. The intersting fact is that we could not find anycorrelation between the standard characteristics of the traps like the energy andthe position and the adequacy of the standard SRH model. In fact, analyzing forexample Trap2 and Trap6, while they feature quite close values for estimatedxt, ET0 andσ0, only Trap6 requires a modification to the SRH model in orderto cope with the large bias dependence ofτc.

On the other hand, the modification of the SRH model by means oftheCoulomb blockade effect can lead to a perfect agreement between experimen-tal and simulatedτc but gives an excessive dependence ofτe on the applied gatevoltage.

5.3.5 Extension for pMOSFETs

We have analyzed the gate voltage dependence of emission andcapture timeconstants also for pMOS transistors. Small-area pMOSFETs fabricated with thesame technology used for nMOSFETs [26] have been measured. Analyzed de-vices featureWxL= 0.4x0.1 µm2 and0.75x0.1 µm2 and gate oxide thickness


0.8 0.85 0.9 0.95 1|V

GS| [V]

10-4

10-3

10-2

10-1

τc,

τ e [s

]τ

c- SRG

τe- SRG

τc- Exper.

τe- Exper.

xt=0.33nm

Trap_1

Figure 5.13: Experimental and simulatedτc andτe for a pMOSFET as a func-tion of |VGS| (SRG approach). Estimatedxt=0.32 nm..

tox=2.2 nm. The same extraction procedure forτc andτe described for nMOS-FETs have been adopted. The drain-to-source voltage has been set to -50 mV inorder to operate in linear regime. Once the RTS signal in the drain current due toa trap has been clearly identified, the gate voltage has been swept over a range of200 mV with -50 mV steps. Modeling of the voltage dependence of emission andcapture time constants have been performed with the standard SRH model even-tually adopting an empirical variation of the capture cross-section prefactor. ForpMOSFETs we used only the single subband approach (SRG) therefore solvingthe system of Eqs. 5.17-5.20 considering now the appropriate effective massesfor both the transport and the tunneling for holes instead than for electrons [82].

Fig. 5.13 reports experimental (symbols) and simulated (lines) emission andcapture time constants for a trap (Trap1) in a pMOSFET as a function of theabsolute value ofVGS. The estimated trap position isxt=0.33 nm. It can benoticed that bothτc andτe are well reproduced by the standard SRH model usingthe single subband approach (SRG). We obtained similar results for other twotraps (Trap2 and Trap3) for which a good fitting of simulated emission andcapture time constants with experiments is achieved. The relevant parameters ofthese traps are reported in Table 5.3.


xt EV S − ET0 σ0

[nm] [eV] [cm2]Trap 1 SRG 0.33 0.20 1.0x10−22

Trap 2 SRG 0.41 0.26 2.1x10−23

Trap 3 SRG 0.85 0.31 1.2x10−19

Table 5.3: Extracted physical model parameters for 3 different traps in 3 dif-ferent pMOS devices. For these traps the SRH model well reproduces theVGS

dependence ofτe andτc. ET0 is the trap energy at flatband voltage andEV S isthe valence band energy at the Si-SiO2 interface.

0.65 0.7 0.75 0.8 0.85|V

GS| [V]

10-4

10-3

10-2

10-1

τc,

τ e [s

]

τc- SRG

τe- SRG

τc- Exper.

τe- Exper.

0.65 0.7 0.75 0.8 0.85|V

GS| [V]

0123456

σ 0 [a

.u.]

xt=0.32nm

Trap_4

σ0

Figure 5.14: Experimental and simulatedτc andτe for a pMOSFET as a func-tion of |VGS| (SRG approach). The model assumes an empirical adjustment ofσ0. Estimatedxt=0.33 nm. In the inset the normalized values ofσ0 are reportedas a function of|VGS|.

As for nMOS devices, also for some traps in pMOSFETs it has notbeenpossible to obtain an adequateVGS dependence of emission and capture timeconstants adopting the standard SRH model. For such traps anempirical varia-tion of the capture cross-section has been necessary to recover a good fitting ofexperimentalτc andτe. An example is shown in Fig. 5.14 where experiments andsimulations are reported for a trap (Trap4) featuring a distance inside the oxidext=0.32 nm. The necessary variation of theσ0 is reported in the inset of the fig-


xt EV S − ET0 σ0 (τc=τe)[nm] [eV] [cm2]

Trap 4 SRG 0.32 0.18 9.8x10−23

Trap 5 SRG 0.54 0.23 1.4x10−21

Trap 6 SRG 0.76 0.31 1.3x10−20

Trap 7 SRG 0.49 0.24 8.1x10−21

Trap 8 SRG 1.21 0.38 1.9x10−18

Table 5.4: Extracted physical model parameters for 5 different traps in 5 differentpMOS devices. Due to the largeVGS dependence ofτc, an empirical adjustmentof σ0 is necessary.ET0 is the trap energy at flatband voltage andEV S is thevalence band energy at the Si-SiO2 interface.

ure as a function of|VGS|. For other four measured traps we needed to empiricalvary the capture cross-section prefactor to reproduce the gate bias dependence ofτc andτe (see Table 5.4).

Also for traps in pMOSFETs it has not been possible to correlate the ade-quacy of the standard SRH model with the trap position insidethe oxide, thetrap energy, and the capture cross-section. In particular,Trap 1 and Trap4 showquite similar values forxt, ET , andσ0, but while for Trap1 the standard SRHmodel well reproduces the gate voltage dependence of emission and capture timeconstants, that’s not true for Trap4, for which an empirical variation ofσ0 isneeded in order to obtain a good agreement with experiments.

Chapter 6

Measurement of flicker and RTSnoise under switched biasconditions

Flicker noise, as reported in previous chapters, may be reduced in MOSFETscycled between strong inversion and accumulation. The origin of flicker noiseis attributed to the random trapping and detrapping of charge carriers into orfrom traps located inside the oxide responsible for the RTS noise. In this chap-ter a study of the flicker and RTS noise under constant bias andswitched biasconditions is proposed. Measurements of flicker noise have been performed inthe frequency domain for nMOS and pMOS transistors adoptingdifferent biasschemes, while RTS noise has been measured for small-area nMOSFETs both inthe time and in the frequency domain. The chapter is organized as follows: in thefirst part we introduce the measurement setup used both to measure flicker andRTS noise. In the second part the flicker noise is analyzed comparing the noiseunder constant and switched bias conditions for different bias schemes. A com-parison of the noise in transistors with two different oxidethicknesses is alsoreported. Finally, RTS noise is investigated both under constant and switchedbias conditions in order to find a correlation with results obtained for flickernoise.

90 Measurement of flicker and RTS noise under switched bias conditions

VBS

VGS_ON

VGS_OFF

VGS

VDSVDS

VBS_OFF

0V

LNA 1

LNA 2

T 1 T 2

Spectrum analyzer

Digital

Oscilloscope

Figure 6.1: Schematic setup for measurement of flicker and RTS noise underconstant and switched gate and substrate bias conditions.

6.1 Measurement setup

The measurement setup used to analyze flicker and RTS noise isreported inFig. 6.1 [83]. The setup measures in a differential scheme the uncorrelated noisein a matched pairs of MOSFETs (T1 & T2). The two transistors have commongate, source and substrate connections. The uncorrelated drain current noise ofT1 and T2 is amplified by two low noise amplifiers (LNA) and the out comingsignals are subtracted. This arrangement cancels out the large signal perturbationdue to the switching gate and substrate signals and adds the noise powers of thetwo transistors. Gate and bulk terminals of the test structure are terminated by50 Ω resistors (not shown in Fig. 6.1). The gate and the substratevoltages ofthe MOSFETs are controlled by a pulse generator which provides for a constantbias (CB) or a periodic switched bias (SB). The biasing of thedrain terminals isprovided by the two low noise amplifiers. The spectum analyzer measures thedrain current noise PSD of the two transistors. Time domain RTS measurementsare performed with a digital oscilloscope. Calibration of the setup as well as ameasurement of the noise floor by measuring the noise-power when the MOS-FETs are ’OFF’ and the probes and the amplifiers are connectedto the spectrumanalyzer have been done.

6.2 Flicker noise measurements 91

T_ON

T_OFF

VGS_OFF

VGS_ON

VGS

VBS

VBS

0 V

VBS_OFF

0 V

VBS_ON

(IP)

(OP)

Figure 6.2: Timing scheme for 1/f noise measurement with in-phase (IP)and180 out-of-phase (OP) switched substrate bias (VBS) with respect to the gatevoltage (VGS) timing.

6.2 Flicker noise measurements

In this part we report results of measurements of flicker noise under constant andswitched bias conditions.

6.2.1 Measurement condition

In this analysis we measured both nMOS and pMOS devices fabricated in a0.13 µm technology [26] with nitrided gate oxide with thicknesstox=2.2 nm.nMOSFETs have a gate lengthL=0.3 µm and a gate widthW=6 µm. pMOS-FETs haveL=0.3 µm andW=12 µm. The threshold voltage isVTH=0.26 Vand VTH=−0.3 V for n and pMOS devices, respectively. Measurements un-der CB conditions are performed biasing the devices withVGS=VDS=1 V andVGS=VDS=−1 V for n and pMOSFETs, respectively. The application of aforward and reverse substrate bias has been investigated. Characterization un-der SB conditions is performed by applying to the gate terminal a square wavewith 50% duty cycle switching between an ON- and an OFF-state (VGS ON andVGS OFF ) and a switching frequencyfsw=2.5 MHz with rising and falling timestr=tf=8 ns. Under SB conditions different substrate biasing schemes have been


analyzed (Fig. 6.2): a) substrate bias with zero voltage (ZSB), b) constant sub-strate bias with forward or reverse bias (FSB, RSB), c) forward substrate biaspulsing in-phase with respect to the gate pulsing (IP), and d) forward substratebias pulsing180 out-of-phase with respect to the gate switching bias (OP). Inthe case b), while to the gate is applied a pulse switching betweenVGS ON andVGS OFF with fsw=2.5 MHz, the applied forward or reverse substrate bias is keptconstant. In the case c) and d) the substrate bias is not anymore kept constantwhile the gate bias switches between the ON- and the OFF-state, butVBS is alsoswitched. In c) theVBS is switched to0 V when the gate pulse is set toVGS OFF

(transistor in the OFF-state) and to a forwardVBS ON when the gate pulse is setto VGS ON (transistor in the ON-state). Hence, the switching frequency of thepulse applied to the substrate is alsofsw=2.5 MHz and has the same rising andfalling times as for the pulse applied to the gate. In d), on the other hand, theVBS is switched to a forward substrate biasVBS OFF when the gate pulse is setto VGS OFF and to0 V when the gate pulse is set toVGS ON .

The effect ofVGS OFF on the noise keeping the substrate bias to zero volt isalso analyzed.

The reported results, unless differently stated, are obtained by averaging mea-surements performed on at least 20 nominally identical devices.

6.2.2 Measurement results

Effect of substrate bias

Figs. 6.3 and 6.4 report the normalized noise power spectraldensity of draincurrent (Sid/Id) as a function of frequency for constant (CB) and switched (SB)gate bias conditions with ZSB and FSB for nMOSFETs and pMOSFETs, respec-tively. Id represents the drain current in the ON-state. Under SB conditions thegate-to-source voltage in the ON-state has been set to the same value used un-der CB conditions (nMOS:VGS ON=1 V, pMOS: VGS ON=−1 V), while in theOFF-state is always set to zero (VGS OFF=0 V).

The FSB is set toVBS=0.6 V andVBS=−0.6 V for nMOS and pMOS, re-spectively.Sid/Id under CB conditions is divided by a factor of 4 in order to becompared to the SB measurements accounting for the intrinsic 6 dB attenuationdue to the ON-OFF modulation of the drain current with 50% duty cycle [57].From Figs. 6.3 and 6.4 it can be noticed that, with zero substrate bias, SB slightlyreduces the1/f noise compared to CB. Application of a forward substrate bias


100

101

102

103

104

Frequency [Hz]

10-17

10-16

10-15

10-14

10-13

S id /

I d [A

/Hz]

CB/4 VBS

=0VCB/4 V

BS=0.6V

SB VBS

=0VSB V

BS=0.6V

nMOS

Figure 6.3: Normalized noise power densitySid/Id for nMOSFET underCB and SB conditions (VGS ON=1 V, VGS OFF=0 V, VDS=1 V) with ZSB(VBS=0 V) and FSB (VBS=0.6 V) vs. frequency.

100

101

102

103

104

Frequency [Hz]

10-17

10-16

10-15

10-14

10-13

S id /

I d [A

/Hz]

CB/4 VBS

=0VCB/4 V

BS=-0.6V

SB VBS

=0VSB V

BS=-0.6V

pMOS

Figure 6.4: Normalized noise power densitySid/Id for pMOSFET under CBand SB conditions (VGS ON=−1 V, VGS OFF=0 V, VDS=−1 V) with ZSB(VBS=0 V) and FSB (VBS=−0.6 V) vs. frequency.


-0.6 -0.4 -0.2 0 0.2 0.4 0.6V

BS [V]

10-14

10-13

S id /

I d @

1H

z [

A/H

z]

CB/4SB

nMOS

Figure 6.5: Sid/Id @ 1 Hz under CB and SB conditions vs. substrate biasVBS

for nMOSFETs withVGS ON=1 V, VGS OFF=0 V, VDS=1 V.

-0.6 -0.4 -0.2 0 0.2 0.4 0.6V

BS [V]

10-14

10-13

S id /

I d @

1H

z [

A/H

z]

CB/4SB

p-MOS

Figure 6.6: Sid/Id @ 1 Hz under CB and SB conditions vs. substrate biasVBS

for pMOSFETs withVGS ON=−1 V, VGS OFF=0 V, VDS=−1 V.


100

101

102

103

104

Frequency [Hz]

10-16

10-15

10-14

10-13

10-12

S id /

I d [A

/Hz]

ZSB : zero substrate biasIP : in-phase substrate bias pulsingOP : out-of-phase substrate bias pulsing

nMOS

Figure 6.7: Sid/Id vs. frequency for a single nMOS device under SB conditions(VGS ON=1 V, VGS OFF=0 V, VDS=1 V) with: zero substrate bias, in-phase and180 out-of-phase substrate bias switching with respect to the gate switchingbias.

under SB provides a strong reduction of the noise, while a FSBapplied underCB condition hardly modifies the flicker noise. These considerations hold forboth nMOS and pMOS transistors.

Another way to visualize the flicker noise is to plot the valueof the normal-ized power spectral density at1 Hz. This is obtained by fitting theSid/Id as afunction of the frequency with a line and by extracting the intercept of this linewith the x-axis where the frequency is equal to1 Hz. Such a method allows aneasy visualization of the noise power spectral density. Figs. 6.5 and 6.6 reportthe dependence ofSid/Id at 1 Hz on the substrate biasVBS under both CB andSB conditions. Substrate bias is varied from reverse to forward biases for bothn and pMOSFETs: fromVBS=−0.6 V to VBS=0.6 V for nMOSFETs and fromVBS=0.6 V to VBS=−0.6 V for pMOSFETs. For both n and pMOSFETs, asmall effect ofVBS when applied under CB can be noticed. Under SB condi-tions, the application of a forward substrate bias reduces significantly the flickernoise when compared to zero substrate bias, while a reverse substrate bias hasonly a marginal effect.

In order to investigate the effect of a FSB under SB conditions, different bi-


asing schemes have been adopted. Results of these measurements are shown inFig. 6.7 where theSid/Id for a single nMOS transistor is plotted as a functionof frequency under SB for different substrate bias schemes:ZSB, forward sub-strate bias pulsing in-phase with respect to the gate pulsing (IP), and forwardsubstrate bias pulsing180 out-of-phase with respect to the gate switching bias(OP). Therefore, in the IP case a FSB is applied when the transistor is in the ON-state and switched to zero volt when the transistor is in the OFF-state; the OPcase is the opposite: the FSB is applied when the transistor is in the OFF-stateand switched to zero volt when the transistor is in the ON-state. The significantreduction of flicker noise occurs when the FSB is applied during the OFF-state(OP) of the transistor; on the contrary, FSB is hardly effective when appliedduring the ON-state (IP). Similar results have been obtained also for pMOS tran-sistors [83].

The results of Fig. 6.7 indicate that the impact on noise of the gate biasswitching between the ON- and OFF-state is enhanced when a forward substratebias is applied during the OFF-state. Since the forward substrate bias tends todrive the MOS system towards accumulation, we may speculatethat the substratebias induced suppression of noise could be related to a transient accumulation ofthe silicon at the oxide interface.

Effect of gate OFF-voltage

In order to confirm the hypothesis made above, we measured thedependenceof flicker noise on the gate OFF-voltage under zero substratebias. Results arereported in Figs. 6.8 and 6.9, for n and pMOSFETs, respectively. Both the tran-sistors show similar qualitative results. The normalized noise power spectraldensitySid/Id shows a small reduction when the gate OFF-voltage is decreasedin magnitude towards the threshold voltage. A saturation plateau is observed forvalues of the gate OFF-voltage corresponding to sub-threshold depletion con-dition. When theVGS OFF is further decreased (increased in the pMOS case),driving the substrate at the gate oxide interface into accumulation, a further sig-nificant drop of the flicker noise occurs, a behavior not observed in previousworks [6, 84].

In addition to the observed saturation plateau, Figs. 6.8 and 6.9 show only asmall reduction in noise for a gate OFF-voltage around zero volts. Our findingis in good agreement with a previously reported noise reduction value in [85]for devices with similar gate oxide thickness. Additionally in [85] a diminishingnoise reduction towards thinner oxides is found. Accordingto the results shown


-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.40.6 0.8 1V

GS_OFF [V]

10-14

10-13

S id /

I d @ 1

Hz

[A

/Hz] CB/4

nMOS

Figure 6.8: Sid/Id @ 1 Hz vs. pulsed gate OFF-voltageVGS OFF for a zero voltsubstrate bias for nMOSFETs withVGS ON=1 V, VDS=1 V.

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.40.6 0.8 1V

GS_OFF [V]

10-14

10-13

S id /

I d @ 1

Hz

[A

/Hz]

CB/4

pMOS

Figure 6.9: Sid/Id @ 1 Hz vs. pulsed gate OFF-voltageVGS OFF for a zero voltsubstrate bias for pMOSFETs withVGS ON=−1 V, VDS=−1 V.


0 0.1 0.2 0.3 0.4 0.5 0.6V

BS [V]

10-14

10-13

S id /

I d @

1H

z [

A/H

z] SB VGS_OFF

=0V

SB VGS_OFF

=-0.9V

nMOS

Figure 6.10: Sid/Id @ 1 Hz vs. substrate biasVBS for nMOSFETs withVGS ON=1 V, VGS OFF=0, −0.9 V , VDS=1 V.

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0V

BS [V]

10-14

10-13

S id /

I d @

1H

z [

A/H

z] SB VGS_OFF

=0V

SB VGS_OFF

=0.9V

pMOS

Figure 6.11: Sid/Id @ 1 Hz vs. substrate biasVBS for pMOSFETs withVGS ON=−1 V, VGS OFF=0, 0.9 V, VDS=−1 V.


in this chapter a significant noise reduction is possible also for thin oxide devicesif a gate voltage beyond zero volts or a respective substratevoltage driving thedevice into accumulation is provided.

In Figs. 6.10 and 6.11 the substrate bias dependence ofSid/Id is comparedfor two different gate OFF-voltages for n and pMOSFETs, respectively. As al-ready reported, for a gate OFF-voltage of 0 V a strong dependence of noiseon forward substrate bias is observed with a significative noise reduction. Onthe other hand, for a gate OFF-voltage driving the device towards accumulation(VGS OFF=−0.9 V for nMOS andVGS OFF=0.9 V for pMOS devices), only avery small noise variation with forward substrate bias can be found. This behav-ior additionally supports the assumption that accumulation of majority carriersis necessary for the noise reduction and the effect of forward substrate bias onnoise reduction depends on the amount of accumulation reached already by theapplied gate OFF-voltage.

Dependence on oxide thickness

In this section, the flicker noise measurements earlier performed are comparedfor devices having two different oxide thicknesses. Results for n and pMOS-FETs, with atox=2.2 nm (SGox) andtox=5.4 nm (DGox) are reported.

In Fig. 6.12(a) theSid/Id normalized to the value atVGS OFF=0 V as a func-tion of the gate OFF-voltage for nMOS devices with SGox and DGox is reported.The ON-voltage is set in order to bias the transistors in strong inversion. Com-paring theSid/Id for the two differenttox it is evident that the higher sensitivityof theSid/Id on theVGS OFF occurs for devices with a thicker oxide thickness(DGox). Fig. 6.12(b) reports theSid/Id normalized to the value atVBS=0 V asfunction of the substrate bias for nMOS devices having SGox and DGox. The ON-voltage is set to operate the devices in strong inversion andtheVGS OFF=0 V.Also in this case, devices with DGox show a stronger sensitivity of the noiseon the substrate voltage. pMOSFETs show similar results (Figs. 6.13(a) and6.13(b).

The different sensitivity amongst devices with different oxide thicknessesmay be related to the following fact: transistors with a thicker oxide thickness re-quire smaller negative voltages to reach accumulation (positive for pMOSFETs)or smaller values of forward substrate bias. Hence, for MOSFETs with DGox

a stronger reduction of the noise compared to SGox for smaller variation of theVGS OFF or of theVBS around zero volt can be found.


-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0V

GS_OFF [V]

0.2

0.4

0.6

0.8

1

Nor

mal

ized

S id

/ Id @

1H

z

SGox

DGox

nMOS

(a) Dependence on the gate OFF-voltageVGS OFF

0 0.1 0.2 0.3 0.4 0.5 0.6V

BS [V]

0

0.2

0.4

0.6

0.8

1

Nor

mal

ized

S id

/ Id @

1H

z

SGox

DGox

nMOS

(b) Dependence on the substrate biasVBS

Figure 6.12: NormalizedSid/Id @1 Hz under SB conditions for nMOS deviceswith different oxide thicknesses.

0 0.1 0.2 0.3 0.4 0.5 0.6V

GS_OFF [V]

0

0.2

0.4

0.6

0.8

1

Nor

mal

ized

S id

/ Id @

1H

z

SGox

DGox

pMOS

(a) Dependence on the gate OFF-voltageVGS OFF

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0V

BS [V]

0

0.2

0.4

0.6

0.8

1

Nor

mal

ized

S id

/ Id @

1H

z

SGox

DGox

pMOS

(b) Dependence on the substrate biasVBS

Figure 6.13: NormalizedSid/Id @1 Hz under SB conditions for pMOS deviceswith different oxide thicknesses.

6.2.3 Discussion

From results reported in the previous sections, we can say that forward sub-strate bias concurs to suppress the flicker noise under switched gate bias bytransiently inducing accumulation at the silicon-oxide interface during the OFF-state. Since the1/f noise affecting MOSFET drain current is usually related tothe trapping/detrapping processes of minority carriers into/from traps located atthe silicon-oxide interface or inside the oxide, we conclude that forward substratebias, by promoting the accumulation of majority carriers atthe interface, reducesthe trap emission time constant for emptying traps in the gate oxide during theMOSFET OFF-state. The reduction in emission time is dependent on the gate


to substrate voltage driving the transistor towards accumulation and most proba-bly originates from an increased recombination rate of trapped minority carrierswith accumulated majority carriers. Besides the accumulated majority carriersone possibly needs also to regard empty interface states that could support therecombination of trapped charges with majority carriers. Interface states residingin energy between conduction and valence band of the siliconand located at thesilicon-oxide interface are empty when they are above the Fermi level during ac-cumulation (nMOS case). Such empty interface states could provide an effectivefast path for carrier recombination. For nMOSFETs trapped charges released tothe conduction band could recombine via fast interface traps or tunnel directlyto interface traps and recombine with the accumulated majority carriers in thevalence band. Analog considerations hold for pMOSFETs.

Based on the results reported in Figs. 6.8 and 6.9, we may conclude thatthe strong reduction of flicker noise can also be obtained by switching the gatebias, provided thatVGS OFF is well below ground or above supply voltage, forthe n-channel and p-channel cases, respectively. In circuits, gate voltages belowground and above supply voltage are more difficult to establish. Hence, forwardsubstrate bias seems appropriate for noise reduction in circuits using scaled tech-nologies and switched bias conditions. Especially the factthat forward substratebias is needed only during the transistor OFF-state suggests new topologies andbiasing schemes in circuits [86, 87].

6.2.4 Measurement on a 45 nm technology

All the measurements proposed in the previous part of this chapter have beenmade on a0.13 µm technology. During this work, has been possible also tomeasure flicker noise in devices fabricated in a45 nm technology. n and pMOS-FETs with nitrided gate oxide with atox of 1.8 nm have been analyzed. The gatelength of the measured devices isL=0.12 µm and the gate width isW=4 µmandW=8 µm for n and pMOSFETs, respectively. The switching frequencyofthe gate pulse isfsw=2.5 MHz with 50% duty cycle. Rising and falling timesaretr=tf=8 ns.

Fig. 6.14 shows the dependence of theSid/Id on the gate OFF-voltage underSB conditions with aVGS ON=1 V andVDS=1 V. Results are similar to the onesobtained for the0.13 µm technology. The curve presents a saturation plateauaround zero volt and the noise is reduced for gate OFF-voltages below zero voltbringing the devices into accumulation.


-1 -0.8-0.6-0.4 -0.2 0 0.2 0.40.6 0.8 1V

GS_OFF [V]

1e-13

1e-12

S id /

I d @ 1

Hz

[A

/Hz] CB/4

nMOS

Figure 6.14: Sid/Id @ 1 Hz vs. pulsed gate OFF-voltageVGS OFF for a zerovolt substrate bias for nMOSFETs withVGS ON=1 V, VDS=1 V.

0 0.1 0.2 0.3 0.4 0.5 0.6V

BS [V]

10-13

10-12

S id /

I d @

1H

z [

A/H

z]

CB/4SB V

GS_OFF=0V

SB VGS_OFF

=-0.8V

nMOS

Figure 6.15: Sid/Id @ 1 Hz vs. substrate biasVBS for nMOSFETs under CB(VGS=1 V) and SB (VGS ON=1 V, VGS OFF=0 and−0.8 V) with VDS=1 V.


-1 -0.8-0.6-0.4 -0.2 0 0.2 0.40.6 0.8 1V

GS_OFF [V]

10-13

10-12

S id /

I d @ 1

Hz

[A

/Hz] CB/4

pMOS

Figure 6.16: Sid/Id @ 1 Hz vs. pulsed gate OFF-voltageVGS OFF for a zerovolt substrate bias for pMOSFETs withVGS ON=−1 V, VDS=−1 V.

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0V

BS [V]

10-13

10-12

S id /

I d @

1H

z [

A/H

z]

CB/4SB V

GS_OFF=0V

SB VGS_OFF

=0.8V

pMOS

Figure 6.17: Sid/Id @ 1 Hz vs. substrate biasVBS for pMOSFETs under CB(VGS=−1 V) and SB (VGS ON=−1 V, VGS OFF= 0 and0.8 V) with VDS=−1 V.


Fig. 6.15 shows the dependence of flicker noise on substrate bias under CBand SB conditions. In particular, under SB conditions two different gate OFF-voltages have been analyzed:VGS OFF=0 and−0.8 V with a VGS ON=1 V andVDS=1 V. A forward substrate bias is hardly effective under CB conditions. Areduction of the flicker noise is achieved when a forward substrate bias is appliedwith aVGS OFF=0 V compared to the caseVBS=0 V. Once the device is broughtinto accumulation (VGS OFF=−0.8 V), the noise reduction is already reachedfor VBS=0 V and not further reduction occurs applying a forward substrate bias.Similar results hold also for pMOSFETs (Figs. 6.16 and 6.17).

Experimental results on a45 nm technology confirms the noise reductionunder SB conditions induced by applying a forward substratebias observed inan older0.13 µm technology.

6.3 RTS noise measurement

In this part we report results of measurements of RTS noise under constant andswitched bias conditions in small-area nMOSFETs [88, 89].

6.3.1 Measurement condition

RTS noise measurements have been performed in small-area nMOSFETs with2.2 nm thick nitrided gate oxide, gate poly lengthL=0.1 µm and widthsW=0.4,0.75 µm manufactured in a0.13 µm technology [26]. RTS noise has been mea-sured in both time and frequency domain using the differential set-up reported inFig. 6.1.

Measurements under CB conditions are performed as describein Chapter 5and the gate bias dependence ofτc andτe allows us to extract the trap distanceinside the oxide (xt) and to recognize between acceptor and donor traps. All theanalyzed traps are acceptor ones.

Time domain analysis of RTS noise under SB conditions with 50% duty-cycle is performed using the technique described in section4.6.2 and proposedin [60]. The switching frequency is set tofsw=10 kHz. For each bias condition along time frame of the drain current in the ON-state (up to 2 minutes) is recordedby the digital oscilloscope. For each semi-period in the ON-state an average al-gorithm gives the level of the current, high or low, and a simple software extractthe capture (τc) and the emission (τe) time constants. Therefore, a possible tran-sition during a single semi-period is lost and the time resolution of the method is

6.3 RTS noise measurement 105

100

101

102

103

104

Frequency [Hz]

10-21

10-20

10-19

10-18

10-17

10-16

10-15

PS

D [A

2 / H

z]CB / 4 V

BS = 0 V

SB VBS

= 0 VOP-SB V

BS_OFF = 0.2 V

Trap_1

SB : VGS_ON

= 0.75 V VGS_OFF

= 0 V

CB : VGS

= 0.75 V

fsw

= 10 kHz

nMOS

Figure 6.18: RTS PSD for: CB; SB; gate- and substrate-SB (OP). Forwardsubstrate bias applied OP with respect to the gate bias reduces the low-frequencyplateau of the PSD.

0.1 ms. To prove the validity of this approach, for each trap and each bias point,the measured power spectral density has been compared to Eq.4.45 in which theemission and capture time constants have been substituted with the respectiveextracted values.

The drain-to-source voltage has been kept toVDS=1.0 V and the same biasschemes used for flicker noise measurement have been analyzed (Fig. 6.2). Theeffect on the PSD and on the time constants of the RTS noise of asubstrate biasapplied in-phase and out-of-phase with respect to the gate switching bias hasbeen studied. Results on the impact of theVGS OFF on the RTS noise have beenalso reported.

6.3.2 Measurement results

Effect of substrate bias

Fig. 6.18 reports the power spectral density of a trap (Trap1) featuring esti-mated trap position into the oxidext=0.65 nm under: CB (VGS=0.75 V), andSB (VGS ON=0.75 V andVGS OFF=0 V) with zero substrate bias and with a for-


100

101

102

103

104

Frequency [Hz]

10-21

10-20

10-19

10-18

10-17

10-16

10-15

PS

D [A

2 / H

z]

CB / 4 VBS

= 0.2 VIP-SB V

BS_ON = 0.2 V

SB VBS

= 0.2 V CONST

Trap_1

SB : VGS_ON

= 0.75 V VGS_OFF

= 0 V

CB : VGS

= 0.75 V

fsw

= 10 kHz

nMOS

Figure 6.19: RTS PSD for: CB; gate and substrate SB (IP); gate SB and constantFSB.

ward substrate bias switched OP with respect to the gate pulsing. In this lattercase the substrate bias in the ON-state is set toVBS ON=0 V and in the OFF-stateto VBS OFF=0.2 V. It is interesting to notice that switching the gate between anON- and an OFF-state only marginally affects the noise compared to the CBcase. In particular, SB slightly increases the low-frequency plateau of the PSD.The application of a FSB during the OFF-state of the transistor decreases thenoise of about one order of magnitude in the low-frequency range.

In order to prove that the FSB is effective only in the OFF-state we per-formed measurements applying the FSB both in-phase with respect to the gatepulsing and with a constant value over all the switching period, i.e. the FSB isapplied both during the ON- and the OFF-state. Results of these measurementsfor Trap 1 are reported in Fig. 6.19. In order to have the same bias conditions, inthe CB case a constant FSB (VBS=0.2 V) has been applied. Fig. 6.19 shows thatthe strong reduction of the low-frequency noise under SB compared to CB occursonly for a constant FSB (VBS=0.2 V), while applying FSB only in the ON-state(VBS ON=0.2 V) only marginally affects the PSD. These measurements provethat, as for flicker noise, the application of a FSB concurs tosuppress the RTSnoise only when applied during the OFF-state of the device.

Fig. 6.20 reports the dependence of the RTS PSD on theVBS OFF under


100

101

102

103

104

Frequency [Hz]

10-20

10-19

10-18

10-17

10-16

PS

D [A

2 /Hz] f

sw = 10 kHz

VGS_ON

= 0.75 V VGS_OFF

= 0 V

Trap_1VBS_OFF

= -0.3 V OP

VBS_OFF

= 0 V

VBS_OFF

= 0.25 V OP

VBS_OFF

= 0.2 V OP

VBS_OFF

= 0.3 V OP

nMOS

Figure 6.20: RTS PSD under gate- and substrate-SB (OP case) for differentvalues of the substrate biasVBS OFF applied during the OFF-state. IncreasingVBS OFF the PSD plateau at low frequencies decreases.

gate SB for Trap1. The gate voltage is switched betweenVGS ON=0.75 VandVGS OFF=0 V while different values of the substrate bias are applied OPwith respect to the gate bias. In particular, starting from areverse substrate biasVBS OFF=−0.3 V, a forward substrate biasVBS OFF=0.3 V is reached. Resultsof Fig. 6.20 show as the application of the reverse substratebias hardly affectsthe RTS PSD compared to the case with zero substrate bias. On the contrary, thelow-frequency plateau of the PSD is significantly decreasedincreasing the FSBup to0.3 V.

As reported earlier in section 4.5.2, the low-frequency plateau of the PSD(Eq. 4.41) and the total power P (Eq. 4.43) associated to the RTS are influencedby three factors: emission and capture time constants and current fluctuationamplitude∆I. We know that the maximum value of the low-frequency plateauof the PSD and of the total power P occurs forτc=τe. In order to obtain in-formation on the time constants and on∆I, a time domain analysis of the RTSnoise is mandatory. In our experiments we measure∆I observing that its valuestays constant for each bias point. Thus, a decreasing of thePSD low-frequencyplateau and of the total power P is caused by the values assumed by the captureand the emission time constants.


10-4

10-3

10-2

τc,

τ e [s

]

τc - Exper.

τe - Exper.

-0.3 -0.2 -0.1 0 0.1 0.2 0.3V

BS_OFF OP [V]

10-16

10-15

10-14

Noi

se P

ower

P [

A2 ]

Trap_1V

GS_ON = 0.75 V V

GS_OFF = 0 V

fsw

= 10 kHz

Figure 6.21: τc, τe and RTS-noise power P under gate and substrate SB (OPcase) as a function of substrate biasVBS OFF applied during the OFF-state. In-creasingVBS OFF τe decreases affecting also the noise power that shows a strongreduction.

In order to prove that we extractedτe andτc under SB conditions with sub-strate bias applied OP with respect to the gate switching bias. Results are re-ported in Fig. 6.21. In the upper part of Fig. 6.21 the substrate bias dependenceof emission and capture time constants under SB is shown. Thesubstrate biasis applied OP with respect to the gate bias. Focusing on theτc andτe values atzero substrate biasVBS OFF=0 V, we can notice that they assume similar valuesgiving therefore the maximum value of the power P, lower partof Fig. 6.21. Theapplication of the reverse substrate biasVBS OFF=−0.3 V hardly modifies bothτc andτe and therefore also the power P. The strong reduction of the power as-sociated to the RTS noise occurs for FSB and the reason is the decrease of theemission time constant while the capture time constant shows a slight increaseenhancing therefore the difference between the two time constants. In fact, in-creasing the FSB from0 to 0.3 V a more than one order of magnitude reductionof theτe occurs. Practically, the trap is almost always empty and, once an elec-tron is captured, it is emitted with a very fast emission timeconstant.

We performed the same analysis also for another trap (Trap2) having an esti-mated trap position inside the oxidext=0.2 nm. Results are shown in Figs. 6.22,6.23, and 6.24. Under switched bias condition the gate has been commutated


100

101

102

103

104

Frequency [Hz]

10-20

10-19

10-18

10-17

10-16

10-15

PS

D [A

2 /Hz]

CB / 4 VBS

= 0 VSB V

BS = 0 V

OP-SB VBS_OFF

= 0.4 V

Trap_2

SB : VGS_ON

= 0.7 V VGS_OFF

= 0 V

CB : VGS

= 0.7 V

fsw

= 10 kHz

nMOS

Figure 6.22: RTS PSD for: CB; SB; gate- and substrate-SB (OP). Forwardsubstrate bias applied OP with respect to the gate bias reduces the low-frequencyplateau of the PSD.

betweenVGS ON=0.7 V andVGS OFF=0 V with a fsw=10 kHz.Fig 6.22 shows that while under gate SB with zero applied substrate bias the

RTS PSD is only slightly influenced compared to the CB case, the applicationof a FSB OP with respect to the gate bias strongly reduces the low-frequencyplateau of the PSD. The applied value of the FSB during the OFF-state is set toVBS OFF=0.4 V.

The dependence of the PSD on different substrate bias valuesapplied alwaysduring the OFF-state of the transistor are reported in Fig. 6.23. As for Trap1,also for Trap2 a reverse substrate biasVBS OFF=−0.4 V hardly influences thePSD of the RTS noise compared to the case with zero substrate bias. On the con-trary, increasing the substrate bias reachingVBS OFF=0.6 V strongly reduces thenoise. Comparing Trap1 to Trap2 (Fig. 6.20 and Fig. 6.23), a different sensi-tivity on VBS OFF can be noticed. In particular, while for Trap1 the applicationof VBS OFF=0.2 V already concurs to the suppression of the noise, for Trap2 itis necessary to increaseVBS OFF to 0.4 V to appreciate a reduction of the PSD.This fact is related to a different dependence of emission and capture time con-stants on the applied substrate bias. Fig. 6.24 showsτc andτe (upper part) and thetotal noise power P (lower part) as a function ofVBS OFF . τc andτe stay almostconstant, and hence also the power P, over the range−0.4 V< VBS OFF < 0.2 V.


100

101

102

103

104

Frequency [Hz]

10-19

10-18

10-17

10-16

PS

D [A

2 /Hz] f

sw = 10 kHz

VGS_ON

= 0.7 V VGS_OFF

= 0 V

Trap_2VBS_OFF

= 0 V V

BS_OFF = 0.2 V OP

VBS_OFF

= -0.4 V OP

VBS_OFF

= 0.6 V OP

VBS_OFF

= 0.4 V OP

nMOS

Figure 6.23: RTS PSD under gate- and substrate-SB (OP case) for differentvalues of the substrate biasVBS OFF applied during the OFF-state. IncreasingVBS OFF the PSD plateau at low frequencies decreases.

10-4

10-3

10-2

τc,

τ e [s

]

τc - Exper.

τe - Exper.

-0.4 -0.2 0 0.2 0.4 0.6V

BS_OFF OP [V]

10-15

10-14

10-13

Noi

se P

ower

P [

A2 ]

Trap_2V

GS_ON = 0.7 V V

GS_OFF = 0 V

fsw

= 10 kHz

Figure 6.24: τc, τe and RTS-noise power P under gate and substrate SB (OPcase) as a function of substrate biasVBS OFF applied during the OFF-state. In-creasingVBS OFF τe decreases affecting the noise power that shows a strongreduction.


100

101

102

103

104

Frequency [Hz]

10-20

10-19

10-18

10-17

10-16

10-15

PS

D [A

2 / H

z]V

GS_OFF = 0.0 V

VGS_OFF

= -0.1 VV

GS_OFF = -0.2 V

VGS_OFF

= -0.3V

VGS_OFF

= -0.4 V

Trap_1

VGS_ON

= 0.75 V fsw

= 10 kHz

nMOS

Figure 6.25: RTS PSD under gate SB for different values of the gate OFF-voltageVGS OFF . DecreasingVGS OFF the PSD plateau at low frequencies de-creases.

As theVBS OFF is increased above0.2 V, a strong reduction of the emission timeconstant concurs to the suppression of the noise power.

Effect of gate OFF-voltage

From previous measurements, we have seen that a strong reduction of the RTSnoise can occurs under SB conditions applying a forward substrate bias duringthe OFF-state of the device. The reduction is due to the decrease of the emis-sion time constant that, enhancing the difference with the capture time constant,concurs to the noise suppression. As for flicker noise measurements, we tried,following investigations proposed in [7, 60], to study the dependence of the RTSnoise for different gate OFF-voltages.

The PSD of RTS noise under SB condition for Trap1 for differentVGS OFF

is shown in Fig. 6.25. As already reported in previous works [7, 60], drivingthe device into accumulation, strongly reduces the RTS noise. In particular, thedecrease is higher for lower gate OFF-voltages.

Fig. 6.26 reports the emission and the capture time constants (upper part) andthe noise power P (lower part) as a function of theVGS OFF . The strong reduction


10-5

10-4

10-3

10-2

10-1

τc,

τ e [s

]

τc - Exper.

τe - Exper.

-0.4 -0.3 -0.2 -0.1 0V

GS_OFF [V]

10-16

10-15

10-14

Noi

se P

ower

P [

A2 ]

Trap_1V

GS_ON = 0.75 V

fsw

= 10 kHz

Figure 6.26: τc, τe and RTS-noise power P under gate SB as a function ofgate OFF-voltageVGS OFF . DecreasingVGS OFF τe decreases affecting the noisepower that shows a strong reduction.

of the PSD low-frequency plateau and the power P is associated to a decreasingof the emission time constant withVGS OFF .

6.3.3 Discussion

Results obtained for RTS noise show that a FSB applied duringthe OFF-state ofthe device strongly reduces the noise. From time domain measurements emissionand capture time constants have been extracted showing thatthe suppression ofthe RTS noise is related to a strong reduction of the emissiontime constant thatenhances the difference with the capture time constant. A departure from theconditionτc=τe implies a reduction of the power associated to the RTS noise.The reduction of the emission time constant can be explainedas follows: theforward substrate bias tends to drive the MOS system towardsaccumulation;hence, we conclude that the FSB-induced suppression of noise could be relatedto a transient accumulation of the silicon at the oxide interface leading to verylarge recombination rate of trapped carriers with accumulated holes during theOFF-state.

Another way to bring the device into accumulation is to decrease the gate


OFF-voltage well below the threshold voltage. Experimentsproved that for thesame traps analyzed applying a forward substrate bias, switching the device tomore negative voltages as zero volt, the RTS noise decreasesdue to a reductionof the emission time constant.

It is important to remark that in some cases the RTS noise can also be in-creased by switching the gate bias and eventually by the application of a forwardsubstrate bias compared to the constant bias case. This could happen in traps forwhich the difference between emission and capture time constants under con-stant bias is high, i.e.τe>τc, and the application of a switched bias tends toequilibrate the time constants increasing the RTS noise power associated to suchtraps.

However, the significant reduction of the RTS noise power of traps with largenoise contribution, hence featuringτc ≃ τe under constant bias conditions, couldjustify the average suppression of flicker noise in large-area devices affected byseveral traps.

The application of a forward substrate bias could benefit circuits using small-area MOSFETs, especially those showing a large noise tail distribution such asCMOS image sensors [5, 90].

Chapter 7

Conclusions

In this thesis we have investigated low-frequency noise in MOSFETs operatingunder constant bias and switched bias conditions. Our work has aimed to provideuseful results about the modeling and the characterizationof flicker and RTSnoise in MOSFETs.

After a brief introduction on electrical characterizationwe performed chargepumping and mobility measurements in order to study the interface state den-sity and the mobility of MOS transistors. We analyzed devices with a differentprocess option that introduces a fluorine doping. Devices having this fluorinedoping step show a lower interface state density and a highermobility. The rea-son for that may be explained based on the hypothesis that thefluorine dopingstep improves the interface quality between the silicon andthe gate oxide and aless interface states are present compared to conventionaldevices. As a conse-quence, the mobility is improved due to the less Coulomb scattering.

Simulation of RTS noise under constant and switched bias conditions hasbeen performed by means of a Monte Carlo simulator. Trappingand detrappingprocesses have been simulated reproducing the occupation probability of a trapboth in time and in frequency domain. Under switched bias condition emissionand capture time constants are modulated by the square wave applied to the gate.This modulation could both increase and decrease the RTS noise compared tothe costant bias case. This fact depends on the modulation ofthe emission andcapture time constants under switched bias conditions compared to their valuesunder constant bias conditions. The superposition of different traps with differenttime constants has been simulated to generate flicker noise under both constantand switched bias conditions.

RTS noise has been analyzed in n and pMOSFETs under constant bias con-

116 Conclusions

ditions, in particular, measuring and simulating the dependence of the emissionand capture time constants on the applied gate bias. Time domain measure-ments have been performed in small-area devices in order to be able to isolatethe contribution of a single trap on the drain current. The gate bias dependenceof the RTS noise allowed us to distinguish between acceptor and donor traps.In our experiments we found only acceptor type traps. The modeling based onthe standard Shockley-Read-Hall theory has shown that emission and capturetime constants can be reproduced only for a subset of the analyzed traps. Forthe others, a much stronger dependence of the capture time constant on the gatebias can be modeled only by empirically varying the capture cross-section of thetraps. Similar results hold both for nMOS and for pMOS devices.

Both flicker and RTS noise have been measured in n and pMOSFETsunderconstant and switched bias conditions analyzing differentbias schemes. We haveshown that the application of a forward substrate bias strongly reduces the flickernoise of transistors operating under switched bias conditions when the gate isswitched between an ON-state in inversion and an OFF-state set to 0 V. Weproved that a forward substrate bias is effective when applied during the OFF-state of the device. We speculated that a forward substrate bias, by promoting theaccumulation of majority carriers at the interface, reduces the trap emission timeconstant for emptying traps in the gate oxide during the MOSFET OFF-state.Similar results can be obtained for zero substrate bias if the gate voltage in theOFF-state is set well below0 V for nMOS and above0 V for pMOS devices.These results show that reaching accumulation is mandatoryto have a reductionof flicker noise. The method presented in this work for the reduction of flickernoise is of particular interest in circuits where it is difficult to reach gate voltagesbelow ground and above supply voltage.

RTS noise measurements in time domain showed a strong reduction of RTSnoise due to the reduction of the emission time constant whena forward substrateis applied during the OFF-state of a switched transistor. This is the case when theapplication of a forward substrate bias enhances the difference between emissionand capture time constants with respect to their values under constant bias con-ditions. We know that an increase of RTS noise can appear under switched biasconditions. However, the significant reduction of the RTS noise power of trapswith large noise contribution under constant bias conditions could justify the av-erage suppression of flicker noise in large-area devices affected by several traps.The application of a forward substrate bias could be useful to reduce the RTSnoise in circuits using small-area MOSFETs, hence affectedby such a noise.

Acknowledgments

During my doctoral course period I have been constantly encouraged, supportedand advised by several people. I want to express my gratitudeto all of them.

I am deeply grateful to my supervisor, Prof. Claudio Fiegna for offering methis opportunity, for supporting me, and for continuously stimulating me duringthis period.

My electronic group-mates Marco Braccioli, Simone Eminente, and ClaudioBerti have always been a great support during this period andI would like tothank them for the nice time we spent together, especially outside the office. Ialso wish to thank all colleagues and friends at university in Cesena, particularlyMatteo Lucchi, Gillo, Francesco Lodesani, Marco Bennati. Aspecial thank alsoto all the friends I met living in Cesena.

I would like to thank all my friends from my hometown, here thelist wouldbe really too long. In particular Filippo, Leonardo, Pierluigi, and Simone. Withthem I spent many wonderful weekends.

My doctoral course has been in collaboration with Infineon TechnologiesAG in Munich. I would like to express my gratitude to all the colleagues at theRF/MS group, especially Dr. Peter Baumgartner, DomagojSiprak and GiovanniCalabrese for their support and continuous help. I am also deeply indebted toAntonius Koller, who has been of invaluable help to perform most of the mea-surements. A special thank also to the friends outside of work, especially Uli,Mario, Nicola, Federico, Pierangelo, Gianluigi, Paola andall the others from our”Stammtisch”.

Finally I wish to express boundless thanks to my girlfriend Wibke, whoselove and encouragement have been essential during these years, to my parentsand my brother for their continuous support.

118 Acknowledgments

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