bhavika project report(1)

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X RAY TOTAL IONIZING DOSE (TID) RADIATION EFFECT ON FPGA

BHAVIKA RANA

MASTER OF SCIENCE ELECTRICAL ENGINEERING

ROY G. PERRY COLLEGE OF ENGINEERING

PRAIRIE VIEW A&M UNIVERSITY

May 2015

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A Project By

BHAVIKA RANA

Submitted to the Office of Graduate Studies of Prairie View A&M University

In partial fulfillment of the requirements for the degree of

MASTER OF SCIENCE

May 2015

Major Subject: Electrical Engineering


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A Project By

BHAVIKA RANA

Submitted to the Office of Graduate Studies of Prairie View A&M University

In partial fulfillment of the requirements for the degree of

MASTER OF SCIENCE

Approved as to style and content by: _________________________ _________________________

Dr. Richard Wilkins Dr. Penrose Cofie Chairperson Member

_________________________

Dr. Pamela Obiomon Head of the Department

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A BST R A C T


Bhavika Rana, B.E, VNSGU

Chair of advisory committee Dr. Richard Wilkins

This project proposes the study and development of X-ray total ionizing dose (TID) radiation effect on Field Programmable Gate Arrays (FPGAs) customizable by SRAM. Spacecraft electronic designers increasingly demand high performance microprocessors and programmable logic, because of their high performance and flexibility. Because SRAM based FPGAs are reprogrammable, they offer the additional benefits of allowing on-orbit design changes. Data can be sent after launch to correct errors or to improve system performance. System including microprocessors and FPGAs covers a wide range of space applications, and consequently, they are the objects of study.

The consideration of using FPGA to space applications are fairly recent and there is

a lot of work to be done in this area so far. Presently, there is no total efficient solution for SRAM based FPGAs that can assure 100% of reliability in all conditions. This project has the goal to investigate the effect of x-ray total ionizing dose on FPGA.

In this study investigated the total ionizing dose effect in static random access

memory (SRAM) based field programmable gate array (FPGA). Spartan 3E (XC3S500E) field programmable device programmed by using verilog code, then the device bombarded with different value x-ray total ionizing dose (TID) radiation. Compare the I/O result of radiated device with non radiated device. As a result the device got catastrophic failure on about 211 KRad x-ray TID.

The space radiation environment and its effect on electronics devices, Spartan 3E

FPGA, experiment, result, conclusion and future work are describe in this project report.

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D E DI C A T I O N This project is dedicated to my parents: Mrs. Induben Rana, Mr. Amrutbhai Rana and my

loving husband Rushikkumar Rana.

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A C K N O W L E D G E M E N TS

My truthful appreciation goes to my advisor Dr. Richard Wilkins for his guidance and invaluable support during the course of this research work. I have benefited immensely from his mentorship and that has greatly impacted my research experience. It is an honor for me to have worked with him.

I would like to thanks other members of my advisory committee namely Dr. Pamela Obiomon and Dr. Penrose Cofie for their valuable suggestions and contributions to my success, I would also like to thanks Dr. Fuller who allowed me to work in his laboratory and Special thanks goes to Dr. Richard Wilkins for his support throughout my program in the department of Electrical and Computer Engineering (ECE). I wish to thank the Head of the ECE Department, Dr. Obiomon, and other faculty members for their teaching and help when needed.

Finally, I take this opportunity to thank all staff, faculty (who impacted me) and the students of the Electrical and Computer Engineering Department, who in one way or the other, have made my time at Prairie View A&M University worth the while.

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IND E X

Page ABSTRACT .............................................................................................................................. . IV

ACKNOWLEDGEMENT .......................................................................................................... VI

TABLE OF CONTENTS ......................................................................................................... VIII

LIST OF FIGURES .................................................................................................................... X

LIST OF TABLES ..................................................................................................................... XI

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T A B L E O F C O N T E N TS

1. IN T R O DU C T I O N...................................................................................................................... 1

1.1 Background 1

1.2 Problem Statement 1

1.3 Objective 1

1.4 Project Outline 2

2. L I T E R A T UR E R E V I E W ......................................................................................................... 3

2.1 Basic of FPGA .........3

2.1.1 Programming Technologies ..................................................................................... 4

2.1.2 Spartan-3E FPGA .................................................................................................... 4

2.1.3 Features ................................................................................................................... 5

2.1.4 Architectural Overview ............................................................................................ 6

2.1.5 Configurations .......................................................................................................... 7

2.1.6 I/O Capabilities ......................................................................................................... 8

2.2 Motivation 8

2.3 Radiation Effects on FPGA 9

2.3.1 Radiation effect on Electronics ................................................................................ 9

2.3.2 Total Ionizing Dose ................................................................................................... 9

2.3.3 Single event effect ................................................................................................. 10

2.4 X-‐Ray Radiation Producing machine 12

2.4.1 Overview ................................................................................................................ 12

2.4.2 Features ................................................................................................................. 12

2.4.3 Specifications ......................................................................................................... 13

2.5 Similar research based on this project 14

2.5.1 Analysis of TID Failure Modes in SRAM-‐Based FPGA under Gamma-‐Ray and Focused Synchrotron X-‐Ray irradiation ................................................................................. 14

2.5.2 Microbeam irradiation by means of synchrotron x-‐ray ......................................... 15

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3. M E T H O D O L O G Y .................................................................................................................. 18

3.1 Verilog program with code that generate outputs with 3 specific patterns for full adder 18

3.1.1 Setting up a New Project and specifying a circuit in Verilog 18 3.1.2 Synthesizing circuit to the Xilinx FPGA 29

3.2 Bombard FPGA with X-ray total ionizing radiation 43

3.2.1 Setup of X-ray machine 43 3.2.2 Now expose the FPGA board with different dose for calculated time (30 cm

SSD) in an x-ray radiation producing machine 45 3.2.3 After applying each dose programming the FPGA and check the result by I/O

switch on FPGA board 45 3.2.4 Annealing process 45 3.2.5 Measure the supply voltage pin on FPGA chip 46 4. R ESU L TS A ND DISC USSI O NS ............................................................................................ 47

4.1 Verilog code for full adder program success 47

4.2 Annealing process..............................................................................................................49

4.3 Conformation of the radiation effect on FPGA chip......................................................49

5. C O N C L USI O NS A ND F U T UR E W O R K ............................................................................. 51

R E F E R E N C ES ............................................................................................................................. 52

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L IST O F F I G UR ES F ig. 2.1.1 Spartan 3E X C3S 500E ................................................................................................. 5 F ig. 2.1.2 Spartan-3E Family A rchitecture [8] ............................................................................ 7 F ig. 2.3.1 Radiation-induced charging of gate oxide in n-channel M OSF E T : (A) normal operation (B) post-ir radiation [69] .............................................................................................. 9 F ig. 2.3.2 Charge deposition by charged particle into the substrate of a transistor [26] ....................................................................................................................................................... 10 F ig. 2.4.1 X-ray radiation producing machine (PV A M U laboratory) [19] 12 F ig. 2.5.1 (B) Supply currents of DU Ts (I C C) as a function of deposited dose when the DU Ts were biased in dynamic mode during the ir radiation procedure. ................................ 14 F ig. 2.5.2 Schematic of synchrotron x-ray ir radiation environment........................................15 F ig. 2.5.3 Locations of several typical components in the SR A M- ..16 F ig. 3.1.1 Spartan 3E starter kit FPG A configuration options ................................................ 36 F ig. 3.1.2 Detailed configuration option ..................................................................................... 37 F ig. 4.1.1 Red L E D indicates the power supply and the yellow L E D indicate the successfully loaded program on FPG A board ................................................................................................ 48 F ig. 4.3.1 Measured voltage for V C C IN T (FPG A chip) ........................................................... 49

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L IST O F T A B L ES

Table 2.1.1 Summery of SPA R T A N- 3E Attr ibutes [8] 6 Table 2.5.1 Summary of the phenomena in the synchrotron x-ray ir radiation exper iment .17

44 Table 4.1.1 I/O switches give the result as shown in below table 48

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Chapter 1: Introduction

1.1 Background

The effect of radiation on semiconductor device have always been a meaningful matter, and lot of work to be done in this area so far. Since, than interest on studying fault tolerant technique in order to keep integrated circuits operation in such a wrathful environment has increased, driven by all possible applications of radiation tolerant circuits, such as space missions, satellites, advanced weaponry, high-energy physics experiments. Spacecraft systems include a large variety of analog and digital components that are potentially sensitive to radiation and must be protected or at least qualified for space operation.

TOTAL IONIZING DOSE (TID) effects in static random access memory (SRAM)-based

field programmable gate array (FPGA) have been studied. Here the x-ray used as a radiation source for whole chip irradiation experiment. Under this circumstance, the entire chip is uniformly irradiated [1], [2]. For small-scale chips or those made up of regular components, whole-chip irradiation-based analysis can provide enough information to identify the internal components responsible for the corresponding functional errors [3], [4]. However, this procedure becomes more difficult, or the information obtained from failure modes is limited for very large integrated circuit (VLSI) [5] [20].

1.2 Problem statement

Field Programmable Gate Array (FPGA) devices have been used in space for more than a

decade with a mixed level of success. SRAM-based FPGA is a kind of VLSI. In most cases, when conducting TID measurement of FPGA, the inner part of the whole chip responsible for degradations are difficult to identify. Thus, the TID sensitivity of different internal circuits cannot be evaluated directly [6]. 1.3 Objective

In this project, there is a Spartan 3E Field Gate programmable device will be programmed using verilog code. The device will then bombard with X-Ray Total Ionizing Dose Radiation. Then

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1.4 Project Outline The presentation of the project is organized as follows:

Chapter 2 introduces the basic structure and principle of operation of the FPGA, Space application of FPGA and X-RAD iR 160 radiation producing machine of PVAMU facility. The knowledge of the basic concepts provides the basic background information required to understand the rest of this project. Xilinx Spartan 3E FPGA topology is discussed in detail.

Chapter 3 discuses methodology used for the project. The Verilog code of full adder circuit

for programming of xc3s500e Spartan 3E FPGA is elaborated in this chapter. The FPGA device bombard with x ray radiation is discussed in this chapter.

Chapter 4 concludes and focuses on future scope of the project.

Chapter 5 documents all the references used for this project.

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Chapter 2: L iterature Review

2.1 Basic of FPG A

Simulations and prototyping have been a very important part of the electronics industry since a very long time now. Before heading in for the actual fabrication of a dedicated hardware, everyone would want to be sure that what they are making will work the way they want it to. Over all these years while electronics companies offered dedicated hardware in their products, it was not possible for the end user to reconfigure them to his own needs. This need led to the growth of a new market segment of customer configurable Field Programmable integrated circuits called Field Programmable Gate Arrays or FPGAs [7].

The FPGA share a common history with most Programmable Logic Devices. The first of

this kind of devices was the Programmable Read Only Memory. Further driven by need of specifically implementing logic circuits, Philips invented the Field-Programmable Logic Array (FPLA) in the1970s. This consisted of two planes, a programmable wired AND-plane and the other as wired OR. It could implement functions in the Sum of Products form [7].

To overcome difficulties of cost and speed, Programmable Array Logics were developed

which had owith other variants are grouped as Simple Programmable Logic Devices (SPLDs). In order to cater to growing technological demands, SPLDs were integrated onto a single chip and interconnects were provided to programmable connect the SPLD blocks. These were called Complex PLDs and were first pioneered by Altera, the first in the family being Classic EPLDs and then, MAX series [7].

Then another class of Electronic devices, Mask-Programmable Gate Arrays consisting of

transistor arrays which could be connected using custom wires motivated the design of the FPGAs. Transistors gave way to Logic Blocks and the customization could now be performed by the user on the field and not in the manufacturing lab. The credit to develop the first commercially viable FPGA goes to Xilinx co-founders Ross Freeman and Bernard Vonderschmitt. The XC2064 was invented in 1985 consisting of 64 Configurable Logic Blocks with 3 Look up Tables. It was in late 198implement a computer with 600,000 reprogrammable gates found sponsors in US Naval Surface Warfare department and later a patent in 1992 [7].

By the end of 1990, a lot of competition sprung up in manufacturing FPGAs when

Lucent and SiliconBlue started entering this field and carving their niche in the world FPGA Market along with Xilinx, as FPGA started gaining acceptance in applications like Digital Signal Processing and Telecommunications. In 1997, Adrian Thompson succeeded in merging a genetic algorithm technology with FPGA and started a new age of Evolvable hardware [7].

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2.1.1 Programming T echnologies

hardware. These are a special form of PLDs with higher densities and with increased capability of implementing functionality in a shorter time span using various flavours based on the programming technology used. These may be programmed using:

1. Antifuse T echnology, which can be programmed only once. Devices manufactured by

QuickLogic are examples of this type. Configuration is done by burning a set of fuses. These act as replacements for Application Specific ICs (ASIC) and used in places where protection of intellectual property is top priority.

2. F lash T echnology based Programming, like devices from Actel. The FPGA may be

reprogrammed several thousand times, taking a few minutes in the field itself for reprogramming and has non-volatile memory.

3. SR A M T echnology based FPGAs, the currently dominating technology offering unlimited reprogramming and very fast reconfiguration and even partial reconfiguration during operation itself with little additional circuitry. Most companies like Altera, Actel, Atmel and Xilinx manufacture such devices [7].

2.1.2 Spartan-3E FPG A

The Spartan®-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The five-member family offers densities ranging from 100,000 to 1.6 million system gates as shown in table 2.1.1. The Spartan 3E family builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration. These Spartan-3E FPGA enhancements, combined with advanced 90 nm process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry. Because of their exceptionally low cost, Spartan-3E FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment. The Spartan-3E family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASIC. Figure 2.1.1 shows image of Spartan 3E (XC3S500E) which is used in this project [8].

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F igure 2.1.1 Spartan 3E X C3S 500E

2.1.3 Features

Very low cost, high-performance logic solution for high-volume, consumer-oriented

applications.

Proven advanced 90-nanometer process technology

Multi-voltage, multi-standard Select - Up to 376 I/O pins or 156 differential signal pairs - LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards - 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling - 622+ Mb/s data transfer rate per I/O - True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL differential I/O - Enhanced Double Data Rate (DDR) support - DDR SDRAM support up to 333 Mb/s

Abundant, flexible logic resources

- Densities up to 33,192 logic cells, including optional shift register or distributed RAM support

- Efficient wide multiplexers, wide logic - Fast look-ahead carry logic - Enhanced 18 x 18 multipliers with optional pipeline - IEEE 1149.1/1532 JTAG programming/debug port

Hierarchical Select

- Up to 648 Kbits of fast block RAM - Up to 231 Kbits of efficient distributed RAM

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Up to eight Digital Clock Managers (DCMs) - Clock skew elimination (delay locked loop) - Frequency synthesis, multiplication, division - High-resolution phase shifting - Wide frequency range (5 MHz to over 300 MHz)

Eight global clocks plus eight additional clocks per each half of device, plus abundant low-

skew routing

Configuration interface to industry-standard PROMs - Low-cost, space-saving SPI serial Flash PROM - x8 or x8/x16 parallel NOR Flash PROM - Low-cost Xilinx® Platform Flash with JTAG [8].

Table 2.1.1 Summery of SPA R T A N- 3E A ttributes [8]

Device System

gate

Equivale

nt logic

cell

C L B Ar ray (One C L B = 4 slices) Distr ibuted

R A M bites

Block

R A M

bites

Dedicated

multipliers

D C Ms Maximu

m user

I/O

Maximum

Differential I/O

pair

Row Column Total

C L Bs

Total

Slices

X C3S100E 100K 2160 22 16 240 960 15K 72K 4 2 108 40

X C3S250E 250K 5508 34 26 612 2448 38K 216K 12 4 172 68

X C3S500E 500K 10476 46 34 1164 4656 73K 360K 20 4 232 92

X C3S1200E 1200K 19512 60 46 2168 8672 136K 504K 28 8 304 124

X C3S1600E 1600K 33192 76 58 3688 14752 231K 648K 36 8 376 156S

2.1.4 A rchitectural Overview: The Spartan-3E family architecture consists of five fundamental programmable functional elements:

Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data.

Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal

logic of the device. Each IOB supports bidirectional data flow plus 3-state operation. Supports a variety of signal standards, including four high-performance differential standards. Double Data-Rate (DDR) registers are included.

Block RAM provides data storage in the form of 18-Kbit dual-port blocks.

Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product.

Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for

distributing, delaying, multiplying, dividing, and phase-shifting clock signals.

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These elements are organized as shown in Figure 2.1.2. A ring of IOBs surrounds a regular array of CLBs. Each device has two columns of block RAM except for the XC3S100E, which has one column. Each RAM column consists of several 18-Kbit RAM blocks. Each block RAM is associated with a dedicated multiplier. The DCMs are positioned in the center with two at the top and two at the bottom of the device. The XC3S100E has only one DCM at the top and bottom, while the XC3S1200E and XC3S1600E add two DCMs in the middle of the left and right sides. The Spartan-3E family features a rich network of traces that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing.

F igure 2.1.2 Spartan-3E Family A rchitecture [8] 2.1.5 Configuration Spartan-3E FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively control all functional elements an configuration data is stored externally in a PROM or some other non-volatile medium, either on or off the board. After applying power, the configuration data is written to the FPGA using any of seven different modes:

Master Serial from a Xilinx Platform Flash PROM Serial Peripheral Interface (SPI) from an industry-standard SPI serial Flash Byte Peripheral Interface (BPI) Up or Down from an industry-standard x8 or x8/x16

parallel NOR Flash Slave Serial, typically downloaded from a processor Slave Parallel, typically downloaded from a processor Boundary Scan (JTAG) typically downloaded from a processor or system tester.

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Furthermore, Spartan-3E FPGAs support MultiBoot configuration, allowing two or more FPGA configuration bitstreams to be stored in a single parallel NOR Flash. The FPGA application controls which configuration to load next and when to load it [8]. 2.1.6 I/O Capabilities The Spartan-3E FPGA Select I/O interface supports many popular single-ended and differential standards. The number of user I/Os as well as the number of differential I/O pairs available for each device/package combination. Spartan-3E FPGAs support the following single-ended standards:

3.3V low-voltage TTL (LVTTL) Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V 3V PCI at 33 MHz, and in some devices, 66 MHz HSTL I and III at 1.8V, commonly used in memory applications SSTL I at 1.8V and 2.5V, commonly used for memory Applications. Spartan-3E FPGAs support the following differential standards: LVDS Bus LVDS Mini-LVDS RSDS Differential HSTL (1.8V, Types I and III) Differential SSTL (2.5V and 1.8V, Type I) 2.5V LVPECL inputs [8].

2.2 Motivation -access memory (SRAM) based

signers of space-based systems due to their on- xible

-suited to space-based digital signal processing tasks, providing the possibility for orders of magnitude increases in performance over processor-based implementations. Unfortunately, the technology making SRAM-also leaves them especially vulnerable to radiation-induced errors in the space environment when compared to traditional non- [9]. Here in this experiment SPARTAN 3E XC3S500E is used.

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2.3 Radiation E ects on FPG A This content provides a brief background on the e ects of total ionizing dose (TID) and single event e ects (SEE) on electronics and then details particular radiation e ects on FPGAs,

-based FPGAs [9]. 2.3.1 Radiation E ects on E lectronics Radiation e e ects, typically known as total ionizing dose (TID), and single event e ects (SEE). TID describes the cumulative e ects of charged particles on the doping levels of substrate materials within

functionality as a result of a single charged particle interacting with the internal material of an electronic component [9]. 2.3.2 Total Ionizing Dose Total ionizing does (TID) in electronics is a cumulative, long-term degradation mechanism due to mainly protons and electrons depositing charge in electronic components, while a smaller contribution occurs from secondary particles arising from interactions between the primary particles and spacecraft electronics [13]. As a result of the slow accumulation of charge in transi ), TID causes threshold shifts in transistor gate voltage, increased transistor leakage current and timing skews [12]. Initially, TID e ects appear as parametric degradation of the device and ultimately results in functional failure [9].

F igure 2.3.1 Radiation-induced charging of gate oxide in n-channel M OSF E T : (A) normal operation (B) post-ir radiation [10]

A rad is the measure of the amount of energy deposited in the material and is equal to 100 ergs (6.24E4 eV or 10 nJ) of energy deposited per gram of material. The energy deposited in a device must be

oxide semiconductor (MOS) transistor, total dose is measured in units of rad (Si) or rad (SiO2). Ability to withstand TID in Radiation Hardened (Rad Hard) components [11]

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Mitigating TID e ects is typically accomplished using radiation hardened by process (RHBP) techniques and/or shielding. RHBP techniques involve modifying the standard wafer fabrication process and include inserting an oxide layer in the transistor substrate, thinning MOS transistor gate oxides, and growing an epitaxial layer under regions of high doping density [12]. Placing shielding material (such as aluminum) around sensitive electronics can reduce TID by absorbing most electrons and lower energy protons. As shielding is increased, however, shielding effectiveness decreases because of the difficulty in slowing down higher energy protons [13]. 2.3.3 Single Event E ects Single event e ects (SEE) are the electrical disturbances caused by an energetic charged

[14]. The passage of a single charged particle through a device or a sensitive region of a microcircuit can induce SEE. Figure 2-2 shows a representation of a charged particle depositing charge as it passes through the physical structure of a transistor.

F igure 2.3.2 Charge deposition by charged particle into the substrate of a transistor [14] In order for a charge particle (heavy ion or proton) to a ect the operation of a circuit, it must transfer su output state changes. The minimum amount of charge required is usually referred to as Qcrit, as shown below in Qcrit = Cnode × Vnode (2.3.1) Where Cnode is the capacitance between transistor nodes and Vnode is the transistor operating voltage. Thus as transistor process sizes shrink (resulting in decreased capacitance) and transistor operational voltage decreases, Qcrit decreases [12], and the charged particle energy necessary for upset is also decreased. In a latching circuit with memory elements, a single event effect can cause the wrong value to be stored and thus produce an error lasting until the value in memory is corrected/m while a single event effect in a combinatorial circuit can create a transient error in a lead to errors such as a pin outputting an incorrect value or a circuit element latching incorrect data [12]. SEE can manifest in several forms:

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Single Event Upset (SE U): Single events upsets occur when a single charged particle causes one or more hin the device to change state. If only a

the SEU is called a multi-bit upset (MBU).

Single Event T ransient (SE T): A single event transient occurs when a single charged

particle causes a temporary voltage/current spike. If the pulse width of this spike is su ciently -propagate through the circuit [15]. The probability of an error being latched increases with increasing clock frequency [16].

Single Event Latchup (SE L): Single event latchup is the high current state of a bi-stable parasitic four-layer PNPN structure inherent in complementary metal oxide semiconductor (CMOS) where a short circuit sustains itself through positive feedback. It may be triggered by single-event charge deposition or electrical noise, but the only way to remove latchup is to cycle power. [17] Traditionally in radiation testing, any sudden high current mode that requires a power cycle of the component to recover functionality

[17] Depending on the duration and amplitude of the high current condition, a SEL may cause permanent damage to a device [12]. Vertical thyristors in CMOS technology cause SEL. [18].

Single Event Functional Inter rupt (SE F I): A single event functional interrupt is an upset of an internal memory element or a circuit whicfunctionality [12]. Traditionally, to recover an FPGA-based system from a device SEFI, the FPGA must be re-involves a minimum outage of some tens or hundreds of milliseconds [17]. Single Event Gate Rupture.

Single event gate ruptures (SE G R): primarily a ect metal oxide semiconductor e ect transistors (MOSFETs) when operating in the OFF condition (no between drain to source). However, MOSFETs in the ON state still are susceptible to over current conditions caused by charged particle interaction.

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2.4 X-ray radiation producing machine (X- R A D iR 160)

F igure 2.4.1 X-ray radiation producing machine (PV A M U laboratory) [19]

2.4.1 Overview

The X-RAD iR-160 is a compact cabinet X-ray irradiator designed for superficial irradiation studies, and is ideal for delivering high doses to cell and tissue cultures. The Operator Interface is simple to use and yet offers the greatest amount of flexibility for performing high and low dose exposures over a broad range of settings [19]. 2.4.2 Features

Dual Focus X-Ray tube for combined use

Beam Conditioning Filters

Fixed Beam Limiting Apertures

Motorized Turntable

http://pxinc.com/

http://pxinc.com/

http://pxinc.com/

http://pxinc.com/

http://pxinc.com/

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2.4.3 Specifications

Cabinet Features Adjustable Sample Shelf: 10 to 100cm SSD Changeable Beam Conditioning Filter Slides Cabinet Port to introduce small tubing and cables into chamber area Complies with US and International regulations for Cabinet X-ray systems

Cabinet Size and W eight

Weight: 1900 lbs (862 kg)

Power Requirement 1N PE 208-230, 50/60 Hz, 8 KVA

High Voltage Generator Maximum Output Voltage: 160 KV Maximum mA: 45

X-ray Tube Maximum Potential: 160 KV Maximum Power: 3000 W (higher power option available) Type: Metal Ceramic, Fixed Anode, Water Cooled Focal Spot: 7.5 mm (per EN12543) Inherent Filtration: 0.8mm Be Cooling Pump: Water-Air

Dose Output Raw Beam: >60 Gy/min at 160KV, 19mA, 30 cm SSD Filtered Beam: >6.5 Gy/min at 160KV, 19mA, 30cm SSD, (Filter = 2mm Al)

Operators Control KV Setting & Display Accuracy: 7.5KV 160 KV in 0.1 KV increments mA Setting & Display Accuracy: 0.5mA to 45 mA in 0.01 mA increments Settings Accuracy: < 1% Exposure Timer: 2-600 seconds or 10-99.9 minutes or continuous Programmable Settings: 500 locations to recall exposure parameters

Additional X-Ray Unit Features

Automatic warm-up [19].

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2.5 Similar research based on this project [20]

2.5.1 Analysis of T ID Failure Modes in SR A M-Based FPG A under Gamma-Ray and Focused Synchrotron X-Ray ir radiation

In this study, the selected commercial FPGA is BQV300, fabricated by Beijing Microelectronics Technology Institute, China. The architecture of BQV family FPGA is similar to the architecture of Xilinx Virtex series. BQV300 is based on a 0.25 µm CMOS/epi -layer metal SRAM bits, four DLL, and a ceramic brazed 228-pin package. Compared with other state-of-the-art devices, this FPGA is chosen for several reasons. First, this study focuses on the TID effect of SRAM-based FPGA, as well as on the implementation of focused synchrotron x-ray in analyzing the TID effect of complicated devices.

The whole-chip TID experiment was executed using Co-60 source in Northwest Institute of Nuclear Techniques with the dose rate of 50rad (SiO2)/ s. Four SRAM-based FPGAs were irradiated under ray environment, with two biased in static mode and the other two biased in dynamic mode during the irradiation procedure. Fig. 2.5.1 and Fig. 2.5.2 show the corresponding supply currents (ICC) as a function of deposited dose. The chip 1-1 worked functionally up to 70 krad (SiO2) as shown in Fig. 2.5.1. However, the DUT (device under test) could not be

the deposited dose reached 75 krad (SiO2). After annealing at room temperature, DUT did not return to its normal state. The chip1-2 was irradiated until the deposited dose reached 60 krad (SiO2), and no functional error occurred. However, when the DUT was mounted to the IC parameters tester and the power supply was on, the supply current of the entire equipment increased remarkably, and then entered the safety mode. In other words, the DUT could not be initialized.

F igure 2.5.1 (A) Supply currents of DU Ts (I C C) as a function of deposited dose when the DU Ts were biased in static mode during the ir radiation procedure. (B) Supply currents of DU Ts (I C C) as a function of deposited dose when the DU Ts were biased in dynamic mode during the ir radiation procedure.

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2.5.2 Microbeam ir radiation by means of synchrotron x-ray. The synchrotron x-ray irradiations were performed in Beijing Synchrotron Radiation facility, with 15 keV photon energy, 20 x 20 µ m2 spot size, and approximately 1 x 1010 photons/s initial yield. The schematic of synchrotron x-ray irradiation environment is illustrated in Fig. 2.5.2. The synchrotron x-ray beam traverses through the shielding Al foil (or Pb foil), the ionization chamber and the focusing capillary, before it strikes the device at a 45 angle. A microscope (450 X) is placed perpendicular to the DUT to display the surface of the device, assist in the seundisturbed.

F igure 2.5.2 Schematic of synchrotron x-ray ir radiation environment.

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-based FPGA, namely, CLB, BRAM, IOB, DLL and POR, were selected to study their comparative vulnerability (Fig. 2.5.3). Given that the size of the x-ray beam was considerably small, apart from IOB circuit, two or three points were chosen for one component. Table 2.5.1 summarizes the corresponding phenomena when striking at chosen positions.

F igure 2.5.3 Locations of several typical components in the SR A M-based FPG A .

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Table 2.5.1 Summary of the phenomena in the synchrotron x-ray ir radiation experiment

The conclusion of this research is the TID failure modes in SRAM-based FPGA were investigated by means of common -ray and focused synchrotron x-ray irradiation. Following the usual procedure, the whole-chip irradiation was conducted under -ray environment. To determine which inner circuit is responsible for the functional error, focused synchrotron x-ray irradiation with beam size of 20 µm was introduced. The results obtained under synchrotron x-ray irradiation show that the POR circuit is responsible for the whole chip failure mode with the lowest threshold. Given the difference between the two irradiation sources, the failure threshold corresponding to Co-60 -ray is 60 krad, whereas that for synchrotron x-ray is 88.7 krad . The main factors that induce the difference are the dose enhancement factor and the charge yield. Given that the packages of the DUTs were refactor. The most vulnerable inner circuit of an SRAM-based FPGA can be investigated directly using the focused synchrotron x-ray. In addition, circuit simulation considering TID degradation was performed. The simulated results are consistent with the experiment results. This procedure can provide additional information of failure mechanism of a DUT.

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Chapter 3: Methodology 3.1 Ver ilog program with code that generate outputs with 3 specific patterns for full adder .

3.1.1 Setting up a New Project and specifying a ci rcuit in Verilog

Start the ISE 14.6 tool from Xilinx.

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Create a new project. The Create New Project wizard will prompt a location for project.

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On the second page of the Create New Project dialog, give the details of the device (in this case Spartan3e Device Family, XC3S500 Device, FG320 Package, -5 Speed Grade).

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module and name it.

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In the next page define the inputs and outputs for new module. Click on finish.

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Template for a Verilog module appears on the screen, with inputs outputs specified from previous step.

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Here example of

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Simulating the Circuit:

ISE simulator with a test bench is used to simulate the circuit. Note that the testbench files that drive the simulations are also Verilog files.

1. NewSource menu again, or select the Create New Source widget. This will bring up the New Source Wizard. Select Verilog Test Fixture in the list on the left and name it.

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2. The Next dialog prompts to select which source to want the testbench constructed from. In this case fulladder.

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3. Note that the generated template has some generated code. That initializes input values in this template. In this case input signals are assigned for full adder under initialize inputs.

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4. Once the testbench fill with Verilog code to drive the simulation, it can check the syntax and run the simulation from the Processes tab.

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5. After run the simulation, another tab will open in which simulation results are shown as waveforms.

3.1.2 Synthesizing ci rcuit to the X ilinx FPG A

After successively simulating Verilog module, ISE (webPACK) tool synthesize Verilog to something that can be mapped to the Xilinx FPGA. That is, the Verilog code will be converted by ISE to some gates that are on the FPGA. To be even more specific, ISE will convert the Verilog project description into a set of configuration bits that are used to program the Xilinx part. Those configuration bits are in a .bit file and are downloaded to the Xilinx part in this section of the tutorial.

Assign inputs (a,b,Cin) to switches and outputs(s,Cout) to LEDs of the pins of FPGA. Synthesize the Verilog code into FPGA configuration. Generate a programming file with all this information (.bit file) Use the impact tools from Xilinx (part of WebPACK) to configure the FPGA through the

USB connection.

1. in the bottom (Processes) pane you will see some options including User Constraints, Synthesize, and Implement Design. Expand that tab and select the I/O Pin Planning (PlanAhead) Pre- Synthesis choice, which will allow assigning pins.

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This will open a whole new tool called PlanAhead which you can use to set your pin constraints. In this case click YES to add a UCF (Universal Constraints File) file to project.

2. The Plan Ahead tools set a number of different types of constraints on how the circuit is

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3. Spartan-and LEDs .The four sliding switches on the Spartan-3E board are, from left to right as

and L13.

The LEDs are also described in the User Guide:

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4. Clicking on each I/O Port in turn will open the I/O Port Properties pane where update the Site field to say which Xilinx pin should be used for that I/O signal. Using the user guide pins, assign input signals to switches and output to LEDs.

5. like following.

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6. Synthesize XST . Double click on this to synthesize the circuit. Got the console. Make sure that the

process is ended with a green check for this process. If there is something else,

7. With the source file selected (fulladder in this case), double click the Implement Design process in the Processes tab. This will translate the design to something that can physically be mapped to t board (the xc3s500e-5fg320 in this case). See a green check mark if this step finishes without issues. If there are issues, need to read them for clues about what went wrong and what should look at to fix things.

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8. If this Implement Design tab is expanded (which is not necessary) that will see the Implement Design process actually consists of three parts:

a. T ranslate: Translate is the first step in the implementation process. The Translate

process merges all of the input netlists and design constraint information and outputs a Xilinx NGD (Native Generic Database) file. The output NGD file can then be mapped to the targeted FPGA device.

b. Map: physical elements that actually implement logic functions in a device. The Map process creates an NCD (Native Circuit Description) file. The NCD file will be used by the PAR process.

c. Place and Route (PA R): PAR uses the NCD file created by the Map process to place

and route your design. PAR outputs an NCD file that is used by the bitstream generator (to actually program the FPGA.

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9. At this point look at the Design Summary to find out all sorts of things about the circuit. One thing that must be check is to click on the Pinout Report and check that the signals were correctly assigned to the pins wanted them to be assigned to.

10. Now double click the process: Generate Programming F ile. This will generate the actual configuration bits into a .bit file that can use to program your Spartan-3E board to behave like the circuit (in this case a full adder).

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11. Now to programming the file, the Spartan-3E board using the iMPA C T tool and the USB cable on the PC/laptop. First, make sure that the jumpers on your Spartan-3E board are installed correctly. In particular, check that the configuration options are correctly set. The configuration options are at the top of the board near the RS232 interfaces.

F igure 3.1.1 Spartan 3E starter kit FPG A configuration options.

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The jumpers on the J30 headers must be set for JTAG programming. This means that only the middle pins of the header should have a jumper on them. See the following illustration from the User Guide. The board should look like this!

F igure 3.1.2 Detailed configuration option.

12. Now that you have the jumpers set correctly, you can plug in the power to your Spartan-3E board, and connect the USB cable between the Spartan- 3E and your PC. Then when you turn on the power, the PC should recognize the Xilinx cable/board and install the drivers.

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13. Once the PC has recognized the USB connection to the Spartan-3E board, use the Process Configure Target Device to start up the iMPACT tool to program the FPGA.

14. The first time configure the Target Device for a new project; get the following message about setting up an iMPACT file. Then click OK here and start up the iMPACT tool.

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15. Now get yet another tool the iMPACT device configuration and programming tool:

16. Double-click the Boundary Scan button to configure the Xilinx part for programming. Boundary Scan is the technique that is used on these devices for uploading the bit file to the Xilinx part through the USB cable. You will be prompted to Right Click to Add Device or Initialize JTAG Chain. JTAG is the acronym for the boundary scan standard that is used for programming in this case. When you right-click you get a menu. Select Initialize Chain. There are actually three programmable parts on the Spartan3 board and they are organized in a chain passing the bits from one device to the other. This is the chain that is being initialized.

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Note that the board must be plugged in to the USB cable and turned on for this step! The initialization procedure sends a query out on the USB cable to see what chips are out there. If you have everything plugged in and turned on it will see the chips and initialize the chain.

Now continue and assign a configuration file:

.

17. Now be asked to choose a configuration file (which will be a .bit file) or each of the programmable chips on the Spartan-3E board. In this case its fulladder.bit

18. If want to attach an SPI or BPI PROM to the device. For this case click no. There is a 16Mbit SPI PROM attached to the Xilinx part and later on that may want to include a PROM data file here so that the bitstream will also load that prom.

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For each of the other chips, choose to open a file (attach a .bit file to that chip), or to bypass. Choose bypass for the other chips (the xcf04s and the xc2c64).

The summary looks like this:

19. In the iMPACT screen, the following window that shows the programmable chips and the associated bit files or bypass configurations.

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20. Now select the Spartan-3E (the xc3s500e) and right click to get a dialog. Select Program in this dialog to program the FPGA.

21. See the following indication that the programming has succeeded. Also see the xc-done LED (a little yellow LED underneath the J30 jumper on the board) light up if the programming is successful.

22. The circuit should now be running on the Spartan-3E board. Now able to set the sw3, sw2, and sw1 switches as inputs and look for the full adder output on LDE1 and LED0. That verifies results with simulation.

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23. Now to make changes and want to reload the bit file to the FPGA (after making changes, for example), restart the iMPACT tool using the Manage Configuration Project (iMPACT) option under Configure Target Device.

Then right click on the xc3s500e device and program it with the new bit file or use the iMPACT Processes in the lower left:

3.2 Bombard FPG A with X-ray total ionizing radiation. 3.2.1 Setup of X-ray machine

In x-ray machine there are 3 positions (dose rate) to bombard the sample. 30 cm 50 cm 70 cm As per ; I = intensity of dose. (3.2.1)

d = distance According to above equation intensity is higher at lower distance, so for this experiment used 30 cm position.

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Here this is the time period calculation for various X-ray radiation doses.

Power mode unfiltered.

P Mode = 59.22Gy/min 100rad = 1Gy

59.22Gy = 5922rad

SoI30 = 5922rad/min

For 1 Krad calculate the time for expose the sample. 5922rad = 1min Table 3.2.1 Calculated time according to given dose.

Dose (Krad)

Calculated time (min)

11 2 31 5 61 10 101 17 151 25 211 35 281 46 361 60 451 75 551 92

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3.2.2 Now expose the FPG A board with different dose for calculated time (30 cm SSD) in an x-ray radiation producing machine

3.2.3 After applying each dose programming the FPG A (repeat the step 12-22 of program 3.1.2) and check the result by I/O switch on FPG A board.

3.2.4 Annealing process

Observe the I/O result of FPGA after 24 hours of annealing at room temperature.

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3.2.5 Measure the supply voltage pin on FPG A chip

Once it stops working, measure the VCCINT voltage on FPGA chip and compare with non radiated chip to confirm effect of radiation on FPGA chip.

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Chapter 4: Result and discussion 4.1 Verilog code for full adder program success.

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F igure 4.1.1 Red L E D indicates the power supply and the yellow L E D indicate the

successfully loaded program on FPG A board. Table 4.1.1 I/O switches give the result as shown in below table for full adder .

Input

Output

A B C in S C out 0 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1

Table 4.1.2 Result after bombard FPG A board with various doses

Dose (krad)

Result Time to load the program on FPGA chip after bombard

1 Program successful 15 20 min






211 Stop working ----

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4.2 Annealing process After 24 hours of annealing at room temperature, FPGA (DUT) did not return to its

normal state. The device may got catastrophic failure after exposed by 60krad x-ray TID

4.3 Conformation of the radiation effect on FPG A chip.

F igure 4.3.1 Measured voltage for V C C IN T (FPG A chip)

After getting this 1.46 voltage at VCCINT pin on bombarded FPGA chip, compare VCCINT voltage of non radiated FPGA chip which is same, proves that the peripheral circuit of FPGA board works properly but the FPGA chip is directly affected by the x-ray radiation dose. Also check the temperature of bombarded chip with infrared temperature detector, which

detect any hotspot on the chip.

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Chapter 5: Conclusion and Future work The TID failure mode in Spartan 3E FPGA is analyzed by applied different value of x-ray total ionizing radiation dose. The result obtain under x-ray total radiation environment, the device got catastrophic failure between 151-211 krad. After 24 hours of annealing at room temperature the device did not get recovery. Compared VCCINT voltage of radiated and non- is 1.46 V, which gives the conformation of FPGA chip affected by x-ray total ionizing radiation dose. There is need to do the further investigation to know which particular sub inner circuit of FPGA chip is responsible for failure mode.

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R e fe r enc es

[1]3524 , D e c .

2006 .

[2] X . Y ao , N . H indman , L . T . C l a r k , K . E . H olbe r t , D . R . A l e xande r , and

T r ans . N uc l . Sc i . , vol . 55 , no . 6 , pp . 3280 3287 , D e c . 2008 .

[3] upse ts i 3114 , D e c . 1996 .

[4i r r ad ia t iononSi ngl e-1772 1778 , A ug . 2006 .

[5] A na lys is of T I D F a i lu r e M od es i n SR A M -B ase d F P G A U nde r G amma-R ay and F oc use d Sync h rot ron X -R ay I r r ad ia t ion L i l i D ing , H ongx ia G uo , W e i C he n , Z h i b in Y ao , Y ihua Y an , Dongl i ang C he n , A l essand ro Pac c agne l l a , Simone G e r a r d in , M a r ta B agat in , L e i C he n , H uabo Sun , and R uyu F an , I E E E T R A NS A C T I O NS O N N U C L E A R S C I E N C E , V O L . 61 , N O . 4 , A U G US T 2014

[6] Prepared by Sandi Habinc, compilation f rom various sources FPG A-002-01 Version 0.4 September 2002

[7] http://www.coe.montana.edu/ee/courses/ee/ee367/pdffiles/truegamer .pdf

[8] http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf

[9] Fault Tolerant Design Implementation on Radiation Hardened By Design SR A M-Based FPG As by F rank Hall Schmidt, Jr . B .S., E lectrical Engineer ing (2011) United States A ir Force Academy.

[10]T .R . O ldham and F .B . Mc Lean Total ionizing dose e ects in M OS oxides and devices. I E E E T ransactions on Nuclear Science, 50(3):483 499, June 2003. 32

[11] James Schwank Marty Shaneyfelt, and Paul Dodd. Radiation Hardness As- surance T esting of Microelectronic Devices and Integrated C ircuits: Radiation Environments, Physical Mechanisms, andFoundations for Hardness Assurance. T echnical Report SA ND-2008-6851P, Sandia National Laboratories, 2008 32

[12] Matthew Mc Cormack . T rade Study and Application of Symbiotic Software and Hardware F ault-tolerance on a Microcontroller-based Avionics System. PhD thesis, Massachusetts Institute of Technology, May 2011. 32, 33, 34, 35, 55, 63, 103, 135

[13] Ray Ladbury. Osi ris-rex radiation hardness assurance plan. Technical Report OSIRIS-R Ex-PL A N-0014, N ASA Goddard Space F light Center , January 2012. 32, 33, 35, 36

http://www.coe.montana.edu/ee/courses/ee/ee367/pdffiles/truegamer.pdf

http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf

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[14] Brendan Bridgford, Carl Carmichael, and Chen W ei Tseng. Single-Event Upset Mitigation Selection Guide. X APP987 v1.0, X ilinx, March 2008. 33, 41, 53, 55, 58, 59, 68, 198

[15] Nathaniel Rollins. Hardware and Software F ault-Tolerance of Softcore Processors Implemented in SR A M-Based FPG As. PhD thesis, B righam Young University, April 2012. 34, 39, 40, 52, 53, 55, 57, 58, 60, 61

[16] J. Engel, M . Wirthlin, K . Morgan, and P. G raham. Predicting On-O rbit Static Single Event Upset Rates in X ilinx V irtex FPG As. Los A lamos National Labo- ratory, September 2006. 34, 36, 45, 46, 47, 49, 50, 51

[17] G . Swift and G . A llen. V irtex-5Q V Static SE U Character ization Summary. T echnical report, X ilinx Radiation Test Consortium, July 2012. 35, 42, 44, 62, 64, 66, 112

[18] H eather Quinn. An Introduction to Mission Risk and Risk Mitigation for X ilinx SR A M FPG As, 2009. 35, 37, 52, 55, 56

[19] http://pxinc.com/products/cabinet-ir radiators/x-rad-160-ser ies/

[20] Analysis of T ID Failure Modes in SR A M-Based FPG A Under Gamma-Ray and Focused Synchrotron X-Ray I r radiation I E E E T R A NSA C T I O NS O N NU C L E A R SC I E N C E , V O L . 61, N O . 4, A U G UST 2014

http://pxinc.com/products/cabinet-irradiators/x-rad-160-series/

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