[email protected] engr-43_lec-14a_ideal_op_amps.pptx 1 bruce mayer, pe engineering-43:...

[email protected] • ENGR-43_Lec-14a_IDeal_Op_Amps.pptx1

Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

Bruce Mayer, PELicensed Electrical & Mechanical Engineer

[email protected]

Engineering 43

Chp 14-2Op Amp Circuits



RC OpAmp Circuits Introduce Two Very

Important Practical Circuits Based On Operational Amplifiers

Recall the OpAmp

The “Ideal” Model That we Use• RO = 0

• Ri = ∞

• Av = ∞

• BW = ∞

Consequences of Ideality• RO = 0 vO = Av(v+−v−)

• Ri = ∞ i+ = i− = 0

• Av = ∞ v+ = v−

• BW = ∞ OpAmp will follow the very Highest Frequency Inputs



RC OpAmp Ckt Integrator

KCL At v− node By Ideal OpAmp• Ri = ∞ i+ = i− = 0

• Av = ∞ v+ = v− = 0

0=+v

ivv

dt

dC

R

vvo2

1

1



RC OpAmp Integrator cont

By the Ideal OpAmp Assumptions

Separating the Variables and Integrating Yields the Solution for vo(t)

A simple Differential Eqn

Thus the Output is a (negative) SCALED TIME INTEGRAL of the input Signal



RC OpAmp Ckt Differentiator

By Ideal OpAmp• v− = GND = 0V

• i− = 0

KCL at v−

2i

1i

KVL

iii 21

Now the KVL

01111 CviRv

1R

0=+v

1Cv



RC OpAmp Differentiator cont.

Recall Ideal OpAmp Assumptions• Ri = ∞ i+ = i− = 0

• Av = ∞ v+ = v− = 0

Then the KCL

Recall the Capacitor Integral Law

Thus the KVL

02

121 R

viii O

t

C dxxiC

tv1

t

dxxiC

iRtv )(1

)( 11

111

Multiply Eqn by C1, then Take the Time Derivative of the new Eqn

)(111

111 t

dt

dvCi

dt

diCR

1i

1R 2i



RC OpAmp Differentiator cont

In the Previous Differential Eqn use KCL to sub vO for i1• Using

Examination of this Eqn Reveals That if R1 were ZERO, Then vO would be Proportional to the TIME DERIVATIVE of the input Signal• In Practice An Ideal

Differentiator Amplifies Electrical Noise And Does Not Operate well

• The Resistor R1 Introduces a Filtering Action. – Its Value Is Kept As Small As

Possible To Approximatea Differentiator

21 R

vi O

)(11211 t

dt

dvCRv

dt

dvCR o

o

1i

1R 200 Rv



Aside → Electrical Noise ALL electrical signals

are corrupted by external, uncontrollable and often unmeasurable, signals. These undesired signals are referred to as NOISE

The Signal-To-Noise Ratio

Simple Model For A Noisy 1V, 60Hz Sinusoid Corrupted With One MicroVolt of 1GHz Interference

)102sin(10)120sin()( 96 ttty

Signal Noise

V

1V10

amplitude noise

amplitude signalSN 6

Use an Ideal Differentiator)102cos(2000)120cos(120)( 9 ttt

dt

dy

The SN is Degraded Due to Hi-Frequency Noise

Signal Noise

50

3

2000

120

amplitude noise

amplitude signalSN



Class Exercise Ideal Differen.

Given Input v1(t)• SAWTOOTH Wave

Let’s Turn on the Lites for 10 minutes for YOU to Differentiate

Given the IDEAL Differentiator Ckt and INPUT Signal

Find vo(t) over 0-10 ms

F 2

k 1

F 2

k 1

Recall the Differentiator Eqn

)(11211 t

dt

dvCRv

dt

dvCR o

o

R1 = 0; Ideal ckt



RC OpAmp Differentiator Ex.

Given Input v1(t)

The Slope from 0-5 mS

F 2

k 1

F 2

k 1

s

V

dt

dvm

31

105

10

For the Ideal Differentiator

)(112 t

dt

dvCRvo

Units Analysis

sFV

QF

Q

sV

sQV

A

V



RC OpAmp Differentiator cont.

Derivative Scalar PreFactor

A Similar Analysis for 5-10 mS yields the Complete vO

F 2

k 1

F 2

k 1

mSin 50:45

20105

10102

331

12

tVVv

S

VS

dt

tdvCRv

o

o

sCR 36312 102F102101

Apply the Prefactor Against the INput Signal Time-Derivative (slope)

InPutOutPut



RC OpAmp Integrator Example

Given Input v1(t)• SQUARE Wave

For the Ideal Integrator

Units Analysis Again

sFV

QF

Q

sV

sQV

A

V

μF 0.2

k 5

t

ioo dxxvCR

vtv021

)(1

)0()(

Vvo 0)0(



RC OpAmp Integrator Ex. cont.

The Integration PreFactor

0<t<0.1 S• v1(t) = 20 mV (Const)

1

21

1000001.0

1

2.05

11

SSFkCR

Next Calculate the Area Under the Curve to Determine the Voltage Level At the Break Points

SmVSmVSvCRNote

tmVduuvvCRtvCR

o

t

oo

21.020)1.0(:

20)()0()(

21

0

12121

0.1t<0.2 S• v1(t) = –20 mV (Const)

tmVSmV

dzzvvCRtvCRt

oo

202

)()1.0()(1.0

12121

Integrate In Similar Fashion over• 0.2t<0.3 S• 0.3t<0.4 S



RC OpAmp Integrator Ex. cont.1 Apply the 1000/S PreFactor and Plot Piece-Wise



Design Example

Design an OpAmp ckt to implement in HARDWARE this Math Relation

t

vdyyvv0

210 25

Examine the Reln to find an

Integrator Summer



Design Example

The Proposed Solution The by Ideal OpAmps & KCL & KVL &Superposition

t

vdyyvv0

210 25

t

vdyyvv0

210 25



Design Example

3

4

21

4 2;5R

R

CRR

R

Then the Design Eqns

t

vdyyvv0

210 25

The Ckt Eqn

TWO Eqns in FIVE unknowns

This means that we, as ckt designers, get to PICK 3 values

For 1st Cut Choose• C = 20 μF• R1 = 100 kΩ

• R4 = 20 kΩ



Design Example

In the Design Eqns

t

vdyyvv0

210 25

kR

FRk

k

20

20100

205

2

2

kR

R

k

10

202

3

3

If the voltages are <10V, then all currents should be the in mA range, which should prevent over-heating

20μ

100k

20k

10k

20k

Then the DESIGN



LM741 OpAmp Schematic



Some LM741 Specs



OpAmp Frequency Response

The Ideal OpAmp has infinite Band-Width so NO Matterhow FAST the inputsignals

However, REAL OpAmps Can NOT Keep up with very fast signals• The Open Loop Gain, AO, starts to degrade

with increasing input frequencies

ov

tvtvAtv Oo 21



Gain∙BandWidth for LM741

520/100 1010 OA

−20db/DecadeSlope

The Unity Gain Frequency, ft, is the

BandWidth Spec

100BOf



BandWidth Limit Implications Recall the OpAmp

based Inverting ckt

The NONideal Analysis yielded

Noting That All the R’s are Constant; Rewrite above as

For Very Large A

o

S

O

RRA

RK

K

v

v

222

2

1

11

1

1

22

1

11lim K

K

RRAK

K

v

v

oA

S

O



BandWidth Limit Implications As Frequency

Increases the Open-Loop gain, A, declines so the Limit does NOT hold in:

If

Then the Denom in the above Eqn ≠ 1

Thus significantly smaller A DECREASES the Ideal gain

For Typical Values of the R’s the Open-Loop Gain, A, becomes important when A is on the order of about 1000

222

1

RRR

A

o

dB 6010log2010 33



Gain∙BandWidth for LM741

520/100 1010 OA

Frequency significantly degrades Amplification Performance for Source Frequencies > 10 kHz



Voltage Swing Limitations Real OpAmps Can

NOT deliver Unlimited Voltage-Magnitude Output

Recall the LM741 Spec Sheet that show a Voltage Output Swing of about ±15V• For Source Voltages

of ±20 V

If the Circuit Analysis Predicts vo of more than the Swing, the output will be “Clipped”

Consider the Inverting Circuit:

k 7.4

k 1

t 2k6.1cosV4k .15



Vswing Clipping Since the Real

OutPut can NOT exceed 15V, the cosine wave OutPut is “Clipped Off” at the Swing Spec of 15V

0 0.5 1 1.5 2 2.5 3 3.5 4-20

-15

-10

-5

0

5

10

15

20V

oIde

al (

V)

Ideal vs. Real

0 0.5 1 1.5 2 2.5 3 3.5 4-20

-15

-10

-5

0

5

10

15

20

time (mS)

VoR

eal (

V)

ENGR43_Lec14b_OpAmp_V_Swing_Plot_1204.m



Short-Ckt Current Limitations Real OpAmps Can

NOT deliver Unlimited Current-Magnitude Output

Recall the LM741 Spec Sheet that shows an Output Short Circuit Current of about 25mA

If the Circuit Analysis Predicts io of more than This Current, the output will also be “Clipped”

Consider the Inverting Circuit:

k 7.4

k 1

t 2k6.1cosV4 105



CurrentSaturation

Since the Real OutPut can NOT exceed 25mA, the cosine wave OutPut is “Clipped Off” at the Short Circuit Current spec of 25mA

ENGR43_Lec14b_OpAmp_Current_Saturation_Plot_1204.m

0 0.5 1 1.5 2 2.5 3-40

-30

-20

-10

0

10

20

30

40iL

-Ide

al (

mA

)

Ideal vs. Real

0 0.5 1 1.5 2 2.5 3-40

-30

-20

-10

0

10

20

30

40

time (mS)

iL-R

eal (

V)



Slew Rate = dvo/dt

For a Real OpAmp we expect the OutPut Cannot Rise or Fall Infinitely Fast.

This Rise/Fall Speed is quantified as the “Slew Rate”, SR

Mathematically the Slew Rate limitation

The 741 Specs indicate a Slew Rate of

SRdt

dvo

SV 500,000 SR

OR µSV 0.5SR



Slew Rate = dvo/dt

If dvin/dt exceeds the SR at any point in time, then the output will NOT be Faithful to input• The OpAmp can

NOT “Keep Up” with the Input

Consider the Example at Top Right

Then the Time Slope of the Source

t

sec

10sinV5.2

5

sec

10

sec

10cosV5.2

55

t

dt

dv s



Slew Rate = dvo/dt

The Maximum value of dvS/dt Occurs at t=0. Compare the max to the SR

Thus the source Rises & Falls Faster than the SR

When the Source Slope exceeds the SR the OpAmp Output Rises/Falls at the SR• This produces a

STRAIGHT-LINE output with a slope of the SR when the source rises/falls Faster than the SR until the OpAmp“Catches Up” withthe Ideal OutPut

t

sec

10sinV5.2

5

sec

V 400 785

sec

101V5.2

max

5

max

dt

dv

dt

dv

s

s



Slew Rate = dvo/dt

Ideal,ov

Real,ov

µS t

t

sec

10sinV5.2

5



Full Power BandWidth The Full Power BW

is the Maximum Frequency that the OpAmp can Deliver an Undistorted Sinusoidal Signal• The Quantity, fFP, is

limited by the SLEW RATE

Determine This Metric for the LM741

The 741 has a max output, Vom, of ±12V

Applying a sinusoid to the input find at full OutPut power (Full Output Voltage)

Recall the Slew Rate

tVtv omo sin

SRdt

dvo



Full Power BandWidth Taking d/dt of the

OpAmp running at Full Output

Thus the maximum output change-rate (slope) in magnitude

Recall ω = 2πf Setting |dvo/dt|max = to

the Slew Rate

tV

dt

tdv

tVtvdt

d

omo

omo

cos

sin

omo

omo

Vdt

tdv

tnVdt

tdv

max

max

or

cos

SRπfVV omom 2



Full Power BandWidth Isolating f in the last

expression yields fFP:

From the LM741 Spec Sheet• SR = 0.5 V/µS• |Vomax|min = 12V

Then fFP:

omFP πV

SRf

2

kHz 63.6

cycle 6316

cycle 0066.0

V 12cycle

2V/µS 5.0

LM741,

LM741,

LM741,

LM741,

FP

FP

FP

FP

fS

f

µSf

πf



Full Power BandWidth Thus the 741

OpAmp can deliver UNdistorted, Full Voltage, sinusoidal Output (±12V) for input Frequencies up to about 6.63 kHz

kHz 63.6LM741, FPf



WhiteBoard Work

60µF

F igure P F E-3

Cx

8V+

-24V

+

-

Let’s Work These Probs

Choose C Such That

Find Energy Stored on Cx

dttvS

v So 10



All Done for Today

OpAmpCircuitDesign



Bruce Mayer, PERegistered Electrical & Mechanical Engineer

[email protected]

Engineering 43

Appendix



Practical Example Simple Circuit Model For a

Dynamic Random Access Memory Cell (DRAM)

Also Note the TINY Value of the Cell-State Capacitance (50x10-15 F)

Note How Undesired Current Leakage is Modeled as an I-Src



Practical Example cont

The Criteria for a Logic “1”• Vcell >1.5 V

Now Recall that V = Q/C• Or in terms of Current

During a WRITE Cycle the Cell Cap is Charged to 3V for a Logic-1• Thus The TIME PERIOD

that the cell can HOLD the Logic-1 value

t

CCC dxxiC

vv0

)(1

)0(

VtC

IV

C

tIVV

cell

leak

cell

leakcell 5.15.13

sA

FVtH

312

15

105.11050

)(1050)(5.1

Now Can Calculate the DRAM “Refresh Rate”

HzmSt

fH

R 6675.1

11min,



Practical Example cont.2 Consider the Cell at the

Beginning of a READ Operation fCoulfCoulfCoulQ

fCoulfFVQ

fCoulfFVQ

total

out

cell

825675150

6754505.1

150503

fFCtotal 50045050 Then The Output

VfF

fCoul

C

QV OI 65.1

500

825/

Calc the Best-Case Change in VI/O at the READ

When the Switch is Connected Have Caps in Parallel

[email protected] engr-43_lec-14a_ideal_op_amps.pptx 1 bruce mayer, pe engineering-43:...

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