WORK PORTFOLIO FOR DAN T. BRACKETT

DAN T. BRACKETT10771 Black Mountain Road# 38San Diego CA 92126 Cell Phone – 602-690-5558 Email - dtbrackett88@gmail.com http://www.linkedin.com/

INTEGRATED CIRCUIT MASK DESIGNER

QUALIFICATIONS:

· Generating IC mask designs targeted for offsite foundries such as TSMC and Samsung Semiconductor. Process design rules for TSMC include 28 nm and 20 nm FinFet. Process design rules for Samsung Semiconductor include the FinFet process rules with the minimum geometries of 20nm, 16nm, 14nm and 10nm . My experience has primarily been focused with designing the mask layouts of complex Analog and Mixed Signal Integrated Circuits· Creating IC mask designs using the Cadence IC mask design toolsVirtuoso, Virtuoso XL · Verifying IC mask designs using the Mentor Graphics Calibreverification tools. Using the Calibre RealTime ™ DRC rules checker· Completing IC mask designs on schedule and verified error free · Communicating with the IC mask design team to generate the ICmask designs as specified by the Circuit Designers and to satisfythe requirements of the intended customer. I also have experience designing Digital Integrated Circuits . My IC mask design history also includes working with Assura. My IC mask design history also includes working with Hercules for LVS verification

WORK HISTORY: IC Mask Design Consultant 1976 to Present

· Qualcomm, San Diego, CA 05/11 – to Present

I have been working at Qualcomm as a direct employee since 2012. Before that date I had worked at Qualcomm as a contractual employee. I worked Qualcomm for a total of 3 contracts before I

became a permanent employee. · Created the Analog IC Mask Designs that were part of the SnapDragon ™ processor that is used in mobile phones that are not made by Apple. Created IC mask designs that were used to parameterize the new process technologies, mainly the FinFet process technology used by Samsung Semiconductor. Geometries include the 20nm, 16nm, 14nm and the 10nm process design rules. Created the Analog IC Mask Designs for the equalizationreceiver and transmitter circuits on an IC for a wirelessBluetooth compatible telephone earpiece and microphonecombination · Coordinated with the team of IC Mask Designers and CircuitEngineers assigned to these projects to create the best possibledesigns for the intended customer · Implemented Design Improvements to the IC Mask Design as needed . Final Products include: Integrated Circuits Designs for use in mobile phones, modems and audio headphones · Area(s) of responsibility: I designed the circuits in the areaof the integrated circuit that dealt with the harmony levels ofthe audio device and the receiver and transmitter circuits forthe communication device · Process Name: CMOS – Design process rules were primarilytargeted towards two offsite foundries:. TSMC – Minimum geometries ranged from 28nm and 20nm for TSMC’s FinFet process. Samsung Semiconductor – Minimum geometries of 20nm, 16nm, 14nm and 10nm process design rules for the FinFet process that is used by Samsung Semiconductor

· Asic North, Williston, VT Home Office 01/11 – 05/11. Asic North also has a branch office in Tempe, AZ · Created the Analog IC Mask Designs for an integrated circuit to transmit and receive a high frequency signal for an Ethernet Network. The details of this device are currently classified. I coordinated my IC mask design tasks with the members of the IC design team who worked to create the schematics and mask layout for this IC. The IC mask design software used was Cadence Virtuoso. The Software tools that were used for verification were Hercules for LVS and Mentor Graphics Calibre for DRC. I worked in tandem along with the rest of the team, coordinating

our IC design efforts between the Vermont and Arizona offices.

. Process used was the IBM SOI (Silicon On Insulator) process and the minimum geometry was 45 nm.

. Created the IC Mask Designs for an integrated circuit that is designed to be combined with the database of another IC and to provide an ’on-chip’ method to identify the type of IC that is in a packaged device without the need open up the package and destroy the integrated circuit in the process.

· Qualcomm, San Diego, CA 06/10 – to 11/10 · Created the Analog IC Mask Designs for the equalization, receiver and transmitter circuits on an IC for a wireless Bluetooth compatible telephone earpiece and microphone combination · Coordinated with the team of IC Mask Designers and Circuit Engineers assigned to these projects to create the best possible design for the customer · Implemented Design Improvements to the IC Mask Design as needed . Final Products: Integrated Circuits Designs for use in audio headphones and in mobile phones · Area(s) of responsibility: I designed the circuits in the area of the integrated circuit that dealt with the harmony levels of the audio device and the receiver and transmitter circuits for the communication device · Process Name: CMOS - Minimum Geometry: 65 nm

· Qualcomm, San Diego, CA 10/09 – to 02/10 · Created the Analog IC Mask Designs for the equalization circuits of an IC for audio headphones · Created the Analog IC Mask Designs for the receiver circuits of an IC for mobile phones · Coordinated with the team of IC Mask Designers and Circuit Engineers assigned to these projects to create the best possible design for the customer · Implemented Design Improvements to the IC Mask Design as needed . Final Products: Integrated Circuits Designs for use in audio headphones and in mobile phones · Area(s) of responsibility: I designed the circuits in the area of the integrated circuit that dealt with the harmony levels of the audio device and the receiver and transmitter circuits for

the communication device · Process Name: CMOS - Minimum Geometry: 65 nm

Intel Corp., Chandler, AZ 01/08 - 12/08

· A 30 percent reduction in packaging costs was achieved by the implementation of design improvements to the Electro-Static Discharge (ESD) protection circuits used on the I/O pads · Created the Analog IC mask designs for the Input/output (I/O) circuitry for an IC voltage regulator · Final Product: Voltage Regulator · Area(s) of responsibility: Designed all of the bonding pad I/O logic and the ESD protection devices for each of the I/O pads - Designed the power and ground pads and the interface logic · Design Tools: Cadence - Virtuoso XL – Cadence Assura IC mask verification software tools · Process Name: CMOS - Minimum geometry: 65 nm

Freescale, Tempe, AZ 07/07 – 1/08

· Final Product: a Digital to Analog Converter (DAC) IC · Created the IC mask designs for two CMOS high voltage twin well analog IC devices that were targeted for usage in WIFI (Wireless Fidelity) communication products· Designed the IC mask designs on the following functional blocks: The Digital Switching logic, the '1st Integrator', the '2nd

Integrator', the 'Quantisizer', the 'Shaper', and the ‘Mirror Logic’ of the DAC IC · Design Tools: Cadence Virtuoso XL for the circuit design – Mentor Graphics Calibre for the DRC/LVS · Cadence Assura for additional LVS and DRC verifications. · Process Name: CMOS90 - Analog process rules - Minimum Geometry: 0.1 um minimum gate lengths

Intel Corp., Chandler, AZ 10/06 - 07/07

· Final Product: An integrated circuit with wireless communication and WIFI capabilities · Designed the registers and the interface logic to the internal circuitry from the I/O pads for this Integrated Circuit · Design Tools: Cadence Virtuoso XL for the circuit design - Cadence Assura software for the DRC/LVS · Process Name: CMOS - Minimum geometry: 65 nm

Freescale, Tempe, AZ 03/06 - 08/06

· Final Product: a Digital to Analog Converter (DAC) integrated circuit for use in mobile phones · Designed the functional blocks that were part of this DAC IC · Design Tools: Cadence Virtuoso XL for the circuit design – Mentor Graphics Calibre for the DRC/LVS · Cadence Assura for additional LVS and DRC verifications - Process: CMOS90 - Analog process rules Intel Corp., Chandler, AZ 03/05 – 03/06

· Final Product: A CMOS Integrated Circuit 'Test Chip' to test and evaluate the design rules for a new fabrication process – Minimum Geometry: classified · Created digital and analog IC mask designs that were based on these new IC design rules · Designed the entire layout of this process design test chip · Design Tools: Cadence Virtuoso XL for the circuit design - Cadence Assura software for the DRC/LVS · Freescale, Tempe, AZ 11/04 – 01/05 - Two Integrated Circuits for hand held communication products · Intel Corp., Chandler, AZ 11/03 – 11/04 – An IC for wireless communication and WIFI applications · Primarion Inc., Tempe, AZ 07/01 – 10/03 - An analog and mixed signal power regulator IC · Hewlett Packard, Fort Collins, CO 1999 – 2000 · Cyrix, Plano, TX 1997 -1998 – Media GX microprocessor · Intel Corp., Chandler, AZ 11/03 – 1995 -1996 - An IC for wireless communication and WIFI applications · The Western Design Center, Mesa, AZ 1982 – 1994 – CMOS W65C02 microprocessor and its derivatives · Motorola, Tempe, AZ 1976 – 1982 – IC mask design, PCB design, Hybrid circuit drafting and design SOFTWARE:

· Experienced with the Cadence ‘VIRTUOSO‘ and ‘VIRTUOSO-XL’ suite of IC mask design software tools · Experienced with the Hercules IC mask verification software tools · Experienced with the Mentor Graphics Calibre IC mask verification software tools

COMPUTERS: · Experienced with UNIX based computer systems and WINDOWS based PC systems EDUCATION: · Bachelor Degree - From the University of Maine, Farmington, ME Professional References supplied upon request