1

ABSTRACT

Variations of power and ground levels affect VLSI circuitperformance. Trends in device technology and in packaginghave necessitated a revision in conventional delay models. Inparticular, simple scalable models are needed to predictdelays in the presence of uncorrelated power and groundnoise. In this paper, we analyze the effect of such noise onsignal propagation through a buffer and present simple,closed-form formulas to estimate the corresponding changeof delay. The model captures both positive (slowdown) andnegative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity satu-ration effects. An application shows that repeater chainsusing buffers instead of inherently faster inverters tend tohave superior supply-level-induced jitter characteristics. Theexpressions can be used in any existing circuit performanceoptimization design flow or can be combined into any delaycalculations as a correction factor.

Categories & Subject Descriptors: [Computer-Aided Engineering]: Computer-aided design (CAD).

General Terms: Algorithms.

Keywords: Power and ground noise, differential modenoise, common mode noise, incremental delay change.

1. INTRODUCTION

This paper describes a new model for the change in bufferdelay caused by both power and ground supply levelvariations and level variations between stages in sequencesof repeaters. These delay changes are a large component ofthe total timing jitter for a signal where the jitter accounts forall noise sources such as substrate noise and coupling noiseas well as power level noise. There is a substantial amount ofprevious work in this area, notably papers: [4][6][13][14][19]. However, for several reasons described below, webelieve that the problem bears re-examination and a renewedeffort to create a fast, simple model suitable for massimplementation in a modern design flow.

Growth in design sizes and scaling of interconnections haveled to the requirement for insertion of very large numbers ofbuffer/repeaters in recent designs [1][7][9][15]. Among

them, [9] proposes an optimum multistage buffer design todrive long uniform lines. [7] and [15] consider simultaneousbuffer insertion and wire sizing for timing optimization. [1]presents comprehensive buffer insertion techniques for noiseand delay optimization. Because of the buffer/repeaters’preponderance in number, use in heavily loaded nets, and usein clock and timing circuits, buffer delays account for a largepercentage of all critical timing nets in a design. In some ofthese applications, total timing uncertainty (not just worst-case delay) is important. Disturbance of the buffer delay willaffect the type, number and position of buffers that optimizethe interconnect delay. Therefore, it is essential to take thechange of delay into consideration in order to adjust thesolution for timing optimization. At the same time, scalingof power supply levels and improving transconductance ofdevices have increased the sensitivity of buffers to supply-level-induced delays. Finally, increases in chip-level designscales and modern packaging strategies such as bumpbonding have localized supply variations so that buffers inone set of supply levels are driving buffers in another zonewith different supply levels. Since power loading is logicswitching-dependent and supply sources are localized,power and ground levels need not be inversely correlated asis typical in a wire bonded die.

Under such conditions, power-level-induced delay changesmay either increase or decrease the effective delay of abuffer, and successive stages may or may not accumulateincremental delays. One must consider both power andground levels at the signal source and at the current buffer toderive an equivalent delay change. This value can besubstantially smaller than that predicted by superposingground-bounce and power level changes [3][5][10][20][21].The superposition approximation works well only if thevariations in the power distribution network are mirrored inthe ground network. However, due to changes in packagingtechnology and the number of pins that can feasibly bedevoted to power and ground connections, no single parasiticdominates the noise on the power and ground nets. Yetanother trend in technology is the relative reduction of gateparasitics compared to those from the interconnectionnetwork. The net effect of this is de-correlation of the powerand ground voltage variations which in turn make delayvariations much more complex. In particular, the worst-case

Buffer Delay Change in the Presence of Power and GroundNoise

Lauren Hui Chen*, Malgorzata Marek-Sadowska**, Forrest Brewer**

*Synopsys Inc., Mountain View, CA, USA** Electrical and Computer Engineering Department, University of California, Santa Barbara, CA 93106, USA

*laurenc@synopsys.com, **{mms, forrest}@ece.ucsb.edu

2

delay caused by power noise may not occur simultaneouslywith the worst-case delay due to ground noise, and thesuperposition may cause a substantial overestimation.Second, the delay effects of common mode voltage shiftswill be shown to be larger in scale than equivalentdifferential mode changes. (Differential mode voltage shiftsare the most commonly studied model). Lastly, changes inpower distribution and clocking strategies, and the potentialfor future changes, create the need for a timing model whichis independent of common assumptions about power levelnoise sources. We do assume that large scale power levelchanges result from an ensemble effect of many devices at avariety of differing slew rates. However, in a practicaldesign there must always be some amount of localdecoupling capacitance (both parasitic and added). Thiscapacitance limits the magnitude of the highest speed noiseexcursions. (This cannot be done in later stages of the powernetwork design because of inductance in both the physicalnetwork and the packaged capacitors). We therefore assumethat the remaining large magnitude noise excursions occurat a somewhat slower time scale than the typical switchingtransitions in buffers meeting common design requirements.

In the following, we analyze the effect of P/G (power/ground) noise on buffer delay, and present linear, closed-form formulas for the corresponding incremental changes indelay based on a short-channel transistor model. Theexpressions simultaneously model both the power supplyand ground levels, resulting in positive (slowdown) ornegative (speedup) delay changes. These expressions areintended for inclusion in timing analysis tools and statisticaldelay estimators as corrections to nominal delay models thataccount for other effects. The expressions make fewassumptions about the specific shape of the P/Gnoise waveform. Furthermore, they are shown to be largelyindependent of the buffer load circuit structure, increasingtheir applicability.

The rest of the paper is organized as follows: sections 2-3define P/G noise, buffer delay nomenclature, and illustratethe P/G-noise-induced buffer delay change. Section 4presents our new model. Section 5 demonstrates theaccuracy and fidelity of the model. Applications of themodel and concluding remarks are presented in sections 6-7. Detailed derivations are given in Appendices A and B.

2. BUFFER DELAY CONVENTIONS

A buffer is a chain of tapered inverters. Here, we considerbuffers consisting of one inverter or two inverters.

2.1 Variation of Vdd and VssWe use Vdd, Vss, Vi (input), Vin (adjusted input), Vo (output),Vout (adjusted output), etc. to represent values related to theideal power and ground levels, and we use Vdd’, Vss’, Vi’,Vin’, Vo’, Vout’, etc. to represent the corresponding values inthe presence of power and ground noise. ∆Vdd and ∆Vss

denote the variation of power supply and ground,respectively.

(power noise) (1)

( ) (ground noise) (2)

In small-scale wire-bond packaging styles, a dominantsupply level noise source is bond wire inductance in thepackage. Neglecting I/O current drives, the power andground noise of the chip due to simultaneous switchingtypically follows an inverse pattern, and ∆Vdd is oftensymmetric to ∆Vss. However, in modern bump-bonded andlow-inductance package styles, the package distributespower over the whole area of the chip (figure 1). Everybump connects to an underlying local power/groundnetwork. To save chip metallization area and improvedensity, global power distribution metal is reduced inpreference to thicker package distribution layers. Increasingdesign scales causes an increase in long wire loading, and inmore wires connecting between different power domains.Logic-level-dependent currents flow between such blocks,causing asymmetric power and ground noise within a block.This noise is increased by the inclusion (within a bumpblock) of long wire repeater buffers which are often addedin a post-placement timing optimization step.

Figure 1 shows a simple circuit which uses bump-bondpackaging. Each block is defined by the subcircuit suppliedby a pair of bumps (Vdd/Vss). Suppose that the cells A to Ehave transitions. Switching of the buffers A, B and D has asymmetric effect on the power and ground noise ( and

), because they drive loads (consisting largely ofparasitic interconnect capacitance) within the same block.On the other hand, switching of the C and E buffers has anon-symmetric effect on and , because theydrive loads which are outside of block 1, causing differentswitching currents to flow through the power and groundports of block 1. Since wires leaving a block are likely to bephysically long, these currents are proportionally large. Ingeneral, there is little reason for the currents flowing out ofthe block via loads to cancel.

2.2 Incremental buffer delay changeTo allow reference to previous work, it is necessary toformally define the model for buffer delay, as themeasurement levels are subject to noise.

Without loss of generality, we define a buffer’s ideal delayas the time interval between its input and output voltagereaching 50% of the power supply level. Figure 2 illustratesthe definition for an inverter delay given ideal power supplyand ground levels. tpHL is the high-to-low delay when theinput of the inverter has a rising transition. The input andoutput transition times are tr and toT, respectively. Othertime values are: ti5, to5, to1 and to9, which are times when the

V dd∆ V dd′

V dd–=

V ss∆ V ss′

V ss V ss′

=–= V ss 0=

V∆ dd′ 1( )

V∆ ss′ 1( )

V∆ dd′ 1( )

V∆ ss′ 1( )

3

input or output voltage reaches 50%, 10%, and 90% of Vdd,respectively.

(3)

(4)

Figure 3 (a) and (b) illustrate the delay and slope when thereis a P/G noise. In figure 3(a), we assume a bump-bondpackaging technique, in which every bump has a smallpower/ground network, relatively independent of the others.Therefore the low and high voltage levels of the inputtransition ( ) are independent of the change ofpower supply and ground level for the buffer. Thecorresponding buffer delays are and . In figure3(b), conventional wire-bond packaging technique isassumed. For such a technique, the dominant noise on thepower supply and ground level is often due to the wiringinductance in the package, so the whole chip’s power andground noises are synchronized. Therefore, the voltage levelof the input transition ( ) will be the same as thatof the buffer. The corresponding buffer delays are and

. Because of power supply and ground level changes,we are interested in delay measured at different voltagelevels: the 50% point between the ideal Vdd and Vss (and ), and the 50% point between the disturbed Vdd’and Vss’ ( and ). Hence we have four types ofdisturbed buffer delays, corresponding to four types ofbuffer delay changes.

The special output voltage points are defined as follows:

The disturbed high-to-low delay and slope are given by:

where , indicating four different definitions ofthe disturbed buffer delay and output slope illustrated infigure 3 (a) & (b).

In figure 3(a) we have and . In figure

3(b) we have and . Therefore,

,

With a rising transition at the input, the changes of delayand output transition time are defined as follows:

The results shown in figure 5 are according to the first typeof delay definition with j = 1.

3. P/G NOISE DELAY EFFECTS

The changes of power supply and ground level affect signalpropagation through an inverter in several different ways,which will be discussed in this section.

CA B

D E

BLOCK 1

BLOCK 2

Vdd’(2)

Vss’(2)

Vdd’(1)

Vss’(1)

Vdd PinParasitics

Vss PinParasitics

Local RedistributionParasitics

Local RedistributionParasitics

Vdd

Vss

Vdd PackageRedistributionLayer / Plane

Vss PackageRedistributionLayer / Plane

Figure 1. Power distribution in bump-bond packaging

t pHL to5 ti5–=

toT

to1 to9–

0.8--------------------=

V ss V dd→

t pHL′ 1( )

t pHL′ 2( )

V ss′

V dd′→

t pHL′ 3( )

t pHL′ 4( )

t pHL′ 1( )

t pHL′ 3( )

t pHL′ 2( )

t pHL′ 4( )

Vdd

0.9Vdd

0.5Vdd

VD0

Vtn

0.1Vdd

V tn

V dd---------tr to9 tr to5 tD0 to1

time

Vi(input)

Vo(output)

Vss

volt

age

1 2 3 4region

NMOS CUT SAT SAT LIN

VTR

ti5

tpHL

0.8toT

Figure 2. Ideal inverter transition and nomenclature

V o1′

V ss′

0.1 V dd′

V ss′

–( )+=

V o5′

V ss′

0.5 V dd′

V ss′

–( )+=

V o9′

V ss′

0.9 V dd′

V ss′

–( )+=

t pHL′ j( )

to5′ j( )

ti5′ j( )

–=

toT′ j( ) to1

′ j( )to9′ j( )

–

0.8------------------------=

j 1 2 3 4, , ,=

to1′ 1( )

to1′ 2( )

= to9′ 1( )

to9′ 2( )

=

to1′ 3( )

to1′ 4( )

= to9′ 3( )

to9′ 4( )

=

toT′ 1( )

toT′ 2( )

= toT′ 3( )

toT′ 4( )

=

t pHLj( )∆ t pHL

′ j( )t pHL–=

toTj( )∆ toT

′ j( )toT–=

4

3.1 Differential mode noiseWe define the differential mode noise (DMN) ∆Vdif as:

where

and

We have observed through HSpice simulations that thevoltage difference (Vdif) between the power supply andground level affects the inverter delay (tpHL/tpLH), which isthe inverter’s ability to propagate signals. Similarly, thechange of the above difference (∆Vdif) affects the change ofdelay (∆tpHL/∆tpLH).

The differential mode noise ∆Vdif may become positive ornegative, depending on the directions and relativeamplitudes of ∆Vdd and ∆Vss. The voltage difference (Vdif)between power supply and ground level determines how fastthe buffer charges/discharges its capacitive load, so it affectsthe delay and the transition time of the buffer output. Thelarger the difference ( ), the faster theoutput charging/discharging and the smaller the buffer delay( ), which is stated in observation 1.

Observation1: The buffer delay change is linearly dependenton the differential mode noise (DMN), as will be shown insection 4:

(5)

where kd is a positive constant dependent on the device andtechnology parameters, the input transition times, and thegate load. The expression of kd can be found from equation(A5) in Appendix B. Similar effects hold for both high-to-low delay ∆tpHL and low-to-high delay ∆tpLH.

3.2 Common mode noiseWe define the common mode noise (CMN) ∆Vcom as:

CMN modifies the effective switching threshold of the gate.The threshold shift changes the gate delay as illustrated infigure 4. Figure 4(a) shows a rising transition arriving at thebuffer. Figure 4(b) illustrates the gate threshold shift and thecorresponding delay change caused by the power andground variations.

In figure 4(b), N and P are the original points when theNFET switches from cutoff to saturation region and PFETswitches from saturation to cutoff, respectively. The

Vdd

0.5Vdd

time

(input) (output)

Vss

volt

age tpHL

0.8toT

, (2)

Vdd

’

tpHL

, (1)

ti5,(1)

ti5,(2)

to5

,(1)

to1,

to5

,(2)

to9,

,

Vo9,

Vo5,

Vo1,

Vss,

Vo,

Vi,

Vss’Vdd

’Vdd

’

Vss’

Vss

Vdd

Figure 3. Notation for disturbed delay and slope

Vdd

0.5Vdd

time

(input) (output)

Vss

volt

age tpHL

, (4)

Vdd

tpHL

, (3)

ti5,(3)

ti5,(4)

to5

,(3)

to1,

to5

,(4)

to9,

,

Vo9,

Vo5,

Vo1,

Vss,

Vo,

Vi,

0.8toT’

Vss’Vdd

’

Vss’Vdd

’Vdd

’

Vss’

(a) (b)

V dif∆ V dif′

V dif– V dd∆ V ss∆–= =

V dif′

V dd′

V ss′

–= V dif V dd V ss–=

V dif′

V dif> V dif∆⇒ 0>

t pHL′

t pHL< t pHL 0<∆⇒

t pHL∆DMN

kd V∆ dif⋅– k– d= V dd∆ V ss∆–( )⋅=

V com∆ V dd∆ V ss∆+=

Vdd

Vi

VGS(P)

VGS(N)

Vss

V GSP( )

V i V dd–=

V GSN( )

V i V ss–=

Vdd

Vdd,

Vss

Vss,

∆Vss

∆Vdd

Vtn

Vtn

|Vtp|

|Vtp|

Vtn(shift)

|Vtp |(shift)

tn, tp

,tn tp

(a)

(b)N’

P’P

N

Figure 4. Threshold shift of an inverter

wireload

Vo

5

corresponding switching times are indicated tn and tp. Fornoise of limited amplitude, the transistor thresholds (Vtn andVtp) do not change significantly, namely,

This causes a shift of the NFET and PFET switching pointsfrom N and P to N’ and P’. The corresponding switchingtime shifts to tn

’ and tp’, respectively.

The points N’ and P’ can be mapped to shifted thresholds infigure 4(a) with ideal power supply and ground level:

We observe in figure 4(b) that:

Obviously, it takes more time for the NFET transistor to beturned on and PFET to be turned off when both powersupply and ground level increase.

On the other hand, when power supply and ground leveldecrease, we have

Hence, it takes less time for the NFET transistor to beturned on and PFET to be turned off for decreased powerand ground level.

Therefore, we make the following observation:

Observation 2: For an input with a rising transition, thedependency between the common mode noise (CMN) andthe buffer delay change can be expressed by:

(6)

where kcr is a positive constant determined by the deviceand technology parameters, input transition time, and thegate load. The expression of kcr can be found from equation(A5) in Appendix B.

Similarly, for an input with a falling transition, thedependency between the common mode noise (CMN) andthe buffer delay change can be expressed by:

(7)

where kcf ia a positive constant determined by the deviceand technology parameters, input transition time, and thegate load.

For a rising transition, the effective switching threshold ofan inverter is set by the current balance of the two activetransistors. For positive common mode noise, this switchingthreshold is higher, and therefore it is reached later by therising transition. Thus the delay is increased even though thevoltage across the inverter, and hence the current drive,remains constant.

For a falling transition, the effective switching threshold ofthe gate rises, so that the threshold voltage level is reachedearlier, and the effective gate delay decreases. This effectoccurs even if the differential mode noise is zero, as it is theswitching level - not the current drive - that is altered by thecommon mode noise.

We note an analogy here: a rising input transition withpositive common mode noise can be thought of as climbinga rising mountain, which takes more time than climbing amountain of initially the same, yet stationary, dimensions. Afalling input transition with the same positive commonmode noise is analogous to going downhill when the bottomof the mountain rises, which takes less time than descendinga corresponding fixed dimensions mountain.

Therefore, common mode noise has a different effect onrising and falling transitions.

3.3 Loading effectsBoth differential mode noise (DMN) and common modenoise (CMN) change buffer delays. Since the delay changecan be of either sign, the noise sources need to be modeledtogether. Figure 5 shows alternative load configurations andthe corresponding simulated delay change (both rising andfalling transition) in 0.18µm technology. Note: ∆delay = 0when ∆Vdd = ∆Vss = 0.

In figure 5 (a), the wire load of the inverter is a distributedRC tree network, including vias, extracted from the layoutof a real circuit. In figure 5 (b), the wire load is simplified toan RC π-model. In figure 5 (c), the wire load is furthersimplified to a single resistor plus a single capacitor. Infigure 5 (d), an effective loading capacitor is used to replacethe inverter’s output load. These simplified wire-loadmodels in figures 5(b)-(d) can be obtained using themethods described in [16]. The delay is measured when itsinput (Vi) and output (Vo / Vo’ / Vo” / Vo”’) voltage reach50% of the ideal power supply voltage, respectively. Therange for the power and ground noise is from -20% (-0.36volt) to 20% (0.36 volt) of the power supply voltage, whichis set to 1.8 volt for the selected technology. The range forthe change of delay is from -30ps to 30ps.

It is interesting to note that each of the four wire loadmodels displays a linear relationship between the change ofpower/ground level and the change of inverter delay.Furthermore, the linearity improves when the change ofpower and ground level is smaller than 20%. In practicaldesigns, the tolerable range for the power and ground levels

V GS′ N( )

CUTV i V ss

′– V tn 0>= =

V GS′ P( )

CUTV i V dd

′– V tp 0<= =

V GSN( )

CUTV i V ss– V tn

shift( )= =

V GSP( )

CUTV i V dd– V tp

shift( )= =

V ss∆ 0> V tnshift( )

V tn> tn′

tn> increasing delay⇒ ⇒ ⇒

V dd∆ 0> V tpshift( )

V tp> t p′

t p> increasing delay⇒ ⇒ ⇒

V ss∆ 0< V tnshift( )

V tn< tn′

tn< decreasing delay⇒ ⇒ ⇒

V dd∆ 0< V tpshift( )

V tp< t p′

t p< decreasing delay⇒ ⇒ ⇒

t pHL∆CMN

kcr V com∆⋅ kcr= V dd∆ V ss∆+( )⋅=

t pLH∆CMN

k– cf V com∆⋅ k– cf= V dd∆ V ss∆+( )⋅=

6

is usually less than .Thus, the CMN and DMN-induced delays can be superposed as noted below.

Observation 3: For a rising input transition and any of thewire load models described in figure 5, the incrementalchange of buffer delay due to P/G noise is expressed as:

(8)

A similar result applies to a falling input transition:

(9)

where k1r, k1f, k2r and k2f are positive constants dependentonly on input transition time, gate load, and the device andtechnology parameters. The actual expressions can be foundfrom equations (11) and (14) in section 4.2, based on thetheoretical model.

Observation 3 brings in two related observations.

Observation 4: Buffer delay change is more sensitive tocommon mode noise than to differential mode noise fordeep submicron designs, and may be dominated by commonmode noise in some instances. This is indicated by the factthat the slope along the ∆Vcom direction is much steeper

10%±

Figure 5. Buffer delay change induced by P/G noise

C2 C1

R1

Ceff

o q

VoVi

o’

Vo’Vi

o’”

Vo’”Vi

(b) π-model load

(d) Effective capacitance load

(a) Distributed RC load

C3

R2

o”

Vo”Vi

(c) Single RC load

(extracted from layout)

∆tpHL

∆Vcom ∆Vdif

-0.4

0.40

-0.4

0.40

∆tpHL

∆Vcom ∆Vdif

-0.4

0.40

-0.4

0.40

∆tpLH

∆Vcom ∆Vdif

0.4

-0.40

0.4

-0.4

0

∆tpHL

∆Vcom ∆Vdif

-0.4

0.40

-0.4

0.40

∆tpLH

∆Vcom ∆Vdif

0.4

-0.40

0.4

-0.4

0

∆tpHL

∆Vcom ∆Vdif

-0.4

0.40

-0.4

0.40

∆tpLH

∆Vcom ∆Vdif

0.4

-0.40

0.4

-0.4

0

∆tpLH

∆Vcom ∆Vdif

0.4

-0.40

0.4

-0.4

0

t pHL∆ k1r V dd∆ V ss∆+( ) k2r V dd∆ V ss∆–( )⋅–⋅=

t pLH∆ k– 1 f V dd∆ V ss∆+( ) k2 f V dd∆ V ss∆–( )⋅–⋅=

7

than the slope along the ∆Vdif direction in figure 5. It alsoindicates k1r > k2r and k1f > k2f in equations (8) and (9).This will be further discussed in section 4.4.

Observation 5: Common mode noise has different effects onrising and falling transitions. As shown in figure 5, for arising transition, with the increase of ∆Vcom from -0.4 to 0.4volt, delay change increases. However, for a fallingtransition, it is with the decrease of ∆Vcom from 0.4 to -0.4volt that the delay change increases. This is indicated bydifferent signs associated with (∆Vdd + ∆Vss) in equations(8) and (9): positive for a rising and negative for a fallingtransition.

Observation 3 indicates that an appropriate simplified wireload model can be used for delay modeling of the bufferitself. With appropriate techniques [2][8][11][16], thedistributed RC load of a gate can be simplified into thenearly equivalent π-model shown in figure 5(b). This π-model is further simplified into an effective capacitanceload, shown in figure 5(d), by equating the average currentsfor the two load models. Such a capacitance model isinaccurate when the gate is behaving like a resistor [16].This inaccuracy occurs primarily in the tail portion of theoutput waveform. However, for our purposes, the bufferdelay is measured at the midpoint of the logic swing.Therefore, the inaccuracy in the gate delay (not the wiredelay) caused by the effective capacitance model isrelatively small, usually less than 5% for the technologiesreported in the results.

The output voltage at node o in figure 5 (a) can beapproximated by the voltage at node o’ in figure 5 (b), o” infigure 5 (c) and o”’ in figure 5 (d):

However, the voltage at node q is different from that of nodeo:

The simplified wire load model is only used to characterizethe interconnect’s driving point (node o) delay, not thereceiving node (node q) delay. A variety of techniques exist[5][11] in order to model the interconnect delay. In thispaper, we focus only on the buffer delay characterizationwhich is typically half of the total wire delay for optimizedlong wires.

Power and ground noise can either be correlated or largelyindependent depending on the relative magnitude of thepower distribution parasitics and the relative number andactivity of signals crossing between power distributionblocks. This noise contributes to the local buffer/inverterdelay in a complex way which can either increase ordecrease the signal delay. For application in performanceestimation, optimization, or analysis, it is useful to developsimple models which can be quickly evaluated and whichcan be linked to theoretical device models.

4. THEORETICAL MODEL

4.1 Inverter modelIn deep submicron circuits, carrier velocity saturationeffects predominate. To capture these effects when derivingthe signal transition delay and slope values in the presenceof power and ground variations, we use the short channelalpha-power law MOSFET model [17].

From Figure 6, we have the following nodal equation:

where

In deep submicron circuits the signal transitions are fast, sowe can ignore the short circuit current [17][18]. (For thetechnologies reported in the results, short circuit errorsamounted to less than 5% for incremental delay and 20% forincremental transition time, over all simulated cases.) For arising transition at the inverter input, short circuit currentfrom the NFET is negligible.

The current flowing through NFET (In) is computed fromthe following equation [17]:

(10)

where

CUT, SAT, and LIN represent cutoff, saturation, and linearmodes of operation, respectively. And:

The above alpha-power law model is based on fourparameters: α (velocity saturation index), Vtn (threshold

V o V o′

V o″

V o′″≈ ≈ ≈

V q V o≠

In I p+ Ic=

Ic CL

d V o V ss–( )dt

-----------------------------–=

Vdd

VoVi

CL

Ip

In Ic

Vss Vss

Figure 6. Propagation of a transition

In

0 V GS V tn≤( ) CUT( )

ID1 V DS V D1≥( ) SAT( )

ID1 V D1⁄( ) V⋅DS

V DS V D1<( ) LIN( )

=

ID1 ID0

V GS V tn–

V dd V tn–------------------------

α

ID0

V in V tn–

V dd V tn–-----------------------

α

==

V D1 V D0

V GS V tn–

V dd V tn–------------------------

α 2⁄

V D0

V in V tn–

V dd V tn–-----------------------

α 2⁄

==

V in V i V ss V GS=–=

V out V o V ss V DS=–=

8

voltage), ID0 (drain current at VGS = VDS = Vdd), VDO (drainsaturation voltage at VGS = Vdd). For MOSFET in currenttechnology, typical values for these parameters are:

, , and . We assumethat for a given transistor with a given loading capacitance,the above four values remain unchanged with a smalldisturbance of power supply and ground levels.

Figure 2 shows a typical traversal path for an inverter’soperation mode when the input is a rising transition [17]. Itis divided into four regions.

In the following two subsections, referring to figures 2~3,we will derive the output waveform and simple formulas toestimate the change of delay and slope induced by thechange of Vdd and Vss.

4.2 Change of buffer delayThe derivation of output waveform can be found inappendix A. According to the results in appendix A, weobtain ti5’, to5’, to1’, and to9’. By setting ∆Vdd and ∆Vss to 0,we can obtain the corresponding ti5, to5, to1, and to9. In orderto differentiate between NFET and PFET, we use subscriptsn and p to represent parameters related to NFET and PFET,respectively. According to equations (A5) and (A6) inappendix B, we have:

(11)

The change of delay can also be expressed as:

(12)

where

, (13)

For the four types of delays defined in figure 3, we obtainedthe following coefficients:

,

,

,

,

Similar equations have been derived for . The maindifference is that the four parameters (α, Vtp, ID0, VD0) areobtained from the corresponding PMOS, and the polarity ofk1p is reversed compared to that of k1n:

(14)

where

, (15)

Equations (11) and (14) match the results in observations 3,4 and 5.

Theorem 1: Equations (11) to (15) demonstrate that theincremental change of buffer delay is linear with respect tothe power and ground variations.

The coefficient k1 quantifies the effect of the common modenoise while k2 characterizes the effect of the differentialmode noise on buffer delay. This theorem shows why theobservations in sections 3.1 through 3.3 hold. k1n, k2n, k1pand k2p are equivalent to k1r, k2r, k1f and k2f defined inobservation 3.

Under certain circumstances, the input transition time canbe changed by the P/G noise. In other words, , and

. The delay change will be slightly different:

where is a function of P/G noise. For example, for thefirst type of delay change, we have:

which can be further simplified to:

(16)

where

,

Equation (16) can be transformed into a form similar to thatof equation (12):

(17)

where

,

Similarly, for the other three types of buffer delay changes,we have:

α 1 1.2∼= V tn V dd⁄ 0.2≈ V D0 0.6V dd≤

t pHLj( )∆ k1n

j( )V com k2n

j( )V dif∆⋅–∆⋅=

k1nj( )

V dd∆ V ss∆+( ) k2nj( )

V dd∆ V ss∆–( )⋅–⋅=

t pHLj( )∆ k3n

j( )V dd∆⋅ k4n

j( )V ss∆⋅+=

k3nj( )

k1nj( )

k2nj( )

–= k4nj( )

k1nj( )

k2nj( )

+=

k1n1( ) tr

2V dd 1 α+( )-------------------------------

CL

2ID0------------+= k2n

1( ) tr

2V dd 1 α+( )-------------------------------

CL

2ID0------------–=

k1n2( ) tr

2V dd------------–

α1 α+-------------⋅= k2n

2( ) tr

2V dd 1 α+( )-------------------------------

CL

2ID0------------–=

k1n3( ) CL

2ID0------------= k2n

3( ) vT t⋅r

1 α+( )V dd---------------------------

CL

2ID0------------–=

k1n4( )

0= k2n4( ) CL

2ID0------------

vT t⋅r

1 α+( )V dd---------------------------–=

t pLHj( )∆

t pLHj( )∆ k– 1 p

j( )V com k2 p

j( )V dif∆⋅–∆⋅=

k3 pj( )

V dd∆⋅ k4 pj( )

V ss∆⋅+=

k3 pj( )

k– 1 pj( )

k2 pj( )

–= k4nj( )

k– 1 pj( )

k2 pj( )

+=

tr∆ 0≠tr′

tr tr∆+=

t pHLj( )∆ k1n

j( )V dd∆ V ss∆+( ) k2n

j( )V dd∆ V ss∆–( ) tr∆ f ds

j( )⋅+⋅–⋅=

f dsj( )

f ds1( ) 1

2---

11 α+------------- 1

V ss∆V dd------------– vT–

⋅–=

t pHL′ 1( )∆ k1n

′ 1( )V dd∆ V ss∆+( ) k2n

′ 1( )V dd∆ V ss∆–( ) k5n

′ 1( )+⋅–⋅=

k1n′ 1( ) tr tr∆+

2V dd 1 α+( )-------------------------------

CL

2ID0------------+=

k2n′ 1( ) tr tr∆+

2V dd 1 α+( )-------------------------------

CL

2ID0------------–=

k5n′ 1( )

tr∆ 12---

1 vT–

1 α+--------------–

⋅=

t pHL′ 1( )∆ k3n

′ 1( )V dd∆⋅ k4n

′ 1( )V ss∆ k5n

′ 1( )+⋅+=

k3n′ 1( ) CL

ID0--------= k4n

′ 1( ) tr tr∆+

V dd 1 α+( )---------------------------=

9

Lemma 1: Using equation (16), we can easily see that thebuffer delay change is linearly related to the power andground noise regardless of the change of input transitiontime.

4.3 The change of slopeAccording to equation (A9) in appendix B, we have thechange of slope:

(18)

where h3 and h4 are determined by the device andtechnology parameters, input transition time, and the gateload.

4.4 DiscussionIn this section, based on the derived equations, we discussrelated issues and special cases.

4.4.1 The trend with technological scalingWith shrinking feature sizes, future deep submicron circuitshave decreased power supply value Vdd and decreasedvelocity saturation index α, leading to increased values forthe coefficients in equation (11). As a consequence, thebuffer delay will become more sensitive to the same powerand ground variations despite better packaging.

In classic wire-bond packaging, the power and ground noisewere closely correlated for the whole chip. Hence it wasappropriate to measure the delay at the 50% point of thechanged power supply and ground level. We considered

as the default value for the high-to-low delay change.It is dominated by the differential mode noise inducedeffect, because .

However, in modern packaging, bump-bond techniques areused. The power and ground noise of each block/cell can berelatively independent of all others. Bump bonding hassignificantly lower parasitics overall - this means that the

on-chip distribution network is more important, but onlybecause the sensitivity has increased and the slew rates haveincreased. It is then appropriate to measure the delay at the50% point of the ideal power supply and ground level. Weconsider as the default value for high-to-low delaychange. It is more sensitive to the common-mode-noiseinduced delays, because . This matches thesimulation results shown in figure 5 and observation 4.

4.4.2 Power v.s. ground variationAs we mentioned in section 2.1, power and groundvariations are related, but not necessarily correlated.Different combinations of variations exist. Usually IR-dropis discussed when assuming and .Ground-bounce is another special case when and

. We list more special cases below.

1. Buffer delay change can be positive (slowdown) or nega-tive (speedup), depending on the polarity of P/G noise,the relative amplitude between ∆Vdd and ∆Vss, and thecoefficients in equation (11).

2. When the changes of power and ground are in the samedirection and have similar amplitudes, we have

. According to equation(11), the buffer delay change will be dominated by theeffect induced by common mode noise for

. However for the fourth type of delaychange, we will have .

On the other hand, when ∆Vdd and ∆Vss change in theopposite directions and have similar amplitudes, we have

. In such a case, if, then , and the buffer delay change

will be dominated by the effect induced by thedifferential mode noise for . isalways dominated by the effect of differential modenoise because .

3. Suppose that, at a certain time period, only power varia-tion exists, i.e. . This degrades to a special casedescribed in [19]. For such a case, buffer delay change islinearly proportional to . In fact in [19] it has beenexperimentally verified that “a given percentage of Vddvariation translates directly to the same percentage ofdelay variation.

4. Similarly, when there is only a ground variation, bufferdelay change is proportional to the .

4.4.3 Definitions of delayThe expressions for delay and slope depend on how wedefine and . We obtained our formulas inappendix A and B based on typical cases. Comparing thesefour different delay definitions, we can see that the same P/G noise has different effects on different ∆delay. Eventhough different coefficients have been obtained, they allfollow theorem 1.

k3n′ 2( ) CL

2ID0------------

tr tr∆+

2V dd-----------------–=

k4n′ 2( ) CL

2ID0------------–

tr tr∆+

2V dd----------------- 1 α–

1 α+-------------⋅+=

k3n′ 3( ) CL

ID0--------

tr tr∆+

V dd----------------- 1

2---

vT

1 α+-------------–

⋅+=

k4n′ 3( ) tr tr∆+

V dd----------------- 1

2---

vT

1 α+-------------+

⋅=

k3n′ 4( ) CL

2ID0------------

tr tr∆+

V dd-----------------

vT

1 α+-------------⋅–=

k4n′ 4( ) CL

2ID0------------–

tr tr∆+

V dd-----------------

vT

1 α+-------------⋅+=

k5n′ j( )

tr∆ 12---

1 vT–

1 α+--------------–

⋅= j 2 3 4, ,=( )

toT∆ h3 V dd∆⋅ h4 V ss∆⋅+=

t pHL4( )∆

k1n4( )

0=

t pHL1( )∆

k1n1( )

k2n1( )>

V dd∆ 0< V ss∆ 0=V ss∆ 0>

V dd∆ 0=

V ss∆ V dd∆– V ss∆ V dd∆+«

delay∆ t pHL1( )∆=

delay∆ t pHL4( )

0≈∆=

V ss∆ V dd∆+ V ss∆ V dd∆–«

k3n1( )

k4n1( )

« k1n1( )

k2n1( )≈

delay∆ t pHL1( )∆= t pHL

4( )∆

k1n4( )

0=

V ss∆ 0=

V dd∆

V ss∆

t pHL∆ tOT∆

10

4.4.4 Change of waveformDelay expressions will be different when the input/outputwaveforms differ from the ones shown in figure 2-3.Through HSPICE simulations, we have observed that thecases shown in figure 2-3 are typical for deep submicroncircuits. When to5 and to5’ fall in region 2 or region 4, theexpression for becomes a little more complicated, butis still closed form. We don’t list all corner cases here.

5. MODEL VALIDATION

We validated our model in both 0.25µm and 0.18µmtechnologies. As mentioned in section 4.1, the alpha-powerlaw MOSFET model relies on four parameters: α, Vtn, ID0(drain current at VGS = VDS = Vdd), VDO (drain saturationvoltage at VGS = Vdd). These four parameters are not listedin the technology files. We determined these values for eachtransistor through HSPICE simulation. The extraction of ID0and VDO are straightforward. We follow the method in [17]to extract α and Vtn.

Table 1 shows our calculated variations in delay and slopecompared to HSpice simulation, for a single inverter withdifferent parameters, in different technologies. 10 sets ofdata are shown. Incremental delays for very fast (<50pS)rise times are not shown, for they are more accuratelymodeled than the presented data are. To achieve very highslew rates, wire parasitics are necessarily low so thatconventional gate-to-gate nominal delay characterizationworks well. The approximations made in the incrementaldelay change model work better for fast slew rates since theshort circuit current is reduced, and feed-forward capacitivecoupling is modeled in the nominal delay.

In the results, we can see that the model provides accurateestimation for delay variations (∆tpHL), with less than 5%error relative to HSPICE over a ±20% supply variation

range. The model is not as accurate in estimating the changeof transition time (∆toT). For delay estimation, this isacceptable because ∆toT has only a second order effect onthe delay of the next stage. Note that this modelingtechnique applies to arbitrary size inverters, loadingcapacitance, and input transition times. Comparison of thetechnologies shows the trend of increasing sensitivity tosupply-level noise with scaling.

6. APPLICATIONS

An important feature of the model is its relative lack ofdependence on the circuit loading structure. This simplifiesinclusion in a design flow as a modification to the existingdelay calculation. Iterations may result, because the updateddelay will further affect the power and ground level. Sinceour formulas are very simple, an iterative process may beaffordable. This section will show some applications of ourmodeling technique.

6.1 Delay change for special buffer designTo preserve duty cycle, clock buffer chain designs oftenpresume equal input and output transition times. Thus:

Substituting tr and ∆tr into equation (11), we have:

(19)

where

t pHL∆

Parameter0.25µm 0.18µm

Simulation Our Method Simulation Our Method

Wp/Wn(µm)

CL(ff)

tr(ps)

∆Vdd(volt)

∆Vss(volt)

∆tpHL(ps)

∆toT(ps)

∆tpHL(ps)

∆toT(ps)

∆tpHL(ps)

∆toT(ps)

∆tpHL(ps)

∆toT(ps)

10/5 100 100 -0.250 -0.250 -21.93 -4.198 -21.23 3.2% -4.849 15% -24.94 -10.71 -24.50 1.8% -12.87 20.1%

10/5 100 100 0.00 -0.100 -4.729 0.169 -4.694 0.7% 0.167 1.1% -6.224 -2.943 -5.970 4.0% -2.598 11.9%

10/5 100 100 0.025 0.100 5.402 0.421 5.644 4.5% 0.418 0.7% 6.950 2.955 6.927 0.3% 3.138 6.2%

10/5 100 100 0.100 0.00 3.760 2.043 3.800 1.0% 2.007 1.8% 3.708 2.680 3.828 3.2% 2.893 8.0%

10/5 20 50 -0.500 0.025 -6.045 -1.683 -5.701 5.6% -1.768 5.1% -8.085 -6.923 -7.802 3.5% -6.238 9.9%

10/5 20 50 0.500 0.100 8.599 2.715 8.195 4.7% 2.525 7.0% 9.729 1.551 10.22 5.0% 1.472 5.1%

5/5 100 100 0.250 0.100 14.13 5.366 14.35 1.6% 4.926 8.2% 17.30 3.639 16.46 4.9% 3.139 13.7%

5/5 100 100 0.500 -0.025 16.47 10.15 17.04 3.4% 10.24 0.8% 19.15 7.701 18.06 5.5% 7.185 6.7%

5/5 100 50 0.025 -0.250 8.294 -4.856 8.686 4.7% -5.137 5.8% 8.524 1.677 8.945 4.9% 1.467 12.5%

10/10 100 100 -0.250 0.050 -4.694 -10.08 -4.644 1.1% -11.78 16.8% -4.733 -2.203 -4.491 5.1% -2.273 3.2%

Table 1: Validation of expressions for incremental buffer delay and slope changes

tr

0.9CL

0.8ID0----------------V dd

CLV D0

0.8ID0-----------------

10V D0

eV dd----------------

ln⋅+=

tr∆0.9CL

0.8ID0---------------- V dd∆ V ss∆–( )

CLV D0

0.8ID0-----------------

V dd

V dd V dd∆ V ss∆–+-----------------------------------------------

ln⋅+=

t pHLj( )∆

CL

ID0-------- f 1n

j( )V com f 2n

j( )V dif∆⋅–∆⋅( )⋅=

CL

ID0-------- f 3n

j( )V dd∆⋅ f 4n

j( )V ss∆⋅+( )⋅=

j 1 4∼=( )

11

, (20)

When ∆tr is ignored, we have:

,

,

,

,

If ∆tr is not negligible, we have:

(21)

where

,

where

For a falling transition, we have:

(22)

Note that equations (19) ~ (22) are independent of inputslope. This result is used below to determine the cumulativejitter in a buffer chain.

6.2 Different buffer chainsThe linear relationship between the P/G noise and delaychange can be used to analyze the delivered jitter for a chainof single-inverter-buffers and a chain of double-inverter-buffers, as shown in figure 7.

Assume the input is a rising transition. For one stage of asingle-inverter-buffer, we have from equation (19):

(23)

For one stage of a double-inverter-buffer, we assume atapered buffer design. According to equations (19) and (22),we have,

(24)

where the superscripts (s) and (d) denote the correspondingparameters for single-inverter-buffer and double-inverter-buffer, respectively. And we assume the parameters for bothbuffer designs are comparable.

In deep submicron technologies, the buffer delay change ismore sensitive to the common mode noise than to thedifferential mode noise. This has been experimentallydemonstrated by our simulation results in figure 5, andtheoretically proved by our equation (11) which indicates

. In other words, we have:

f 1nj( )

f 3nj( )

f 4nj( )

+( ) 2⁄= f 2nj( )

f 4nj( )

f 3nj( )

–( ) 2⁄=

f 3n1( )

1= f 4n1( ) 1

1 α+------------- f 01⋅=

f 3n2( ) 1

2---

12--- f 01⋅–= f 4n

2( ) 12---–

12--- 1 α–

1 α+------------- f 01⋅ ⋅+=

f 3n3( )

1 12---

vT

1 α+-------------–

f 01⋅+= f 4n3( ) 1

2---

vT

1 α+-------------+

f 01⋅=

f 3n4( ) 1

2---

vT

1 α+------------- f 01⋅–= f 4n

4( ) 12---–

vT

1 α+------------- f 01⋅+=

t pHLj( )∆

CL

ID0-------- f 3n

j( )′V dd∆⋅ f 4n

j( )′V ss∆⋅+( )⋅= j 1 4∼=( )

f 3nj( )′

f 3nj( )

f 03+= f 4nj( )′

f 4nj( )

f 03–=

f 010.90.8-------

V D0

0.8V dd-----------------

10V D0

eV dd----------------

ln⋅+=

f 020.90.8-------

V D0

0.8V dd-----------------–=

f 0312---

1 vT–

1 α+--------------–

f 02⋅=

t pLHj( )∆

CL

ID0-------- f– 1 p

j( )V com f 2 p

j( )V dif∆⋅–∆⋅( )⋅=

(a) Single-inverter-buffer chain

(b) Double-inverter-buffer chain

Figure 7. Delay change for single-inverter chain v.s. double-inverter chain

delays( )∆ t pHL

s( )∆CL

ID0s( )-------- f 1n

s( )V com f 2n

s( )V dif∆⋅–∆⋅( )⋅= =

delayd( )∆ t pHL

d( )∆ t pLHd( )∆+=

CL

ID0d( )-------- f 1n

d( )f 1 p

d( )–( ) V com f 2n

d( )f 2 p

d( )+( ) V dif∆⋅–∆⋅[ ]⋅=

k1n1( )

k2n1( )>

12

, ,

When the amplitude of the common mode noise is at least aslarge as that of the differential mode noise, the delay changeof both buffer designs will be dominated by common modenoise. However, when and are comparable, thedelay change induced by common mode noise fromequation (24) will cancel while the delay change given bythe equation (23) will dominate. Hence, we make thefollowing observation:

Observation 6: The delay of a double-inverter-buffer chainis less sensitive to the power/ground noise variations thanthat of a single-inverter-buffer chain.

Figure 8 shows simulation results of buffer delay change forthe buffer chains shown in figure 7. The power/ground noiseof each buffer in the chain is independent of the others andranges over of Vdd. Inverter sizes are determinedsuch that both buffer chains in figure 7 have a similarnominal delay (around 280ps). This is done to simplifycomparison of the delay changes, because buffer chainswith un-correlated delay would be difficult to compare. Wechoose similar wire loads for each stage. We randomlysimulate 20000 combinations of P/G noise induced jitter.The statistics in figure 8 clearly show that the overall

delivered jitter (total delay change of the buffer chain) forthe double-inverter buffers is smaller than that of a single-inverter buffer chain. In other words, a single-inverter bufferchain has larger delay uncertainty than the double-inverterbuffer chain. This provides us a new guideline for design: interms of power/ground noise avoidance, the double-inverterbuffer chain is a better choice. Double-inverter buffers haveslightly larger current requirements than inverters due bothto tapering and to the domination of load capacitance by theinterconnect, so the effect of additional current is minor.This result is affected by rapidly changing power levelsprimarily in the slow rise-time (RC dominated) extents ofthe interconnect. However, such effects should be similarfor both styles of repeater.

7. CONCLUSION

Maintaining signal integrity in deep submicron circuits is adifficult problem. Variations of power and ground levelsplay an important role because this type of noisesignificantly degrades circuit performance. Deep submicroncircuits have decreased power supply level Vdd anddecreased velocity saturation index α, leading to increasedsensitivity of delay to P/G noise. Thus, despite the reductionof noise from lower-inductance packaging, the relativemagnitude of the delay changes is still a serious potentialproblem.

We studied the effects of differential and common modepower/ground noise on buffer delay. Using the α-power lawMOSFET model, we derived general formulas to estimatethe influence of power and ground noise on delay and slope.As our model does not rely on the circuit structure, it can beincorporated into any existing gate delay calculationtechniques. It is simple and accurate. An application inclock buffer chain design shows that repeater chains, usingbuffers instead of inherently faster inverters, tend to havesuperior level - induced delay characteristics.

ACKNOWLEDGEMENTThis work was supported in part by the NSF grant # CCR-0098069 and in part by the California MICRO programthrough Synopsys and Mindspeed.

REFERENCES

[1] C. J. Alpert, A. Devgan, S. T. Quay, Buffer insertion fornoise and delay optimization, IEEE Transactions onComputer-Aided Design of Integrated Circuits and Sys-tems, vol.18, no.11, Nov.1999, pp.1633-45.

[2] R. Arunachalam, F. Dartu and L. T. Pillage, CMOS gatedelay models for general RLC loading, ICCD, pp.224-229, 1997.

[3] K. A. Bowman, X. Tang, J. C. Eble and J. D. Meindl,Impact of extrinsic and intrinsic parameter fluctuations

f 1ns( )

f 2ns( )> f 1n

d( )f 2n

d( )> f 1 pd( )

f 2 pd( )>

f 1nd( )

f 1 pd( )

Figure 8. Comparison of buffer delay change(histogram)

0 2 4 6 8-2-4

350030002500200015001000500

0

0 2 4 6 8-2-4 10-6

4000

350030002500200015001000500

0

(a) Delay change for a single-inverter-buffer chain

(b) Delay change for a double-inverter-buffer chain

Num

ber

of c

lass

es

Num

ber

of c

lass

es

(multiply by 10ps)

(multiply by 10ps)

10%±

13

on CMOS circuit performance, IEEE Journal of Solid-State Circuits, vol.35, no.8, Aug.2000, pp.1186-1193.

[4] H.-R. Cha and O.-K. Kwon, An analytical model ofsimultaneous switching noise in CMOS systems, IEEETransactions on Advanced Packing, vol.23, no.1, Feb-ruary 2000, pp.62-68.

[5] H. H. Chen and J. S. Neely, Interconnect and circuitmodeling techniques for full-chip power supply noiseanalysis, IEEE Trans. on Components, Packaging, andManufacturing Technology-Part B, vol.21, no.3,Aug.1998, pp.209-215.

[6] L. H. Chen, M. Marek-Sadowska, F. Brewer, Copingwith buffer delay change due to power and groundnoise, Design Automation Conference, June, 2002.

[7] C.C. N. Chu and D. F. Wong, A new approach to simul-taneous buffer insertion and wire sizing, ICCAD, 1997,pp.614-621.

[8] F. Dartu, N. Menezes, J. Qian, and L. T. Pillage, A gate-delay model for high-speed CMOS circuits, Proc. DAC,pp.576-580, 1994.

[9] S. Dhar and M. A. Franklin, Optimum buffer circuits fordriving long uniform lines, IEEE Journal of Solid-StateCircuits, vol.26, no.1, Jan.1991, pp.32-40.

[10]K.-H. Erhard, F. M. Johannes and R. Dachauer, Topol-ogy optimization techniques for power/ground networksin VLSI, EURO-DAC’92, pp.362-367.

[11]P. D. Gross, R. Arunachalam, K. Rajagopal, and L. T.Pileggi, Determination of worst-case aggressor align-ment for delay calculation, Proc. ICCAD, pp. 212-219,1998.

[12]N. Hedenstierna and K. O. Jeppson, CMOS circuitspeed and buffer optimization, IEEE Trans. Computer-Aided Design, vol.CAD-6, no.2, pp.270-280,Mar.1987.

[13]P. Heydari and M. Pedram, Analysis and optimizationof ground bounce in digital CMOS circuits, Proceed-ings of IEEE International Conference on ComputerDesign: VLSI in Computers & Processors, 2000,pp.121-126.

[14]A. Kabbani and A. J. Al-Khalili, Estimation of groundbounce effects on CMOS circuits, IEEE Trans. on Com-ponents and Packaging Technology, vol.22, no.2, June1999, pp.316-325.

[15] J. Lillis, C. K. Cheng, and T.-T. Y. Lin, Optimal wiresizing and buffer insertion for low power and a general-ized delay model, IEEE Journal of Solid-State Circuits,vol.31, no.3, March 1996, pp.437-47.

[16] J. Qian, S. Pullela, and L. Pillage, Modeling the “effec-tive capacitance” for the RC interconnect of CMOSgates, IEEE Trans. on CAD, vol.13, no.12, Dec.1994.

[17]T. Sakurai, Alpha-power law MOSFET model and itsapplications to CMOS inverter delay and other formu-las, IEEE Journal of Solid-State Circuits, vol.25, no.2,April 1990, pp.584-594.

[18]T. Sakurai and A.R. Newton, Delay analysis of series-connected MOSFET circuits, IEEE Journal of Solid-State Circuits, vol.26, no.2, Feb.1991, pp.122-131.

[19]R. Saleh, S. Z. Hussain, S. Rochel, and D. Overhauser,Clock skew verification in the presence of IR-drop in thepower distribution network, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems,vol.19, no.6, June 2000, pp.635-644.

[20]S. R. Vemuru, Effects of simultaneous switching noiseon the tapered buffer design, IEEE Trans. on VLSI Sys-tems, vol.5, no.3, Sep.1997, pp.290-300.

[21]Y. Yang and J.R. Brews, Design for velocity saturated,short-channel CMOS drivers with simultaneous switch-ing noise and switching time considerations, IEEEJournal of Solid-State Circuits, vol.31, no.9, September1996, pp.1357-1360.

APPENDIX A: DERIVING THE OUTPUTWAVEFORM IN THE PRESENCE OFPOWER AND GROUND NOISE

We first derive the output waveform for figure 3(a). Thederivation is based on the definitions from figures 2 and3(a).

In region 1, NMOS is in cutoff. So we have:

(A1)

In region 2, NMOS is in saturation mode, and the input isdefined by equation (10). The output waveform satisfies thefollowing differential equation:

Let . With initial condition ,, we get:

(A2)

where

Referring to figure 3, we have:

V in′

V i′

V ss∆–ttr--- V dd⋅ V ss∆–= =

V out′

V dd ∆V dd V ss∆–+= 0 tV ss∆ V+

tn

V dd-------------------------- tr⋅≤ ≤

CL

dV out′

dt-------------- ID0

V in′

V tn–

V dd ∆V dd V tn–+-------------------------------------------

α

–=

vT V tn V dd⁄= V in′

V tn=V out

′V dd ∆V dd ∆V ss–+=

V out′

V dd ∆V dd ∆V ss–+( )ID0 tr⋅

CL----------------- g t( )⋅–=

region 2:∆V ss V tn+( ) tr⋅

V dd---------------------------------------- t tr≤ ≤

g t( )

ttr---

∆V ss

V dd------------– vT–

1 α+

1 α+( ) 1∆V dd

V dd------------- vT–+

α--------------------------------------------------------------=

14

In region 3, NMOS is still in saturation mode. But the inputis fixed at:

Substituting the above equation into region 2’s differentialequation, with initial condition (tr, ), we get:

(A3)

where

and is the time when , expressed as follows:

where

In region 4, the input is the same as in region 3, but NMOSgoes into linear operation mode. The discharging process isdescribed by the following differential equation:

Substituting the initial condition (tD0’, VD0), we get:

(A4)

where

,

When , equations (A1), (A2), (A3) and(A4) describe the output waveform with ideal Vdd and Vss.

Similar results were obtained when the inverter has a fallingtransition at its input. In such a case, we consider PMOS tobe on, and NMOS to be off. PMOS will start from its cutoffregion, traverse the saturation region and finally settle in itslinear region.

A similar procedure can be applied to obtain the outputwaveform for figure 3(b).

APPENDIX B: DERIVING THE BUFFERDELAY CHANGE

We use the derivation of as an example. Derivationand the results for the other three types are similar.

According to the results in appendix A, we obtain ti5’, to5’,to1’, to9’ and tD0’. By setting ∆Vdd and ∆Vss to 0, we canobtain the corresponding ti5, to5, to1, to9 and tD0. Therefore,we have:

According to figure 3, for the signal transition withdisturbed Vdd and Vss, we have:

where is defined in appendix A.

where tD0’ and R3’ are defined in appendix A.

where

According to the definitions in section 3.2, we obtain:

(A5)

where

,

The change of delay can also be expressed as:

(A6)

where

,

We also obtain the change of slope as follows:

V TR′

V out′

t tr=( )=

V in′

V dd ∆V ss–=

V TR′

V out′

V dd ∆V dd V ss∆–+( )ID0 kv⋅

CL------------------ t tα

′–[ ]⋅–=

region 3: tr t tD0′≤ ≤( )

tα′

tr 1

1∆V ss

V dd------------ vT––

1 α+---------------------------------–

⋅=

tD0′

V out′

V D0=

tD0′ CL

ID0 kv1⋅-------------------- V dd ∆V dd ∆V ss– V D0–+( )⋅ tα

′+=

kv1

V dd ∆V ss– V tn–

V dd ∆V dd V tn–+-------------------------------------------

α

1≈=

CL

dV out′

dt--------------

ID0

V D0----------

V dd ∆V ss– V tn–

V dd ∆V dd V tn–+-------------------------------------------

α 2⁄

V out′

–=

V out′

V D0et tD0

′–( ) CLR3′( )⁄–

= region 4: t tD0≥( )

R3′ V D0

ID0kv2----------------= kv2 kv1 1≈=

V dd∆ V ss 0=∆=

t pHL1( )∆

ti5

tr

2---=

to5

CLV dd

2ID0----------------

vT α+

1 α+---------------- tr⋅+=

to1 tD0 CLR3

10V D0

V dd----------------

ln⋅+=

to9 trvT tr

V ddCL

10ID0tr------------------- 1 α+( ) 1 vT–( )α⋅

1 1 α+( )⁄+=

ti5′ 1( ) tr

2---=

to5′ 1( ) CL

ID0kv1----------------

V dd

2--------- V dd∆+

⋅ tα′

+=

tα′

to1′ 1( )

tD0′

CLR3′ 10V D0

V dd V dd∆ V ss∆–+-----------------------------------------------

ln⋅+=

to9′ 1( )

tr

V ss∆V dd------------ vT q( )1 1 α+( )⁄

+ +⋅=

qCLV dd

10ID0tr------------------- 1 α+( )⋅ 1

V dd∆ V ss∆–

V dd-------------------------------+

1V dd∆

V dd------------- vT–+

α=

t pHL1( )∆ k1

1( )V dd∆ V ss∆+( ) k2

1( )V dd∆ V ss∆–( )⋅–⋅=

k11( ) tr

2V dd 1 α+( )-------------------------------

CL

2ID0------------+= k2

1( ) tr

2V dd 1 α+( )-------------------------------

CL

2ID0------------–=

t pHL1( )∆ k3

1( )V dd∆⋅ k4

1( )V ss∆⋅+=

k31( )

k11( )

k21( )

–= k41( )

k11( )

k21( )

+=

15

(A7)

where

By applying a Taylor expansion, we obtain:

Therefore the change of output slope can be simplified asfollows:

(A8)

or,

(A9)

where

,

toT1( )∆ toT 1∆ toT 2∆ toT 3∆ toT 4∆+ + +( ) 0.8⁄=

toT 1∆CL

ID0-------- V dd∆ V ss∆–( )⋅=

toT 2∆CL

ID0-------- V D0

V dd

V dd V dd∆ V ss∆–+--------------------------------------------

ln⋅ ⋅=

toT 3∆ trα

1 α+-------------

V ss∆–

V dd---------------⋅ ⋅=

toT 4∆ tr p0 1 vT–( )α 1 α+( )⁄p1–[ ]⋅ ⋅=

p0

CLV dd 1 α+( )10ID0tr

-----------------------------------1 1 α+( )⁄

=

p1 1V dd∆ V ss∆–

V dd-------------------------------+

1V dd∆

V dd------------- vT–+

α 1 α+( )⁄⋅=

toT 2∆CL V D0⋅ID0 V dd⋅---------------------- V dd∆ V ss∆–( )⋅–=

toT 4∆ tr p0

1 2α αvT–+

1 α+--------------------------------

V dd∆V dd

-------------⋅–1 α αvT–+

1 α+-----------------------------

V ss∆V dd------------⋅+

⋅ ⋅=

toT1( )∆ h1

1( )V dd∆ V ss∆+( ) h2

1( )V dd∆ V ss∆–( )⋅–⋅=

toT1( )∆ h3

1( )V dd∆⋅ h4

1( )V ss∆⋅+=

h11( ) h3

1( )h4

1( )+

2-------------------------= h2

1( ) h41( )

h31( )

–

2------------------------=

h31( ) 1

0.8-------

CL

ID0-------- 1

V D0

V dd----------–

⋅1 2α αvT–+( ) p0 tr⋅ ⋅

1 α+( ) V dd⋅--------------------------------------------------------–=

h41( ) 1

0.8-------

CL

ID0-------- 1

V D0

V dd----------–

⋅–1 α αvT–+( ) p0 α–[ ] tr⋅

1 α+( ) V dd⋅---------------------------------------------------------------+=