Built-In Self-Test of Configurable Cores in SoCsUsing Embedded Processor

Dynamic Reconfiguration

John Sunwoo (ETRI, Korea)

and Charles Stroud (Electrical & Computer Engineering

Auburn University, USA)

OutlineAtmel AT94K SoC architecture

FPGA core and AVR-FPGA interfaceDynamic Cache Logic

Major feature used for this workLogic and routing BIST architecture of embedded FPGA core in AT94K series SoCs

Dynamic reconfiguration sequence of BIST componentsConfiguration routine analysis

Experimental resultsImprovements in total test time and external memory storage savings

Summary and conclusions

On-Chip BIST and DiagnosisAtmel SoCs contain:

Program & Data RAMsProcessor coreFPGA core

Use processor to:Configure FPGA for BISTRun BISTGet BIST resultsPerform diagnosis

Reduces test and diagnosis timeStore only one BIST and diagnostic program on-chip

Atmel AT94K Series SoC

PLB ArrayAT94K40 = 48x48AT94K20 = 36x26

Never manufacturedAT94K10 = 24x24AT94K05 = 16x16

Too small

Program Memory20Kbytes minimumUp to 32Kbytes

Data Memory4Kbytes minimumUp to 16Kbytes

FPGA Core Architecture in AT94K SoC

FPGA

Horizontal Repeater Vertical Repeater

Set/Reset Clock free RAM

AVR

8-bit data bus

FPGAIORE/WE

16 IOSEL

16 INT

Y

Y

Y Y

X X

X XPLB

= Programmable Interconnect

Point

FPGA coreFine-grain architecture

Large number of small PLB cells1 PLB has 2 LUTs, 1 FF

Symmetrical NxN arrayVertical & horizontal repeaters every 4x4 PLBs

x4 and x8 global routing resourcesBank clock and set/reset linesDedicated free RAMs PLB has X and Y direct connections

AVR core8-bit RISC (32 general purpose regs)General purpose I/O ports (PORTE)

AVR-FPGA interface8-bit bi-directional data bus16 I/O select lines from AVR to FPGA 16 interrupts from FPGA to AVR

a) Local Routing b) Global Routing

Dynamic Cache Logic

PLB addressableFPGAX, FPGAY, FPGAZWrite 1 byte at a time (FPGAD + config CLK)

No configuration memory readback capability

Results in longer BIST development time

Cannot do read-modify-write

Configuration Word(24 Bit Address + 8 Bit Data)

ProcessorCore(AVR)

FPGA Core

FPGAXFPGAYFPGAZFPGAD

32-Bit

X

YZ

= PLB

Write

Embedded AVR processor core can write FPGA configuration memory without disturbing operations

Main feature used to eliminate external downloads to embedded FPGA core

Logic BIST for AT94K Series SoCs

A PLB cannot have more than one X-input and one Y-input at a timeEach ORA monitors a diagonal X-output and orthogonal Y-output from neighboring BUTsTwo routing schemes for complete test of X & Y outputs

BUTs are reconfigured in various modes to completely test BUTsBIST architecture is flipped, by configuring PLBs that were previously TPGs/ORAs to be BUTs

a) West Session b) East Session

=TPG=BUT=ORA

Routing Scheme 2

RoutingScheme 1

Conventional FPGA BISTTest Phase 1 Test Phase 2

FPGAFPGAResetReset

READREADORAORA

READREADORAORA

FPGAFPGAResetReset

External downloads consume major portion of testing timeMore test phases means more external storage is requiredTo find faulty blocks, ORA results are retrieved after each test phase

download of the next test phase causes FPGA core to be reset

External controller is neededBIST clocks from external pinORA results are retrieved outside through external pinEmbedded processor is not a main BIST component

Empty

TPG

ORA

BUT1

BUT2

Fault

AVR-generated FPGA BISTTest Phase 1 Test Phase 2

No download to FPGA coreSingle AVR program contains algorithmic reconfiguration routines for configuring FPGA core for each test phase

TPG and ORA configurations are reusable for next phaseUntil architecture flips to next test sessionAVR reconfigures - BUTs for each test phase

ORA results can be retrieved after multiple phases Because FF values in ORAs remain throughout subsequent phases

ResetResetREADREADORAORA

ResetResetREADREADORAORA

Empty

TPG

ORA

BUT1

BUT2

Fault

Dynamic Reconfiguration Sequence (1)Clear FPGA core

PLBs, repeaters, clk, FFs, freeRAMs, IOBsNo need for chip reset

Configure ORAsComparison-based ORAReset ORA FFsRouting scheme 1 or 2

Configure BUTsChange BUT configurationsWrite FF contents from AVR (FF set/reset test)

Cannot be tested by external download

Configure TPGsTwo 5-bit countersRoute TPG signals to BUTs

Need extra attention when configuring repeatersReset TPG FFs

=TPG=BUT=ORA

Route BIST clockBIST clock driven by AVR

Configure AVR-FPGA interfaces that cannot be called from MGLRoute from FPGAIOWE to GCK4Route clock signal to all BUTs, ORAs and TPGs

Run BIST clockReconfigure ORAs as a scan chain

Dynamic partial reconfiguration of ORAs to scan chain without destroying ORA FF contents

Route scan out pathORA scan chain output to one of the 8-bit bus between AVR and FPGA

AVR Data In (ADIN)Retrieve ORA results

On-chip diagnosis by AVR

Dynamic Reconfiguration Sequence (2)

FIGARO

Total Configuration Routine for logic BIST

97,37024,87945402Route scan out

24,7916,37180282ORA/shift register

594,427157,9574,0004,676TotalN/AN/A2,659388Miscellaneous

75,85919,33935306Retrieve results

456456632Generate clocks

4,9111,92340234Route BIST clock14,8664,6526001,486Instantiate TPG60,68614,84470220Instantiate ORA

100,36025,829300834Instantiate BUT215,12859,664150492Clear FPGA

K40K10

Processor Execution Cycles

Number of Lines of C Code (Approx.)

Program Memory

Size (Bytes)

BISTReconfiguration

Subroutines

Largest subroutine in program memory and in lines of code is for configuring TPGsDue to its irregular structures

Clearing FPGA and configuring BUTs/ORAs need less program memory sizeDue to regular structure of BIST architecture

Subroutines are parameterized to be used for both east and west sessionsAnd any size FPGA core

Routing BIST ArchitectureComparison-based BIST(Stroud et.al., ITC 1997)

Inefficient for small PLBsOnly compare 2 wires in a 1 PLB ORA

Parity-based approach(Sun, Chan, et.al. ITC 2000)

Good for small PLBs2-bit up-counter w/ even parity, and2-bit down-counter w/ odd parity

Gives opposite logic values forStuck-on switches & bridging faults

Parity used as test pattern3 wires under test in a 1 PLB ORAOpposite logic values between any pair of wires for bridging faults

COCO

Pass/FailPass/Fail

OORRAA

WUTsWUTs

TPGTPGC1C1ParPar

+PPee CC11 CC0 0 PPoo CC11 CC00

0 0 0 1 1 10 0 0 1 1 11 0 1 0 1 01 0 1 0 1 01 1 0 0 0 11 1 0 0 0 10 1 1 1 0 00 1 1 1 0 0

Routing BIST for AT94K Series SoCs

Modified parity-based routing BIST3-bit TPG = 2-bit counter + parity

Drive all five x4 global busesparity bit applied through the middle wire segmenttwo count values (C0 & C1) are applied to both pairs of outer wire segments

Detects allstuck-at faults, bridging faults and opens in wire segments stuck-on/off faults in switches and repeater multiplexers

Par

local routing resources

C1C0 ORA ORA

global×4

lines

FPGA Core Architecture in AT94K SoC

FPGA

Horizontal Repeater Vertical Repeater

Set/Reset Clock free RAM

AVR

8-bit data bus

FPGAIORE/WE

16 IOSEL

16 INT

Y

Y

Y Y

X X

X XPLB

= Programmable Interconnect

Point

FPGA coreFine-grain architecture

Large number of small PLB cells1 PLB has 2 LUTs, 1 FF

Symmetrical NxN arrayVertical & horizontal repeaters every 4x4 PLBs

x4 and x8 global routing resourcesBank clock and set/reset linesDedicated free RAMs PLB has X and Y direct connections

AVR core8-bit RISC (32 general purpose regs)General purpose I/O ports (PORTE)

AVR-FPGA interface8-bit bi-directional data bus16 I/O select lines from AVR to FPGA 16 interrupts from FPGA to AVR

a) Local Routing b) Global Routing

Original Repeater Routing BIST24 total tests

3 sets of tests1-Loopback2-Criss-cross3-Straight through

Each set applied 4 timesVertical E & A bussesHorizontal E & A busses

Applied again to reverse direction

O T O T O T

Set #1ESet #1E

Set #1ASet #1A

O T O T O T

O T O T O T

Set #2ESet #2E

O T O T O T

Set #2ASet #2A

TOSwap TPGs/ORAs for directional testSwap TPGs/ORAs for directional test

O T T

T O O

Set #3ESet #3E

O

T O O

Set #3ASet #3A

O

4 additional test configurations were need to test pass gate for a total of 28

0

5

10

15

20

25

30

35

40

X3Y3

Z0B0

S0

X3Y3

Z0B2

S0

X3Y3

Z0B4

S0

X3Y3

Z0B6

S0

X3Y3

Z1B1

S0

X3Y3

Z1B3

S0

X3Y3

Z1B5

S0

X3Y3

Z1B7

S0

X3Y3

Z2B1

S0

X3Y3

Z2B3

S0

X3Y3

Z2B5

S0

X3Y3

Z3B0

S0

X3Y3

Z3B2

S0

X3Y3

Z3B4

S0

X3Y3

Z4B0

S0

X3Y3

Z4B2

S0

X3Y3

Z4B4

S0

X3Y3

Z4B6

S0

X3Y3

Z5B1

S0

X3Y3

Z5B3

S0

X3Y3

Z5B5

S0

X3Y3

Z5B7

S0

X3Y3

Z6B1

S0

X3Y3

Z6B3

S0

X3Y3

Z6B5

S0

X3Y3

Z7B0

S0

X3Y3

Z7B2

S0

X3Y3

Z7B4

S0

X3Y3

Z8B0

S0

X3Y3

Z8B2

S0

X3Y3

Z8B4

S0

X3Y3

Z8B6

S0

X3Y3

Z9B1

S0

X3Y3

Z9B3

S0

X3Y3

Z9B5

S0

X3Y3

Z9B7

S0

Faults

#Con

figur

atio

ns D

etec

ting

Faul

t

Fault Injection AnalysisOriginal 24 downloaded routing BIST configurations

12 faults of 130 possible faults were not detected

Configurations 5 & 6Configurations 5 & 6test pass gatestest pass gates

Flip to test directionFlip to test direction

Rotation to testRotation to testvertical routingvertical routing

40 40 configsconfigs totaltotal

LLLL

LXLX RXRX

RLRL

CountCount--downdownOdd parityOdd parity

CountCount--upupEven parityEven parity

O T O T O T O TO T O T

1

O T O T O T O TO T O T

4,5

O T O T O T O T O T O T

2

O T O T O T O T O T O T

3

OT OT OT OT OT TO

6,7

8OT OT OT OT OTO T

9

10

OTOT OTOT OT TO

K10K10 K40K40

FPGAWEFPGAWE

OT OT OT OT OT TO

3f,8f3f,8f2,3f2,3f1,101,106,7,96,7,96f,7f,10f6f,7f,10fRXRX

2f2f2,82,83f,8f3f,8f991,6,7,101,6,7,10

1f,6f,7f,9f1f,6f,7f,9fLXLX

4f4f8,8f8,8f7711--3,1f3,1f--3f3fLLLLRLRL

muxmuxinputinput

9,109,103,83,82f,8f2f,8f66--881,1f,9,10f1,1f,9,10fRXRX

338,98,98f,9f8f,9f10f10f1,6,71,6,7

1f,6f,7f1f,6f,7fRLRL

2f,8f2f,8f9,9f9,9f1,91,96,7,6f,7f6,7,6f,7fLLLLLXLXmuxmuxinputinput

3f3f8,98,98f,9f8f,9f10101,6,71,6,7

1f,6f,7f1f,6f,7fLLLLRXRXmuxmuxinputinput

448,8f8,8f7f7f11--3,1f3,1f--3f3fRLRLLLLL

muxmuxinputinput

5,5f5,5f88--10,8f10,8f--10f10f6,6f6,6f11--3,1f3,1f--3f3fPass gatePass gate

EbusEbusAbusAbusRepeaterRepeater

1,1f,9f,101,1f,9f,106,7,6f,7f6,7,6f,7f

1,6,7,91,6,7,91f,6f,7f,10f1f,6f,7f,10f

6,7,106,7,106f,7f,9f6f,7f,9f

StuckStuck--onon

6f6f--8f8f1f,9f1f,9f

9f9f

1f,10f1f,10f

StuckStuck--offoff

2,3f,8,8f2,3f,8,8f9,9f9,9f

3,83,82f,8f2f,8f

2,3f2,3f

StuckStuck--onon

2,82,8RLRL

22RXRX

FaultFault

9f,10f9f,10f

3,83,8

StuckStuck--offoff

LXLX

LXLX

LXLX

LLLL RLRLLXLXRXRXRLRL

RXRXRLRLLLLL

LXLXRLRLLLLL

LXLXRXRXLLLL

PAS

RXRX

LLLL

LXLX RXRX

RLRL

Fault Injection Analysis

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

X2Y3

Z0B0

S0

X2Y3

Z0B2

S0

X2Y3

Z0B4

S0

X2Y3

Z0B6

S0

X2Y3

Z1B1

S0

X2Y3

Z1B3

S0

X2Y3

Z1B5

S0

X2Y3

Z2B1

S0

X2Y3

Z2B3

S0

X2Y3

Z2B5

S0

X2Y3

Z3B0

S0

X2Y3

Z3B2

S0

X2Y3

Z3B4

S0

X2Y3

Z4B0

S0

X2Y3

Z4B2

S0

X2Y3

Z4B4

S0

X2Y3

Z4B6

S0

X2Y3

Z5B1

S0

X2Y3

Z5B3

S0

X2Y3

Z5B5

S0

X2Y3

Z6B1

S0

X2Y3

Z6B3

S0

X2Y3

Z6B5

S0

X2Y3

Z7B0

S0

X2Y3

Z7B2

S0

X2Y3

Z7B4

S0

X2Y3

Z8B0

S0

X2Y3

Z8B2

S0

X2Y3

Z8B4

S0

X2Y3

Z8B6

S0

X2Y3

Z9B1

S0

X2Y3

Z9B3

S0

X2Y3

Z9B5

S0

Horizontal Abus Repeater Faults

# C

onfig

s D

etec

ting

Faul

tNew AVR generated 40 routing BIST configurations

all 130 possible faults were detected

Configurations Routines for Routing BIST

Routing BIST generation and reconfiguration program are similar to logic BIST shown previouslySingle AVR program generates all 56 routing BIST configurations

8,578,7181,1557,85456Total6,671,9736364,41240Repeaters1,906,7455193,44216Cross-points

Processor Cycles K40

Lines of C Code

Memory(bytes)

# Configs

BISTSubroutine

Analyzing Total Speed-up and Memory ReductionLogic and routing BIST configurations were implemented and verified on both AT94K10 and AT94K40

Experimental results data from AT94K40 SoCs (48x48 array)

Up to 32Kbyte program memory space available

Total test time = download time (1MHz) + Run time (25MHz)

1MHz in order to use ‘Check sum’ function25MHz AVR processor clock (Maximum)

Data obtained from simulations of AVR C code and calculations of actual download/execution time

Experimental Results (Speed-up)

182.40.110 sec20.064 secDownload0.0750.343 sec0.026 secExecution

76.00.101 sec7.680 secDownload0.20.085 sec0.016 secExecution

43.50.639 sec27.786 secTotal Test Time20.090 sec

7.696 sec

Download

0.453 sec

0.186 sec

Processor

44.3Total timeRouting BIST

41.4Total timeLogic BIST

Speed-upFunctionResource

Configuration download time dominates total test time for conventional download approachLonger execution time on processor-generated BIST approach than download approach

Experimental Results (Memory Reduction)

Download approach needs 60 configuration downloads to the chipProcessor-generated BIST approach requires only one (relatively small) download to the program memory of AVR processor

158122 Kbyte6058 KbyteCombined179114 Kbyte4457 KbyteRouting80112 Kbyte1660 KbyteLogic

# FilesFile Size#

FilesAverageFile Size

Memory Reduction

Factor

ProcessorDownloadResource

Tested

Conclusions

BIST in SoCs gives more control over the embedded cores than other external test methodsDynamic partial reconfiguration capability improves testabilitySingle program in embedded processor memory

eliminates the downloads to FPGA coregives improves total test time (by factor of 43.5) reduces external configuration memory storage required (by factor of 158) facilitates on-chip, on-demand BIST and diagnosis

New work: Apply same idea to Virtex II & 4