by xiaodong yang
TRANSCRIPT
1
STRAIN EFFECTS ON THE PERFORMANCE OF SILICON MOSFETS
By
XIAODONG YANG
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
2009
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© 2009 Xiaodong Yang
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To my dear mother
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ACKNOWLEDGMENTS
First of all, I would like to thank my advisor, Dr. Scott E. Thompson, for his continuous
encouragement and patient guidance. I have learned from Dr. Thompson not only how to do
experimental and theoretical research, but also how to explore this world as an electrical
engineer. I would also like to thank Dr. Toshikazu Nishida for his numerous critical advices in
experimental measurements and academic writings. I would like to thank Dr. Christopher J.
Stanton and Dr. Jing Guo for serving as my committee members in their busy schedules and
providing important comments about this dissertation. I would like to thank Dr. Thomas
Hoffman for offering me an excellent internship opportunity at IMEC where I met lots of
talented experts in semiconductor field and learned the differences between industry and
academia.
I would like to thank my colleagues at SWAMP. They have contributed a lot to my
research activities. Dr. Yongke Sun and Dr. Guangyu Sun provide a lot of help in the simulation
process. Dr. Jisong Lim, Dr. Younsong Choi, Srivatsan Parthasarathy, and Andrew Koehler gave
me tremendous suggestions in experimental measurements. I would also like to thank other
pervious and present group members, Dr. Sagar Suthram, Dr. Kehui Wu, Min Chu, Hyunwoo
Park, Uma Aghoram, Tony Acosta, Ukjin Roh, and Mehmet Baykan for their helps.
This dissertation is dedicated to my family. I would like to especially thank my mother for
her constant support and understanding. I also would like to thank my beautiful girlfriend Yajing
Wang for motivating and helping me realize my dream.
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TABLE OF CONTENTS page
ACKNOWLEDGMENTS.................................................................................................................... 4
LIST OF TABLES................................................................................................................................ 7
LIST OF FIGURES .............................................................................................................................. 8
ABSTRACT ........................................................................................................................................ 12
CHAPTER
1 INTRODUCTION....................................................................................................................... 15
Traditional CMOS limits ............................................................................................................ 15 Strained Silicon ........................................................................................................................... 16
Biaxial Strained Silicon Devices ........................................................................................ 17 Uniaxial Strained Silicon Devices ...................................................................................... 18
Motivation.................................................................................................................................... 19 Outline of the Dissertation .......................................................................................................... 20
2 STRAIN EFFECTS ON BULK SILICON BAND STRUCTURE.......................................... 22
Stress and Strain .......................................................................................................................... 22 Strain Effect on Conduction Band ............................................................................................. 25 Strain Effect on Valence Band ................................................................................................... 26
3 STRAIN INDUCED LEAKAGE CURENT CHANGE .......................................................... 29
Leakage Current Change in Inversion Regime ......................................................................... 30 Quantum Mechanical Model for n-Channel MOSFETs ................................................... 33
A. Self-consistent solution of Schrödinger and Poisson equations ........................... 35 B. Tunneling current .................................................................................................... 36
Quantum Mechanical Model for p-Channel MOSFETs ................................................... 39 Qualitative Analysis of Tunneling Current Change .......................................................... 43
Leakage Current Change in Accumulation Regime for n-Channel MOSFETs ...................... 46 Summary ...................................................................................................................................... 55
4 LOW TEMPERATURE EFFECT ON MOBILITY IN STRAINED MOSFETS .................. 57
Scattering Mechanism ................................................................................................................. 58 Phonon Scattering ................................................................................................................ 59 Surface Roughness Scattering............................................................................................. 60
Low Temperature Effect on Mobility in Strained p-channel MOSFETs ................................ 61 Low Temperature Effect on Mobility in Strained n-channel MOSFETs ................................ 68 Summary ...................................................................................................................................... 72
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5 EFFECTIVE WORK FUNCTION CHANGE WITH THE APPLIED STRESS ................... 73
Effective Work Function Change with the External Mechanical Stress ................................. 74 Experimental Setup.............................................................................................................. 75 Experimental Results ........................................................................................................... 78
Effective Work Function Change with the Process Introduced Stress .................................... 81 Bowing Technique for Stress Measurement ...................................................................... 81 Charge Pumping for Interface States Measurement .......................................................... 82
Summary ...................................................................................................................................... 86
6 SUMMARY AND SUGGESTIONS ABOUT FUTURE WORKS ........................................ 87
Summary ...................................................................................................................................... 87 Suggestions about Future Works................................................................................................ 88
LIST OF REFERENCES ................................................................................................................... 90
BIOGRAPHICAL SKETCH ........................................................................................................... 103
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LIST OF TABLES
Table page 1-1 Performance enhancement challenges, difficulties, and possible solutions. ...................... 16
2-1 Independent component of the elastic tensor in GPa and elastic compliance constants in 10-12m2/N. ........................................................................................................................... 25
3-1 Luttinger-Kohn parameters, deformation potentials and split-off energy for Si and Ge. ................................................................................................................................................. 41
5-1 EWF and its change with different metal gate thickness as 10, 5, and 2 nm, respectively. ............................................................................................................................ 78
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LIST OF FIGURES
Figure page 1-1 Biaxial tensile stressed Silicon on relaxed SiGe layer ......................................................... 18
1-2 TEM micrographs of p- and n-channel MOSFETs with 45-nm gate length. ..................... 18
2-1 Nine stress components acting on a small cube. .................................................................. 23
2-2 (a) Conduction band structure of silicon in the unstrained case. Ellipsoids of constant electron energy in reciprocal k space, each corresponding to one of the degenerate conduction band valleys. (b) A longitudinal uniaxial tensile stress in the (001) silicon place removes the degeneracy between the four in-plane valleys (Δ4) and the two out-of-plane valleys (Δ2). ...................................................................................................... 26
2-3 Valence band and constant energy surfaces (E=25meV) in k space for the top band and bottom band in the case of (a) unstressed silicon, (b) longitudinal compressive stress, and (c) biaxial tensile stress. ...................................................................................... 27
3-1 The four point bending jig used to apply uniaxial stress to the substrate. In this picture, (a) uniaxial tensile and (b) compressive stresses are generated on the p-type silicon and n-type silicon substrates respectively. ............................................................... 30
3-2 Schematic diagrams illustrate the carrier separation measurement for n-channel MOSFETs. Is/d measured the electron current tunneling from p-type silicon substrate. The set up for p-channel MOSFETs is similar with this. .................................................... 31
3-3 Carrier separation measurement results indicate that electron conduction process is dominant in n-channel MOSFETs (a) and hole is dominant in p-channel MOSFETs (b). ........................................................................................................................................... 32
3-4 The normalized the electron and hole tunneling current change versus the applied tensile and compressive stress on (100) wafer for n-channel MOSFETs (a) and p-channel MOSFETs (b), respectively. .................................................................................... 34
3-5 Unstressed, biaxial stressed, and uniaxial stressed Silicon constant surface at 25meV below valence band. ............................................................................................................... 43
3-6 Charge density versus applied stress for the top, bottom, and split off bands for three applied stresses. (a) uniaxial compression, (b) biaxial compression, and (c) biaxial tension. The inset shows the simplified hole valence band structure for out-of-plane direction with the corresponding effective mass. ................................................................. 44
3-7 The relative change of the tunneling currents versus applied uniaxial compression, biaxial compression, and biaxial tension, respectively. Dots are experimental data and lines are physical model.................................................................................................. 45
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3-8 Schematic band diagram and subband splitting diagrams for direct carrier tunneling process in (a) n-channel MOSFETs and (b) p-channel MOSFETs, respectively. Black (white) dots represent electrons (holes). Number of the dots represents the population density of carriers. ............................................................................................... 47
3-9 Schematic band diagram for direct electron tunneling in an n-channel MOSFET for accumulation layer (a) and inversion layer (b), respectively. ............................................. 50
3-10 The normalized the electron tunneling current change versus the applied uniaxial longitudinal tensile stress on (100) wafer for accumulation layer (a) and inversion layer (b), respectively............................................................................................................. 52
3-11 (a) The lowest subband energy level in ∆2 and ∆4 valley versus the applied uniaxial stress for both inversion and accumulation layer, where the zero of energy is taken to be the bottom of the conduction band; (b) The normalized lowest subband energy level change with the applied uniaxial stress in ∆2 and ∆4 valley for inversion and accumulation layer. ................................................................................................................ 53
3-12 Spatial distributions of the electron density in the n-channel MOSFETs for accumulation layer (a) and inversion layer (b), respectively. The inset shows the surface charge density change for the ∆2 and ∆4 valleys with the applied uniaxial tensile stress from compressive 3GPa to tensile 3GPa, i.e. -3000~3000MPa................... 55
4-1 Schematic diagram of effective field dependence of total mobility in inversion layer. Total scattering mechanism including the phonon, surface roughness and coulomb scattering. Coulomb scattering is neglected for high effective field [77]........................... 59
4-2 Measured (dots) and calculated (lines) hole mobility and normalized mobility enhancement (Inset) for (100) Si along the <110> channel direction as a function of temperature for unstressed, 20MPa, 45MPa, and 60MPa longitudinal compressive stressed p-channel MOSFETs. .............................................................................................. 62
4-3 (a) Energy contours at 25meV (red line) and 150meV (blue line) to the top band edge on the (100) surface with zero (solid line), 0.06GPa (dotted line), and 1GPa (dashed line) uniaxial compressive stress along the <110> direction. (b) Normalized conductivity effective mass reduction as a function of temperature for 20MPa, 45MPa, and 60MPa longitudinal compressive stressed p-channel MOSFETs. ................. 64
4-4 Calculated phonon-limited mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed (triangle dots) and 60MPa longitudinal uniaxial compressive stressed (square dots) p-channel MOSFETs. ................................... 66
4-5 Relative contribution by phonon-limited mobility and surface roughness limited mobility for a (100)/<110> Si p-channel MOSFET with 60MPa longitudinal uniaxial compressive stress. ................................................................................................................. 66
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4-6 Calculated surface roughness limited mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed (triangle dots) and 60MPa longitudinal uniaxial compressive stressed (square dots) p-channel MOSFETs. .............. 67
4-7 Calculated optical phonon, acoustic phonon, and surface roughness scattering rate for p-channel MOSFETs along the <110> channel direction as a function of longitudinal compressive stress at (a) 300K and (b) 87K, respectively. ............................ 68
4-8 Measured (dots) and calculated (lines) electron mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed and 60MPa longitudinal compressive stressed n-channel MOSFETs. ......................................................................... 69
4-9 Calculated phonon-limited mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed and 60MPa longitudinal tensile stressed n-channel MOSFETs. ............................................................................................................ 71
4-10 Calculated surface roughness limited mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed and 60MPa longitudinal tensile stressed n-channel MOSFETs. .............................................................................................. 71
5-1 Terraced oxide wafer with different silicon oxide thickness from 1 to 4 nm. High-k and metal gate are deposited with the same thickness. ........................................................ 74
5-2 (a) Measured capacitance–voltage curve results for a single terraced wafer with different silicon oxide thickness. (b) The flat band voltage as a function of EOT. A good linear relation is show for these devices. ..................................................................... 76
5-3 Experimental setup of four point bending jig for uniaxal stresses (a) schematic diagram (b) actually jig from side view. ............................................................................... 77
5-4 Extracted EWF for TiN gate stack with uniaxial stress (a), and biaxial stress (b). WF_D21, WF_D22, WF_D23 represent the TiN gate thickness as 10, 5, and 2nm, respectively. ............................................................................................................................ 79
5-5 Normalized EWF change for TiN gate stack with uniaxial stress (a), and biaxial stress (b). WF_D21, WF_D22, WF_D23 represent the TiN gate thickness as 10, 5, and 2nm, respectively. ........................................................................................................... 80
5-6 Schematic diagram of high-k/metal gate MOSFETs with different metal gate thickness. Higher stress in expected for MOSFETs with thinner metal gate. IL is the interfacial layer between the Silicon and HfSiO. ................................................................. 81
5-7 Diagram for Bowing measurement, where R is the calculated radius of curvature, ts is the substrate thickness, tf is the film thickness, and rsc is the scan distance. ...................... 82
5-8 Measured average stress on the wafer for MOSFETs without thermal treatment, 600C annealing, and 1035C annealing, respectively. It is clearly shown that the stress always increase for MOSFETs with thinner metal gate thickness. ..................................... 83
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5-9 Schematics of charge pumping measurement setup for an n-channel MOSFET [143]..... 84
5-10 Schematics illustration of the two level charge pumping method for an n-channel MOSFET. In this situation, base level of the gate pulse is increased and the substrate switches from strong accumulation to strong inversion. The upper curve shows the charge pumping current change with the base gate voltage level. ...................................... 84
5-11 Measured Charge pumping current on an n-channel MOSFET with 2, 5, and 10 nm TiN gate electrode. ................................................................................................................. 85
5-12 Schematic diagram for stress induced generation of donor-like interface traps between the interfacial layer and the Silicon substrate. ....................................................... 85
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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
STRAIN EFFECTS ON THE PERFORMANCE OF SILICON MOSFETS
By
Xiaodong Yang
December 2009
Chair: Scott E. Thompson Major: Electrical and Computer Engineering
Since the first integrated circuits were invented in the 1960s, semiconductor technology
has been so successful to exponentially improve the microprocessor performance during the past
half century. This amazing growth becomes more difficult as physical limits of materials are
being challenged. Strain technology is a key element in current 32nm node and is widely
believed to be used in the future 28 and 22nm technology, since the technique is compatible with
other new device structures such as high-k/metal gate, SOI, and FinFETs to deliver large drive
current. In this dissertation, strain induced gate leakage current change, mobility enhancement at
low temperature, effective work function change are comprehensively studied which could
provide a better understanding of the strain technology and its potential application for the most
advanced semiconductor devices.
A simple physical picture for stress altered gate direct tunneling current in n and p-channel
metal-oxide-semiconductor field effect transistors (MOSFETs) is presented. It is shown that the
gate electron tunneling current decreases (increases) for uniaxial tensile (compressive) stress.
The stress altered gate hole tunneling current is opposite to the electron current. These results can
be understood from the strain-altered out-of-plane effective mass, energy splitting, and carrier
population. It is indicated that longitudinal uniaxial tensile stress increases the carrier population
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in the Δ2 valley having a large out-of- plane mass which results in a decreased electron tunneling
current. Whereas, uniaxial tension enlarges the hole gate direct tunneling current by decreasing
the density of holes from top band with a larger out-of-plane mass. However, due to weak
confinement in accumulation, the normalized leakage current change is higher in accumulation
than in inversion. A self-consistent solution to the Poisson and Schrödinger’s equation
considering the strain Hamiltonian combined with the transfer matrix method are used for
modeling the tunneling process.
Hole and electron mobility is studied for strained p-channel and n-channel MOSFETs at
low temperature. Longitudinal compressive stress increased hole mobility enhancement is
observed as temperature is lowed from 300K to 87K. With a six band k•p model and finite
difference formalism, comparison with calculation suggests hole mobility is phonon-limited at
room temperatures, while it is limited by both surface roughness and phonon scattering around
87K. Strain induced mobility enhancement at low temperature arises from the reduction of the
average hole conductive effective mass due to band warping. However, surface roughness
reduction is the dominant physical mechanism for n-channel MOSFETs. Several physical models
are discussed and a reasonable modification of present model is presented.
Metal gate induced effective work function change provide a good candidate for work
function tuning which is one of the most challenge parts for the present high-k/metal gate
devices. Both external mechanical stress and process induced large stress indicated that the
effective work function always decrease with the applied stresses regardless the type of stresses.
Although the stress induced by the TiN gate strongly depends on the thermal treatment, thermal
annealing process constantly generates tension inside the gate. Bowing technique and charge
pumping method are used for stress and interface state measurement, respectively. It is indicated
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that the EWF decrease with the reduction of metal gate thickness and the interface states increase
induced donor-like charge generation is the dominant physical mechanism.
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CHAPTER 1 INTRODUCTION
Traditional CMOS limits
The first metal-oxide-semiconductor field-effect-transistor (MOSFET) and integrated
circuits (IC) were invented in the beginning of 1960s. From that time traditional semiconductor
technologies have been so successful to exponentially improve performance during the past fifty
years. This amazing growth was predicted in 1965 by Gordon Moore [1] who is the co-founder
of the largest semiconductor company in the world, Intel Corporation. However, further scaling
down of the feature size to the nanometer region becomes more difficult as physical limits of
existing structures and materials are reached. Key reasons that prevent the continuous scaling
down of current semiconductor devices are 1) static power consumption due to direct gate
tunneling and band to band tunneling [2]; 2) large source-drain series resistance in the source
and drain region [3,4]; 3) The lithography limitations; 4) the limited subthreshold slope.
With the above restrictions, possible solutions fall into two categories: 1) changes of the
present transistor structures, and 2) substitutes of new materials or modifications of current
material. Non-traditional device structures such as FinFETs, double gate MOSFETs and ultra-
thin body MOSFETs (SOI) are promising candidates. Similarly, on the new materials, high-k
materials such as Hafnium component dielectrics with metal gate materials have shown high
performance results beyond 45nm technology node [5], and are considered favorable for
continuous scaling down to 28 and 22nm.
Table 1-1 [6] summarizes these challenges, difficulties, and corresponding possible
technology options. The performance of MOSFETs is increased with better charge control,
electron/hole transportation, and less parasitic resistance/capacitance. Especially, the mobility
enhancement could improve the performance greatly for advanced MOSFETs beyond 90nm. A
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proper structure or material is required here to provide continuous mobility enhancement in order
to continue the famous Moore’s Law.
Table 1-1. Performance enhancement challenges, difficulties, and possible solutions. Source of
enhancement Parameters been changed Possible method
Charge density
1.S (subthreshold slope) 2. Qinv (inversion charge)
1. Multigate MOSFETs. 2. Low working temperature.
Electron/hole transport
1.Mobility 2. Velocity 3. Ballistic transport
1. Strained silicon. 2. High mobility materials (e.g., Ge, III-V). 3. Low working temperature.
Parasitic resistance 1.RS/D 1. Extended source and drain. 2. Lower Schottky contact.
Parasitic capacitance 1.Cj
2.CGD, CGS, CGB 1. SOI. 2. Multigate MOSFETs.
Strained Silicon
As shown in Table 1-1, Carrier transport could be improved by high mobility materials,
e.g., Germanium, which was the first material which is utilized in the modern semiconductor
devices, but silicon substituted it very quickly during the beginning of 1960s, because Silicon has
several advantages compared with Germanium. At first, Silicon can be easily oxidized as SiO2
with high quality as a insulator layer for MOSFETs. Secondly, there is tremendous Silicon
element available on the earth and it is very easy to obtain, which made Silicon an excellent
material used for high volume industry production. Wide band gap of Silicon compared with
Germanium made it easily to operate at critical conditions like high temperatures. Meanwhile,
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well established processing advantages were the dominant reasons for the use of Silicon over
other semiconductor materials like III-V materials [7].
Without sacrificing too much production cost and still maintaining performance
improvements as stated in Moore's law, strain technology is a key element in current MOSFET
technologies and is widely believed also in the future 22 nm technology node, since it can
enhance the drain current without decreasing the transistor gate length. Furthermore, the
technique is compatible with other new device structures such as multigate, SOI and high-
k/metal gate devices, with delivering large drive currents [8, 9]. For example, the advantages of
an ultra thin body MOSFET, such as the better inversion charge control of the channel by the
gate, can be combined with enhanced electron or hole mobility provided by strained Silicon.
Therefore, better understanding of strain technology is critical to improve the performance of
Silicon MOSFETs. There are normally two kind of strain were applied for the silicon devices.
Biaxial strain is evenly distributed over the whole surface, whereas the uniaxial strain is applied
along a particular direction within the transport surface which is commonly along the channel
direction or longitudinal direction.
Biaxial Strained Silicon Devices
Because the lattice constants of Silicon and Germanium are different by 4.2%, the epitaxial
layers of Silicon will be naturally biaxial tensioned as shown in Fig. 1-1. Stress, strain, band gap
and piezoresistance on SiGe technology have been widely studied since 1950s [10]. In 1975, first
Si1-xGex layers with x<0.15 were grown on Silicon surface using ultra high vacuum epitaxial
technology [11]. At the beginning, because strain destroys the original crystal structure and
cannot be avoided, it was considered as a disadvantage and people were always trying to
eliminate strain from the process. However, in 1982, it was found that strain provided an
additional choice for band structure engineering [12]. After that, MOSFETs with biaxial strain
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were fabricated [13]. To date, biaxial tensile strain has been widely investigated both
experimentally and theoretically in CMOS technology [9]. Normally, it improves the electron
mobility, but decreases the hole mobility at small stress range.
Figure 1-1. Biaxial tensile stressed Silicon on relaxed SiGe layer
Uniaxial Strained Silicon Devices
In 2002, uniaxial stress has been applied to 90nm technology node by Intel to improve the
mobility without substantially increased manufacturing complexity [14]. In order to achieve
mobility enhancement, longitudinal compressive stress for p-channel MOSFETs and longitudinal
tensile stress for n-channel MOSFETs are the most effective ones. Usually, uniaxial strain is
Figure 1-2. TEM micrographs of p- and n-channel MOSFETs with 45-nm gate length.
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introduced from the source and train using SiGe for p-channel MOSFETs and a nitride capping
layer with a large tensile stress for n-channel MOSFETs. Transmission electron micrographs
(TEMs) of p-channel and n-channel MOSFETs are shown in Fig. 1-2.
Based on the performance from both biaxial and uniaxial strained MOSFETs, industry
prefer the uniaxial strain because: 1) uniaxial stress enhances hole mobility at both low stress and
high electric field due to the large band warping of the valence band induced conductivity
effective mass reduction [15]; 2) uniaxial stress could be used to enhance the mobility of
nanoscale short channel devices, whereas biaxial stress is becoming more and more difficult to
apply beyond 90nm technology node; 3) process induced uniaxial stress causes much smaller
threshold voltage change which is critical for high-k/metal gate devices[8]. Based on the above
advantages for uniaxial stress, the industry is now looking at other uniaxial stressors except the
two method mentioned above. For instance, Yang et al. Reported a high performance CMOS
devices, in which nitride contact layers were used as dual stress layers to induce tensile and
compressive stress simultaneously. This dual stress layers technology results in about 10% and
30% effective mobility enhancement for both electrons and holes, respectively [16].
Motivation
Based on the above discussion, we noticed that strain technology has been widely used in
the semiconductor industry and is very promising in the future technology node. For better
utilizing of strain technology, physical mechanism understanding is inevitable for the advance
MOSFET devices.
Although the strain altered MOSFETs in-plane conductivity mass and its effect on
mobility has been studied[17~20], much less understood is how strain alters the out-of-plane
conductivity effective mass and the band offset between Si and SiO2, both of which will affect
the direct tunneling gate current which dominates in ultra-thin oxides. For these reasons, it is
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important to understand how strain alters the MOSFET gate current from inversion layers.
Meanwhile, the direct tunneling process of electrically programmable read only memories
(EPROMs) [21], and the gate tunneling current occurring in memory cells [22,23] make the
understanding of the tunneling process in the accumulation layer increasingly important.
Large mobility enhancement has been experimentally achieved for holes by longitudinal
compression at normal operation condition. Further study of hole mobility at low temperature
can provide more physical insight on strain-enhanced performance of Silicon MOSFETs. To
date, much less understood is how strain alters the phonon scattering, surface roughness
scattering, and conductivity effective mass for p-channel MOSFETs at low temperature. While
enormous studies has been placed on the temperature effect on n-channel strained MOSFETs
[24, 25]. However, a big discrepancy still exists between experimental and theoretical
expectations [26~29] for n-channel MOSFETs due to less understanding about surface roughness
change with the applied stress.
Strain induced work function change provides another effective candidates for threshold
voltage tuning. Meanwhile, considering the mobility degradation for high-k/metal gate devices,
the compatibility between the strain technology and promising insulator substitutes with high
dielectric constant is critical, especially beyond 45nm. Both process and external mechanical
bending induced stresses could provide a deep understanding for strain effects on high-k/metal
gate Silicon devices.
Outline of the Dissertation
This research focuses on the physics underlying the strain effects on leakage current,
mobility, and metal gate work function for Silicon MOSFETs. Chapter 2 provides a description
of the strain effect on silicon band structure. Chapter 3 presents a detailed analysis for strain
induced leakage current change for n and p-channel MOSFETs in inversion layers and
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accumulation layers. In Chapter 4, strain induced mobility change for p-channel and n-channel
MOSFETs at low temperatures were discussed. Strain induced effective work function change
for high-k/metal gate Silicon device are covered in Chapter 5. Finally, Chapter 6 provides some
possible future study for strain and low temperature effects on novel devices, e.g., FinFETs, SOI.
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CHAPTER 2 STRAIN EFFECTS ON BULK SILICON BAND STRUCTURE
The band structure provides the information about the states of energy and the electronic
dispersion relation under a specific condition. Lots of studies have shown that if the band
structure of the material is modified, mechanical and electrical properties of the material will be
also changed, such as effective mass and corresponding mobility [30]. Band structure analysis
could provide more details about strain effects on electron/hole transport property. For instance,
strain induced lattice constant change will induce band warping in both conduction band and
valence band. However, the effective mass change is much more important for holes in valence
band due to strong correlation between six subbands.
Stress and Strain
Because of the elasticity of the materials, the deformation of structure under the application
of an external force could be recovered back to their original shape after the force is removed.
The external applied force is known as stress, while the amount of deformation is named the
strain.
The stress at one particular position may be considered as forces F put on a very small area
A. By making the area infinitesimally smaller, the stress vector σ is expressed as the limit [31]
0
limA
FA
σ→
= (2.1)
From Figure 2-1, we could understand that the force acting on a small area can be
decomposed into a force within the small area, a shear component, and a force which is
perpendicular to the small area, a normal component. The shear stress can be further divided into
two orthogonal force components. Totally, there are three total stress components on each small
area.
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Figure 2-1. Nine stress components acting on a small cube.
Thus, the stress on a small element can be expressed by nine stress components, i.e., three
normal and six shear components. These components compose the stress tensor as
xx xy xz
yx yy yz
zx zy zz
σ σ σσ σ σ σ
σ σ σ
=
, (2.2)
where the shear stress components across the diagonal are identical due to static equilibrium of
materials
, ,xy yx yz zy xz zxσ σ σ σ σ σ= = = . (2.3)
Similarly as stress, strain could also be expressed with a symmetric tensor ε
xx xy xz
yx yy yz
zx zy zz
ε ε εε ε ε ε
ε ε ε
=
. (2.4)
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The relation between stress and strain was first expressed by Hook’s law, which concluded
that deformation of a material shape is linearly related to the outside force applied. The Hook’s
law in matrix form for crystals with cubic symmetry is
11 12 12
12 11 12
12 12 11
44
44
44
0 0 00 0 00 0 0
20 0 0 0 020 0 0 0 020 0 0 0 0
xx xx
yy yy
zz zz
yz yz
xz xz
xy xy
C C CC C CC C C
CC
C
σ εσ εσ εσ εσ εσ ε
= , (2.5)
where Cij is the independent element of the elastic tensor matrix. Normally, people interested in
the strain value with a certain stress applied. The strain components could be expressed by
inverted Hook's law and using the compliance coefficients Sij as
11 12 12
12 11 12
12 12 11
44
44
44
0 0 00 0 00 0 0
2 0 0 0 0 02 0 0 0 0 02 0 0 0 0 0
xx xx
yy yy
zz zz
yz yz
xz xz
xy xy
S S SS S SS S S
SS
S
ε σε σε σε σε σε σ
= . (2.6)
The three independent compliance coefficients can be expressed as
11 1211 2 2
11 11 12 12
1212 2 2
11 11 12 12
4444
,2
,2
1 .
C CSC C C C
CSC C C C
SC
+=
+ −
= −+ −
=
(2.7)
The compliance coefficients and Cij for Si and Ge are listed in Table 2-1.
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Table 2-1. Independent component of the elastic tensor in GPa and elastic compliance constants in 10-12m2/N.
C11 C12 C44 S11 S12 S44
Si 166.0 64.0 79.6 -2.13 -7.67 12.6
Ge 126.0 44.0 67.0 -2.50 9.69 14.8
For <110> longitudinal stress, the strain tensor could be expressed as
11 12 44
44 11 12
12
( ) / 2 / 4 0/ 4 ( ) / 2 0
0 0
S S SS S S
Sε σ
+ = + . (2.8)
For biaxial stress, the strain tensor could be expressed as
11 12
11 12
12
0 00 00 0 2
S SS S
Sε σ
+ = + . (2.9)
Strain Effect on Conduction Band
For n-channel MOSFETs, the band structure close to the conduction band edge can be
approximately expressed by parabolic energy dispersion. For the momentum at the bottom of the
conduction band min 02 / (0,0,0.85)k aπ= , the energy dispersion is
2 2 22 2
min( )( )( )
2 2x yz
l t
k kk kE km m
+−= +
, (2.10)
where ml=0.92m0 is the longitudinal mass and mt=0.19m0 is the transverse mass of Silicon. Due
to the point symmetry of the fcc lattice structure of Silicon, the six ellipsoidal energy surfaces are
equivalent and generated. Consequently, the conduction band is consists of six equal valleys (Δ6)
with the same energy as shown in Fig. 2-2 (a). Stress longitudinal to the <110> channel or
26
vertical electrical field from the applied gate to source voltage removes the degeneracy between
the four in-plane valleys (Δ4) and the two out-of-plane valleys (Δ2) due to the energy splitting,
as shown in Fig. 2-2 (b).
Kz
Kx
Ky
Kz
Ky
Kx
Δ2
Δ2
Δ4
Δ4
Δ4
Δ4
(a) (b)
Δ6
Δ6
Δ6
Δ6Δ6
Δ6
Unstrained Bulk Strained Bulk
Δ2
Δ4Δ6
Figure 2-2. (a) Conduction band structure of silicon in the unstrained case. Ellipsoids of constant electron energy in reciprocal k space, each corresponding to one of the degenerate conduction band valleys. (b) A longitudinal uniaxial tensile stress in the (001) silicon place removes the degeneracy between the four in-plane valleys (Δ4) and the two out-of-plane valleys (Δ2).
Strain Effect on Valence Band
For holes, the valence-band structure of silicon is much more complicated than the
conduction band. For unstrained silicon at room temperature, holes occupy the top two subbands.
The unstrained constant energy surfaces (E=25meV) for the top and bottom bands are shown in
Fig. 2-3 (a). With the application of strain, the light and heavy hole bands, which is normally
27
used, lose their meaning with energy levels and become mixtures of two bands due to band
warping and band shifting. Correspondingly, we name the bands the top and the bottom band.
The warped bands diagram and the corresponding 3D constant energy surfaces are shown in Fig.
2-3 (b) and (c) for the applied longitudinal compressive stress and biaxial tensile stress,
respectively [26, 32], in which strain remove the degeneracy and reduce the coupling between
the top band and the bottom band. It is observed that the out-of-plane effective mass of the top
Top Band
Bottom Band
E
K
(a)
Top Band
Bottom Band
K
E
(b)
Top Band
Bottom Band
K
E
(c)
Unstrained Uniaxial Strained Biaxial Strained
<001> <110>
Kx
KyKz
<001> <110>
Figure 2-3. Valence band and constant energy surfaces (E=25meV) in k space for the top band
and bottom band in the case of (a) unstressed silicon, (b) longitudinal compressive stress, and (c) biaxial tensile stress.
band is larger than that of the bottom band for the longitudinal compressive stress while the
opposite results for biaxial tensile stress as see in Fig. 2-3 (b) and (c). However, the much
smaller conductivity effective mass along the <110> direction of the top band is shown in Fig. 2-
28
3 (b) compared with the effective mass indicated in the unstrained situation. Both out-of-plane
and in-plane effective mass change are very important to understand the physical mechanism of
strain induced performance change for Silicon MOSFETs.
29
CHAPTER 3 STRAIN INDUCED LEAKAGE CURENT CHANGE
The rapid scaling down of MOSFETs drives increasing device performance and fast
growth of the information technology innovation. The feature size of the technology node has
been reduced to the nanometer scale during the past fifty years and fast gate oxide thickness
scaling has resulted in a ~1nm physical oxide [33] which already reaches the gate direct
tunneling limit for SiO2. Strained silicon is being introduced to improve net transistors
performance for MOSFETs beyond 90nm technology [14]. This chapter explains the physical
mechanism for strain altered gate leakage current in both n-channel and p-channel MOSFETs
under inversion or accumulation operation regime.
There are several process techniques to introduce uniaxial stress into the silicon
underlayer: a tensile or compressive capping layer over a MOSFET [34, 35], high stress shallow
trench isolation (STI) fill [36], or heteroepitaxy in the source and drain of nanoscale transistors
[37]. For this work, a 4-point bending jig is used to apply uniaxial mechanical stress which is
longitudinal or transverse to the <110> channel on a (100) wafer silicon as shown in Fig. 3-1 [15,
38, 39]. The external mechanical bending method is a very good candidate to investigate the
strain effects on the performance of MOSFETs. The external bending jig excludes other process
induced effects besides stress, like interface traps, nitrogen diffusion, annealing temperature
effects, etc. These undesirable effects also contribute a lot to the performance change of
MOSFETs and they are very hard to decouple from the strain effect for the process induced
stress case.
The device samples used are from Intel 90nm technologies and consist of heavily doped
poly-silicon gates, 1.3nm physical thickness SiO2 gate dielectrics, and ~5×1017cm-3 substrate
30
doping. The gate tunneling current is measured with the drain, source, and body all tied to
ground using a Keithley 4200 DC semiconductor characterization system.
(a)
(b)
Tension
Compression
Figure 3-1. The four point bending jig used to apply uniaxial stress to the substrate. In this picture, (a) uniaxial tensile and (b) compressive stresses are generated on the p-type silicon and n-type silicon substrates respectively.
Leakage Current Change in Inversion Regime
For direct tunneling in MOSFETs, there are three major mechanisms: (a) electron
tunneling from conduction band (ECB); (b) electron tunneling from valence band (EVB); and (c)
holes tunneling from valence band (HVB). In order to determine the dominant tunneling
mechanism, sample wafers were measured by carrier separation method [40]. Fig. 3-2 shows the
experimental set up for n-channel MOSFETs, in which the n+ polysilicon gate is positively
biased, while the p-type silicon substrate and n-type source/drain are grounded. Electrons
tunneling from the inverted silicon substrate to the polysilicon gate is measured by the
source/drain current (Is/d). Holes are collected by the substrate current (Isub). The gate tunneling
31
current (Ig) is measured at 1.0V gate bias. For p-channel MOSFETs, it is the exact same setup
with 1.0V negative gate bias.
A
N+ N+
P-Substrate
N+ Poly
A
A Isub (holes)
Is/d (electrons)
Ig (electrons)
Vg>0
electrons
Figure 3-2. Schematic diagrams illustrate the carrier separation measurement for n-channel MOSFETs. Is/d measured the electron current tunneling from p-type silicon substrate. The set up for p-channel MOSFETs is similar with this.
Fig. 3-3 shows the measured results, in which the Ig is dominated by Is/d for both n and p-
channel MOSFETs. The results show that ECB tunneling dominates in the inversion regime in n-
channel MOSFETs [41]. In contrast, HVB dominates the gate leakage of the inverted p-channel
MOSFETs in the bias range Vg<1.0V [12]. In all ECB cases, electrons can tunnel through the
relatively smaller 3.15eV barrier rather easily than holes with 4.50V barrier.
The experimental results for normalized the gate tunneling current changes versus the
applied uniaxial compression (negative stress) and tension (positive stress) is shown for n-
channel MOSFETs in Fig. 3-4 (a) and p-channel MOSFETs in Fig. 3-4 (b). The gate current
32
0.0 0.2 0.4 0.6 0.8 1.0
10-12
10-10
10-8
10-6
10-4
Ig (electrons)
Isub (holes)
Curr
ent (
A)
Vg (V)
Is/d (electrons)
N-MOSFET
(a)
0.0 -0.2 -0.4 -0.6 -0.8 -1.0
10-13
10-11
10-9
10-7
10-5
Ig (holes)
P-MOSFET
Curr
ent (
A)
Vg (V)
Is/d (holes)
Isub (electrons)
(b)
Figure 3-3. Carrier separation measurement results indicate that electron conduction process is dominant in n-channel MOSFETs (a) and hole is dominant in p-channel MOSFETs (b).
33
decreases/increases with tensile/compressive stress for electrons. However, the feature of the
hole currents are opposite to the electron currents, which are consistent with Zhao’s recent
results [42]. Because the most work on strained silicon during the past twenty years were focused
on biaxial stress [43], we also show gate tunneling currents results for p-channel MOSFETs with
applied biaxial stress compared with uniaxial stress in Fig. 3-4 (b).
Strain induced gate tunneling leakage current change can be understood from the strain-
altered out-of-plane effective mass, subbands splitting, and carrier repopulation. The direct
tunneling current density usually is expressed as a sum of the tunneling current contributions of
the total subbands
nG
n n
NJ qτ
= ∑ , (3.1)
where Nn is the inversion charge population for the nth subband, q is the electronic charge, and τn
is the corresponding lifetime of the nth subband which depends on the out-of-plane effective
mass and relative tunneling barrier height.
Quantum Mechanical Model for n-Channel MOSFETs
The main effect of strain on electron band structure in silicon comes from the conduction
band splitting. Longitudinal tensile strain causes the six-fold degenerated valleys in unstrained
silicon to split into two different valleys. The group with lower energy is the two-fold
degenerated 2∆ valley, whose longitudinal effective conductivity mass, ml, is perpendicular to
the electron channel surface and the transverse effective conductivity mass, mt, is parallel with
the surface. The other group, the four-fold degenerated 4∆ valley with higher energy, has a mt
normal to the surface [26]. A full subband structure solution of the silicon inversion layer
involves a self-consistent numerical solution of the Poisson’s and Schrödinger’s equations [44].
34
-300 -200 -100 0 100 200 300-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
longitudinal stress, Zhao 2005
N-MOSFET
∆JG/J
G (%
)
Stress (MPa)
longitudinal stress, this work
(a)
-300 -200 -100 0 100 200 300-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
transverse stress, this work
longitudinal stress, this work
biaxial stress, this work
longituidnal stress , Zhao 2005
P-MOSFET
∆JG/J
G (%
)
Stress (MPa)
(b)
Figure 3-4. The normalized the electron and hole tunneling current change versus the applied
tensile and compressive stress on (100) wafer for n-channel MOSFETs (a) and p-channel MOSFETs (b), respectively.
35
A. Self-consistent solution of Schrödinger and Poisson equations
In the framework of the effective mass approximation, the electron nth eigenfunctions Ψn
and the nth subband energy levels En are derived from the time independent Schrödinger equation
for a particular electrostatic potential V(x),
2 2
* 2 ( ) ( ) ( ),2 strain n n n
n
d H qV z z E zm dz
− + + Ψ = Ψ
(3.2)
where *nm is the out-of-plane effective mass associated with the electron motion
perpendicular to the surface, is the reduced Planck constant, strainH is the strain Hamiltonian,
and q is the electron charge. For a (100) crystal of silicon, the out-of-plane effective mass for the
2∆ valley and 4∆ valley are *2 00.92m m∆ = and *
4 00.19m m∆ = , respectively, where 0m is the
mass for a free electron. In the oxide, an isotropic effective mass *00.5OXm m= is used here
[45]. To obtain the strain Hamiltonian, the strain tensor is employed according to the
deformation potential theory as in Eq. 2.8 [46, 47]. In general, the strain induced shift of the
conduction band edge has a hydrostatic and a shear component. These shifts are conventionally
expressed in terms of the deformation potentials, Ξd and Ξu, respectively,
, 2 33 221 2( ) ( ) ( )3 3strain d u ij uH Tr ε ε ε∆ = Ξ + Ξ + Ξ − , (3.3)
, 4 33 221 1( ) ( ) ( )3 3strain d u ij uH Tr ε ε ε∆ = Ξ + Ξ − Ξ − , (3.4)
where Hstrain,∆2 and Hstrain,∆4 are the strain Hamiltonians for the ∆ 2 and ∆4 valleys, respectively.
For the shear deformation potential, Ξu, used to calculate energy level splitting is well known
with good accuracy from piezoresistance measurements and extracted to be 9.16eV [48].
However, the hydrostatic deformation potential, Ξd, is difficult to directly measure using the
36
conventional optical techniques. As a result, a very wide range of values even with opposite
signs have been reported (1.13 to -10.7eV) [49]. According to our previous measurement results
based on the gate leakage current change for n-channel MOSFETs, Ξd is extracted to be 1.0±
0.1eV [39] which used in here for numerical simulation.
Once the strain Hamiltonian has been identified, the simulation of the electron density is
obtained by adding the population of each subband in each valley. The electron concentration in
the quantum well is given by,
*
22( ) ln[1 exp( / )] ( ) ,d B
F n B nn
m k Tn z E E k T zπ
= + − × Ψ∑
(3.5)
where T is the absolute temperature, kB is the Boltzmann constant, , and EF is the Fermi energy
level. The DOS, *dm , for the 2∆ and 4∆ valleys are *
, 2 00.19dm m∆ = and *, 4 00.417dm m∆ = ,
respectively The electrostatic potential ( )V z in Eq. (3.2) is self-consistently determined using
the total charge density from Poisson’s equation [20],
2
2 ( ) [ ( ) ( ) ( ) ( )],d aSi
d qV z p z n z N z N zdx ε
+ −− = − + − (3.6)
where Siε is the permittivity of silicon, ( )p z is the hole density, ( )n z is the electron density,
( )dN z+ is the dopant concentration, ( )aN z− is the accepter concentration. For strong inversion
case in n-channel MOSFETs, ( )n z and ( )aN z− are dominant. Based on the method of finite
differences, carrier population and the subband energy in the inversion layer were obtained by
the self-consistent solution.
B. Tunneling current
To compute the transmission probability, a simple analytical method based on the WKB
approximation is normally used [50~52] and is pretty accurate for traditional MOSFETs with
37
thick oxide layer. The WKB approximation is only valid when the change of wave vector is
much greater than the particle wave length. In other words, WKB approximation accuracy
diminishes for ultra thin and low barriers [53]. Although modified WKB has been used for
devices with ultra thin oxide layers [54, 55], empirical parameters are required for this
approximation, e.g., group velocity of electrons leaving the oxide layer which ideally should be
obtained from the transmission probability solution.
Another method for solving the tunneling process is the transfer matrix method [56~58].
Any barrier shape is suitable for transfer matrix method and there is no need for other empirical
parameters. Transfer matrix method is an ideal candidate for advanced MOSFETs with ultra thin
oxide layer around 1nm. To apply this approach, the tunneling barrier is separated into many
small rectangular batters, and assumes the finite quantum well is restricted in the region [0, L].
The potential is zero at z<0 or z>L. If we divide the region into N (N>>1) segments, the
modulation potential may be considered as a constant in each part. Thus, the plane wave
functions can be expressed as
( ) ( )
( ) ( )
, 0,
( ) , ,
( 1, 2, , ), 0 ,j j
ik z ik z
ik z L ik z L
ik z jd k z jdj j
c e c e zz c e c e z L
c e c e j N z L
− −
+ +
−− −
− − −+ +
− − −
+ <Φ = + >
+ = ≤ ≤
(3.7)
where 22 ykEkk −== +− ， ( ) ( )22 ( ) ( )j j y jk E V z k A z= − − + ( jz jd= ). According to the
continuity of the wave function and the corresponding derivatives at z=0 and z=L,
1
11 1
cos( ) sin( )
sin( ) cos( )
cos( ) sin( )( ) ,
sin( ) cos( )
N N
N NN N
N
j
k d i k dc c
ik kk d k dc ck k
k d i k dc c
M j ik kk d k d c ck k
+ +
+ ++ +
− −−− −
− −− −= − −
+ = −
+ • −
∏
（3.8）
38
where
=
++
)cos()sin(
)sin()cos()(
11
dkkk
dkkik
dkidkjM
jj
jj
j
j
jj
.
Eq. 3.8 reduces to a simpler form:
−+
=
−+
−−
−−
++
++
cccc
mmmm
cccc
2221
1211． （3.9）
Noting that there are only transmission waves in the absence of reflected waves when z L< , that
is +c =0, we obtain
22111221
22211211
mmmmmmmm
cc
−−+−−+
=−
− ． （3.10）
Thus, the transmission coefficient is given by [59]
2 2
11 12 21 22
12 21 11 22
( ) 1 1 1c m m m mT E Rc m m m m−
−
+ − −= − = − = −
+ − −． （3.11）
We assumed here that the transmission probability depends only on the momentum which
is vertical to the interface. Furthermore, the lifetime of an nth subband state is derived by [60],
*
0
1 ( )2 /[ ( )]n
n nz
n n n C
T Em E E z dzτ
=−∫
, (3.12)
where Ec(z) is the edge of the conduction band and zn is the classical turning point for the nth sub-
state. Combining Eq. 3.5 to Eq. 3.12 and the tunneling current can be given by a sum of the
tunneling current contributions from n subbands
, 2 , 4
, 2 , 4
( )n nG
n n n
N NJ q
τ τ∆ ∆
∆ ∆
= +∑ , (3.13)
where , 2nN ∆ and , 4nN ∆ are the nth subband inversion charge density for 2∆ and 4∆ valley,
39
respectively, and , 2nτ ∆ and , 4nτ ∆ are the corresponding lifetime of the nth subband.
Quantum Mechanical Model for p-Channel MOSFETs
In this work, the strain-induced Silicon subband energy level change, valence band
warping, and band to band repopulation among the top three valence subbands is calculated by
the k•p method because: 1) this numerical solution is around the gamma point where only a very
small set of wave vectors are required; 2) it is based on Luttinger Hamiltonian which deals with
band structures precisely. The tight banding method and pseudopotential method have to treat the
strained silicon band structure as a much more sophisticated system.
Based on the theory of Luttinger [20], the valence band structure of strained Silicon is
expressed by a 6×6 Hamiltonian in the envelope-function space. In the inversion layer for n-type
Silicon, holes are restricted in a quantum well which is formed by the oxide and Silicon interface
and substrate surface potential and it is very similar as electron for n-channel MOSFETs, in
which a two dimensional treatment is required. The charge density and subband energy levels are
calculated also by a self-consistent solution of the coupled Schrödinger’s and Poisson’s
equations. Based on the effective mass approximation, the nth subband energy level En and the
corresponding eigenfunctions Ψn are given by the time independent Schrödinger equation for a
given electrostatic potential VH(x),
Luttinger ( ) ( ) ( ),H n n nH qV x x E x + Ψ = Ψ (3.14)
where, LuttingerH is the Luttinger Hamiltonian which determines the band shift and repopulation
between subbands. For a MOSFET in the z-direction, )(zVH is calculated from the total charge
density,
2
2 ( ) [ ( ) ( )],H dSi
d qV z p z N zdx ε
+− = + (3.15)
40
where ( )n z and ( )aN z− neglected due to strong inversion which is opposite with the case in
Eq. 3.6 for n-channel MOSFETs.
Because the split-off energy (0.044eV) is much smaller than the band gap for Silicon
(1.12eV), all valence bands can be described by six subbands without considering the influences
from conduction bands [61]. Using the basis of the angular momentums, six subbands
considering the spin effect can be expressed as |3/2,3/2> , |3/2,1/2>, |3/2,-1/2>, |3/2,-3/2>,
|1/2,1/2>, and |1/2,-1/2>, where the total angular momentum and the angular momentum for a
specific axis are represented by the first and the second number, respectively. The corresponding
Hamiltonian for the top six bands with spin effect, i.e., heavy-hole bands (HH), light hole bands
(LH), and split-off bands (SO) is expressed as [62]
10 22
30 22
30 22
10 22
1 32 2 022
3 12 2 02 2
P Q S R S R
S P Q R R S
R P Q S S Q
R S P Q R S
S Q S R P
R S Q S P
+
+ +
+ + + +
+
+ +
+ −
− − −
−
+ − − − − − + ∆
− + ∆
, (3.16)
where
22 2 2
10
, ,, ,
( ),2
k k
k k
k x y z
P P P Q Q QR R R S S S
P k k km
ε ε
ε ε
γ
= + = += + = +
= + +
41
22 2 2
20
22 2
2 30
2
30
( 2 ),2
3 ( ) 2 ,(3.17)2
2 3 ( ) ,2
( ),
( 2 ),23 ( ) ,
2( ),
k x y z
k x y x y
k x y z
v xx yy zz
xx yy zz
xx yy xy
zx yz
Q k k km
R k k i k km
S k ik km
P abQ
R b id
S d i
ε
ε
ε
ε
γ
γ γ
γ
ε ε ε
ε ε ε
ε ε ε
ε ε
= + −
= − − +
= −
= − + +
= − + −
= − −
= − −
where the wave vector k is interpreted as a differential operator i− ∇ ; ijε is the symmetric strain
tensor; 1γ , 2γ , and 3γ are the Luttinger parameters; av, b, and d are deformation potentials; ∆ is
the split-off energy which is 44meV. The Luttinger constants and deformation potentials of
Silicon and Geminium are listed in Table 3-1.
Table 3-1. Luttinger-Kohn parameters, deformation potentials and split-off energy for Si and Ge. 1γ 2γ 3γ av (eV) b (eV) d (eV) ∆ (eV)
Si 4.22 0.39 1.44 2.46 -2.58 -14.3 0.044
Ge 13.4 4.24 5.69 1.24 -2.9 -5.3 0.296
Fig. 3-5 shows the 3D equal energy surface of Silicon top two valence bands with no
stress, 1GPa biaxial tensile stress, and 1 GPa longitudinal compressive stress obtained by the 6×6
Luttinger Hamiltonian [8]. The top band is the most important subband in which most holes
occupied due to the lowest energy level close to the oxide/substrate interface. It is shown in Fig.
42
3-5, both biaxial and uniaixal stress decreases the effective mass along the channel direction.
However, the out-of-plane effective mass change is much smaller compared with the in-plane
conductivity effective mass change for all different kind of stresses.
Further study for band-to-band repopulation is necessary to fully understand the average
out-of-plane effective mass modification impact on the gate direct tunneling leakage current
change. Fig. 3-6 plots the charge density in the top three bands versus stress on (100) wafer at 1V
gate bias. Also listed in Fig. 3-6 is the out-of-plane effective mass at the gamma point for the
three top subbands: 0.29 0m (0.27 0m ), 0.20 0m (0.22 0m ), and 0.24 0m (0.23 0m ) respectively for
biaxial (uniaxial) stress on (100) wafers. The out-of-plane masses in the top three subbands are
observed to be fairly constant at the Γ point for about 500MPa of stress. However, the average
out-of-plane effective mass increases with the applied compression due to the charge density
increase in the top band as shown in Fig. 3-6. This out-of-plane effective mass change will
increase the tunneling barrier height for holes and decrease the corresponding gate direct
tunneling leakage current.
With the electron charge density obtained from the k•p method, the lifetime of an nth
subband state in the inversion layer is given by
*
,
( )12 /[ ]
n n
n n V n
T Em E E dzτ
⊥
=−∫
, (3.18)
where Ev is the top of the valence band. The tunneling current can be readily obtained as a sum
of the tunneling current contributions of the n subbands which is similar as Eq. 3.13. The
simulated change of gate current is compared with the experimental data in Fig. 3-7 which
showing a good agreement. Deformation potential av describes the shift in the energy levels
while b and d indicating the splitting between the subbands. Values of av, b, and d used are 2.46
43
Figure 3-5. Unstressed, biaxial stressed, and uniaxial stressed Silicon constant surface at 25meV below valence band.
[63], -2.58 [64], and -14.3, respectively. The values chosen for av and b are commonly used [65]
and similar values provide good fits to the strain-induced MOSFET threshold voltage shift [66].
The modeled results primarily depend on b and d and are only weakly affected by av. The value
of d used in this work is larger than reported elsewhere [65] and is needed to fit the magnitude of
the tunneling current decrease for compressive uniaxial stress (d has no effect on the modeled
biaxial stress).
Qualitative Analysis of Tunneling Current Change
A qualitative schematic of the direct electron or hole tunneling process and subband
splitting for n-channel and p-channel MOSFET are shown in Fig. 3-8, where EC, EV, and EF are
the silicon conduction band edge, valence band edge, and Fermi energy level, respectively. EΔ2
44
0 100 200 3000.0
3.0x1012
6.0x1012
9.0x1012
Split Off Band
Bottom Band
Char
ge D
ensit
y (c
m-2)
Stress (MPa)
E
0.24m0
0.20m0
0.29m0
K
Top Band
Biaxial Tension (c)
0 100 200 3000.0
3.0x1012
6.0x1012
9.0x1012
Split Off Band
Bottom Band
Char
ge D
ensit
y (c
m-2)
E
0.24m0
0.20m0
0.29m0
K
(b)
Top Band
Biaxial Compression
0 100 200 3000.0
4.0x1012
8.0x1012
1.2x1013
Split Off Band
Bottom Band
Top Band
Char
ge D
ensit
y (c
m-2)
E
0.23m0
0.22m0
0.27m0
K
Uniaxial Compression (a)
Figure 3-6. Charge density versus applied stress for the top, bottom, and split off bands for three applied stresses. (a) uniaxial compression, (b) biaxial compression, and (c) biaxial tension. The inset shows the simplified hole valence band structure for out-of-plane direction with the corresponding effective mass.
45
0 50 100 150 200 250 300
-0.06
-0.04
-0.02
0.00
0.02
0.04
Biaxial Tension Biaxial Compression Uniaxial Compression Model
∆J/J
0
Stress (MPa)
Figure 3-7. The relative change of the tunneling currents versus applied uniaxial compression, biaxial compression, and biaxial tension, respectively. Dots are experimental data and lines are physical model.
and EΔ4 are the energy levels for the Δ2 and Δ4 valley, and ΦB,Δ2 andΦB,Δ4 are the corresponding
tunneling barriers at the oxide/substrate interface for n-channel MOSFETs. ETop and EBottom are
the energy levels of the top and bottom band in the quantized inversion layer for p-channel
MOSFETs. ΦB,Top and ΦB,Bottom is the tunneling barrier for the holes from the top band and
bottom band, respectively. Black (white) dots represent electrons (holes), in which number of the
dots represents the population density of carriers. Since the subband splitting is large for strong
inversion situation, nearly all the electrons and holes occupy the ground state for the different
valley, i.e., EΔ2 and EΔ4 (ETop and EBottom) for n (p)-channel MOSFETs as shown in Fig. 3-8.
Strain alters the subband energy levels and hence the gate tunneling process. For example,
tensile stresses increase the electron population in the Δ2 valley and increase barrier height with
tensile stress, as shown in Fig. 3-8 (a), both of which increase τn. Similarly, in Fig. 3-8 (b),
46
compressive stresses increase the hole tunneling barrier height and corresponding life time.
According to Eq. 3.1, due to the increase of τn, the gate leakage current is observed to decrease
for the types of stresses adopted by the industry, i.e., tensile and compressive stress for n and p-
channel MOSFETs, respectively.
From the band structures for bulk silicon, we can further understand the strain altered gate
leakage. The conduction band is comprised of six degenerate valleys (Δ6) with the equal energy
as shown in Fig. 2-2 (a). Stresses longitudinal to the <110> channel or effective vertical
electrical field removes the degeneracy between the four in-plane valleys (Δ4) and the two out-
of-plane valleys (Δ2) due to the energy splitting, as shown in Fig. 2-2 (b). The lower energy of
the Δ2 valleys and larger effective mass (0.98m0) in Fig 3-8 (a) both decrease the gate leakage
current for n-channel MOSFETs. For holes, the valence-band structure of silicon is much more
complex than the conduction-band. For unstrained silicon at room temperature, most holes
occupy the top two bands. The unstrained constant energy surfaces (E=25meV) for the top two
bands are shown in Fig. 2-2 (a). It is observed that the out-of-plane effective mass of the top
band is smaller than that of the bottom band for the biaxial tensile stress while the opposite
results for uniaxial compressive stress as see in Fig. 2-2 (b) and (c). This results in stress altered
gate leakage current for p-channel MOSFETs to increase for biaxial tensile stress but to decrease
for uniaxial compressive stress.
Leakage Current Change in Accumulation Regime for n-Channel MOSFETs
Strain induced changes in the gate tunneling current can reduce the leakage current for
performance enhancing uniaxial strain on polysilicon gate n-channel MOSFETs [38,39,67] Since
the tunneling probability depend on the effective mass, the strain dependence of the gate
tunneling current can also provide an estimate for the change in the out-of-plane effective mass,
which is of technological importance since it determines whether the mobility enhancement is
47
E∆2 EF
EC
EV
Poly-gate Oxide Si-channel
4,∆Bφ2,∆Bφ
E∆4
Unstrained Tensile Strained2E∆
4E∆
(a)
0.98m0
0.19m0
increase
Repopulation
Δ4
Δ2
2,∆Bφ
EBottom
ETopEF
EC
EV
,B Topφ
Poly-gate Oxide Si-channel
,B Bottomφ
Unstrained Compressive Strained
Top
Bottom
(b)
TopE
BottomE
0.27m0
0.22m0
increase
Repopulation
,B Topφ
Figure 3-8. Schematic band diagram and subband splitting diagrams for direct carrier tunneling process in (a) n-channel MOSFETs and (b) p-channel MOSFETs, respectively. Black (white) dots represent electrons (holes). Number of the dots represents the population density of carriers.
48
maintained or lost at high vertical field. The strain effect and 2D-inversion layer confinement
sub-band splitting are additive for uniaxial stress, in which mobility enhancement maintained at
high vertical fields, but subtractive for biaxial stress, in which mobility enhancement lost in the
inversion layer[8,19]. Recently, strain-induced changes in the gate tunneling current for p-
channel MOSFETs in inversion has been measured [38]. However, the tunneling current for n-
channel MOSFETs in accumulation is not well characterized. The leakage current from gates for
the erase mode of electrically erasable programmable read only memories (EPROMs) [21], and
the gate leakage current occurring in memory cells [22,23] make the understanding and modeling
of the tunneling process in the accumulation layer increasingly important. In this chapter, we also
experimentally and theoretically investigate the strain-induced leakage current change for n-
channel MOSFETs in both accumulation and inversion for externally applied uniaxial tensile
stress for polysilicon gate, using a four-point bending apparatus and self-consistent solution to
Schrödinger and Poisson equation and Transfer Matrix method mentioned in the above section.
A qualitative schematic of the direct electron tunneling process for a n-channel MOSFET
is shown in Fig. 3-9 for electron tunneling from the gate, Fig. 3-9 (a), and electron tunneling
from the substrate, Fig.1 (b), where CE , VE , and FE are the silicon conduction band edge,
valence band edge, and Fermi energy level, respectively. 2E∆ and 4∆E are the energy levels for
the 2∆ and 4∆ valley, and 2,∆Bφ and 4,∆Bφ are the tunneling barriers for the 2∆ and 4∆ valleys.
As qualitatively illustrated in Fig. 3-9 (b), quantization results in a redistribution of the carrier
density close to the interface, and only the discrete bound states are considered for 2DEG.
However, the situation is much complicated in the accumulation situation [45]. Electrons are not
only quantized but also wave functions spread as traveling waves forming a quasi-bound state
close to the interface [60]. In accumulation, electrons are divided into the discrete subbands and
49
a continuous energy region. It is shown as a shaded region in Fig. 3-9 (a). However, the direct
tunneling current from the extended region is approximately only related to the highest quantized
energy level, EnMAX, which is still restricted in the substrate surface potential well, and the Fermi
energy level in the silicon [52, 53, 60]. The value of EnMAX depends on how many quantized
subbands are included in the model [68]. Since EF is essentially independent of the applied
uniaxial stress [38, 39], only the strain-effect on the bounded states need to be considered for the
leakage current change with stress since electrons in the extended region contribute nothing to
the leakage current change in accumulation.
It should be noticed that the bounded states in polysilicon are different from that in single
crystal silicon due to the crystal grain boundaries. Each polysilicon grain can be treated as a
perfect single crystal structure, surrounded by a grain boundary. Thus, each grain can be
assumed as a three dimension well, which is conductive as an ohmic contact. The size of grains
is approximately around 100 nm which is much bigger than the typical dimension of the
tunneling structure we investigated [69]. Here, a perfect crystal structured and heavily doped
polysilicon gate with (100) surface is assumed for simplicity [70].
As mentioned before, there are three major mechanisms for direct tunneling in MOSFETs.
ECB tunneling process dominates in the accumulation regime for p-channel MOSFETs and in
both bias polarities for n-channel MOSFETs as shown in Fig. 3-9 [71]. In all these ECB cases,
small 3.15eV barrier for electrons can be directly tunneled easily. In contrast, the gate leakage of
the inverted p-channel MOSFETs devices is dominated by HVB in the low bias range [54]. In
order to distinguish the tunneling current in experiments for different carriers and major
mechanisms, carrier separation measurement for n-channel MOSFET is used as shown before in
Fig. 3-2. The experimental data (dots) and physical model (lines) for a normalized change in the
50
(a)
(b)
Figure 3-9. Schematic band diagram for direct electron tunneling in an n-channel MOSFET for accumulation layer (a) and inversion layer (b), respectively.
51
gate tunneling currents versus the applied uniaxial tensile stress is shown for accumulation layer
in Fig. 3-10 (a) and for inversion layer in Fig. 3-10 (b). For these n-channel MOSFETs, it is
observed that the gate tunneling current linearly decreases with longitudinal tensile stress for
both inversion layer and accumulation layer. Furthermore, the normalized change is smaller with
increase of the gate voltage. Similar trends have been reported for n-channel MOSFETs in
inversion [39, 67].
Without stress, the silicon conduction bands are six-fold degenerated along the ∆-axes.
Due to the breaking of symmetry induced by uniaxial stress, the degeneracy of ∆-valleys
separated as ∆2 and ∆4 valleys. The uniaxial longitudinal tensile stress decreases the ∆2 valley
and increases the ∆4 valley. Decreases in the gate tunneling current for longitudinal tensile
stresses primarily result from electron repopulation into subbands with larger out-of-plane
effective mass [39].
However, the magnitude of the normalized leakage current change in the accumulation
layer is about twice higher than that in the inversion layer. To understand this result, Fig. 3-11 (a)
shows the lowest subband energy level in the ∆2 and ∆4 valley versus the applied uniaxial stress
for both inversion and accumulation layer, where the zero of energy is taken to be the bottom of
the conduction band close to the oxide/substrate interface. Due to the strong confinement in
inversion layer as shown is Fig. 3-9(b), E∆2 and E∆4 in the inversion layer are higher than that in
the accumulation layer. Meanwhile, the normalized lowest subband energy level change with the
applied uniaxial stress in ∆2 and ∆4 valley for inversion and accumulation layer are plotted in
Fig. 3-11 (b). It is obviously shown that valleys with a weak confinement in the accumulation
layer will shift more in energy relative to valleys with a strong confinement in the inversion
layer. Since the tunneling probability from bound states depend exponentially on the electrons
52
(a)
(b)
Figure 3-10. The normalized the electron tunneling current change versus the applied uniaxial longitudinal tensile stress on (100) wafer for accumulation layer (a) and inversion layer (b), respectively.
53
(a)
(b)
Figure 3-11. (a) The lowest subband energy level in ∆2 and ∆4 valley versus the applied uniaxial stress for both inversion and accumulation layer, where the zero of energy is taken to be the bottom of the conduction band; (b) The normalized lowest subband energy level change with the applied uniaxial stress in ∆2 and ∆4 valley for inversion and accumulation layer.
54
energy perpendicular to the barrier, this different energy shift for the accumulation layer and
inversion layer will result in the different leakage current change as is shown in Fig. 3-10. To see
the different confinement more clearly, the concentration of electrons is calculated as a function
of the distance from the Si/SiO2 interface for the particular case of an n-channel MOSFET in
accumulation layer, Fig. 3-12 (a), and in inversion layer, Fig. 3-12 (b), respectively. It is seen
that electrons are confined in a much wider region in the accumulation layer. Although the band
bending is much smaller in the accumulation layer, the peak of the ∆2 valley electron distribution
is not much lower than that in the inversion layer due to the Fermi energy approaching the
conduction band edge in the accumulation layer, which is shown in Fig. 3-9(a).
Longitudinal tensile stress increases the electron population in the ∆2 valleys that have a
high out of plane mass. The inset of Fig. 3-12 shows the surface charge density change for the ∆2
and ∆4 valleys with the applied longitudinal tensile stress. The value of the stress in the
(a)
55
(b)
Figure 3-12. Spatial distributions of the electron density in the n-channel MOSFETs for accumulation layer (a) and inversion layer (b), respectively. The inset shows the surface charge density change for the ∆2 and ∆4 valleys with the applied uniaxial tensile stress from compressive 3GPa to tensile 3GPa, i.e. -3000~3000MPa.
simulation is varied from compressive -3GPa to tensile 3GPa. In contrast, the electron
concentration in the ∆2 valleys decreases with applied longitudinal compressive stress which
increases the electron tunneling current for n-channel MOSFETs [39]. All results are consistent
with the ∆2 valleys have a larger out of plane conductivity mass (0.98m0).
Summary
In summary, a simple picture is provided for physical underlying of the strain effect on
change of gate tunneling current for n and p-channel MOSFETs in inversion regime. It is shown
that a model based on strain-altered out-of-plane effective mass, energy splitting, and subband
repopulation reveals the key mechanism of gate tunneling process in inversion regime for both n-
channel and p-channel MOSFETs. For stresses that produce favorable hole mobility versus
56
electric field (biaxial and uniaxial compression), it is observed that the gate tunneling current is
reduced by stress which results in the top subband having a larger out-of-plane effective mass.
The same is true for strain-induced electron mobility enhancement. For instance, n-channel
MOSFETs benefited from stresses such as longitudinal tensile stress which decreases the direct
electron tunneling current and increases the electron mobility. Meanwhile, due to the weak
confinement, the normalized leakage current change in accumulation layer is higher than that in
inversion layer.
57
CHAPTER 4 LOW TEMPERATURE EFFECT ON MOBILITY IN STRAINED MOSFETS
Although large mobility enhancement has been experimentally achieved for electrons and
holes, further studies of mobility at low temperature can provide useful physical insight on the
surface roughness scattering mechanism, which are responsible for the strain enhanced mobility
at high vertical electrical field [20, 61, 72~74]. So far, lots of works have been done for the
temperature effect on n-channel strained MOSFETs for electron mobility [24, 25], and large
surface roughness scattering reduction is expected even for small tensile stresses (500MPa)
[26~29, 75]. Cammarata predict that the compressive stress has much less effect on the surface
roughness compared with tensile stress for thin films [76]. However, it is not clear how
compressive stress could change the interface roughness in the heterostructure of MOSFETs.
Low temperature hole mobility measurement is a good candidate to investigate the compressive
stress induced surface roughness change in MOSFETs and also physical mechanism for strain
induced hole mobility enhancement. Meanwhile, low temperature electron mobility
measurement with the tensile stress could further confirm the previous conclusion about the
reduced surface roughness scattering for n-channel MOSFETs. In this chapter, controlled
external uniaxial mechanical stress is applied to MOSFETs to measure the strain altered hole and
electron mobility versus temperature. A k•p method and a modified surface roughness scattering
model are used to simulate the low temperature mobility as low as 77K.
Boltzmann equation is used for the calculation of the mobility in inversion layers. The xx
component of the mobility tensor, ij , can be written as [20]
2
2 0
0 02 2 0,
,
,, , 1 (4.1)
4E
xx x
B s x K E
K E
K Eq Ed dE K E f E f E
Ek Tn KK
58
where s v vN n=∑ , and nv is the carrier population of the subband v, ( ) ( , )vx Kτ φ is the
relaxation time, and 10 {1 exp[( ) /( )]}F Bf E E k T −= + − . Based on the results from Chapter 3,
momentum relaxation rate is still needed for mobility calculation.
For simplicity, the hole mobility also could be expressed by the carrier scattering rate and
conductivity effective mass,
*
,//p
emτ
µ = , (4.2)
where *,//pm is the conductivity effective mass in the channel direction, and τ is the average
carrier momentum relaxation time, which is evaluated by considering phonon scattering and
surface roughness scattering for high effective field here.
Scattering Mechanism
For ideal periodic lattice, electron or holes may be transport freely without considering the
boundary condition. However, due to the fluctuation of temperature or any other outside
deviations, like impurities and crystal defects, scatterings are generated. Usually, phonon
scattering, impurity scattering and surface roughness scattering are considered for MOSFETs
mobility simulation as shown in Fig. 4-1 [77]. It is indicated that the total mobility increase with
lower temperatures. Meanwhile, phonon scattering and surface roughness scattering are
dominant at high electrical field regime for room temperature. With the decrease of the
temperature, surface roughness scattering becomes the dominant scattering mechanism and it is
clearly shown in low temperature case, especially below 77K [77]. Charged and neutral impurity
scattering, or coulomb scattering is neglected here since only high transverse electric field
(0.6MV/cm) is considered. Due to strong field from inversion charge layer, screening effect
eliminated the electrical potential generated from ionized dopants.
59
Figure 4-1. Schematic diagram of effective field dependence of total mobility in inversion layer. Total scattering mechanism including the phonon, surface roughness and coulomb scattering. Coulomb scattering is neglected for high effective field [77].
Phonon Scattering
It is know that there are two types of phonon scattering, i.e., intravalley phonon scattering
and intervalley phonon scattering. According to the selection rules for the phonon scattering in
Silicon, intravalley phonon scattering usually only allowed for acoustic phonons with lower
energy, but forbidden for optical phonons. The momentum relaxation time for deformation
potential scattering by intravalley acoustic phonons is given by
2
2
21 ( )B effv v
vac l
k TF E K
u µ µ
πρ
τ ρΞ
= ∑
. (4.3)
where effΞ equals 7.18eV and 9eV as the effective acoustic deformation potential of the valence
band and conduction band, respectively. vρ is the two dimensional DOS of subband v which is
defined as
60
2(0)
20
( , )
1 ( , )( ) [ ](2 )
v
vv
v
K E
K EE E E dEK
π
φ
φρ θ φπ
= −∂∂
∫. (4.4)
The form factor Fμv is given by
2( ) ( )
0 00
( ) ( )W
vvF dz z zµ
µ ψ ψ += ∫ . (4.5)
The momentum relaxation time for intervalley phonon scattering is given by
20
0
( ) 1 [ ( ) ]1 1 1( )1 [ ( )] 2 2
op opv v op op
vop op
DK f E KF E K n
f E Kµ
µ µµ
π ωρ ω
τ ρω− = × + ± −
∑
, (4.6)
where the average deformation potential (DK)op equals 13.24eV and 19.2eV for valence band and
conduction band, respectively.
Surface Roughness Scattering
Surface roughness scattering is associated with roughness at the interface between the
oxide and the Silicon substrate, where is not microscopically smooth for free transport. These
random variations in the interface cause an electrical potential change that scatters the electrons
or holes. The effect of the surface roughness is usually included in the potential and is expressed
by a Taylor series expansion of the scattering element. Using the Ando’s model [78] for surface
roughness scattering, the momentum relaxation time is given as
( )
22
30
1 ( )2
dij
SR
m M q dK
π
θτ π
= ∫
(4.7)
where the scattering matrix element, Mij is given by
2 2
22 2
2 2( ) ( ) ( ) ( )
12
nij i j
LM q e z E z z dzq L
πψ ψ ∆=
+
∫ (4.8)
where ∆ is a average surface roughness potential height and L is a correlation length.[20].
61
Low Temperature Effect on Mobility in Strained p-channel MOSFETs
Experiments are performed on industrial (100)/<110> oriented Si long channel (W/L =
10μm/10μm) MOSFETs with boron doped p+ poly-Silicon gate electrodes, 5×1017cm-3 n-type
well doping, and 1.2 nm nitrided SiO2 gate insulators. Mechanical longitudinal compressive
stress along the <110> direction is introduced into the MOSFET using a 4-point bending setup
[38] that was custom built to be used in a Desert Cryogenics variable temperature probe station.
The electrical data is measured with a Keithley 4200 DC semiconductor characterization system
at temperatures ranging from 300K to 87K.
The experimentally measured and theoretically calculated hole mobility versus temperature
for unstrained, 20MPa, 45MPa, and 60MPa compressive stressed p-channel MOSFETs are
shown in Fig. 4-2. Mobility is extracted from the drain current at low drain voltage (VDS=50mV)
in linear region [79], It is observed in the inset of Fig. 4-2 that strain enhancement increases at
lower temperatures. This result contrasts with present n-channel MOSFET experimental results
in which mobility enhancement decreases [24~26] or remains constant at lower temperatures
[75]. Although decreased interface surface roughness scattering rate [27, 28] for n-channel
MOSFETs may explain the electron case for tensile stress, increase of hole mobility
enhancement at lower temperatures reveals different mechanisms for compressive stressed p-
channel MOSFETs.
At room temperature, the dominant mechanism responsible for hole mobility enhancement
is expected to be reduced conductivity effective mass for small compressive stress. The
modeling shows that, for stresses below 500MPa, the stress enhanced mobility results mainly
from band warping. The band warping creates strong in-plane energy anisotropy in the top band
with a light hole like mass occurring along the <110> channel direction near the band edge.
62
50 100 150 200 250 300 3500
100
200
300
400
500
50 100 150 200 250 300
0.05
0.10
0.15
0.20
0.25
0.30 20MPa 45MPa 60MPa
(µ-µ
(0M
Pa))/µ(
0MPa
)
Temperature (K)
0MPa 20MPa 45MPa 60MPa
µ(cm
2 /(V•S
)
Temperature (K)
Figure 4-2. Measured (dots) and calculated (lines) hole mobility and normalized mobility enhancement (Inset) for (100) Si along the <110> channel direction as a function of temperature for unstressed, 20MPa, 45MPa, and 60MPa longitudinal compressive stressed p-channel MOSFETs.
Lower temperatures decrease the Fermi energy level from -272meV at 300K to -304meV at 87K,
in which the zero energy level is the valence band edge at the interface. The top subband edge
also decreases from -273meV to -283meV. Both Fermi energy level decrease and Fermi
distribution step sharpen at lower temperatures concentrate more hoes at states with lower
subband energy levels, which has a light hole conductivity mass along the channel direction for
longitudinal compressive stress. Confined 2D 25meV and 150meV energy contours are plotted
in Fig. 4-3 (a) near the top band edge on (100) plane for unstressed, 60MPa, and 1GPa uniaxial
stressed Silicon. The energy contour is composed of four wings of which two longitudinal wings
contribute larger conductivity effective mass and two transverse wings contribute smaller mass.
63
The total conductivity effective mass is the average contribution by the four wings. The
conductivity mass along the <110> direction for 25meV is smaller than that for 150meV for
uniaxial compressive stressed Silicon; this trend is more clear for the 1GPa uniaxial compressive
stressed Silicon compared with the 60MPa case. The normalized conductivity effective mass
reduction is shown in Fig. 4-3 (b), it is clearly shown that the effective mass decrease more at
lower temperatures with the same stresses. Meanwhile, the effective mass reduction is almost the
same as the mobility enhancement as shown in the inset of Fig. 4-2.
Scattering rate change is very important for low temperature electron mobility, but, it is
shown that most enhancement for low temperature hole mobility are from band warping effects.,
Optical phonon scattering dominates at room temperature, and both the heavy hole (HH)-like
band and the light hole (LH)-like band contribute to the carrier transport for unstrained Silicon.
Strain induced band warping mixes these bands and redistribute the hole population. Based on
the Boltzmann equation [78], we calculated the phonon-limited mobility as a function of
temperature for unstressed (triangle dots) and 60MPa longitudinal compressive stressed (square
dots) p-channel MOSFETs as shown in Fig. 4-4. As expected, Phonon limited mobility increases
exponentially with lowering temperatures. Moreover, phonon limited mobility is enhanced by
the stress, and this enhancement is increasing with lowing temperature which is similar with the
total mobility.
Meanwhile, surface roughness scattering starts to dominate at low temperature because
more holes will be confined in the lower subband which exhibits lower surface roughness limited
mobility. As shown in Fig. 4-5, the relative contribution by surface roughness limited mobility
for p-channel MOSFETs with 60MPa longitudinal compressive stress increases with lowering
temperatures. At 87K, surface roughness start dominates for strained p-channel MOSFETs.
64
(a)
50 100 150 200 250 300-0.25
-0.20
-0.15
-0.10
-0.05
0.00
20MPa 45MPa 60MPa
(m*-
m*(
0MP
a))/
m*(
0MP
a)
Temperature (K)
(b)
Figure 4-3. (a) Energy contours at 25meV (red line) and 150meV (blue line) to the top band
edge on the (100) surface with zero (solid line), 0.06GPa (dotted line), and 1GPa (dashed line) uniaxial compressive stress along the <110> direction. (b) Normalized conductivity effective mass reduction as a function of temperature for 20MPa, 45MPa, and 60MPa longitudinal compressive stressed p-channel MOSFETs.
65
Using Ando’s model [78], the surface roughness scattering matrix element is given by Eq.
4.8, where ∆=0.4nm is the average surface roughness potential height, L=2.6nm is the
correlation length, and n usually is between 3/2 and 3, [20, 28] we choose n=5/2 here. The
scattering matrix element is inversely proportional to the effective width of the inversion layer as
given by
2
1( ) ( )i j
Wz z dzψ ψ
=∫
(4.9).
The momentum relaxation time of holes is determined by the density-of-states effective mass
and the effective width of the inversion layer. However, the strain induced decrease of the
effective width of the inversion layer in the top band is compensated by the strain induced
reduction of the density-of-states effective mass. Consequently, for a strained p-channel
MOSFET, repopulation almost does not change the surface roughness scattering rate [74].
Therefore, the applied stress effectively enhances surface roughness limited mobility mainly by
decreasing the effective mass for the HH band as shown in Fig. 4-6.
Both strain enhanced phonon and surface roughness limited mobility result in increased
total mobility enhancement at low temperature as shown in Fig. 4-2. This result is consistent
with biaxial stress offering little hole mobility enhancement at small stress and requiring ~2GPa
to alter the scattering rates and enhance mobility [9]. However, the physics for uniaxial stress is
much different than biaxial stressed Silicon which has much less band warping induced effective
mass change and little gain observed in the hole mobility at low temperatures.
To further verify the above conclusion, we calculated the phonon and surface roughness
scattering rates as a function of stress in p-channel MOSFET inversion layer at 300K and 87K as
shown in Fig. 4-7 (a) and (b), respectively. As expected, the phonon scattering rate decreases
66
50 100 150 200 250 3000
200
400
600
800
1000
Unstrained
µ ph (c
m-2/V∗S
ec)
Temperature (K)
Uniaxial Compression 60MPa
Figure 4-4. Calculated phonon-limited mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed (triangle dots) and 60MPa longitudinal uniaxial compressive stressed (square dots) p-channel MOSFETs.
50 100 150 200 250 3000.0
0.2
0.4
0.6
0.8
1.0
Phonon Scattering
Mob
ility
Con
tribu
tion
Temperature (K)
Uniaxial Compression 60MPa
Surface Roughness Scattering
Figure 4-5. Relative contribution by phonon-limited mobility and surface roughness limited mobility for a (100)/<110> Si p-channel MOSFET with 60MPa longitudinal uniaxial compressive stress.
67
50 100 150 200 250 3000
2000
4000
Unstrained
µ SR (c
m-2/V∗S
ec)
Temperature (K)
Uniaxial Compression 60MPa
Figure 4-6. Calculated surface roughness limited mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed (triangle dots) and 60MPa longitudinal uniaxial compressive stressed (square dots) p-channel MOSFETs.
0 1 2 3
0.0
5.0x1012
1.0x1013
1.5x1013
2.0x1013
2.5x1013
Optical Phonon Acoustic Phonon Surface roughness
Scat
terin
g Ra
te (S
ec-1
)
Uniaxial Compressive Stress (GPa)
T=300K
(a)
68
0 1 2 3
0.0
8.0x1011
1.6x1012
2.4x1012
3.2x1012
4.0x1012
Sc
atte
ring
Rate
(Sec
-1)
Uniaxial Compressive Stress (GPa)
Optical Phonon Acoustic Phonon Surface roughness
T=87K
(b)
Figure 4-7. Calculated optical phonon, acoustic phonon, and surface roughness scattering rate for p-channel MOSFETs along the <110> channel direction as a function of longitudinal compressive stress at (a) 300K and (b) 87K, respectively.
dramatically when lowering temperatures. Due to the decrease of kinetic energy of holes in the
inversion layer, the surface roughness scattering rate increases at lower temperatures [20]. In
modeling the experimental data, we do not observe any significant strain-altered phonon or
surface roughness scattering rates at the small stresses (500MPa) in this work. Optical phonon
scattering is dominant at 300K and Surface roughness scattering is crucial at 87K. Acoustic
phonon scattering is not sensitive as optical phonon scattering and surface roughness scattering.
Low Temperature Effect on Mobility in Strained n-channel MOSFETs
Based on previous empirical model [80], dotted line in Fig. 4-8 shows the mobility change
with temperature for unstrained and 60MPa stressed MOSFETs. The model matches
experimental data well for unstrained devices, but the simulated mobility enhancement for
stressed device is much lower than experimental data, especially at low temperature. The only
available assumption for the present experimental data is reduced surface roughness scattering in
69
strained Si [27]. For p-channel MOSFETs, the mobility enhancement could be explained by the
band warping. However, there is not much effective mass change either by band warping or
repopulation between subbands for n-channel MOSFETs and the mechanism of mobility change
could only be explained by scattering rate change [27].
50 100 150 200 250 300300
400
500
600
700
800
900
SB/OP=5/1
0MPa 60MPa
Mob
ility
(cm
2 /s.V
)
Temperature (K)
The model based onHadjisavvsa's work [28] (SB/OP=1/3)
the model withoutscattering rate change
Figure 4-8. Measured (dots) and calculated (lines) electron mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed and 60MPa longitudinal compressive stressed n-channel MOSFETs.
There are mainly two different theoretical models about scattering rate decreasing with the
applied stresses. Bonno’s model claimed that roughness amplitude decreases with the applied
biaxial tensile stress [81]. The surface roughness scattering matrix element is given by Eq. 4.8.
For high electrical field and high inversion charge density, scattering matrix element could be
simplified as
2
2( )ijM q
L∆
∝ . (4.10)
70
According to Bonno’s model, scattering rate decreases with the reduction of roughness
amplitude, correspondingly, the mobility should be enhanced with the applied biaxial tensile
stress for n-channel MOSFETs. Meanwhile, according to Eq. 4.10, correlation length should be
another important factor for surface roughness scattering rate change with the applied stresses.
However, L is considered as a constant value in Bonno’s model. In real situation, L could be
either increase or decrease with tensile stresses. Based on the experimental results, L has a liner
relationship with ∆ for most materials [82], in which, decrease of roughness amplitude means
shorter correlation length. For Silicon, the relation between L and stresses is still unknown.
Correspondingly, Bonno’s model could not explain the relation between surface roughness
scattering rate and the applied stresses precisely. The validation of the model still needs further
experimental verification.
Recently, another quantum mechanical electron motility model without any empirical
parameters showed that reduced surface scattering is the dominant mechanism for strain
enhancement electron mobility [28, 83]. According to this model, surface roughness scattering
matrix element is
( )ijM q ik V jk′=< ∆ >
(4.11)
where ∆V is the potential change due to defects and it could represent by
def refV V V∆ = − . (4.12)
Vdef is a potential with scattering centers and Vref is a reference potential.
Although the concept of this model is different from Bonno’s model, the feature size of
roughness amplitude is similar which is around 0.3nm. Potential change with the applied stresses
depends on the type of scattering centers or defects. OP (oxide protrusion) represents an extra O
atom in Silicon substrate which provide an attractive potential due to the presence of extra
71
50 100 150 200 250 3000
1x103
2x103
3x103
4x103
5x103
6x103
7x103
Unstrained
µ ph (
cm-2/V∗S
ec)
Temperature (K)
Uniaxial Compression 60MPa
Figure 4-9. Calculated phonon-limited mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed and 60MPa longitudinal tensile stressed n-channel MOSFETs.
50 100 150 200 250 3000.0
5.0x102
1.0x103
1.5x103
Unstrained
µ SR (
cm-2/V∗S
ec)
Uniaxial Compression 60MPa
Temperature (K)
Figure 4-10. Calculated surface roughness limited mobility for (100) Si along the <110> channel direction as a function of temperature for unstressed and 60MPa longitudinal tensile stressed n-channel MOSFETs.
72
oxygen ion. On the other hand, SB (suboxide bond) represents an Si-Si bond in the oxide layer,
and repulsive potential is created by oxygen missing here [28, 83]. As shown in Fig. 4-8, atomic
scale roughness was incorporated in empirical model in the dashed line. However, there is still
discrepancy between simulation and experiments. It is reasonable to change the defects ratio
assumptions. Here, we assume that SB/OP=5/1 and the solid line in Fig. 4-8 indicated that the
surface roughness scattering change with stress is critical to reproduce strain induced mobility
enhancement for n-channel MOSFETs. Fig. 4-9 and 4-10 show the phonon-limited and surface
roughness-limited mobility change with temperature in unstrained and strained MOSFETs,
respectively. Similar trend as p-channel MOSFETs is shown here for electrons due to the
surface roughness instead of band warping.
Summary
With applied compressive uniaxial stress, lower temperatures cause more holes to populate
states at the band edge which have a lighter hole conductivity mass in the channel direction and
hence results in the larger stress-induced mobility gain. The experimental data and modeling
suggests that small stresses do not significantly alter the hole scattering rates.
It is shown that the surface roughness scattering becomes dominant at low temperature,
and compressive stress induced surface roughness limited hole mobility enhancement mainly due
to the smaller effective mass along the channel direction for p-channel MOSFETs. However,
increase of electron surface roughness limited mobility by tensile stress is contributed mostly
from scattering rate change for n-channel MOSFETs.
73
CHAPTER 5 EFFECTIVE WORK FUNCTION CHANGE WITH THE APPLIED STRESS
One of the biggest issues in modern CMOS technology is the gate dielectric. As the gate
oxide became scaling down to the ultra thin oxide region, the direct tunneling current increases
[5]. Furthermore, quantum mechanical effects and the polysilicon depletion effect start dominate
as the SiO2 thickness decreasing. Due to these limitations of SiO2, alternative gate dielectrics
with higher dielectric constant are necessary to decrease the effective oxide thickness, and
increase the physical thickness of the insulator [84~87]. During past decades, numerous
candidates has been used as the high-k dielectric layer [88], e.g., rare earth [89], Zirconium oxide
[90~92], and Hafnium oxide [93,94]. Due to the capability with the present processing
technology, Hafnium based high-k dielectric materials became more and more dominant.
Besides HfO2, HfSiON [95], HfAlON [96], and HfTaON [97] has also been widely used
recently.
Polysilicon depletion effect is another limitation for current CMOS technology. This
effect becomes more critical as the effective dielectric thickness is decreased. Threshold voltage
is strongly affected by the Fermi level pinning effect due to polysilicon gate induced interface
states [98]. Replacing polysilicon gate with metal gates could be able to eliminate this issue
[99~101], and lots of metal gate materials has been studied [102], such as FUSI [103], Al [104],
Au [105], ScN [106], and TiSiN [107]. In 2007, MOSFETs with TiN gate have been
productively achieved in the industry in the 45nm technology node [108].
Although several studies have been reported about the strain induced contact resistance
reduction [109], strain effect on the properties of high-k dielectrics [110~113], and strain effect
on radiation [114] for high-k/metal gate devices, there is much less understanding about
electrical parameter compatibility of high-k/metal gate devices and strained Silicon technology.
74
In this chapter, strain induced effective work function (EWF) change for high-k/metal gate
devices will be discussed.
Effective Work Function Change with the External Mechanical Stress
The metal work function choice is a very important consideration because the threshold
voltage and the performance of MOSFETs are determined by metal work function [115, 116].
Work function represents the minimum energy for electrons to escape from the solid surface, and
it is normally measured by Kelvin probe force microscopy (KFM) [117]. However, the
measurement of EWF is a challenging task because the overall work functions for gate stacks are
different from traditional metal work function for metal only [118~122], and EWF also depends
on process conditions. EWF is modified by Lanthanum or Aluminum Doping [123~127],
thermal treatment [128~131], and capping layers [132]. In this section, we investigated WEF
tuning with the applied stress.
Figure 5-1. Terraced oxide wafer with different silicon oxide thickness from 1 to 4 nm. High-k and metal gate are deposited with the same thickness.
75
Experimental Setup
A capacitance based method [133] with a single “wedding” structured wafer was used to
extract the EWF as shown in Fig. 5-1. The thermally grown SiO2 are etched into rings with
various thicknesses of 1, 2, 3, 4 nm. High-k dielectrics, HfSiO, and metal gate, TiN, are
deposited with the same thickness on the terraced SiO2 [134]. Capacitance–voltage (C-V) curves
were measured with an HP 4284 semiconductor characterization system at 100 kHz, and the flat
band voltage, Vfb, and effective oxide thickness, EOT, values were simulated from the North
Carolina State University (NCSU) CVC program [135]. The EWF for gate stack is extracted
from the work function difference between gate and substrate, msΦ , by equation
int
0
1 1( ) ( )h tox
ffb ms ox h o
hox h o
Q QV T x x dx x x dxρ ρ
ε ε ε+
= Φ − − −∫ ∫ (5.1)
where Qf is the fixed charge at the silicon oxide and substrate interface, Qint is the interface
charges which is depends on the effective electrical field and electrically communicable with the
substrate, Tox is the EOT, oxε is the permittivity of silicon oxide, hε is the permittivity of high-k
dielectrics, hρ is the charge density inside the high-k dielectrics, oε is the permittivity of silicon
oxide, oρ is the charge density inside the silicon oxide.
Fig. 5-2 (a) shows C-V measurement results for a single terraced wafer with different
silicon oxide thickness. Fig. 5-2 (b) shows the flat band voltage as a linear function of EOT
which indicated that the charges inside the HfSiO and SiO2 are much less than interface charges.
Otherwise, there is a parabolic relation between flat band voltage and EOT. As shown in Fig. 5-2
(b), a linear function is simplified from Eq. 5.1, which is used for the EFW extraction in this
work.
76
(a)
(b)
Figure 5-2. (a) Measured capacitance–voltage curve results for a single terraced wafer with different silicon oxide thickness. (b) The flat band voltage as a function of EOT. A good linear relation is show for these devices.
77
(a)
(b)
Figure 5-3. Experimental setup of four point bending jig for uniaxal stresses (a) schematic diagram (b) actually jig from side view.
External stresses are applied by a four point bending jig for uniaxial stresses as shown in
Fig. 5-3. Applied external stresses are calculated by
−
⋅⋅= =
32
22 aLa
ytE axσ , (5.2)
78
where σ is the stress, E is Young’s modulus, t is the sample thickness, y is the vertical
displacement, a and L are rod spacing. Biaxial stresses are applied by two rings with different
sizes.
Experimental Results
Fig. 5-4 shows the extracted EWF for TiN gate stack with uniaxial stress (a), and biaxial
stress (b). WF_D21, WF_D22, WF_D23 represent the TiN gate thickness as 10, 5, and 2nm,
respectively. It is observed that the EWF linearly deceases with the applied stresses regardless
the stress type and the thickness of TiN metal gate. This trend is more clearly shown in Fig. 5-5
as the normalized EWF change with uniaxial stress (a) and biaxial stress (b). Strain induces more
interface defects and they are contributing to the capacitance measurement with response to the
applied gate voltage [136,137].
It is shown in Fig. 5-4 that the WEF is smaller for the capacitors with thinner metal gate.
The WEF shift could reach as large as 0.21eV which is shown in Tab. 5-1. This EWF tuning
results are consistent with previous published results [138,139]. With the metal gate thickness
decrease, more tensile stress are induced in the metal gate and substrate where more defects are
generated in the interface due to the dangling bond activation energy decrease. Stresses either
increase or decrease the dangling bond angel and this bond angel change induces more interface
defects correspondingly. To further verify this assumption, interface state measurement under
different stresses is required.
Table 5-1. EWF and its change with different metal gate thickness as 10, 5, and 2 nm, respectively.
TiN 10 nm 5 nm 2 nm
EWF (eV) 4.5983 4.4200 4.3862
ΔEWF (eV) 0.0000 -0.1783 -0.2121
79
(a)
(b)
Figure 5-4. Extracted EWF for TiN gate stack with uniaxial stress (a), and biaxial stress (b). WF_D21, WF_D22, WF_D23 represent the TiN gate thickness as 10, 5, and 2nm, respectively.
80
(a)
(b)
Figure 5-5. Normalized EWF change for TiN gate stack with uniaxial stress (a), and biaxial stress (b). WF_D21, WF_D22, WF_D23 represent the TiN gate thickness as 10, 5, and 2nm, respectively.
81
Effective Work Function Change with the Process Introduced Stress
External mechanical stresses are too small to induce enough interface state change for
measurement. Process induced stress for different metal gate thickness is a good option for this
measurement. The high-k metal gate device for the interface state measurement is shown in
Fig.5-6. Different metal gate thickness was deposited on the Silicon substrate and the inevitable
interfacial layer thickness is 1nm. Polysilicon gate is added after TiN gate formed. Larger
process induced stress is expected for MOSFETs with thinner metal gate thickness.
Figure 5-6. Schematic diagram of high-k/metal gate MOSFETs with different metal gate thickness. Higher stress in expected for MOSFETs with thinner metal gate. IL is the interfacial layer between the Silicon and HfSiO.
Bowing Technique for Stress Measurement
Bowing technique provides a useful tool to characterize the surface stress on the wafer
[140,141]. Fig. 5-7 show the bowing measurement set up, where R is the calculated radius of
curvature, ts is the substrate thickness, tf is the film thickness, and rsc is the scan distance. The
average surface stress is given by Stoney’s equation
21 1
6 1s
f
tEt R
σν
= − (5.3)
where σ is the average film stress, E/1-v is biaxial elastic modulus of substrate, ts is the substrate
thickness, tf is the film thickness. There are several assumptions for Eq. 5.2: 1) tf << ts << wafer;
2) substrate is elastically isotropic and flat; 3) uniform film and substrate thickness and
82
Figure 5-7. Diagram for Bowing measurement, where R is the calculated radius of curvature, ts is the substrate thickness, tf is the film thickness, and rsc is the scan distance.
temperature; 4) maximum wafer deflection is less then half of ts. Stress measurement results are
shown in Fig. 5-8. It is indicated that the stress value is always increases with the decrease of the
metal gate thickness. However, the stress magnitude, even the stress type strongly depends on
the thermal treatment. For the film as deposited, the stress is compression and it is larger for
MOSFETs with thinner TiN. Whereas, tension is introduced for film after annealing and the
stress is larger for low temperature process. Although, stress type and value are process
dependent, higher stress always corresponding to MOFETs with thinner TiN. These provide a
clear picture about how stress will change the interface states for different metal gate thickness.
Charge Pumping for Interface States Measurement
Charge pumping method using a MOSFET precisely measure the selective recombination
of carriers trapped in the interface states [142]. Measurement setup is shown in Fig. 5-9 for an n-
channel MOSFET. Gate pulse is applied to the gate and source and drain are tied together with a
83
small reverse bias applied. The silicon surface switches from strong accumulation to strong
inversion with a large gate pulse.
A schematic illustration of the two level charge pumping method for an n-channel
MOSFET is shown in Fig. 5-10. In this case, base level of the gate pulse is increased and height
of the gate pulse is constant. The upper curve shows the charge pumping current change with the
base gate voltage level. In strong accumulation region, all gate voltage is lower than the flat band
voltage, and there is no holes came out for recombination. In weak accumulation region, the
holes captured in the interface traps start recombine electrons from channel and the charge
pumping current is increased. In depletion region, the recombination process saturated and the
charge pumping current reaches the maximum value. In weak inversion region, the interface
traps can not be fully filled with holes and the recombination process is not completed as it does
Figure 5-8. Measured average stress on the wafer for MOSFETs without thermal treatment, 600C annealing, and 1035C annealing, respectively. It is clearly shown that the stress always increase for MOSFETs with thinner metal gate thickness.
84
Figure 5-9. Schematics of charge pumping measurement setup for an n-channel MOSFET [143].
Figure 5-10. Schematics illustration of the two level charge pumping method for an n-channel MOSFET. In this situation, base level of the gate pulse is increased and the substrate switches from strong accumulation to strong inversion. The upper curve shows the charge pumping current change with the base gate voltage level.
85
in depletion region. In strong inversion region, there is no holes captured in the interface traps
and the charge pumping current is zero.
Figure 5-11. Measured Charge pumping current on an n-channel MOSFET with 2, 5, and 10 nm TiN gate electrode.
Figure 5-12. Schematic diagram for stress induced generation of donor-like interface traps between the interfacial layer and the Silicon substrate.
Fig. 5-11 shows the measured charge pumping current on an n-channel MOSFET with 2, 5
and 10 nm TiN gate electrode. It is indicated that the interface traps increase for MOSFETs with
thinner metal gate electrode which corresponding to larger stress on the wafer surface as shown
86
in Fig. 5-8. This result confirmed the measurement of the EWF of capacitors in Fig. 5-4 and 5-5.
Meanwhile, the negative shift of the peak of charge pumping current implies the capture of more
positive charges, and the stress generates more donor-like interface states [144] as shown in Fig.
5-12.
Summary
Effective work function change is studied for both external mechanical applied stress and
process induced high stress. Stress within the TiN surface strongly depends on the thermal
treatment for process induced stress. Bowing technique and charge pumping method are used for
stress and interface state measurement, respectively. It is indicated that the EWF always decrease
with the applied stress and the interface states increase induced donor-like charge generation is
the dominant physical mechanism.
87
CHAPTER 6 SUMMARY AND SUGGESTIONS ABOUT FUTURE WORKS
Summary
Low power device will be benefited from gate direct tunneling leakage current reduction.
Drain current increase depends on the mobility enhancement. Effective work function tuning will
greatly improve the performance of high-k/metal gate MOSFETs. In this work, several physical
models are provided for the strain effect on the performance of Silicon MOSFETs, and different
electrical characterizations is used to investigate leakage current, mobility, and work function.
Strain effect on the change of gate tunneling current for n and p-channel MOSFETs in both
inversion and accumulation regimes are characterized. A physical model based on out-of-plane
effective mass, energy splitting, and repopulation indicates the insight of gate tunneling process
for both n-channel and p-channel MOSFETs. Biaxial and uniaxial compression not only improve
the hole mobility, but also reduce the gate tunneling leakage current for p-channel MOSFETs.
The same benefit is applicable to n-channel MOSFETs due to the repopulation induced out-of-
plane effective mass change. The relative leakage current change in accumulation regime is
lager than that in inversion layer due to the weak confinement and less energy splitting.
Temperature dependent mobility measurement provides a clear picture of conductivity
effective mass and scattering mechanism. Banding warping induced effective mass is much more
important of p-channel MOSFETs. Whereas, the repopulation between subbands induced
effective mass reduction is critical for n-channel MOSFETs. With applied compressive stress,
lower temperatures concentrate more holes to the states near the band edge where the band
warping effect is most dominant. Phonon scattering is dominant at 300K, and the surface
roughness scattering starts to be critical beyond 87K, and will be the dominant scattering
88
mechanism close to 33K. Both experimental data and modeling suggests that much larger
mobility enhancement will be observed for large stress under low temperature.
Work function selection has been the most difficult challenge for high-k/metal gate devices
for the most recent 32nm technology node. Gate last formulation introduces large stress in the
metal gate. Not only mobility is enhanced tremendously, but also a novel effective work function
tuning candidate is provided. Both tension and compression effectively reduced the work
function for n-channel MOSFETs which is confirmed by external mechanical stress and process
induced large biaxial stress.
Suggestions about Future Works
Silicon-on-insulator (SOI) transistor architecture has been considered a promising
candidate to greatly improve the performance of the traditional MOSFETs. The basic idea of SOI
is to fabricate traditional transistor structure on a very thin Silicon layer which is separated from
the bulk substrate by a thick insulator layer, in which, parasitic capacitance is dramatically
decreased and the maximum working frequency will be increased correspondingly. Meanwhile,
to more effectively control the inversion charge for short channel devices, FinFETs have been
widely investigated theoretically and experimentally recently. SOI and FinFET devices have
been shown to enhance the device performance and decrease the power consumption.
Combination of these two novel device structures are very promising to be used in the future
22nm CMOS technology node.
Besides strain effects on traditional Silicon MOSFETs, strained SOI may add the strain
induced contact resistance reduction with their control advantages. Meanwhile, how multi
interfaces with insulator should affect surface roughness scattering more than the traditional
Silicon MOSFETs, which made surface roughness change with the applied stress more important.
At low temperature, we could obtain more detailed information. Comparing with SOI, mobility
89
change of FinFETs should provide a clear picture of surface roughness scattering mechanism due
to its multi gate controlled transport channels and two simultaneously applied electrical field
which will also provide more information at low temperature.
90
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BIOGRAPHICAL SKETCH
Xiaodong Yang obtained the B.S. degree in physics from Inner Mongolia Normal
University in 2001, M.S. degree in materials from Beijing University of Technology in 2004,
M.S. degree in management from Warrington College of Business Administration at University
of Florida in 2008, respectively. He has been work with Dr. Thompson’ group since 2005 and
graduated with a PhD degree in electrical and computer engineering at the University of Florida
in the fall of 2009.
He was with the CMOS Development and Research Department, IMEC, at Belgium as a
device research engineer intern at 2008. During that period, he was involved in the high-k/metal
gate device development for the 32nm technology node. His current research interests are strain
effects on the performance of MOSFETs.