c10lp eval a1 sch rl0 20170816 - mouser electronics · 1 ,2 ',)),2b/ 1 1 ,2 583 . ,2 5'1...
TRANSCRIPT
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Cyclone 10 LPFPGA
Clock(50M + programmable)
HyperRAMx8
Button
RGMII
JTAG
U256 Package14x14mm
USB InterfaceOn-BoardUSB BlasterTM II
PMOD
JTAG Header
EPCQ64
Ethernet
LED
Switch
Arduino
Mini-USB2.0
ADC I2CSystemMAX
Arduino Digital
Arduino Analog
HyperBus
2x20 GPIO Header
DESCRIPTIONREV DATE PAGES
PAGE DESCRIPTION
2
NOTES:
Title, Notes, Block Diagram, Rev. History1
A1 08/16/17 All Initial Release1. Project Drawing Numbers:
Raw PCB Gerber Files PCB Design Files Assembly Drawing Fab Drawing Schematic Drawing PCB Film Bill of Materials Schematic Design Files Functional Specification PCB Layout Guidelines Assembly Rework
100-0321321-A1110-0321321-A1120-0321321-A1130-0321321-A1140-0321321-A1150-0321321-A1160-0321321-A1170-0321321-A1180-0321321-A1210-0321321-A1220-0321321-A1320-0321321-A1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Power Diagram
Cyclone 10 Bank 1~4
Clock Daigram
Cyclone 10 Power
MAX10 - UBII-A
MAX10 - UBII-B
Cyclone 10 Bank 5~8
HyperRAM
Ethernet
Arduino Header
MAX10 - ADC
LED, PB, DIP SW
Clock
Power Input
PMOD, 2x20 GPIO
1.2V, 1.8V, 2.5V, 3.3V
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
1 17Wednesday, August 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
1 17Wednesday, August 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
1 17Wednesday, August 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
C10_VCCINT
EP5358HUI (U26)
0.6A Max.
EP5358HUI (U27)
0.6A Max.
EN5339QI (U23)
3A Max.
EN5329QI (U25)
2A Max.
C10_VCCD_PLL
C10_VCCIO_1.8V
C10_VCCA
C10_VCCIO_3.3V
USB_5V(5V@1A)
5V_DCIN ( 5V,>1A )
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
2 17Tuesday, August 01, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
2 17Tuesday, August 01, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
2 17Tuesday, August 01, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
On-BoardUSB BlasterTM II
CypressCY7C68013A
USB Controller
2 5
6
3 4
78Si5351
Default LVCMOS 125MHz
Default LVCMOS 50MHz
LVCMOS Adjustable
1
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
3 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
3 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
3 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCIO1=3.3V
VCCIO2=3.3V
VCCIO4=1.8V
VCCIO3=3.3V
E2 is GND on CIV E U256
HyperRAM (HyperBUS)
C10 JTAG
Clocks
2x20 GPIO
EP4CE22U14I7N
Reserved For MCP/Flash
Arduino I2C
Arduino Digital IO
C10_JTAG_TDIC10_JTAG_TCKC10_JTAG_TMSC10_JTAG_TDO
C10_AS_DATA0C10_AS_DCLK
C10_AS_CSn
C10_AS_ASDO
C10_NCONFIG
C10_NSTATUS
RUP2RDN2
C10_NCE
HBUS_CKpHBUS_CKn
C10_AS_DCLK
C10_AS_CSnC10_AS_DATA0
C10_AS_ASDO
C10_CLK50M
ARDUINO_IO9ARDUINO_IO10
HBUS_RSTnHBUS_DQ3HBUS_DQ4
HBUS_DQ2HBUS_DQ5
HBUS_DQ6HBUS_DQ0HBUS_CS2n
HBUS_DQ7HBUS_DQ1
ARDUINO_IO2
ARDUINO_IO0ARDUINO_IO1
ARDUINO_IO3
ARDUINO_IO4ARDUINO_IO5
ARDUINO_IO6ARDUINO_IO7ARDUINO_IO8ARDUINO_IO11
ARDUINO_IO13ARDUINO_IO12
ARDUINO_SDAARDUINO_SCL
ARDUINO_RSTn
GPIO35GPIO33GPIO34
GPIO31
GPIO28GPIO29GPIO30
GPIO26GPIO27GPIO24GPIO25
GPIO22GPIO23
GPIO21
GPIO18GPIO19
GPIO17
GPIO16
GPIO12GPIO13
GPIO14GPIO15
GPIO10GPIO11
HBUS_RSTOn
ENET_CLK_125M
HBUS_RWDS
HBUS_INTn
HBUS_CS1n
GPIO20
GPIO32
C10_VCCIO_3.3V
C10_VCCA_FLT
VCC_3.3V
VCC_3.3V
C10_VCCIO_1.8V
C10_VCCIO_3.3V
C10_NSTATUS<7>
HBUS_DQ[7:0]<10>
C10_NCONFIG<14>
C10_JTAG_TDO<8>C10_JTAG_TDI<8>C10_JTAG_TMS<8>C10_JTAG_TCK<8>
C10_CLK50M<15>
GPIO[0:35]<5,13>
HBUS_CKp<10>HBUS_CKn<10>
HBUS_CS2n<10>HBUS_RSTn<10>
HBUS_RWDS<10>
HBUS_CS1n<10>HBUS_RSTOn<10>HBUS_INTn<10>
ARDUINO_SDA<12>ARDUINO_SCL<12>
ARDUINO_IO[13:0]<12>
ARDUINO_RSTn<12>
ENET_CLK_125M<15>
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
4 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
4 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
4 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
R10 24.9
R8 0
R2 10K
C1 0.1uF
R288 10K
10CL025YU256Bank 1
10CL025YU256I7G
U1A
IO_B1_0B1
IO, DIFFIO_L3PC2
IO, DIFFIO_L3N, DATA1, ASDOC1
IO, VREFB1N0F3
IO, DIFFIO_L4P, FLASH_NCE, NCSOD2
IO, DIFFIO_L4ND1
NSTATUSF4
IO, DIFFIO_L6PG2
IO, DIFFIO_L6NG1
DCLKH1
IO, DATA0H2
NCONFIGH5
TDIH4
TCKH3
TMSJ5
TDOJ4
NCEJ3
CLK0, DIFFCLK_0PE2
CLK1, DIFFCLK_0NE1
R276 2K
Bank 4
10CL025YU256
10CL025YU256I7G
U1D
CLK13, DIFFCLK_7PR9
CLK12, DIFFCLK_7NT9
IO_B4_0N9
IO, DIFFIO_B16PR10
IO, DIFFIO_B16NT10
IO, DIFFIO_B17PR11
IO, DIFFIO_B17NT11
IO, DIFFIO_B18PR12
IO, DIFFIO_B18NT12
IO_B4_1P9
IO, VREFB4N0P11
IO, DIFFIO_B20PR13
IO, DIFFIO_B20NT13
IO, RUP2M10
IO, RDN2N11
IO, DIFFIO_B23PT14
IO, DIFFIO_B23NT15
IO_B4_2N12
IO, PLL4_CLKOUTPP14
IO, PLL4_CLKOUTNR14
R11 0
R12 49.9
R277 2K
R6 1K
R9 0
Bank 3
10CL025YU256
10CL025YU256I7G
U1C
IO, DIFFIO_B1PN3
IO, DIFFIO_B1NP3
IO, DIFFIO_B2PR3
IO, DIFFIO_B2NT3
IO_B3_0T2
IO, PLL1_CLKOUTPR4
IO, PLL1_CLKOUTNT4
IO, DIFFIO_B4PN5
IO, DIFFIO_B4NN6
IO_B3_1M6
IO, VREFB3N0P6
IO_B3_2M7
IO, DIFFIO_B6PR5
IO, DIFFIO_B6NT5
IO, DIFFIO_B7PR6
IO, DIFFIO_B7NT6
IO_B3_3L7
IO, DIFFIO_B8PR7
IO, DIFFIO_B8NT7
IO_B3_4L8
IO_B3_5M8
IO_B3_6N8
IO_B3_7P8
CLK15, DIFFCLK_6PR8
CLK14, DIFFCLK_6NT8
R13 49.9
R1 10K
R4 10K
Bank 2
10CL025YU256
10CL025YU256I7G
U1B
CLK2, DIFFCLK_1PM2
CLK3, DIFFCLK_1NM1
IO, DIFFIO_L7PJ2
IO, DIFFIO_L7NJ1
IO, DIFFIO_L10PK2
IO, DIFFIO_L10NK1
IO, DIFFIO_L11PL2
IO, DIFFIO_L11NL1
IO, VREFB2N0L3
IO, DIFFIO_L13PN2
IO, DIFFIO_L13NN1
IO, RUP1K5
IO, RDN1L4
IO_B2_0R1
IO, DIFFIO_L15PP2
IO, DIFFIO_L15NP1
U2
EPCQ64
VCC/DATA31
VCC2
NC13
NC24
NC35
NC46
nCS7
DATA18
VCC/DATA29GND10NC511NC612NC713NC814DATA015DCLK16
R7 10K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCIO6=3.3V
Ethernet
VCCIO8=3.3V
VCCIO7=3.3V
VCCIO5=3.3V
Clock
Arduino ADC I2C
C10 M10 Interconnetion
C10 Misc. Signals
MAX10 USB Interface
User PBs, LEDs, SWs
2x20 GPIO
PMOD
MSEL[2:0]=101: ASx1, Fast POR, 3.3V IO
2.5V
C10_CONF_DONE
C10_INIT_DONE
C10_RESETnC10_DEV_OE
ENET_RG_RXCLK
C10_RG_TXCLKC10_USB_CLK
C10_MSEL0C10_MSEL1C10_MSEL2
C10_CRC_ERROR
USB_CLK
C10_CLK_ADJ
HBUS_CLK_50M
C10_M10_IO3
USER_LED0
USER_LED1
USER_LED2USER_LED3
USER_PB0
USER_PB1
USER_PB2
ARDUINO_ADC_SCLARDUINO_ADC_SDA
C10_M10_IO0C10_M10_IO2
ENET_RG_RXD0ENET_RG_RXD1ENET_RSTnENET_RG_RXD2ENET_RG_RXD3
C10_M10_IO1C10_RG_TXD0
ENET_RG_RXCTLENET_INT
C10_RG_TXCTLENET_MDIOENET_MDC
C10_RG_TXD3
C10_RG_TXD2C10_RG_TXD1
GPIO9GPIO8
GPIO4GPIO5
GPIO7GPIO6
GPIO2GPIO3
GPIO0GPIO1
PMOD_D1
PMOD_D5PMOD_D3
PMOD_D7
PMOD_D0
PMOD_D4PMOD_D6
PMOD_D2
USER_PB3
C10_MSEL0
C10_MSEL1
C10_MSEL2
USER_DIP0
USER_DIP1
USER_DIP2
USB_ADDR0
USB_ADDR1
USB_DATA0
USB_DATA1USB_DATA2USB_DATA3USB_DATA4
USB_DATA5USB_DATA6
USB_DATA7
USB_EMPTY
USB_FULL
USB_OEn
USB_RDn
USB_RESETn
USB_SCL
USB_SDA
USB_WRn
ENET_RG_TXCLK
ENET_RG_TXD3
ENET_RG_TXD2ENET_RG_TXD1
ENET_RG_TXD0
ENET_RG_TXCTL
C10_VCCIO_3.3V
C10_VCCIO_3.3V
C10_VCCIO_3.3V
C10_VCCA_FLT
ENET_RG_RXCLK<11>ENET_RG_RXCTL<11>
ENET_RG_RXD0<11>ENET_RG_RXD1<11>ENET_RG_RXD2<11>ENET_RG_RXD3<11>
ENET_RG_TXCLK<11>ENET_RG_TXCTL<11>
ENET_RG_TXD0<11>ENET_RG_TXD1<11>ENET_RG_TXD2<11>ENET_RG_TXD3<11>
ENET_MDIO<11>ENET_MDC<11>
ENET_INT<11>ENET_RSTn<11>
C10_CLK_ADJ<15>
HBUS_CLK_50M<15>
ARDUINO_ADC_SDA<8>ARDUINO_ADC_SCL<8>
C10_M10_IO[3:0]<7>
C10_RESETn<14>C10_CONF_DONE<7>
C10_INIT_DONE<7>C10_CRC_ERROR<7>
USB_DATA[7:0]<8>
USB_ADDR[1:0]<8>
USB_SDA<8>
USB_FULL<8>USB_EMPTY<8>USB_SCL<8>
USB_RESETn<8>USB_OEn<8>USB_RDn<8>USB_WRn<8>
USB_CLK<7>
USER_PB[0:3]<14>
USER_LED[0:3]<14>
GPIO[0:35]<4,13>
PMOD_D[0:7]<13>
USER_DIP[0:2]<14>
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
5 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
5 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
5 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
R20 0Bank 6
10CL025YU256
10CL025YU256I7G
U1F
CLK5, DIFFCLK_2NE16
CLK4, DIFFCLK_2PE15
CONF_DONEH14
MSEL0H13
MSEL1H12
MSEL2G12
IO, DIFFIO_R5N, INIT_DONEG16
IO, DIFFIO_R5P, CRC_ERRORG15
IO_B6_0F13
IO, DIFFIO_R4N, NCEOF16
IO, DIFFIO_R4P, CLKUSRF15
IO_B6_1B16
IO, VREFB6N0F14
IO_B6_2D16
IO_B6_3D15
IO, DIFFIO_R1NC16
IO, DIFFIO_R1PC15
R304 33
Bank 7
10CL025YU256
10CL025YU256I7G
U1G
IO, DIFFIO_T24NC14
IO, DIFFIO_T24PD14
IO, DIFFIO_T23ND11
IO, DIFFIO_T23PD12
IO, DIFFIO_T22NA13
IO, DIFFIO_T22PB13
IO, PLL2_CLKOUTNA14
IO, PLL2_CLKOUTPB14
IO, RUP4E11
IO, RDN4E10
IO, DIFFIO_T21NA12
IO, DIFFIO_T21PB12
IO, DIFFIO_T20NA11
IO, DIFFIO_T20PB11
IO, VREFB7N0C11
IO_B7_0A15
IO_B7_1F9
IO, DIFFIO_T16NA10
IO, DIFFIO_T16PB10
IO, DIFFIO_T15NC9
IO, DIFFIO_T15PD9
IO_B7_2E9
CLK8, DIFFCLK_5NA9
CLK9, DIFFCLK_5PB9
R22 0
R305 33
R306 33
R23 DNI
R278 2K
R246 10K
R16 10K
R279 2K
R19 DNI
R17 0
R136 10K
Bank 8
10CL025YU256
10CL025YU256I7G
U1H
CLK10, DIFFCLK_4NA8
CLK11, DIFFCLK_4PB8
IO_B8_0C8
IO_B8_1D8
IO, DIFFIO_T10N, DATA2E8
IO, DIFFIO_T10P, DATA3F8
IO, DIFFIO_T9NA7
IO, DIFFIO_T9P, DATA4B7
IO, VREFB8N0C6
IO, DIFFIO_T7NA6
IO, DIFFIO_T7PB6
IO, DATA5E7
IO, DATA6E6
IO, DIFFIO_T5N, DATA7A5
IO, DIFFIO_T5PB5
IO_B8_2D6
IO, DIFFIO_T3NA4
IO, DIFFIO_T3PB4
IO, DIFFIO_T2NA2
IO, DIFFIO_T2PA3
IO_B8_3B3
IO, PLL3_CLKOUTNC3
IO, PLL3_CLKOUTPD3
R207 10K
R18 DNIBank 5
10CL025YU256
10CL025YU256I7G
U1E
IO, RUP3N14
IO, RDN3P15
IO, DIFFIO_R15NP16
IO, DIFFIO_R15PR16
IO, DIFFIO_R13NN16
IO, DIFFIO_R13PN15
IO, VREFB5N0L14
IO_B5_0L13
IO, DIFFIO_R11NL16
IO, DIFFIO_R11PL15
IO, DIFFIO_R10NK16
IO, DIFFIO_R10PK15
IO, DIFFIO_R9N, DEV_OEJ16
IO, DIFFIO_R9P, DEV_CLRNJ15
IO_B5_1J14
IO_B5_2J13
CLK7, DIFFCLK_3NM16
CLK6, DIFFCLK_3PM15
R301 33
R248 0
R302 33
R21 10K
R303 33
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.2V
2.5V
1.2V
D5, F1, F2, G5 are IO on CIV E U256
C10_VCCIO_3.3V
C10_VCCD_PLL
C10_VCCA_FLT
C10_VCCIO_3.3VC10_VCCINT
C10_VCCIO_3.3VC10_VCCINT C10_VCCA_FLT
C10_VCCIO_1.8V
C10_VCCIO_1.8VVCC_1.8V C10_VCCD_PLLVCC_1.2V
C10_VCCA
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
6 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
6 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
6 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
C124
0.022uF
10CL025YU256Misc. Power
10CL025YU256I7G
U1L
VCCD_PLL3D4
GNDA3E5
VCCA3F5
VCCA1L5
GNDA1M5
VCCD_PLL1N4
VCCD_PLL4N13
GNDA4M12
VCCA4L12
VCCA2F12
GNDA2E12
VCCD_PLL2D13
C141
0.047uF
C193
47uF
C130
1uF
C194
4.7uF
C129
0.022uF
C196
0.47uF
TP25
C115
1uF
C120
0.01uF
TP26
C117
0.1uF
TP27
C134
4700pF
R236 0.2
C122
0.01uF
C136
4700pF
L151.5A, 180 Ohm FB
C142
0.22uF
L171.5A, 180 Ohm FB
C143
0.1uF
VCCINT
10CL025YU256
10CL025YU256I7G
U1I
VCCINTF7
VCCINTF11
VCCINTG6
VCCINTG7
VCCINTG8
VCCINTG9
VCCINTG10
VCCINTH6
VCCINTH11
VCCINTJ6
VCCINTK7
VCCINTK11
VCCINTL6
VCCINTK9
VCCINTK10
VCCINTM9
VCCINTM11
VCCINTJ12
C195
4.7uF
C139
0.01uF
10CL025YU256GND
10CL025YU256I7G
U1K
GNDH7
GNDH8
GNDH9
GNDH10
GNDJ7
GNDJ8
GNDJ9
GNDJ10
GNDF6
GNDF10
GNDJ11
GNDK8
GNDK6
GNDL9
GNDL10
GNDL11
GNDK12
GNDG11
GNDB2
GNDB15
GNDC5
GNDC12
GNDD7
GNDD10
GNDE4
GNDE13
GNDG4
GNDG13
GNDK4
GNDK13
GNDM4
GNDM13
GNDN7
GNDN10
GNDP5
GNDP12
GNDR2
GNDR15
GNDH16
GNDH15
GNDD5
GNDF1
GNDF2
GNDG5
VCCIO
10CL025YU256
10CL025YU256I7G
U1J
VCCIO1E3
VCCIO1G3
VCCIO2K3
VCCIO2M3
VCCIO3P4
VCCIO3P7
VCCIO3T1
VCCIO4P10
VCCIO4P13
VCCIO4T16
VCCIO5K14
VCCIO5M14
VCCIO6E14
VCCIO6G14
VCCIO7A16
VCCIO7C10
VCCIO7C13
VCCIO8A1
VCCIO8C4
VCCIO8C7
C138
0.01uF
C197
1uF
R237 0.2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB: 90Ohm Differential Pair
C10 M10 Interconnetion
C10 Misc. Signals
FX2_D_NFX2_D_P
24M_XTALIN24M_XTALOUT
FX2_RESETn
USB_CLK
FX2_PA0FX2_PA1FX2_PA2FX2_PA3FX2_PA4FX2_PA5FX2_PA6FX2_PA7
FX2_PB0FX2_PB1FX2_PB2FX2_PB3FX2_PB4FX2_PB5FX2_PB6FX2_PB7
FX2_PD0FX2_PD1FX2_PD2FX2_PD3FX2_PD4FX2_PD5FX2_PD6FX2_PD7
FX2_SLWRnFX2_SLRDn
FX2_FLAGCFX2_FLAGBFX2_FLAGA
FX2_WAKEUP
FX2_SDAFX2_SCL
FX2_RESETn
FX2_WAKEUP
M10_CONF_DONE
M10_TDIM10_TCKM10_TMS
M10_TDO
M10_JTAGEN
M10_CONFIG_SELM10_NCONFIG
M10_NSTATUS
FX2_PD0FX2_PD1
FX2_PD2FX2_PD3
M10_TDOM10_TMS
M10_TCK
M10_TDI
M10_DEV_OE
M10_CONFIG_SEL
C10_NSTATUSC10_CONF_DONESYS_CONF_DONE
FX2_SLWRn
C10_CRC_ERROR
USB_CLK M10_USB_CLK
FX2_PA5
FX2_PD4FX2_PD5
C10_M10_IO1C10_M10_IO0
C10_INIT_DONE
FX2_RESETn
M10_DEV_CLRn
FX2_PA7
C10_M10_IO3FX2_PA6FX2_PD7FX2_PA4FX2_SLRDn
FX2_PD6FX2_PA3FX2_PA2FX2_PA0FX2_PA1
FX2_FLAGBFX2_SCLFX2_FLAGC
FX2_SDA MAX_SDAFX2_FLAGA
FX2_PB2FX2_PB0FX2_PB5FX2_PB1FX2_PB7FX2_PB6
C10_M10_IO2
FX2_PB4FX2_PB3
M10_CLK50M
VCC_3.3V VCC_3.3V
VCC_3.3V
VCC_3.3V
USB_5V
VCC_3.3V
VCC_3.3VVCC_3.3V
VCC_3.3V
USB_5V
USB_CLK<5>
C10_NSTATUS<4>C10_CONF_DONE<5>SYS_CONF_DONE<14>
M10_CLK50M<15>
C10_CRC_ERROR<5>
C10_M10_IO[3:0]<5>
C10_INIT_DONE<5>
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
7 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
7 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
7 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
R47 10K
C15DNI
R50 DNI
VBUSD-
D+
ID
J17USB MINI-B
12345
6789
C10
0.1uF
R213 DNI
MAX10 10M08SA U169
U3D
IO_3_L5/DIFFIO_TX_RX_B1NL5
IO_3_M4/DIFFIO_RX_B2NM4
IO_3_L4/DIFFIO_TX_RX_B1PL4
IO_3_M5/DIFFIO_RX_B2PM5
IO_3_K5/DIFFIO_TX_RX_B3NK5
IO_3_N4/DIFFIO_RX_B4NN4
IO_3_J5/DIFFIO_TX_RX_B3PJ5
IO_3_N5/DIFFIO_RX_B4PN5
IO_3_N6/DIFFIO_TX_RX_B5NN6
IO_3_N7/DIFFIO_RX_B6NN7
IO_3_M7/DIFFIO_TX_RX_B5PM7
IO_3_N8/DIFFIO_RX_B6PN8
IO_3_J6/DIFFIO_TX_RX_B7NJ6
IO_3_M8/DIFFIO_RX_B8NM8
IO_3_K6/DIFFIO_TX_RX_B7PK6
IO_3_M9/DIFFIO_RX_B8PM9
IO_3_J7/DIFFIO_TX_RX_B9NJ7
IO_3_K7/DIFFIO_TX_RX_B9PK7
IO_3_N12N12
IO_3_M13/DIFFIO_TX_RX_B10NM13
IO_3_N10/DIFFIO_RX_B11NN10
IO_3_M12/DIFFIO_TX_RX_B10PM12
IO_3_N9/DIFFIO_RX_B11PN9
IO_3_M10/DIFFIO_TX_RX_B16NM10
IO_3_L10/DIFFIO_TX_RX_B16PL10
IO_3_K8/DIFFIO_TX_RX_B14PK8
IO_3_J8/DIFFIO_TX_RX_B14NJ8
IO_3_L11/DIFFIO_TX_RX_B12PL11
IO_3_M11/DIFFIO_TX_RX_B12NM11
R33 10K
U6
CY7C68013A_QFN
RDY01
RDY12
XTALIN5
AVCC03
DMINUS9
AGND06
VCC011
GND012
PD752
CLKOUT54
XTALOUT4
AVCC17
DPLUS8
AGND110
IFCLK13
RESERVED14
PD550PD449
PD651
SCL15
SDA16
PB018
GND126
GND228
GND341
PB119
PB321PB220
VCC117
VCC227
PB624PB523PB422
PD348PD247
PA740
PA437
PA134
PB725
PD146
WAKEUP44
PA639
GND453
VCC443
PA336
CTL130CTL029
PD045
RESET42
PA538
GND556
VCC555
PA235
PA033
CTL231
VCC332
EXPOSED_PAD57
R38 10K
R293 DNI
C5
12pF
R27100K
C9
0.1uF
R32
20K
MAX10 10M08SA U169
U3C
IO_2_M3/PLL_L_CLKOUTN/DIFFIO_RX_L27NM3
IO_2_L3/PLL_L_CLKOUTP/DIFFIO_RX_L27PL3
IO_2_J1/DIFFIO_RX_L19NJ1
IO_2_J2/DIFFIO_RX_L19PJ2
IO_2_M1/DIFFIO_RX_L21NM1
IO_2_M2/DIFFIO_RX_L21PM2
IO_2_L2L2
IO_2_K1/DIFFIO_RX_L28NK1
IO_2_K2/DIFFIO_RX_L28PK2
C202
1nF/3kV
R43 10K
R30 2K
R39 10K
C8
0.1uF
R29 2K
R35 0
Y1
24.00MHz
1 3
24
C2
0.1uF
C4
12pF
R31 10K
U4
ADM811
GND1
RESET2
VCC4
MR3
R42 10K
C7
0.1uF
U5
TPD2EUSB30
D-2D+1
GND3
R44 DNIMAX10 10M108SA U169
U3H
IO_2_G5/CLK0N/DIFFIO_RX_L18NG5
IO_2_H6/CLK0P/DIFFIO_RX_L18PH6
IO_2_H5/CLK1N/DIFFIO_RX_L20NH5
IO_2_H4/CLK1P/DIFFIO_RX_L20PH4
IO_2_N2/DPCLK0/DIFFIO_RX_L22NN2
IO_2_N3/DPCLK1/DIFFIO_RX_L22PN3
IO_6_G9/CLK2P/DIFFIO_RX_R14PG9
IO_6_G10/CLK2N/DIFFIO_RX_R14NG10
IO_6_F13/CLK3P/DIFFIO_RX_R16PF13
IO_6_E13/CLK3N/DIFFIO_RX_R16NE13
IO_6_F9/DPCLK3/DIFFIO_RX_R26PF9
IO_6_F10/DPCLK2/DIFFIO_RX_R26NF10
IO_1B_H1/VREFB1N0H1
IO_2_L1/VREFB2N0L1
IO_3_N11/VREFB3N0N11
IO_5_K13/VREFB5N0K13
IO_6_D13/VREFB6N0D13
IO_8_B7/VREFB8N0B7
R36 0
J1
DNI
11
33
55
77
22
44
66
88
99
1010
C6
0.1uF
C14
0.1uF
R2470
R260
R41 10K
C13
0.1uF
C16
0.1uF
R37 0
R46 10K
C12
0.1uF
R34 0
R40 10K
MAX10 10M08SA U169
U3I
IO_1B_E5/JTAGENE5
IO_1B_G1/TMS/DIFFIO_RX_L11NG1
IO_1B_G2/TCK/DIFFIO_RX_L11PG2
IO_1B_F5/TDI/DIFFIO_RX_L12NF5
IO_1B_F6/TDO/DIFFIO_RX_L12PF6
IO_8_B9/DEV_CLRN/DIFFIO_RX_T16NB9
IO_8_D8/DEV_OE/DIFFIO_RX_T18PD8
IO_8_D7/CONFIG_SELD7
INPUT_ONLY_8_E7/NCONFIGE7
IO_8_D6/CRC_ERROR/DIFFIO_RX_T22ND6
IO_8_C4/NSTATUS/DIFFIO_RX_T24PC4
IO_8_C5/CONF_DONE/DIFFIO_RX_T24NC5
C11
0.1uF
R45 1K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB Blaster Programming Header
MAX10 USB Interface
C10 JTAG
System I2C
Arduino ADC I2C
(uses JTAG mode only)
VCCIO=2.5V
Power Good
C10_JTAG_TDIC10_JTAG_TCKC10_JTAG_TMSC10_JTAG_TDO
ARDUINO_ADC_SCLARDUINO_ADC_SDA
USB_DISABLEn
SYS_I2C_SCLSYS_I2C_SDA
VCC_3.3V_PGVCC_1.2V_PG
PWR_GD_LED
EXT_JTAG_TDOEXT_JTAG_TMS
EXT_JTAG_TDIEXT_JTAG_TCK
USB_DISABLEn
VTAP_BYPASSn
EXT_JTAG_TDOEXT_JTAG_TMS
EXT_JTAG_TDI
EXT_JTAG_TCK
USB_ADDR0
USB_ADDR1
USB_DATA0
USB_DATA1
USB_DATA2
USB_DATA3USB_DATA4
USB_DATA5
USB_DATA6USB_DATA7
USB_EMPTY
USB_FULL
USB_OEnUSB_RDn
USB_RESETn
USB_SCL
USB_SDA
USB_WRn
M10_VCCIO1AVCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
M10_VCCA_3.3VVCC_3.3V
VCC_3.3V
VCC_2.5V
VCC_3.3V
VCC_3.3V
VCC_3.3V
SYS_I2C_SDA<15>
USB_RDn<5>
USB_DATA[7:0]<5>
USB_ADDR[1:0]<5>
USB_FULL<5>USB_EMPTY<5>USB_SCL<5>USB_SDA<5>
USB_OEn<5>
C10_JTAG_TDI<4>C10_JTAG_TDO<4>
C10_JTAG_TMS<4>C10_JTAG_TCK<4>
USB_WRn<5>
USB_RESETn<5>
SYS_I2C_SCL<15>
VTAP_BYPASSn<14>
ARDUINO_ADC_SDA<5>ARDUINO_ADC_SCL<5>
PWR_GD_LED<14>
VCC_1.2V_PG<17>VCC_3.3V_PG<17>
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
8 17Monday, June 26, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
8 17Monday, June 26, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
8 17Monday, June 26, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
MAX10 10M08SA U169
U3F
IO_6_F12/DIFFIO_RX_R18PF12
IO_6_E12/DIFFIO_RX_R18NE12
IO_6_C13C13
IO_6_F8/DIFFIO_RX_R27PF8
IO_6_B12/DIFFIO_RX_R28PB12
IO_6_E9/DIFFIO_RX_R27NE9
IO_6_B11/DIFFIO_RX_R28NB11
IO_6_C12/DIFFIO_RX_R29PC12
IO_6_B13/DIFFIO_RX_R30PB13
IO_6_C11/DIFFIO_RX_R29NC11
IO_6_A12/DIFFIO_RX_R30NA12
IO_6_E10/DIFFIO_RX_R31PE10
IO_6_D9/DIFFIO_RX_R31ND9
IO_6_D12/DIFFIO_RX_R33PD12
IO_6_D11/DIFFIO_RX_R33ND11
R61 10K
C189
0.22uF
L21.5A, 180 Ohm FB
R56 2K
MAX10 10M08SA U169
U3G
IO_8_A8/DIFFIO_RX_T15PA8
IO_8_A9/DIFFIO_RX_T15NA9
IO_8_B10/DIFFIO_RX_T16PB10
IO_8_A10/DIFFIO_RX_T17PA10
IO_8_A11/DIFFIO_RX_T17NA11
IO_8_E8/DIFFIO_RX_T18NE8
IO_8_A7/DIFFIO_RX_T19PA7
IO_8_A6/DIFFIO_RX_T19NA6
IO_8_B6/DIFFIO_RX_T20PB6
IO_8_A4/DIFFIO_RX_T21PA4
IO_8_B5/DIFFIO_RX_T20NB5
IO_8_A3/DIFFIO_RX_T21NA3
IO_8_E6/DIFFIO_RX_T22PE6
IO_8_B3/DIFFIO_RX_T23PB3
IO_8_B4/DIFFIO_RX_T23NB4
IO_8_A5A5
IO_8_A2/DIFFIO_RX_T26PA2
IO_8_B2/DIFFIO_RX_T26NB2
IO_8_C10/DIFFIO_RX_T14PC10
IO_8_C9/DIFFIO_RX_T14NC9
L31.5A, 180 Ohm FB
R214 2K
R55 2K
R57 DNI
C177
10uF
C182
1uF
C18
0.1uF
R215 2K
C179
0.1uF
R54 1K
C178
0.1uF
R52 1K
C151
0.047uFMAX10 10M08SA U169
U3A
VCCIO1A__F2F2
VCCIO1B__G3G3
VCCIO2__K3K3
VCCIO2__J3J3
VCCIO3__L8L8
VCCIO3__L7L7
VCCIO3__L6L6
VCCIO5__J11J11
VCCIO5__H11H11
VCCIO6__G11G11
VCCIO6__F11F11
VCCIO8__C8C8
VCCIO8__C7C7
VCCIO8__C6C6
VCCA1__K4K4
VCCA2__D10D10
VCCA3__D4D4
VCCA4__K9K9
VCC_ONE__H7H7
VCC_ONE__G8G8
VCC_ONE__G6G6
VCC_ONE__F7F7
C176
10uF
C156
0.22uF
C180
0.1uF
J2
2X5_100mil
11
33
55
77
22
44
66
88
99
1010
C170.1uF
C146
4.7uF
C153
0.01uF
C181
0.1uF
MAX10 10M08SA U169
U3K
GND__A1A1
GND__A13A13
GND__B8B8
GND__C3C3
GND__D5D5
GND__E11E11
GND__F3F3
GND__G7G7
GND__H12H12
GND__J4J4
GND__L9L9
GND__M6M6
GND__N1N1
GND__N13N13
R51 1KR53 1K
R591K
MAX10 10M08SA U169
U3E
IO_5_K10/DIFFIO_RX_R1PK10
IO_5_J10/DIFFIO_RX_R1NJ10
IO_5_K11/DIFFIO_RX_R2PK11
IO_5_L12/DIFFIO_RX_R2NL12
IO_5_K12/DIFFIO_RX_R7PK12
IO_5_L13L13
IO_5_J12/DIFFIO_RX_R7NJ12
IO_5_J9/DIFFIO_RX_R8PJ9
IO_5_J13/DIFFIO_RX_R9PJ13
IO_5_H10/DIFFIO_RX_R8NH10
IO_5_H13/DIFFIO_RX_R9NH13
IO_5_H9/DIFFIO_RX_R10PH9
IO_5_G13/DIFFIO_RX_R11PG13
IO_5_H8/DIFFIO_RX_R10NH8
IO_5_G12/DIFFIO_RX_R11NG12
C155
0.01uF
R58 1K
C190
4.7uF
R60 10K
C157
0.01uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Arduino Analog IO
EXT_VREF
ADC1IN1
ADC1IN4
ADC1IN6ADC1IN7ADC1IN8
ADC1IN2
ADC1IN3
ADC1IN5
VCCINT_ISENSEVCCA_ISENSE
ANAIN1
VCCIO_3.3V_ISENSE
A4+ARDUINO_ANA4
ARDUINO_ANA5
A5+ARDUINO_AMP5
ARDUINO_AMP4ARDUINO_AMP4
ARDUINO_ANA0
ARDUINO_AMP1
ARDUINO_ANA1
ARDUINO_ANA2
ARDUINO_ANA3
ARDUINO_AMP5
A0+
A1+
ARDUINO_AMP0
ARDUINO_AMP1
ARDUINO_AMP0A2+
A3+
ARDUINO_AMP2
ARDUINO_AMP3
ARDUINO_AMP2
ARDUINO_AMP3
ARDUINO_AMP1
ARDUINO_AMP2
VCCINT_ISENSE
ARDUINO_AMP5
ARDUINO_AMP0
VCCA_ISENSE
VCCIO_3.3V_ISENSE
ARDUINO_AMP4
ARDUINO_AMP3
A_GND
A_GNDA_GND
A_GND
A_GND
C10_VCCINT VCC_1.2V
A_GND
C10_VCCA VCC_2.5V
A_GND
A_GND
VCC_3.3VC10_VCCIO_3.3V
A_GND
M10_VCCA_3.3VM10_VCCA_3.3VM10_VCCA_3.3V
EXT_VREF
A_GND
A_GND
A_GND
M10_VCCA_3.3V
A_GNDA_GND
A_GND
A_GND
A_GND
A_GND
M10_VCCA_3.3V
A_GND
A_GND
A_GND
M10_VCCA_3.3V
A_GND
EXT_VREF
EXT_VREF_AR
ARDUINO_ANA[0:5]<12>
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
9 17Thursday, June 29, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
9 17Thursday, June 29, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
9 17Thursday, June 29, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
L141.5A, 180 Ohm FB
C1691nF
R85 10R227 316
C33 1pF
R67100
R63 0.04
C34 1pF
C1680.1uF
R68100
R218316
R87 10
R65100
C35 1pF
R86 10
C29 1pF
MAX10 10M08SA U169
U3B
IO_1A_D1/ADC1IN1/DIFFIO_RX_L1ND1
IO_1A_C2/ADC1IN2/DIFFIO_RX_L1PC2
IO_1A_E3/ADC1IN3/DIFFIO_RX_L3NE3
IO_1A_E4/ADC1IN4/DIFFIO_RX_L3PE4
IO_1A_C1/ADC1IN5/DIFFIO_RX_L5NC1
IO_1A_B1/ADC1IN6/DIFFIO_RX_L5PB1
IO_1A_F1/ADC1IN7/DIFFIO_RX_L7NF1
IO_1A_E1/ADC1IN8/DIFFIO_RX_L7PE1
IO_1B_F4/DIFFIO_RX_L14NF4
IO_1B_G4/DIFFIO_RX_L14PG4
IO_1B_H2/DIFFIO_RX_L16NH2
IO_1B_H3/DIFFIO_RX_L16PH3
C36 1pF
C1730.1uF
C19
0.1uF
R66100
R219 316
U7
LT6105IMS8
-IN1
V+2
V-4
VOUT5
NC37+IN8
NC13
NC26
U11
LT6105IMS8
-IN1
V+2
V-4
VOUT5
NC37+IN8
NC13
NC26
R89 10
R220316
C20
DNI
C37 1pF
C1880.1uF
C1711nF
R88 10
C22
DNI
C38 1pF
R83 10
C1701nF
R90 10
C23
0.1uF
R223 316
C39 1pF
R724.99K
R91 10
R225 316
R222316
C26
0.1uF
U32
MCP6242-E/MS
VOUTA1VINA-
2
VINA+3
VS
S4
VD
D8
VOUTB7VINB-
6
VINB+5
R224316
R221 316
R714.99K
C1721nF
R64 0.2
C28
DNI
R228DNI C1741nF
R84 10
R77 0.2
R216316
MAX10 10M08SA U169
U3J
REFGND__E2E2
ADC_VREF__D3D3
ANAIN1__D2D2
C212
DNI
R226316
R217 316
U8
LT6105IMS8
-IN1
V+2
V-4
VOUT5
NC37+IN8
NC13
NC26
R814.99K
R78100
C1751nF
C213
DNI
R79100
U34
MCP6242-E/MS
VOUTA1VINA-
2
VINA+3
VS
S4
VD
D8
VOUTB7VINB-
6
VINB+5
C32 1pF
U33
MCP6242-E/MS
VOUTA1VINA-
2
VINA+3
VS
S4
VD
D8
VOUTB7VINB-
6
VINB+5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.8V I/O
HyperRAM (HyperBUS)
Reserved For MCP/Flash
Reserved For MCP/FlashHBUS_CS1n: For Flash (Reserved)HBUS_CS2n: For RAM
In customer's design, please consult with HyperRAM vendorto decide if need to assemble this parallel resister (R243) withspecified HyperRAM design
HBUS_CKpHBUS_CKn
HBUS_CS2n
HBUS_RSTn
HBUS_CKp
HBUS_CKn
HBUS_RSTn
HBUS_DQ3HBUS_DQ4HBUS_DQ5
HBUS_DQ7HBUS_DQ6
HBUS_RWDS
HBUS_DQ0HBUS_DQ1HBUS_DQ2
HBUS_CS1n
HBUS_RSTOnHBUS_INTn
HBUS_RSTOnHBUS_INTn
VCC_1.8V
VCC_1.8V
HBUS_DQ[7:0]<4>
HBUS_CKp<4>HBUS_CKn<4>
HBUS_CS2n<4>HBUS_RSTn<4>
HBUS_RWDS<4>
HBUS_CS1n<4>HBUS_RSTOn<4>HBUS_INTn<4>
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
10 17Monday, June 26, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
10 17Monday, June 26, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
10 17Monday, June 26, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
R920
C185
1uF
R24510K
HyperRAM
U13
IS66WVH16M8ALL-166B1LI
VSS1/DNPA1
RFU1A2
CS#A3
RESET#A4
RFU2A5
CK#B1 CKB2
VSS2B3
VCCB4
RFU3B5
VSSQ1C1
RFU4C2
RWDSC3
DQ2C4
RFU5C5
VCCQ1D1
DQ1D2 DQ0D3
DQ3D4
DQ4D5
DQ7E1 DQ6E2 DQ5E3
VCCQ2E4
VSSQ2E5
R262DNI
R256 33
R253 33
R250 33
C43
0.1uF
C40
10uF
C41
0.1uF
R259DNI
R257 33
R254 33
R251 33
R258DNI
R261DNI
C183
1uF
R243100
C184
0.1uF
C42
0.1uFR255 33
R260DNI
R252 33
R249 33
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Rcal for calibration
LED0
LED1
LED2
ADR[3]
ADR[4]
CONF[1]
0
0
ADR[2] 0 ADR[1] 0 ADR[0] 0
MODE[1] 0 MODE[0] 0 FLOW 0
CONF[0] ANEG[1] ANEG[0]0 1 0 0
11K+DNI
11K+DNI
3.92K+DNI
CBV[3] CBV[2] CBV[1] CBV[0] Rcfg + Ccfg
Ethernet RGMII
IND 4.7uH 850mA 310mOhm
NET
NET_LED2
NET_LED1
ON
Link-up
100Mbps
OFF
Link-down
Other Status
Blink
Traffc
N/A
NET_LED0
1000Mbps Other Status N/A
RG_RXCLKRG_RXCTLRG_RXD0RG_RXD1RG_RXD2RG_RXD3
ENET_RG_RXCLKENET_RG_RXCTLENET_RG_RXD0ENET_RG_RXD1ENET_RG_RXD2ENET_RG_RXD3
ENET_RG_TXCLKENET_RG_TXCTLENET_RG_TXD0ENET_RG_TXD1ENET_RG_TXD2ENET_RG_TXD3
TPIDNTPIDPTPICNTPICPTPIBNTPIBPTPIANTPIAP
ENET_RSTnENET_MDC
ENET_INT
ENET_TDOENET_TDIENET_TMSENET_TCK
ENET_XTAL1ENET_XTAL2
ENET_LED0ENET_LED1ENET_LED2
ENET_REGO
ENET_LED0
ENET_LED1
ENET_LED2
ENET_XTAL1ENET_XTAL2
MX4-MX4+
MX1+MX1-MX2+MX3+MX3-MX2-
ENET_MDIOENET_VDD_3.3V
VCC_3.3V ENET_VDD_3.3V
ENET_VDD_3.3V
ENET_VDD_1V
ENET_VDD_1V
ENET_VDD_3.3VENET_VDD_3.3V
ENET_VDD_3.3V
ENET_VDD_3.3V
ENET_VDD_3.3V
ENET_RG_TXCLK<5>ENET_RG_TXCTL<5>
ENET_RG_TXD0<5>ENET_RG_TXD1<5>ENET_RG_TXD2<5>ENET_RG_TXD3<5>
ENET_RG_RXCLK<5>ENET_RG_RXCTL<5>
ENET_RG_RXD0<5>ENET_RG_RXD1<5>ENET_RG_RXD2<5>ENET_RG_RXD3<5>
ENET_MDC<5>
ENET_INT<5>ENET_MDIO<5>
ENET_RSTn<5>
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
11 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
11 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
11 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
R955.1
C64
0.1uF
R242 390
U14
PEF7071
MDC41
MDIO42
MDINT47
LED024
LED123
LED222
SCL43
SDA44
TX_CLK9
TX_CTL15
TXD014
TXD112
TXD211
TXD310
RX_CLK6
RX_CTL48
RXD05
RXD14
RXD23
RXD31
RSTn16
XTAL136
XTAL237
CLKOUT46
TDO21
TDI18
TMS20
TCK19
TPIDN34
TPIDP33
TPICN32
TPICP31
TPIBN29
TPIBP28
TPIAN27
TPIAP26
RE
GO
39
VD
DL
17
VD
DC
313
VD
DC
18
VD
DC
240
VD
DH
125
VD
DH
230
VD
DH
335
VD
DR
38
VD
DP
12
VD
DP
27
VD
DP
345
EPAD49
TP7
R297DNI
R11016K
C57
0.1uF
C161 68pF
R981K
R307 0
R103 33
C162 68pF
Y2
25.00MHz
13
2 4
C49
10uF
R102 33
R100 499
R971K
R104 33
C47330pF
C163 68pF
R20
87
5
R10911K
R11211K
R240 390
C60
0.1uF
C44 27pF
C55 DNI
R105 33
C58
0.1uFC159
1nF/3kV
C4522uF
C56 DNI
C65 DNI
R101 10K
D10GREEN_LED
C59
10uFD11GREEN_LED
C50
0.1uF
L94.7uH
1 2
PHY Cable
U28
749020010A
TCT11
TD1+2
TD1-3
TCT24
TD2+5
TD2-6
TCT37
TD3+8
TD3-9
TCT410
TD4+11
TD4-12
MCT124
MX1+23
MX1-22
MCT221
MX2+20
MX2-19
MCT318
MX3+17
MX3-16
MCT415
MX4+14
MX4-13
R21
07
5
C46330pF
C51
0.1uF
R20
97
5
R106 33
R241 390
C52
0.1uF
R10816K
R28 DNI
C63
10uF
R21
17
5
TP5
C54
DNI
C62
0.1uF
R107 33
D12GREEN_LED
J16
615008140121
1+1 1-2 2+3 3+4 3-5 2-6 4+7 4-8
CGND113CGND214
C160 68pF
R991K
C164
1nF/3kV
TP6
R1143.92K
C53 27pF
C61
0.1uF
C48
10uFR961K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Arduino
ARDUINO_IO0ARDUINO_IO1ARDUINO_IO2ARDUINO_IO3ARDUINO_IO4ARDUINO_IO5ARDUINO_IO6ARDUINO_IO7
ARDUINO_IO8ARDUINO_IO9ARDUINO_IO10ARDUINO_IO11ARDUINO_IO12ARDUINO_IO13GNDANA_VREFARDUINO_SDAARDUINO_SCL
ARDUINO_ANA5ARDUINO_ANA4ARDUINO_ANA3ARDUINO_ANA2ARDUINO_ANA1ARDUINO_ANA0
VCC_5V (Reserved)GNDGNDVCC_5V_AR1VCC_3.3VARDUINO_RSTnIOREF(3.3V)NC
J5
J7J6
J4
J18
Arduino Digital IO
Arduino Analog IO
Arduino I2C
Arduino Power Output Capability3.3V: J4.2, J4.4 100mA Max. total5V: J4.5, J18.2 500mA Max. totalUsing external adaptor power input (J12)
ARDUINO_IO8ARDUINO_IO9ARDUINO_IO10ARDUINO_IO11ARDUINO_IO12ARDUINO_IO13
ARDUINO_IO1ARDUINO_IO0
ARDUINO_IO7ARDUINO_IO6ARDUINO_IO5ARDUINO_IO4ARDUINO_IO3ARDUINO_IO2
ARDUINO_SDAARDUINO_SCL
ARDUINO_ANA0ARDUINO_ANA1ARDUINO_ANA2ARDUINO_ANA3
ARDUINO_ANA5ARDUINO_ANA4
IOREFARDUINO_RSTn
ARDUINO_IO11
ARDUINO_IO12
ARDUINO_IO13
ARDUINO_RSTn
ANA_VREFEXT_VREF_AR
A_GND
VCC_5V
VCC_3.3V
VCC_5V_AR1
VCC_5V_AR2
VCC_5V VCC_5V_AR1
EXT_VREF
VCC_5V
A_GND
ARDUINO_IO[13:0]<4>
ARDUINO_RSTn<4>
ARDUINO_ANA[0:5]<9>
ARDUINO_SDA<4>ARDUINO_SCL<4>
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
12 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
12 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
12 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
J561301011821
11 22 33 44 55 66 77 88 99 10
10
J6
61300611821
112233445566
R308DNI
J18
61300621121
2
3 4
1
5 6
J4
61300811821
1122334455667788
R295 DNI
R2800
R275 DNI
U12
REF3130/DNI
VIN1
VOUT2
GND3
F31A
J7
61300811821
11 22 33 44 55 66 77 88
C30
DNI
F2 1A
C31DNI
L5DNI
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PMOD
2x20pin GPIO Header
PMOD Specification not specified module power consumption but assumed no more than approximately 100mA.
2x20 GPIO
PMOD
PMOD_IO3PMOD_IO2PMOD_IO1PMOD_IO0 PMOD_IO4
PMOD_IO5
VCC_3.3V VCC_3.3V
PMOD_IO3PMOD_IO2PMOD_IO1PMOD_IO0 PMOD_IO4
PMOD_IO5PMOD_IO6PMOD_IO7
GPIO0 GPIO1GPIO2GPIO4GPIO6GPIO8
PMOD_D0
PMOD_D7
GPIO10GPIO12GPIO14GPIO16GPIO18GPIO20GPIO22GPIO24
GPIO26GPIO28GPIO30GPIO32GPIO34
GPIO3GPIO5GPIO7GPIO9
GPIO13GPIO15GPIO17
GPIO11
GPIO21GPIO23GPIO25
GPIO19
GPIO29GPIO31GPIO33
GPIO27
GPIO35
PMOD_IO6PMOD_IO7
PMOD_D1PMOD_D2PMOD_D3
PMOD_D5PMOD_D4
PMOD_D6
VCC_3.3VVCC_3.3V
VCC_3.3V
VCC_5V_GPIO
VCC_3.3V VCC_3.3V
VCC_5V
GPIO[0:35]<4,5>
PMOD_D[0:7]<5>
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
13 17Monday, July 24, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
13 17Monday, July 24, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
13 17Monday, July 24, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
R123 200
U15
824013
IO11
IO23
IO34
IO46
VDD5
GND2
R119 200
J10
Header 2x20 Shrouded
11
33
55
77
99
1111
1313
1515
1717
1919
22
44
66
88
1010
1212
1414
1616
1818
2020
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
2222
2424
2626
2828
3030
3232
3434
3636
3838
4040
R269DNI
R116 200
R120 200
R265 DNIR270DNI R266 DNI
R121 200R118 200
F1 1A
R117 200
U16
824013
IO11
IO23
IO34
IO46
VDD5
GND2
R122 200
J8
2x6 PMOD Connector
11
77
22
88
33
99
44
1010
55
1111
66
1212
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ON = 0OFF = 1
Logic 0 = Vitual JTAG BypassLogic 1 = Vitual JTAG Enable
POWER LED
Configuration LED
User LED
DIP Switches
Push Buttons
C10_NCONFIG
C10_RESETn
SYS_CONF_DONE_RSYS_CONF_DONE
USER_LED0_R
USER_LED1_R
USER_LED2_R
USER_LED3_R
USER_LED0
USER_LED1
USER_LED2
USER_LED3
USER_PB0
USER_PB1
USER_PB2
USER_PB3
USER_DIP2USER_DIP1USER_DIP0VTAP_BYPASSn
PWR_GD_LED
REG_PG_LED_R
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_5V
C10_NCONFIG<4>
C10_RESETn<5>
SYS_CONF_DONE<7>
VTAP_BYPASSn<8>
USER_LED[0:3]<5>
USER_PB[0:3]<5>
USER_DIP[0:2]<5>
PWR_GD_LED<8>
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
14 17Monday, July 24, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
14 17Monday, July 24, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
14 17Monday, July 24, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
R138 390
S2 PB Switch1 2
C206 0.1uF
R148 10K
R143 390
Q5
FDV305N
D6 GREEN_LED
R235 1K
OPEN
SW1
DIPSWITCH4
1234 5
678
R137 10K
D4 BLUE LED
D9 GREEN_LED
R145 10K
R142 390
S3 PB Switch1 2
D5 YELLOW_LED
C205 0.1uF
R141 10KD8 GREEN_LEDS5 PB Switch
1 2
R140 390
S1 PB Switch1 2
R146 10K
C204 0.1uF
D7 GREEN_LED
R309DNI
R135 390
C208 0.1uF
C209 0.1uF
R147 10K
R139 10KC207 0.1uF
R144 10K
S4 PB Switch1 2
S6 PB Switch1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
3.3V CMOS3.3V CMOS
3.3V CMOS
3.3V CMOS
Use Clock GUI to Program Si5351ADefault Prequency:CLK0: 125MHzCLK1: 100MHzCLK2: 50MHzI2C Address: 0x60
3.3V CMOS
Si5351A
50MHz Oscillator
System I2C
Clocks
3.3V_SI510M10_CLK50MC10_CLK50M
M10_CLK50M_RC10_CLK50M_R
XAXB
SYS_I2C_SDASYS_I2C_SCL
HBUS_CLK_50M
ENET_CLK_125MC10_CLK_ADJ
VCC_3.3V
VCC_3.3V VCC_3.3V
M10_CLK50M<7>
C10_CLK50M<4>
ENET_CLK_125M<4>
HBUS_CLK_50M<5>
C10_CLK_ADJ<5>
SYS_I2C_SCL<8>SYS_I2C_SDA<8>
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
15 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
15 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
15 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
R264 0
R160 33
C67
0.1uF
R162 33
R152 0
C66 DNI
R155 0
R157 0
Y3
25.00MHz1
324
L161.5A, 180 Ohm FB
U20
510MCA50M0000AAGR
VDD6
GND3
NC1
CLKp/14
CLKn/25
OE2
L101.5A, 180 Ohm FB
C74
0.1uF
L121.5A, 180 Ohm FB
C73 DNI
C72
0.1uFU31
Si5351A-B07321-GT
VDD1
XA2
XB3
SCL4
SDA5
CLK010
CLK19
GND8
VDDO7
CLK26
R263 0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
5V DC InputID=2.1mm,OD=5.5mm
5V Input Selection, Protection and Control
VCC_5V_IN5V_DCIN
VCC_5V
USB_5V
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
16 17Tuesday, August 01, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
16 17Tuesday, August 01, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
16 17Tuesday, August 01, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
C200
DNI
TP12
R290 1K
TP13
C210
DNI
R165 DNI
C201
0.47uF
C76
47uF
TP14
R164 DNI
TP15
J12
DC Input Jack
123
R300DNI
TP16 TP17
Q29
MMST3906-7-FSOT-323
R29110K
R289300
C203 DNI
TP18R173
1K
Q30DNI
SD
G
D28
BZX84C5V1 5.1V-ZENER
R29410
R298DNI
R296 DNI
Q15DMG2305UX
S D
G
R299DNI
C211
DNI
R29210K
D20 DFLS2402 1
D41 PMEG3050EP
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC_1.2V (1.2V@2A Max.) VCC_1.8V ([email protected] Max.)
VCC_2.5V ([email protected] Max.)VCC_3.3V (3.3V@3A Max.)
VCC_1.2V_EN
VCC_1.2V_PG
VCC_1.2V_FB
VCC_1.8V_EN
1.8V_VSENSE
VCC_2.5V_EN
2.5V_VSENSE
VCC_3.3V_EN
VCC_3.3V_PG
VCC_3.3V_FB
VCC_5V
VCC_1.2V
VCC_5V
VCC_1.8VVCC_5V
VCC_2.5VVCC_5V
VCC_3.3V
VCC_3.3VVCC_5V
VCC_5V
VCC_3.3V
VCC_1.2V_PG<8>
VCC_3.3V_PG<8>
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
17 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
17 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
Title
Size Document Number Rev
Date: Sheet o f
A1
Cyclone 10 LP FPGA Evaluation Kit Board
B
17 17Tuesday, May 16, 2017
150-0321321-A1 (6XX-44504R)
Intel Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
Copyright (c) 2016, Intel Corporation All Rights Reserved
C89
1uF
C103
DNI
R178100K
TP20
C107
10uF
C165
DNI
C108
10uF
C101
DNI
C98
22uF
R198
0
R17910K
C99
22uF
C166
DNI
C88
DNI
C96
22uF
C86
47uF
C97
8.2pF
C111
DNI
U27
EP5358HUI
NC11
PGND2
PGND3
VFB/NC44
VSENSE5
AGND6
VOUT7
VOUT8
VS29 VS1
10 VS011
ENABLE12
AVIN13
PVIN14
NC1515
NC1616
C83
22uF
TP21
C104
DNI
C100
DNI
R20010K
R2010
C85
47uF
C87
DNI
TP19 C106
4.7uF
R197
0
R180
348K
C112
DNI
C113
DNI
EN5329QI
U25
PGND2
PGND3
PGND8
PGND9
TST210
TST111
TST012
NC
13
AGND15
AVIN16
ENABLE18
PVIN19
PVIN20
NC
(SW
)01
NC
(SW
)121
NC
(SW
)222
NC
(SW
)323
NC
(SW
)424
VOUT4
VOUT5
VOUT6
VOUT7
VFB14
POK17
PG
ND
25
PG
ND
26
R19010K
TP22
C110
10uF
R181
76.8K
C114
DNI
U26
EP5358HUI
NC11
PGND2
PGND3
VFB/NC44
VSENSE5
AGND6
VOUT7
VOUT8
VS29 VS1
10 VS011
ENABLE12
AVIN13
PVIN14
NC1515
NC1616
R189100K
C109
10uF
C105
4.7uF
EN5339QI
U23
PGND2
PGND3
PGND8
PGND9
TST210
TST111
TST012
NC
13
AGND15
AVIN16
ENABLE18
PVIN19
PVIN20
NC
(SW
)01
NC
(SW
)121
NC
(SW
)222
NC
(SW
)323
NC
(SW
)424
VOUT4
VOUT5
VOUT6
VOUT7
VFB14
POK17
PG
ND
25
PG
ND
26
C102
1uF
R192
340K
R19910K
C84
8.2pF
R191
348K