capture-power-safe test pattern determination for at-speed scan-based testing

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 1, JANUARY 2014 127

Capture-Power-Safe Test Pattern Determination forAt-Speed Scan-Based Testing

Yi-Hua Li, Wei-Cheng Lien, Student Member, IEEE, Ing-Chao Lin, Member, IEEE, Kuen-Jong Lee, Member, IEEE

Abstract—During an at-speed scan-based test, excessive cap-ture power may cause significant current demand, resulting inthe IR-drop problem and unnecessary yield loss. Many methodsaddress this problem by reducing the switching activities ofpower-risky patterns. These methods may not be efficient whenthe number of power-risky patterns is large or when some ofthe patterns require extremely high power. In this paper, wepropose discarding all power-risky patterns and starting withpower-safe patterns only. Our test generation procedure includestwo processes, namely, test pattern refinement and low-powertest pattern regeneration. The first process is used to refine thepower-safe patterns to detect faults originally detected only bypower-risky patterns. If some faults are still undetected after thisprocess, the second process is applied to generate new power-safepatterns to detect these faults. The patterns obtained using theproposed procedure are guaranteed to be power-safe for the givenpower constraints. To the best of our knowledge, this is the firstmethod that refines only the power-safe patterns to address thecapture power problem. Experimental results on ISCAS’89 andITC’99 benchmark circuits show that an average of 75% of faultsoriginally detected only by power-risky patterns can be detectedby refining power-safe patterns and that most of the remainingfaults can be detected by the low-power test generation process.Furthermore, the required test data volume can be reduced by12.76% on average with little or no fault coverage loss.

Index Terms—At-speed testing, low capture power testing,scan-based testing, transition fault.

I. Introduction

SCAN-BASED testing is the most widely used design fortest (DFT) methodology due to its simple structure, high

fault coverage, and strong diagnostic support [20]. However,the test power of scan tests may be significantly higher thannormal functional power because circuits may enter nonfunc-tional states during testing [29]. The test power required toload or unload test data with shift clock control is called

Manuscript received April 3, 2013; revised June 29, 2013 and August 13,2013; accepted August 17, 2013. Date of current version December 16, 2013.This work was supported by the National Science Council of Taiwan, underGrant NSC 100-2221-E-006-177, Grant NSC 102-2221-E-006 -281, and GrantNSC102-2221-E-006-266-MY3. This paper was recommended by AssociateEditor X. Wen.

Y.-H. Li is with Storart Technology Co., Ltd., Taiwan (e-mail:[email protected]).

I.-C. Lin is with the Department of Computer Science and InformationEngineering, National Cheng Kung University, Tainan 701, Taiwan (e-mail:[email protected]).

W.-C. Lien and K.-J. Lee are with the Department of Electronic En-gineering, National Cheng Kung University, Tainan 701 Taiwan (e-mail:[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCAD.2013.2282281

shift power, and the power required to capture test responseswith an at-speed clock rate is called capture power. Excessiveshift power can lead to high temperatures that can damagethe circuit under test (CUT) and may reduce the circuit’sreliability. Excessive capture power induced by test patternsmay lead to large current demand and induce a supply voltagedrop, known as the IR-drop problem [12]. This would causea normal circuit to slow down and eventually fail the test,thereby inducing unnecessary yield loss.

To estimate shift power and capture power, several metricshave been proposed. Among these metrics, the one employingthe circuit level simulation may be the most accurate one[1]. However, this method is time consuming and memoryintensive. Thus, most previous works use simpler metrics.The toggle count metric considers the state changes of nodes(FFs or gates) and the weighted switching activity (WSA)[7], [9], [10], [26] metric considers both node state changesand fanouts of nodes. Metrics that consider paths are alsoproposed. The critical capture transition (CCT) metric assesseslaunch switching activities around critical paths [24], and thecritical area targeted (CAT) metric estimates launch switchingactivities caused by test patterns around the longest sensitizedpath [3]. In this paper, we will employ the WSA metric as it ishighly correlated to the real capture power and has been usedin most related work to determine power-safe test patterns [7],[9], [10], [26]. Also we will focus on the capture-power-safepatterns.

To address the capture-safe-power problem, numerous meth-ods have been proposed. These methods can generally beclassified into hardware- and software-based methods. Thehardware-based methods [1]–[5], [11], [13], [14] attempt toreduce test power by modifying the circuit/clock in test struc-tures or by adding some additional hardware to the CUT. In[5] and [11], scan chain segmentation methods are proposed toreduce both shift and capture power. In [14], a partial launch-on-capture (LOC) scheme is proposed to reduce the capturepower, which allows only partial scan cells to be activatedduring the capture cycle. Some clock gating schemes havealso been proposed to limit the test power consumption [1],[4], [13]. In general, the hardware-based methods effectivelyreduce test power. However, they may increase circuit areaand degrade circuit performance, and may be incompatiblewith existing design flows.

The software-based methods attempt to generate power-safe test patterns that will not consume excess power duringtesting by modifying the traditional automatic test pattern

0278-0070 c© 2014 IEEE

128 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 1, JANUARY 2014

generation (ATPG) procedure [17], [18], [23] or by modifyingpredetermined test sets. These methods are generally basedon the X-filling technique to assign fixed logic values todon’t care bits (X-bits) in test patterns to minimize test powerdissipation. Devanathan et al. [17] and Wu et al. [18] modifiedthe PODEM-based ATPG procedure by adding some powerconstraints to the backtrace and dynamic compaction processesto directly generate power-safe test sets. In [23], a low-capture-power (LCP) X-filling method is proposed and incorporatedinto the dynamic compaction process of the test generationflow to reduce the capture power. Although these methodscan achieve a large reduction in capture power, they oftenincrease the test data volume in comparison with that producedby conventional at-speed scan test methods due to the fact thatduring the dynamic compaction process, many X-bits that canbe assigned to detect more faults are reserved to reduce capturepower.

Instead of modifying the ATPG procedure, some post-ATPGmethods modify a given test set by using X-filling to reduceas much test power as possible [7], [10], [16] or to satisfy thepower constraints [6], [21], [26]. Butler et al. [16] proposea method, named adjacency fill, which assigns deterministicvalues to the X-bits in line with the adjacent bit valuesto reduce shift power. For example, given the test pattern(1, X, X, 1, 0), the X-bits in this pattern are filled as(1, 1, 1, 1, 0). Remersaro et al. [10] proposes preferred fill toreduce the capture power. This method fills X-bits accordingto the signal probability of pseudo primary outputs (PPOs). Inthis approach, the X-bits in primary inputs (PIs) and pseudoprimary inputs (PPIs) are first randomly filled with the one-probability of 0.5. The output signal probability of each gate isthen calculated and propagated to the PPOs. The logic valuesfor X-bits in PPIs are then updated to 0 if zero has higherpossibility in the corresponding PPOs; otherwise, they are setto one. All of the X-bits in PPIs are updated only once toachieve high scalability.

Another method to reduce the capture power is to use thecircuit’s steady states to fill X-bits [7]. This method, calledACF in [7], first fills X-bit randomly. Then, it applies a numberof functional clock cycles starting from the scan-in state of atest vector to obtain the final states and uses these states tofill the X-bits to get more realistic patterns. Although boththe Preferred Fill and the ACF methods can quickly assignthe X-bits in PPI, they cannot ensure capture power safetybecause they do not consider the power constraint of thecircuit. Another problem with the above two methods is thatthey try to assign values to all X-bits in all test patterns toreduce test power as much as possible. However, not all ofthe test patterns are power-risky [19]. For patterns that arepower-safe, it is not necessary to reduce their capture power.

Li et al. [6] proposed iFill to reduce both shift and capturepower. This method tries to fill as few X-bits as possible tomaintain the capture power within the power constraint. Theremaining X-bits are then filled to reduce the shift poweras much as possible. However, since power-risky patternsoften have a small amount of X-bits, as illustrated below, theconsumed power may be still higher than the capture powerconstraint even after X-filling.

Some other post-ATPG methods [21], [26] combineX-filling with X-identification [8] to reduce the capture powerof fully-specified test sets. The X-identification process isconducted to identify the bits in power-risky patterns that canbe arbitrarily assigned without degrading the fault coverage.These bits are then filled by using X-filling to reduce thecapture power. These methods can reduce the capture powerof power-risky patterns. However, similar to iFill, power-riskypatterns tend to contain only a smaller number of X-bits, andthus, the efficiency of filling the X-bits of these patterns maynot be significant.

A. Overview of the Proposed Method

Unlike previous methods that reduce the capture power bymodifying power-risky patterns, this paper proposes modifyingonly power-safe patterns to address this issue. The rationalebehind this strategy is illustrated in Fig. 1. Fig. 1(a) showsthe relationship between the X-bit ratio and the switchingactivities, and Fig. 1(b) shows the relationship between theX-bit ratio and the detected fault count (in a log scale). It canbe seen that the patterns that can detect more faults normallyhave larger switching activity and lower X-bit ratios, and thenumber of detected faults decreases drastically with increasingX-bit ratio. Hence, filling X-bits in power-risky patterns maynot be efficient as they tend to have lower X-bit ratios. Incontrast, power-safe patterns usually have higher X-bit ratiosand many unused X-bits. Therefore, using the X-bits in power-safe patterns to detect faults within the power constraints maybe more efficient than using those in power-risky patterns.

Based on the above observation, this paper proposes a noveltest pattern determination procedure to determine a power-safe test set with the LOC clocking scheme. The proposedprocedure contains two processes, namely, test pattern re-finement and low-power test pattern regeneration. Given apregenerated compacted partially-specified test set without anypower constraints, the power-risky patterns are all dropped.This will make faults that were detected only by the power-risky patterns become undetected. The test pattern refinementprocess then tries to properly fill the X-bits in the power-safe patterns such that the power-risky faults can be detectedwith the power constraint still being satisfied. If some power-risky faults remain undetected after this process, the low-powertest pattern regeneration process is employed to generate morepower-safe test patterns for these faults.

B. Paper Contribution

The contributions of this paper can be summarized asfollows.

1) To the best of our knowledge, this is the first workthat refines the power-safe patterns rather than power-risky ones to address the capture power problem. Theexperimental results show that more than 75% of power-risky faults can be detected by refining the power-safepatterns.

2) The required test data volume is less than the originaltest data volume in most cases. This is because ourproposed procedure discards power-risky patterns and

LI et al.: CAPTURE-POWER-SAFE TEST PATTERN DETERMINATION FOR AT-SPEED SCAN-BASED TESTING 129

Fig. 1. Relationship between X-bit ratio, detected fault count, and switch-ing activity for s38417 test patterns. The patterns are filled with ACF.(a) Relationship between X-bit ratio and switching activities. (b) Relationshipbetween X-bit ratio and detected fault count.

does not require many new patterns to detect power-risky faults. Experimental results show that the test datavolume can be reduced by 12.76% on average undersome power constraints. A few cases with strict powerconstraint have a slight test data volume increase (0.57%increase on average).

3) The capture power reduction ratio of the proposed pro-cedure is not influenced significantly by the X-bit ratioin the patterns. This is because instead of filling X-bits inthe power-risky patterns to reduce capture power, power-risky patterns are discarded and power-safe patterns arerefined to detect power-risky faults. Experimental resultsshow the peak capture power is 27.7% to 53% less thanthat of ACF.

4) Extensive experiments are conducted to evaluate theeffectiveness of the proposed procedure. Experimentswith various power thresholds of 15% and 20% of themaximum weighted switching activity (WSA) as well asthe functional peak WSA are conducted. Experimentalresults show that the proposed procedure can effectivelyaddress the capture power issue with little or no loss offault coverage.

The rest of this paper is organized as follows. Section IIprovides the preliminaries. Section III presents the main ideaof this paper and the details of the proposed test pattern de-termination procedure. Experimental results and comparisonsare given in Section IV. Finally, conclusions are given inSection IV.F.

Fig. 2. At-speed scan testing with LOC scheme.

II. Preliminaries

This section first describes the LOC clocking scheme, whichis widely used to detect transition faults in scan-based designsand the capture power problem. Then, it introduces the powermetrics employed in this paper to verify the effectiveness ofthe proposed procedure.

A. Capture Power Problem in Scan-Based At-Speed Testing

The architecture of the scan-based design and the LOCclocking scheme are shown in Fig. 2. Depending on the scanenable signal, the circuit operates in either shift mode orcapture mode during testing.

In shift mode, where SE is one, the test pattern is shiftedinto scan cells by a series of low-speed test clock pulses toinitialize the circuit state. Once the pattern is shifted in, thecircuit operates in capture mode, where SE is 0. One clockpulse is then applied to the circuit to create the transition forthe target faults, and another clock pulse is then used to capturethe test response from the combinational logic of the circuitusing the at-speed functional clock. These two consecutiveclock pulses include a launch cycle (L) and a capture (C)cycle, as shown in Fig. 2. Finally, the test response in thescan cells is shifted out for observation with SE asserted, andthe next test pattern is shifted into the scan cells at the sametime.

During the LOC tests, the test pattern may cause excessiveswitching activity at the launch cycle, leading to large cur-rent demand and increased IR-drop. Increased IR-drop mayincrease the gate delay and lead to an incorrect test responsebeing captured at the capture cycle. An incorrect response willcause the circuit to be identified as defective, which resultsin test-induced yield loss and increased cost. Therefore, toprevent such test-induced yield loss, it is important to ensurecapture power safety during the launch cycle.

B. Capture-Power Calculation and Safety-Checking

As mentioned before, in this paper the WSA metric is usedto calculate the circuit’s switching activity. The WSA of a gateis the number of capture transitions (ti) at the gate multiplied


by (gate’s fanout + 1). If a transition (0 to 1 or 1 to 0) occursat gate i, ti is set to 1; otherwise ti is set to 0. If the gate isconnected directly to a primary output, then its fanout is setto 0. The WSA of whole circuit for one test pattern is the sumof the WSA for each gate in the circuit, shown as follows:

WSA =∑

∀gatei

ti×(fanouti + 1).

This WSA is called the maximum WSA, since all of thegates in the circuit transit in the launch.

Note that when calculating the capture power of partially-specified test patterns, it is necessary to estimate the number oftransitions caused by the X-bits at the internal gates. A simplemethod is to assign a weight to the transition (ti) of eachX-bit to calculate the switching activity with the previouslymentioned power metrics. However, it is difficult to determinea proper weight for an X-bit. If the weight of X-bits is toolarge, then a power-safe pattern may be incorrectly regarded asa power-risky pattern, and vice versa. Another method is to fillthe X-bits with 0 or 1 and then to calculate the capture powerof patterns. There has been extensive research on X-fillingtechniques, as mentioned in Section I. In this paper, the ACFX-filling technique is used to temporarily fill the X-bits andcalculate the capture power of partially-specified test patterns.The reason to choose the ACF X-filling technique is that theobtained capture power is lower than most other X-fillingtechniques [7], and thus, is a good candidate to calculate thecapture power of partially specified patterns before using ourproposed technique.

III. Capture-Power-Safe Test Pattern

Determination

This section first uses a simple example to illustrate themain idea of the proposed procedure. Then, it describes theoverall flow and its details.

A. Main Idea

The main idea of this paper is to utilize the X-bits inpower-safe patterns to detect as many faults that are previouslydetected only by power-risky patterns as possible. If there arestill undetected faults, then a low-power pattern generationprocess is used to generate patterns to detect the remainingfaults. The following is an example to illustrate the main idea.

Considering the circuit in Fig. 3, three transitionfaults, f 1, f 2, and f 3, are detected by two pattern pairsP1 = < v1,v2 > = < (X, X, 1, 0, 1, 0), (X, X, 1, 1, 0, 0) > andP2 = < v3, v4 > = < (0, X, 1, X, X, X), (1, X, 1, X, X, X) > .When pattern P1 is applied to the circuit, the output values ofgates N2, N4, N6, and N7 will switch and faults f 2 and f 3 canbe detected by P1. When pattern P2 is applied to the circuit,the output values of gate N5 will switch and fault f1 can bedetected by P2. The capture powers of P1 and P2 calculatedusing WSA are 6 (=2 + 2 + 1 + 1) and 1 (because gate N5, N6,and N7 are each connected to an output directly, and theirfanouts are set to 0), respectively.

If the power threshold Pth of this circuit is set to five and allof the wires with an X-signal have no transitions, the WSA

Fig. 3. Example of two partially-specified pattern pairs in the original ATPGtest set to detect the faults f 1 (N5 slow-to-rise), f 2 (N7 slow-to-fall) and f 3(N2 slow-to-rise). (a) Partially-specified pattern pair P1 detects f 2 and f 3.(b) Partially-specified pattern pair P2 detects f 1.

of P1 is higher than Pth, and the WSA of P2 is lower thanPth. Then, P1 is a power-risky pattern and P2 is a power-safepattern. Based on our main idea, pattern P1 is dropped since itsWSA is higher than Pth. Now, f2 and f3 become undetected. Toavoid fault coverage loss, the power-safe pattern P2 is refinedto detect more faults.

If the refined P2 < (0, X, 1, X, 1, 0), (1, X, 1, X, 0, 1) > candetect f 2, as shown in Fig. 4(a), the WSA of the refined P2

becomes 4 (=1 + 2 + 1). Now, the refined P2 can detect bothf 1 and f 2 without violating the power threshold. It should benoted that the capture power of the refined power-safe patternalso increases because the power-safe pattern detects morefaults (the WSA of P2 is 1 in Fig. 3(b), but the WSA of therefined P2 in Fig. 4(a) is 4). Therefore, to ensure that the WSAof the refined pattern does not exceed the power threshold, itmust be calculated and checked again.

Since f 3 remains undetected, the fault coverage is still lessthan the original. In order to recover the fault coverage loss,another power-safe pattern, P3 = < v5, v6 > = < (X, X, 1, 0, X,X), (X, X, 1, 1, X, X) > , can be generated to detect f 3, asshown in Fig. 4(b). By using the two power-safe pattern pairs,refined P2 (WSA = 4) and P3 (WSA = 3), all three faults canbe detected without test data inflation, loss of fault coverage,and capture power issues.

B. Overall Flow of Proposed Procedure

Based on the main idea, a technique is proposed to deter-mine a test set such that the power constraint is satisfied andthe test data inflation is minimized. Fig. 5 shows an overviewof the proposed capture-power-safe test pattern determination


Fig. 4. Two new pattern pairs detect the faults f 1 (N5 slow-to-rise), f 2 (N7slow-to-fall), and f 3 (N2 slow-to-rise). (a) Refined P2 that detects f 1 and f 2.(b) New pattern pair P3 that detects f 3.

procedure. The inputs to this procedure include a pregeneratedpartially specified test set T for the LOC test, a list F oftransition faults that are detected by T, and a predefined powerthreshold Pth to determine whether a pattern is power-risky.

In order to obtain the power-safe patterns T s and the power-risky fault list Fr, at step , the capture power of each patternin T is calculated and compared with Pth. The power-riskyfault list Fr is the list of faults that are only detected bypower-risky patterns. To get a deterministic capture power ofthe partially specified pattern, the X-bits must be temporarilyfilled with zero or one. In the proposed procedure, the ACFtechnique is used to fill these X-bits temporarily to calculatecapture power. If the pattern’s capture power is less than Pth,the pattern is added into T s; otherwise, the pattern is dropped.The faults that are only detected by the power-risky patternsare identified by fault simulation using T s and F. These power-risky faults are added into Fr.

Note that there may exist some power-safe patterns thatcan detect power-risky faults in Fr but are not part of theoriginal test set. Thus it can only be said that these faults aredetected only by power-risky patterns in the original test set.The obtained power-safe test set T s and power-risky fault listFr will then serve as the inputs to the test pattern refinementprocess (step ).

In the test pattern refinement process, values are assignedto X-bits of power-safe patterns in T s under the Pth limitationto detect as many power-risky faults in Fr as possible. Afterthis step, a fully specified power-safe test set Tms and anundetected fault list Fu are determined. If the refined power-safe test set (Tms) detects all of the power-risky faults, thepattern determination procedure is complete. Otherwise, the

Fig. 5. Overview of proposed capture-power-safe test pattern determinationprocedure.

low-power test pattern generation (step ) is conducted togenerate new power-safe test patterns to detect these faults.The newly generated power-safe test patterns are stored inTns. The power-risky faults that still cannot be handled by theproposed procedure are considered as unresolved and are putinto an unresolved fault list Fur. With the above processes, apower-safe test set, including the refined power-safe test setTms and newly generated test set Tns, can be determined. Thedetails of these processes are described below.

C. Algorithm for Test Pattern Refinement Process

The goal of the test pattern refinement process is to utilizethe X-bits in power-safe patterns to detect as many power-risky faults as possible. This process ends when there are noremaining faults in Fr or all the power-safe patterns in T s havebeen refined. The pseudo code is shown in Fig. 6.

In each iteration, an unrefined power-safe pattern is selectedas sel−pt (line 2). Then, the X-filling is applied to sel−pt fordetecting power-risky faults (line 3). In this step, a commercialATPG tool is configured to keep the specified bits of sel−pt,and the ATPG tool generates a partially specified test set calledcandidate test set T c for power-risky faults. For example, ifsel−pt is (1, 0, X, X, 1), the candidate test set T c may includeP1 = (1, 0, 0, 0, 1) and P2 = (1, 0, X, 0, 1), but not P3 = (0, 0,X, X, 0) because the values of some specified bits of P3 aredifferent from those of sel−pt. The capture power of each testpattern in T c is then calculated by using the power metricsdiscussed in Section II (line 4).

After the capture power of each candidate pattern is ob-tained, the patterns with capture power higher than Pth are


Fig. 6. Pseudo code for test pattern refinement process.

removed from T c (line 5). If T c is not empty, a fully specifiedpattern that detects the most faults in Fr is chosen as max−pt,and the faults detected by max−pt are dropped from Fr (line7–8). The pattern max−pt is then copied to sel−pt, and sel−ptbecomes fully specified and is marked as refined (line 9–11). The fault list Fr is checked if it has any power-riskyfaults. If Fr is empty, the remaining unrefined power-safepatterns in T s are replaced with the corresponding prefilledpatterns in Step 1 these patterns are added to Tms. Then,the refinement process is terminated. Otherwise, the nextpattern will be selected for modification (line 12–14). Ifsome power-risky faults still remain undetected after the whileloop, these faults will be put in the undetected fault list Fu

(line 17–19), which will be processed by the low-power testpattern generation process, which is discussed in the nextsection. In summary, after the test pattern refinement process,a refined fully specified power-safe test set Tms is obtained.

D. Algorithm for Low Power Test Generation Process

The low-power test generation process attempts to generatea new power-safe test set to detect all the undetected faultsand minimize the test data inflation at the same time. In

Fig. 7. Pseudo code for low-power test pattern regeneration process.

order to achieve this goal, this process uses a dynamic datacompression flow [20]. The pseudo code is shown in Fig. 7.

In this process, a commercial ATPG tool is first used togenerate a compact partially specified test set T tmp for Fu

(line 2). After the capture power of each pattern in T tmp iscalculated, the patterns with capture power greater than Pth

are removed from T tmp (line 3–4). Similar to the refinementprocess, the pattern which detects most faults is selected asmax−pt if T tmp is not empty (line 5–6). Then max−pt is refinedby the test pattern refinement process in an attempt to increaseits detected faults (line 7). These detected faults are droppedfrom Fu and max−pt is added to the test set Tns (line 8–9).Note that at this moment the generated power-safe patternsmay be unable to detect all faults in Fu (line 10) because thegenerated patterns may only have a small number of X-bitsdue to dynamic data compression in ATPG. Therefore, thefollowing steps consider only a small fraction of undetectedfaults for pattern generation based on the observation that thepatterns generated for a smaller number of faults tend to havea larger number of X-bits and hence a higher chance to bepower-safe. In the experiment, 10% of undetected faults arerandomly selected from Fu as F tmp (line 11–12). The ATPGtool then generates a partially specified test set T tmp and thecapture power of each patterns in T tmp is calculated. Thepatterns with capture power higher than Pth are removed fromT tmp (line 13–14).


TABLE I

Information of ISCAS’89 and ITC’99 Circuits

If ATPG cannot generate any power-safe pattern for thecurrent F tmp, the faults in F tmp will be added to an unresolvedfault list Fur and removed from Fu (line 16–18); otherwise,this process goes to line 6 to process the power-safe patternsgenerated for F tmp (line 15). This procedure is repeated untilthere are no faults in Fu. Then, a newly generated power-safetest set Tns and unresolved faults Fur are obtained.

IV. Experimental Results

The proposed procedure was implemented in the C languageand a commercial ATPG tool was used in the procedure to gen-erate test patterns. In order to quickly calculate the WSAs ofpatterns, an event-driven power calculator was implemented.The experiments were conducted on ISCAS’89 and ITC’99benchmark circuits using a 2.5-GHz Intel Xeon CPU with16 GB of memory on a Linux platform. These circuits weresynthesized using a commercial DFT compiler. The statisticsof these circuits are listed in Table I, where the columns|sc| and |F| list the number of scan cells and uncollapsedtestable transition faults, respectively. The columns |T atpg| andX-bits% show the number of partially specified test patternsand the average percentage of X-bits in the initial test setT atpg, respectively. The column max WSA lists the circuit’stheoretical maximum WSA, which is obtained by assumingthat all gates in the circuit are switched simultaneously. Thefault list F and the initial test set T atpg were generated by acommercial ATPG tool.

A. Test Pattern Refinement

The effectiveness of the test pattern refinement process wasinvestigated for power thresholds of 15% and 20% of maxWSA [26]. The results for reducing the number of power-risky faults by the test pattern refinement process are listed inTables II and III. The columns |T s| and |Fr| provide the initialnumber of power-safe patterns and the number of power-riskyfaults which are only detected by the power-risky patterns.The number of remaining power-risky faults after the processis shown in column |Fu|. The reduction ratio of the numberof power-risky faults in column |Fr| Red (%) is calculated by(|Fr| – |Fu|) / |Fr|*100.

TABLE II

Power-risky faults reduction With Test Pattern Refinement

Only on ISCAS’89 Benchmark

From Table II, it can be seen that the number of power-risky faults was reduced by 64.55% and 76.7% on averagewith the test pattern refinement process for power thresholdsof 15% and 20% of max WSA, respectively. This means thatrefining the power-safe patterns can significantly increase thedetection of power-risky faults given the power constraints. InTable II, the power-risky fault reduction ratios of many circuitsare even higher than 90%. In particular, the reduction ratio fors13207 is 100% when the threshold is 20%, which means thatrefined power-safe patterns can detect all power-risky faults,and thus there is no need to generate new low-power patternsfor this circuit. However, it can also be seen that for somecases the method is inefficient. For example, test cases s1423and s35932 have very low reduction ratios (only 9.74% and2.27% for 15% threshold, respectively). This is due to theinitial numbers of power-safe patterns in s1423 and s35932being extremely small; fewer than ten power-safe patterns canbe used in these cases. Therefore, the refined power-safe testpatterns cannot detect many power-risky faults. From Table II,it can also be seen that when the power threshold is increased,the number of power-safe patterns increases and thus morepower-risky faults can be detected by refining power-safepatterns.

The results for the ITC’99 benchmark are similar to thosefor ISCAS’89 benchmark, as shown in Table III. The averagereduction ratios of power-risky faults are 67.04% and 79.83%for 15% and 20% of max WSA, respectively. In cases b17 tob19, it can be seen that power-risky fault reduction ratios arehigher than 97%. The ratio reaches 100% when Pth is 20%of WSA. In cases b20 to b22, the power-risky fault reductionratios are 26.9% to 39.6% when Pth is 15%, and 56.7% to62.5% when Pth is 20%. This is also due to these cases havingfewer power-safe patterns under the same power threshold.

B. Low-Power Test Pattern Regeneration

The effectiveness of the low-power test pattern regenerationprocess was examined next. This process is used to generatepatterns to detect the undetected power-risky faults, Fu. Thenewly detected faults are removed from Fu and the patternsdetecting these faults are added into Tns. The remaining faultsare unresolved faults. Table IV shows the experimental results.


TABLE III

Power-Risky Faults Reduction With Test Pattern Refinement

Only on ITC’99 Benchmar

The column |Fur| lists the number of unresolved faults thatcannot be solved using the proposed low-power test patternregeneration for a given Pth. The column |Tns| lists the numberof newly generated power-safe patterns and the column |T all|lists the number of final power-safe patterns which is the sumof |T s| and |Tns|. The column � # of PT (%) shows the ratioof the pattern number difference between Tall and Tatpg over|Tatpg|, i.e., (|Tall|-|Tatpg|)/|Tatpg|*100%.

It can be seen that for most cases the proposed test patternregeneration process can effectively detect power-risky faultsin Fu (Fu for ISCAS’89 and ITC’99 are listed in Table IIand III). This is likely due to most power-risky faults havingbeen detected by the test refinement process and only a smallnumber of power-risky faults being left. However, test casess1423 and s35932 still have many power-risky faults aftertest pattern regeneration. This is because the power thresholdsetting for these two cases are too strict and thus many power-risky patterns exist (96.8% and 98.4% of patterns are power-risky for s1423 and s35932 when Pth is 15% of max WSAas shown in Table II). In the next section, we will discusshow to determine a more reasonable power threshold. Anotherspecial case is s38417. The final test pattern number |Tall| ofcase s38417 is 48.26% higher than |Tatpg|. The reason is thatthe regenerated patterns for this case have a quite high WSA.Therefore, each regenerated pattern cannot detect many faults,and more regenerated patterns are needed to achieve high faultcoverage.

When Pth is set at 20% of max WSA, the final patternnumbers, |Tall|, of all cases other than cases s1423 ands35932 are less than the initial pattern numbers, |Tatpg|. Onaverage, Tall is respectively 9.65% and 6.27% less than Tatpg

in ISCAS’89 and ITC’99, respectively, and almost no power-risky faults are left. This is again due to the fact that manypower-risky faults are detected by the test pattern refinementprocess and only a few power-risky faults are left.

When Pth is 15% of max WSA, the final pattern number islarger than that obtained with Pth of 20% of max WSA, andin some cases is even higher than the initial pattern number.This is because when the power threshold is lower, moreX-bits need to be specified for power reduction, which reducesthe detectability of these patterns. Therefore, more power-safepatterns need to be generated to detect power-risky faults.

TABLE IV

Experimental Result of Low-Power Test Pattern Regeneration

Fortunately, the total pattern numbers are just slightly largerthan the original values in these circuits.

C. Functional Peak Power Threshold

In Section IV-B, the ISCAS’89 benchmark has two specialcases (s1423 and s35932) with very small numbers of power-safe patterns that can be used to detect power-risky faults.This is because the power thresholds for these cases are toostrict and the proposed procedure does not have sufficientpower-safe patterns to detect power-risky faults. Therefore,how to properly choose the power threshold was explored.Wen et al. [21] indicated that the appropriate power thresholdcan be obtained by simulating the functional peak power ofthe circuit. We thus simulate one million functional patternsfor each circuit. The peak capture power of each functionalpattern, called functional peak WSA, was calculated. Theresults are shown in Table V.

Table V compares 15% of max WSA, 20% of max WSA,average WSA, and functional peak WSA. It can been seenthat both functional peak WSA and average WSA are largerthan or close to 20% of max WSA for most cases. Therefore,setting the power threshold as 20% of max WSA may betoo low and may result in many power-risky patterns. If thepower threshold is set too low, the number of power-safepatterns may be insufficient to detect many power-risky faults.Also, s1423 and s35932 are two special cases that have highfunctional peak power and few power-safe patterns. Therefore,it is difficult to generate power-safe patterns to detect thepower-risky faults with 15% and 20% of max WSA. Thisexplains why both cases still have many remaining power-risky faults.

Note that test cases s5378 and s38584 also have functionalpeak WSA values larger than 20% of max WSA but onlyfew power-risky patterns are left. This is because functionalpeak WSA of both cases only occurs on few patterns andmost patterns are still power-safe (in s5378, 65.2% of patterns


TABLE V

Comparison Between Different WSAs

TABLE VI

Experimental Results When Pth Is Functional Peak WSA

are power-safe and in s38384, 94.2% of patterns are power-safe when Pth is 20% of max WSA). Therefore, the proposedprocedure can still detect most power-risky faults in these twocircuits.

Table VI shows the experimental results when the powerthreshold was set to functional peak WSA. It can be seen thatall the power-risky faults were detected with the proposedprocedure in all cases. The test data volume was reducedby 12.76% on average. The results show that setting anappropriate power threshold can provide sufficient power-safepatterns to eliminate all power-risky faults and reduce the testdata volume at the same time.

D. Comparison of Proposed Procedure and ACF

The section compares the power-risky fault reduction ratio,test data volume and fault coverage of ACF[7] and theproposed procedure. First, ACF is compared to the proposedtest pattern refinement process in Table VII. Next, ACF iscompared to both proposed test pattern refinement and testpattern regeneration in Table VIII.

From Table VII, ACF can reduce power-risky faults by33.32% and 42.94% on average under the two power thresh-olds for the ISCAS’89 benchmark, and the proposed testpattern refinement process can reduce power-risky faults by64.55% and 76.62%, which are 31.23% and 33.68% higher,respectively. Similarly, in the ITC’99 benchmark, the proposedtest pattern refinement process can reduce power-risky faults

TABLE VII

Power-Risky Fault Reduction of ACF and Test Refinement

Process Only

TABLE VIII

Test Data Volume and Fault Coverage of ACF and Proposed

Procedure Under Various Pth When using WSA Power Metric

by 67.04% and 79.83% when the Pth is 15% and 20% of maxWSA, which are 21.18% and 27.7% higher than those for ACF,respectively. This is expected because ACF fills the X-bits onlyto reduce the capture power of both power-safe and power-risky patterns. Since some patterns are already power-safe, itis not necessary to reduce their capture power. In the proposedrefinement process, only power-safe patterns are refined todetect power-risky faults. Therefore, more power-risky faultsare reduced.

Table VIII compares test data volume and fault coverageof ACF and the proposed procedure (which includes both testpattern refinement and test pattern regeneration) under two


TABLE IX

Peak Capture Power (WSA) Reduction Ratio. The Reduction ratio Is Compared to Random Fill

power thresholds. Note that the term fault coverage here refersto the percentage of detectable faults that are detected, whichis often called test efficiency in the literature. The column FC% lists the fault coverage of T all, and the column �|T all| %lists the reduction ratio of the proposed procedure comparedto the |T all| obtained using ACF. It can be seen that the faultcoverage of the proposed procedures is similar to that of ACF.However, the test data volumes for the proposed procedure are20.16% and 21.63% less than those of ACF on average for theISCAS’89 benchmark when Pth is 15% and 20% of max WSA.

Clearly, the test data volume reduction ratio is closelyrelated to the number of power-risky patterns. If there arefewer power-risky patterns, the test data volume reductionratio will be less. This can be seen from the experimentalresults of the ITC’99 benchmark, where the test data volumeare reduced by only 5.59% and 4.10% since the test cases inthis benchmark have fewer power-risky patterns.

E. Peak Capture Power reduction

In the proposed procedure, power-risky patterns are dis-carded and power-safe patterns are used to detect power-risky faults. Since power-risky patterns are discarded, thepeak capture WSA of the procedure is significantly reduced.Table IX compares the peak capture power of random fill,ACF, and the proposed procedure. The peak capture poweris measured in WSA and the reduction ratio is compared torandom fill. It can be seen that ACF can reduce peak capturepower by 15.57% on average in the ISCAS’89 benchmark.The proposed procedure can reduce peak capture power by68.6% and 58.18% under the two power thresholds, whichare 53.03% and 42.61% higher.

For ACF, if the patterns that cause the peak capture powerhave only a few X-bits, only a small ratio of capture powercan be reduced. For example, ACF does not reduce the peak

capture WSA of case s35932. This is because the pattern thatgenerates the peak capture WSA does not contain any X-bits.

However, the proposed procedure does not have this prob-lem because it removes power-risky patterns. Therefore, theproposed procedure produces a much greater reduction in peakcapture power. Another significant result is that since ACFdoes not consider the power threshold, it does not guaranteethat its results can meet the power budget in real circuits.From Tables V and IX, it can be seen that after ACF, the peakcapture WSA was still higher than the functional peak power.

The last three columns list the runtime in hours, how manytimes the ATPG tool runs and the fraction of time spent inthe ATPG tool. The proposed procedure under different powerthresholds had different runtimes, but only the largest one islisted. The runtime of ACF is about several minutes becauseit attempts to reduce capture power by X-filling and does notconsider the power threshold. It can be seen that the overallruntime of our procedure ranges from 10 minutes to 2.17 days.The long running time is because our implementation has toinvoke a commercial ATPG tool many times to perform all X-filling and fault simulation processes. As shown in Table IX,on average more than 90% of time is spent on the ATPGprocess. As we are unable to incorporate our procedure intothe commercial ATPG tool, the most time-consuming part ison the file I/O and data structure reconstruction for the ATPGtool, which typically consume more than 85% of the ATPGtime in our experiments. The run time can be significantlyreduced if our proposed method is integrated in the ATPG toolor a more efficient ATPG tool is used. Nevertheless, since thisis a one-time job, once the power-safe patterns are determined,there is no need to execute the proposed procedure again.

F. Pattern Size

Table X compares the number of partially specified and fullyspecified patterns generated by the commercial ATPG tool


TABLE X

Pattern Number Comparison

used in our experiment. The column |Tatpg| shows the numberof the original partially specified test pattern and the column|Trand| random fill shows the number of fully specified testpatterns when the random fill technique is used. Our patternnumber |Tatpg| is larger than the pattern number |Trand| randomfill because our patterns contain X-bits, but the differences arenot significant in most cases. We also show the number of safepatterns generated by our method in the column |Tall| when20% of max WSA is used (from Table VIII). It can be seenthat |Tall| is quite close to |Trand|. In some cases |Tall| are evensmaller than |Trand|. We do find that that for b17, b18, and b19,|Tatpg| is much larger than |Trand|, This is because the X-bitratios of these circuits are quite large (over 91%) and mostpatterns in |Tatpg| are safe patterns. Since all safe patterns willbe included in Tall, our method does not reduce the numberof patterns well. If the number of X-bits can be reduced whengenerating Tatpg, then |Tall| can also be reduced. Another wayto deal with this problem is to explore the detectability of asafe pattern on not only the faults detected by risky-patterns,but also on those faults detected by other safe patterns. By thisway, we can do some test compaction among the safe patternsand may further reduce the number of safe patterns.

V. Conclusion

This paper proposed a novel capture-power-safe test patterndetermination procedure to address the capture power problem.Unlike previous methods, the test pattern refinement processin the proposed procedure refines power-safe patterns to detectthe power-risky faults and discards the power-risky patterns toensure the capture power safety. The capture power of newlygenerated patterns is also guaranteed to be under the powerconstraints. The experimental results show that more than 75%of power-risky faults can be detected by refining the power-safe patterns, and that the required test data volumes can bereduced by 12.76% on average under the appropriate powerconstraints without fault coverage loss.

References

[1] N. Ahmed, M. Tehranipoor, and V. Jayaram, “Transition delay fault testpattern generation considering supply voltage noise in a SOC design,”in Proc. Design Autom. Conf., 2007, pp. 533–538

[2] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravos-soudovitch, “A gated clock scheme for low power scan testing of logicICs or embedded cores, ” in Proc. Asian Test Symp., 2001, pp. 253–258.

[3] K. Enokimoto, X. Wen, Y. Yamato, K. Miyase, H. Sone, S. Kajihara,M. Aso, and H. Furukawa, “CAT: A critical-area-targeted test setmodification scheme for reducing launch switching activity in at-speedscan testing,” in Proc. Asian Test Symp., 2009, pp. 99–104

[4] T.-C. Huang and K.-J. Lee, “A token scan architecture for low powertesting,” in Proc. Int. Test Conf., 2001, pp. 660–669.

[5] K.-J. Lee, S.-J. Hsu, and C.-M. Ho, “Test power reduction with multiplecapture orders,” in Proc. Asian Test Symp., 2004, pp. 26–31.

[6] J. Li, Q. Xu, Y. Hu, and X. Li, “X-Filling for simultaneous shift- andcapture-power reduction in at-speed scan-based testing,” IEEE Trans.Very Large Scale Integr. Syst., vol. 18, no. 7, pp. 1081–1092, Jul.2010.

[7] E. K. Moghaddam, J. Rajski, S. M. Reddy, and M. Kassab, “At-speedscan test with low switching activity,” in Proc. VLSI Test Symp., 2010,pp. 177–182.

[8] K. Miyase and S. Kajihara, “XID: Don’t care identification of testpatterns for combinational circuits,” IEEE Trans. Comput. Aided DesignIntegr. Circuits Syst., vol. 23, no. 2, pp. 321–326, Feb. 2004.

[9] I. Pomeranz and S. M. Reddy, “Switching activity as a test compactionheuristic for transition faults,” IEEE Trans. Very Large Scale Integr. Syst.,vol. 18, no. 9, pp. 1357–1361, Sep. 2010.

[10] S. Remersaro, X. Lin, Z. Zhang, S. M. Reddy, I. Pomeranz, andJ. Rajski, “Preferred fill: A scalable method to reduce capture powerfor scan based designs,” in Proc. Int. Test Conf., 2006, pp. 1–10.

[11] P. Rosinger, B. M. Al-Hashimi, and N. Nicolici, “Scan architecture withmutually exclusive scan segment activation for shift- and capture-powerreduction,” IEEE Trans. Comput. Aided Design Integr. Circuits Syst.,vol. 23, no. 7, pp. 1142–1153, Jul. 2004.

[12] J. Saxena, K. M. Butler, V. B. Jayaram, S. Kundu, N. V. Arvind,P. Sreeprakash, and M. Hachinger, ”A case study of IR-drop in structuredat-speed testing,” in Proc. Int. Test Conf., 2003, pp. 1098–1104.

[13] B. Yang, A. Sanghani, S. Sarangi, and C. Liu, “A clock-gating basedcapture power droop reduction methodology for at-speed scan testing,”in Proc. Design, Autom. Test Eur. Conf. Exhibition, 2011, pp. 1–7

[14] C. Zhen and X. Dong, “Low-capture-power at-speed testing usingpartial launch-on-capture test scheme,” in Proc. VLSI Test Symp., 2010,pp. 141–146.

[15] I. Pomeranz and S. M. Reddy, “Switching activity as a test compactionheuristic for transition faults,” in Proc. IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst., vol. 18, no. 9, pp. 1357–1361, Sep. 2010.

[16] K. M. Butler, J. Saxena, A. Jain, T. Fryars, J. Lewis, andG. Hetherington, “Minimizing power consumption in scan testing:Pattern generation and DFT techniques,” in Proc. Int. Test Conf., 2004,pp. 355–364.

[17] V. R. Devanathan, C. P. Ravikumar, and V. Kamakoti, “A stochasticpattern generation and optimization framework for variation-tolerant,power-safe scan test,” in Proc. Int. Test Conf., 2007, pp. 1–10.

[18] M.-F. Wu, K.-S. Hu, and J.-L. Huang, “LPTest: A flexible low-powertest pattern generator,” J. Electron. Test., vol. 25, no. 6, pp. 323–335,2009.

[19] S.-J. Wang, Y.-T. Chen, and S.-M. Li, “Low capture power test gener-ation for launch-off-capture transition test based on don’t-care filling,”in Proc. Int. Symp. Circuits Syst., 2007, pp. 3683–3686.

[20] L.-T. Wang, C.-W. Wu, and X. Wen, Eds., VLSI Test Principles andArchitectures: Design for Testability, San Francisco, CA, USA: Elsevier,2006.

[21] X. Wen, K. Miyase, S. Kajihara, H. Furukawa, Y. Yamato, A. Takashima,K. Noda, H. Ito, K. Hatayama, T. Aikyo, and K. K. Saluja, “A capture-safe test generation scheme for at-speed scan testing,” in Proc. Eur. TestSymp., 2008, pp. 55–60.

[22] X. Wen, K. Miyase, S. Kajihara, T. Suzuki, Y. Yamato, P. Girard,Y. Ohsumi, and L.-T. Wang, “A novel scheme to reduce power supplynoise for high-quality at-speed scan testing,” in Proc. Int. Test Conf.,2007, pp. 1–10.

[23] X. Wen, Y. Yamashita, S. Morishima, S. Kajihara, L.-T. Wang, K. K.Saluja, and K. Kinoshita, “Low-capture-power test generation for scan-based at-speed testing,” in Proc. Int. Test Conf., 2005, pp. 1–10.

[24] X. Wen, K. Miyase, T. Suzuki, S. Kajihara, Y. Ohsumi, and K. Saluja,“Critical-path-aware X-filling for effective IR-drop reduction in at-speedscan testing,” in Proc. Design Autom. Conf., 2007, pp. 527–532

[25] X. Wen, K. Miyase, T. Suzuki, S. Kajihara, L.-T. Wang, K. K. Saluja,and K. Kinoshita, “Low capture switching activity test generation forreducing IR-drop in at-speed scan Testing,” J. Electron. Test., vol. 24,no. 4, pp. 379–391, 2008.


[26] M. A. Kochte, K. Miyase, X. Wen, S. Kajihara, Y. Yamato, K. Enoki-moto, and H. Wunderlich, “SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures,” in Proc. Int.Symp. Low Power Electr. Design, 2011, pp. 33–38.

[27] X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. A. Kochte, S.Kajihara, P. Girard, and M. Tehranipoor, “Power-aware test generationwith guaranteed launch safety for at-speed scan testing,” in Proc. VLSITest Symp., 2011, pp. 166–171.

[28] Y. Yamato, X. Wen, K. Miyase, H. Furukawa, and S. Kajihara, “AGA-based method for high-quality X-filling to reduce launch switchingactivity in at-speed scan testing,” in Proc. Pacific Rim Int. Symp.Dependable Comp., 2009, pp. 81–86.

[29] Y. Zorian, “A distributed BIST control scheme for complex VLSIdevices,” in Proc. VLSI Test Symp., 1993, pp. 4–9.

Yi-Hua Li received the B.S. degree in computer sci-ence from Chang Gung University, Taoyuan, Taiwan,in 2010, and M.S. degree in computer science andinformation engineering from National Cheng KungUniversity, Tainan, Taiwan, in 2013.

She is currently with Storart Technology Co.,Ltd., Hsinchu, Taiwan. Her current research interestsinclude CAD for very large-scale integration (VLSI)and low power testing.

Wei-Cheng Lien (S’10) received the B.S. degreein electrical engineering from National Cheng KungUniversity, Tainan, Taiwan, in 2007, where he iscurrently pursuing the Ph.D. degree in electricalengineering.

His current research interests include design fortestability, diagnosis, test compaction, and logicBIST.

Ing-Chao Lin (M’09) received the M.S. degreein computer science from National Taiwan Uni-versity, Taipei, Taiwan, and the Ph.D. degree fromthe Computer Science and Engineering Department,Pennsylvania State University, University Park, PA,USA, in 2007.

From 2007 to 2009, he was with Real Intent,Inc., where he was engaged in automatic timingexception verifier, and since 2009, he has been withthe Department of Computer Science and Informa-tion Engineering, National Cheng Kung University,

Tainan, Taiwan, where he is currently an Assistant Professor. His currentresearch interests include very large-scale integration (VLSI) design andcomputer-aided design for nanoscale silicon, low power testing, and computerarchitecture.

Kuen-Jong Lee (S’84–M’91) received the B.S.,M.S., and Ph.D. degrees from National Taiwan Uni-versity, Tainan, Taiwan, University of Iowa, IowaCity, IA, USA, and the University of SouthernCalifornia, Los Angeles, CA, USA, respectively.

He was with the Faculty of National Cheng KungUniversity (NCKU), Tainan, Taiwan, in 1991, wherehe is currently a Professor with the Department ofElectrical Engineering. He served as the Director ofthe NCKU SOC Research Center from 2008 to 2010and was elected as the fourth President of the Taiwan

Integrated Circuit Design Society. He holds six ROC and five U.S. patents. Hiscurrent research interests include SOC testing/debugging, scan-based design,and electronic system level design and test.

Dr. Lee has served on technical program and organization committees of sev-eral professional conferences, including Program Chairs and General Chairsof Asian Test Symposium, VLSI Design, Automation and Test Symposiumand VLSI Test Technology Workshop. He also served as the first Chairman ofthe IEEE Circuits and Systems Tainan Chapter. He received the ExceptionalContribution Award from the National Applied Research Laboratory in 2007and the Best Project Achievement Award from the National Science Councilof Taiwan in 2007 and 2013. He has also won the Golden Medal of the GoldenSilicon Award in 2013 and the Best Paper Awards of the 2011 VLSI-CADSymposium and the 2012 VLSI Test Technology Workshop. He has workedon many aspects of the design and test of VLSI circuits.

capture-power-safe test pattern determination for at-speed scan-based testing

Documents