centipede-pci cnc interface board mach3 version · centipede-pci cnc interface board mach3 version...
TRANSCRIPT
CENTIPEDE-PCI CNC Interface Board
Mach3 Version
Firmware V3.0.1
KSI Labs, LLC
2013
COPYRIGHT
© 2013 KSI Labs, LLC. All rights reserved.
The trademarks mentioned in this manual are legally registered totheir respective owners.
Disclaimer
Information in this manual is protected by copyright laws and is the property ofKSI Labs, LLC. Changes to speci�cation and features in this manual may bemade by KSI Labs, LLC at any time without prior notice. All information inthis manual including schematics is for sole use by KSI Labs, LLC end usersONLY. Any commercial use of information contained in this document requiresa written permission from KSI Labs, LLC. All violators will be prosecuted tothe fullest extent of the law. For product-related information and latest versionscheck our web site:
http://www.ksilabs.com
1
Contents
1 HARDWARE 31.1 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . 41.1.2 External Connector . . . . . . . . . . . . . . . . . 41.1.3 Extension Connector . . . . . . . . . . . . . . . . 6
2 FIRMWARE 82.1 PCI Device Registers . . . . . . . . . . . . . . . . . . . . 92.2 Registers Description . . . . . . . . . . . . . . . . . . . . 11
2.2.1 DATA_OUT, O�set 0x00 . . . . . . . . . . . . . 112.2.2 DATA_IN, O�set 0x04 . . . . . . . . . . . . . . 122.2.3 DAC, O�set 0x08 . . . . . . . . . . . . . . . . . . 142.2.4 ADC, O�set 0x0c . . . . . . . . . . . . . . . . . . 152.2.5 IRQ_RAW, O�set 0x10 . . . . . . . . . . . . . . 152.2.6 IRQ_MASK, O�set 0x14 . . . . . . . . . . . . . 172.2.7 IRQ_STAT, O�set 0x18 . . . . . . . . . . . . . . 172.2.8 MACH_IDX_[XYZABC], O�sets 0x1c, 0x20,
0x24, 0x28, 0x2c, 0x30 . . . . . . . . . . . . . . . 182.2.9 MACH_CONFIG, O�set 0x34 . . . . . . . . . . 182.2.10 MACH_CONFIG2, O�set 0x38 . . . . . . . . . 202.2.11 MACH_CTL, O�set 0x3c . . . . . . . . . . . . . 212.2.12 MACH_STAT, O�set 0x40 . . . . . . . . . . . . 222.2.13 MACH_FIFO, O�set 0x44 . . . . . . . . . . . . 242.2.14 MACH_ENC, O�set 0x48 . . . . . . . . . . . . 242.2.15 MACH_SPCNT, O�set 0x4c . . . . . . . . . . . 252.2.16 MACH_SPCTL, O�set 0x50 . . . . . . . . . . . 252.2.17 MACH_CONFIG3, O�set 0x54 . . . . . . . . . 26
3 Appendix A - Hardware di�erences between rev.1.0 and rev.1.1 28
4 Appendix B - CENTIPEDE-PCI rev.1.0 Schematics 30
5 Appendix C - CENTIPEDE-PCI rev.1.1 Schematics 33
2
Chapter 1
HARDWARE
CENTIPEDE-PCI is a PCI-2.2 compatible interface card for CNC control appli-cations. It may be used for other purposes as well but it was designed to controla CNC machine when used with optional breakout board, CENTIPEDE-BRK.It is universal PCI Add-In card i.e. it will work in both 3.3V and 5V PCI/PCI-Xslot.
CENTIPEDE-PCI (simply PCI from now on) board is designed in the waythat allows for maximum �exibility and extensibility. Entire functionality isimplemented in in�nitely reprogrammable Altera MaxII© CPLD so all board'shardware is actually an HDL code. That code can be changed and programmedinto the CPLD thus allowing for easy bug �xes, new functionality addition, andultimately for making it into something totally di�ererent. All CPLD sourcecode (in VHDL) is available for free from KSI Labs, LLC web site. New releases,extensions, user-contibuted add-ons etc. will be also available from our web siteas well as precompiled CPLD images (*.pof �les) that can be directly writteninto the CPLD.
All external connections are made through a single 100-pin connector. Thereare 32 galvanically isolated dedicated inputs, 32 Open Drain dedicated outputs,2 LVDS inputs and 10 LVDS outputs (all galvanically isolated.) LVDS I/O issupposed to implement SPI-like interfaces to external devices with up to 1MHzclock rate. Some of them used for communication with DAC/ADC peripheralson the breakout board (BRK from now on,) some are free for future use withadd-on extension boards.
ALL external I/O is designed as galvanically isolated; there is no provisionfor a direct galvanic connection to the PCI board. Open Drain outputs aresupposed to drive optocouplers so no ground connection is provided. There is+5V power from the external connector and external devices' optocouplers areconnected between that +5V power and OD outputs. In the similar fashionall input optocouplers' LED anodes are connected together and routed to theexternal connector for connection to external +5V power and their cathodes aresupposed to be connected to that external 5V ground to pass a signal to thePC.
3
LVDS I/O is also galvanically isolated with ISO72xx digital isolators. Thosehave 2 separate power supplies; the PCI board side is powered from the PC andconnected to CPLD pins while the external side is powered from external 5Vpower. There is no galvanic connection between those two sides.
8 of 32 digital inputs use high speed FOD053L optocouplers with 1 μS prop-agation time for time-critical signals. Remaining 24 use regular MOCD207Mdevices with 3 μS propagation time.
1.1 Connectors
1.1.1 JTAG
Connector J2 in the center of the board is a standard Altera JTAG connectorfor programming the CPLD. It is fully compatible with standard Altera pro-gramming tools (ByteBlasterII, USB-Blaster etc.) This connector is keyed toprevent from inserting the programming tool plug a wrong way. Other thanthat there is nothing more to say about it. CPLD programming is fully docu-mented in QuartusII Web Edition software available for free from Altera website. There is a brief programming procedure description in �Setting up CEN-
TIPEDE board set for Mach3 � document. Here is the schematics fragment withJTAG connector:
108642 1
3579
+3.3V
J2 JTAG
R2
10K
R1
10K
R3 10K
TDI
TMS
TCKTDO
Figure 1.1: JTAG Connector
1.1.2 External Connector
External connector is high quality 100-pin N102A0-52E2PC connector from 3M.All I/O signals come from this connector. Special cable is used for connectingPCI to BRK board. It is 1:1 cable and it is made to order when orderingPCI/BRK boards from KSI Labs, LLC. Cable length can be up to 20 ft.according to the customer's speci�cation.
Here is the external connector pinout and signals description:
4
123456789
1011121314151617181920
51525354555657585960616263646566676869707172737475767778798081828384858687888990
100999897969594939291
2122232425262728293031323334353637383940
50494847464544434241
+5VJ3
IGND
V+IN0..7IN0IN1IN2IN3IN4IN5IN6IN7
V+IN8..15IN8IN9IN10IN11IN12IN13IN14IN15
V+IN16..23IN16IN17IN18IN19IN20IN21IN22IN23
V+IN24..31IN24IN25IN26IN27IN28IN29IN30IN31
IVCCMISO1+MISO1−MOSI1+MOSI1−SPCK1+SPCK1−NSS11+NSS11−NSS12+NSS12−NSS13+NSS13−
IGND
OUT0OUT1OUT2OUT3OUT4OUT5OUT6OUT7
OUT8OUT9OUT10OUT11OUT12OUT13OUT14OUT15
OUT16OUT17OUT18OUT19OUT20OUT21OUT22OUT23
OUT24OUT25OUT26OUT27OUT28OUT29OUT30OUT31IVCC
MISO2+MISO2−MOSI2+MOSI2−SPCK2+SPCK2−NSS21+NSS21−NSS22+NSS22−NSS23+NSS23−
Figure 1.2: External Connector
IN0..31 Input optocouplers cathodes. Connect them to external power nega-tive (or ground) rail to set input to '1' level. IN0 is bit 0 of DATA_INregister.
V+IN0..7-V+IN24..32 Input optocouplers anodes in groups of 8. Theyshould be connected to the positive rail of an external power supply. Thereare series 330 Ω resistors installed for each optocoupler so there is no needfor additional resistors if 5V external power is used. Those are usuallypowered from BRK board 5V power supply. 4 separate pins are used tospread the load between 4 wires.
OUT0..31 Open Drain outputs for driving external optocouplers. There isNOcommon ground connection on the external connector from PCI board
5
version 1.1 and up. These outputs MUST drive external optocouplersonly to provide galvanical isolation. They should be connected to externaloptocouplers LED cathode. Anodes of those LEDs should be connected to+5V outputs (pins 51,60,69,78.) Series resistors are required for externaloptocouplers. They should be designed for 5V operation. OUT0 is bit 0of DATA_OUT register.
+5V Power for external optocouplers on OUT0..31 lines. This is taken directlyfrom PCI bus and should NOT be used for anything else (there is noground connection anyway.) There is 4 pins for this power to spread theload between 4 wires. OUT0..31 OD outputs make ground connection forthis power rail when corresponding DATA_OUT register bits set to '1.'
MISO1+/- SPI1 data input di�erential pair. Not accessible directly fromapplication software.
MOSI1+/- SPI1 data output di�erential pair. Not accessible directly fromapplication software.
SPCK1+/- SPI1 clock di�erential pair. Not accessible directly from applica-tion software.
NSS1[1..3]+/- SPI1 chip select di�erential pairs. Not accessible directly fromapplication software.
MISO2+/- SPI2 data input di�erential pair. Not accessible directly fromapplication software.
MOSI2+/- SPI2 data output di�erential pair. Not accessible directly fromapplication software.
SPCK2+/- SPI2 clock di�erential pair. Not accessible directly from applica-tion software.
NSS2[1..3]+/- SPI2 chip select di�erential pairs. Not accessible directly fromapplication software.
IVCC External +5V power for machine side SPI interface. Usually connectedto BRK board 5V power supply.
IGND External 5V power supply ground for machine side SPI interface. Usu-ally connected to BRK board ground.
1.1.3 Extension Connector
Extension connector is used for connecting add-on boards. It is NOT isolatedfrom PC so add-on boards implementing external interface to a machine mustprovide their own galvanic isolation.
There is no particular add-on interface implemented for this connector asof right now (�rmware v3.0.1) but it is going to change in near future when
6
add-on boards are out. There is at least one such board in early design stageas of v3.0.1 �rmware time. This interface is NOT software accessible right nowand should have some VHDL code added to use it.
Here is the connector pinout and signals description:
+3.3V
302826
42 1
3
252729
2422 21
23
2018 17
19
1614 13
15
1210 9
11
86 5
7
3432 31
33
3836 35
37
4240 39
41
4644 43
45
5048 47
49+5V
EX40EX38EX36EX34EX32EX30EX28EX26EX24EX22EX20EX18EX16EX14EX12EX10EX8EX6EX4EX2EX0
EX41EX39EX37EX35EX33EX31EX29EX27EX25EX23EX21EX19EX17EX15EX13EX11EX9EX7EX5EX3EX1
J1+5V
+3.3V
Figure 1.3: Extension Connector
EX0..41 CPLD signals. EX0..41 lines are connected to CPLD pins so they canbe used for any purpose with custom VHDL additions.
Power Power rails are self-explanatory. They are supposed to power add-onboards. +5V, +3.3V, and ground all come directly from PCI bus.
7
Chapter 2
FIRMWARE
CENTIPEDE-PCI board is a set of di�erent bu�ers/optocouplers/isolators andone big CPLD. The entire functionality is implemented in the CPLD; all othercomponents are just simple interface components not implementing any logicalfunctions. That means that functionality may by radically changed by pro-gramming CPLD with di�erent �rmware. Such design allows for easy hardwarebug�xes, almost unlimited �exibility, new functionality addition by simply re-programming the CPLD etc.
It is necessary to understand that CPLD code implements HARDWAREunlike some code for an embedded microcontroller that implements FIRMWARE.The principal di�erence is that CPLD code is actually a table of interconnectsbetween di�erent basic hardware blocks that CPLD is made of. In other wordsit is a bunch of wires and instructions where each wire is connected. Micro-controller �rmware, on the other hand, is a PROGRAM i.e a set of instruc-tions that microcomtroller fetches from memory and executes one-by-one. Thatmeans that �rmware is always slower because every action is usually a sequenceof instructions. Another �rmware disadvantage is that MCU (MicroControllerUnit) can only execute a single instruction at a time (actually there are MCUsthat are able of executing several instructions at a single step but that is nota regular case and there are other limitations) so it can not act fast enough onseveral di�erent tasks, it can get into an in�nite loop in one execution branchand all other tasks will get suspended inde�nitely and there are other issueswith such approach. In CPLD, on the other hand we can implement severaldi�erent units that are working in parallel totally independent of each other.
There is another fundamental di�erence between CPLD and MCU�there isno program running in CPLD. The interconnection table is loaded from inter-nal FLASH-like memory only once (usually on powerup) and then it is purehardware operation. It is not bootup like it is in MCU where the initial pro-gram is loaded and then that program executes for the entire time the MCU isoperating; it is a one-time CONFIGURATION that only executes once.
That does not mean that CPLD can not execute some action sequences butthose sequences are purely hardware ones. Machine gun also performs some
8
sequence of actions when trigger is pulled but there is no software program init. MCU counts pulses by incrementing some variable while CPLD implementsit as a string of triggers changing their states.
Yet another di�erence is that unlike MCU CPLD does not have its pinfunctions preassigned to particular pin (except a few such as power/ground pinsor JTAG pins for initial programming.) Almost any signal can be connected toalmost any CPLD pin upon initial con�guration that makes PCB design mucheasier because one can reassign signals to di�erent pins if it makes PCB layouteasier. There are some limitations of course but they are not all that strict.
There are di�erent ways to make that CPLD (Complex Programmable LogicDevice) con�guration table. One can use a pure schematic approach by drawingschematics with special CAD software and then it is translated to the particularCPLD device con�guration image by special �compiler.� This is the most preciseway but it is cumbersome and not actually suitable for bigger and more com-plex designs. Another way is using some kind of HDL (Hardware DescriptionLanguage) that describes how the hardware is supposed to operate. Then sucha description is processed by a set of CAD tools that synthesize a schematic im-plementation of the described behavior. This way is easier to work with, bettersuited for big complex designs, more maintainable and more portable betweendi�erent devices. Here in KSI Labs, LLC we use one of HDL languages, VHDLfor CPLD design. The entire VHDL source for CENTIPEDE-PCI board CPLDis available for free from our web site so everybody can customize our board ashe sees �t and/or change/extend its functionality.
So strictly speaking �FIRMWARE� is not a right word to call the CPLDcon�guration but we will be using it for the lack of better one.
This chapter does NOT describe how to con�gure the CENTIPEDE set ofboards for use with particular software (e.g. Mach 3;) it is the description whatthe board looks like from a programmer's standpoint so he can write his ownsoftware for it. Please note that ��rmware� may change at every moment soplease visit our web site, http://www.ksilabs.com for the latest information.
The included information describes Mach3-specic �rmware version 3.0.1 thatis programmed in CENTIPEDE-PCI boards as they shipped. There is also aGeneric GPIO �rmware available for this board from our web site that does nothave any particular use as of time of writing but can be used for any task bywriting an appropriate software for it. There is no particular purpose of writingthat �rmware but it is released in full binary and source form as a service forthe public. It can be used for any type of control applications and much more.
2.1 PCI Device Registers
CENTIPEDE-PCI is a regular PCI board fully conforming to PCI 2.2 standard.It has one 4Kbyte PCI Memory BAR that is initialized for proper system mem-ory mapping by PC BIOS. VendorID is 0xFEFF (That might be changedto KSI Labs, LLC VendorID when it is obtained.) DeviceID is 0x0002,ClassCode 0x078000. All register o�sets are from BAR0 base. Registers are
9
32-bit andMUST be accessed with 32-bit instructions. Write operations otherthat 32-bit will have unpredictable results and probably will lead to faulty op-eration and computer crash.
Here is the register map:
Register O�set DescriptionDATA_OUT 0x00 Output Data Register, R/WDATA_IN 0x04 Input Data Register, R/O
DAC 0x08 DAC Data Register, W/OADC 0x0c ADC Data Register, R/W
IRQ_RAW 0x10 Raw IRQ Status Register, R/CIRQ_MASK 0x14 IRQ Mask Register, R/WIRQ_STAT 0x18 Masked IRQ Status Register, R/O
MACH_IDX_X 0x1c Mach3 Axis X Index, R/WMACH_IDX_Y 0x20 Mach3 Axis Y Index, R/WMACH_IDX_Z 0x24 Mach3 Axis Z Index, R/WMACH_IDX_A 0x28 Mach3 Axis A Index, R/WMACH_IDX_B 0x2c Mach3 Axis B Index, R/WMACH_IDX_C 0x30 Mach3 Axis C Index, R/WMACH_CONFIG 0x34 Mach3 Con�guration Register, R/WMACH_CONFIG2 0x38 Mach3 Second Con�guration Register, R/W
MACH_CTL 0x3c Mach3 Control Register, R/WMACH_STAT 0x40 Mach3 Status Register, R/CMACH_FIFO 0x44 Mach3 FIFO Register, W/OMACH_ENC 0x48 Mach3 Encoders Count Register, R/C
MACH_SPCNT 0x4c Mach3 Spindle Count, R/OMACH_SPCTL 0x50 Mach3 Spindle Control, R/W
MACH_CONFIG3 0x54 Mach3 Third Con�guration Register, R/W
Table 2.1: CENTIPEDE-PCI/Mach3 Register Map
10
2.2 Registers Description
2.2.1 DATA_OUT, O�set 0x00
D31 D30 D29 D28
D27 D26 D25 D24
D23 D22 D21 D20
D19 D18 D17 D16
D15 D14/CPUMP D13/SPSTEP D12/SPDIR
D11/CSTEP D10/CDIR D9/BSTEP D8/BDIR
D7/ASTEP D6/ADIR D5/ZSTEP D4/ZDIR
D3/YSTEP D2/YDIR D1/XSTEP D0/XDIR
Table 2.2: DATA_OUT Register
D0..31 Output Data, R/W. All data written to this register is immediatelyre�ected on External Connector OUT0..31 pins. '1' will make the outputFET to open i.e. the output will go LOW . In other words writing '1' to aparticular bit will turn the corresponding external optocoupler LED ON.Read operation will give the current actual output register state. D0..D11outputs are physically disconnected from output pins when correspondingAxis (XYZABC) is enabled in MACH_CONFIG register. In this case youcan still read/write the corresponding bits but the actual output pins arecontrolled by FIFO outputs so such R/W operations will not have anye�ect on the actual physical outputs. Defaults to all '0' on powerup.
xDIR Direction outputs for x Axis (XYZABC) when that Axis is enabled inMACH_CONFIG register. In this case the corresponding DATA_OUTregister outputs are not connected to anything. You can write to thosebits and you will read back what you wrote but they are physically dis-connected from the output pins. Generates di�erent step sequence(along with corresponding xSTEP output) when put in Boss IIstep mode by setting a corresponding bit in MACH_CONFIG3register.
xSTEP Step outputs for x Axis (XYZABC) when that Axis is enabled inMACH_CONFIG register. In this case the corresponding DATA_OUTregister outputs are not connected to anything. You can write to thosebits and you will read back what you wrote but they are physically dis-connected from the output pins. Generates di�erent step sequence(along with corresponding xDIR output) when put in Boss IIstep mode by setting a corresponding bit in MACH_CONFIG3register.
11
SPDIR/SPSTEP Direction and Step outputs for Spindle drive when Dir/StepSpindle is enabled in MACH_CONFIG2 register. In this case the corre-sponding DATA_OUT register outputs are not connected to anything.You can write to those bits and you will read back what you wrote butthey are physically disconnected from the output pins.
CPUMP Charge Pump output when Charge Pump is enabled in MACH_CONFIG3register. In this case the corresponding DATA_OUT register output isnot connected to anything. You can write to this bit and you will readback what you wrote but it is physically disconnected from the outputpin.
2.2.2 DATA_IN, O�set 0x04
D31/ENC4_B D30*/ENC4_A D29/ENC3_B D28*/ENC3_A
D27/ENC2_B D26*/ENC2_A D25/ENC1_B D24*/ENC1_A
D23*/SP_IDX D22/SP_TIMING D21* D20
D19*/ESTOP_SW D18/PROBE_SW D17*/CHome D16/CMinus
D15/CPlus D14/BHome D13/BMinus D12/BPlus
D11/AHome D10/AMinus D9/APlus D8/ZHome
D7/ZMinus D6/ZPlus D5/YHome D4/YMinus
D3/YPlus D2/XHome D1/XMinus D0/XPlus
Table 2.3: DATA_IN Register
D0..D31 Input Data, R/O. IN0..31 External Connector data state directlyfrom connector pin latched on every PCI clock (through an optocoupler.)The same rule as for DATA_OUT register applies�'1' means there is cur-rent through the input optocoupler LED (switch connected to the corre-sponding BRK board terminal is CLOSED,) '0' means optocoupler LEDis OFF. Bits marked with '*' have fast optocouplers on inputs on rev.1.0CENTIPEDE-PCI board. Starting from rev.1.1 fast optocouplers are onbits 24..31. Input changes are re�ected immediately. Raw state for alloptional signals (xHome etc.) can be read from corresponding Dxx bits ifneeded. Raw means it is ELECTRICAL, not LOGICAL state i.e. it onlytells if there is current through an optocoupler or not. That can be inter-preted by the user software (Driver) and hardware as either activated ornot depending on �Negated� setting in appropriate con�guration registersor in software con�guration.
xPlus/xMinus Plus and minus side Limit Switch inputs for x Axis (XYZ-ABC) when the corresponding Axis is enabled in MACH_CONFIG reg-ister. Those perform a speci�c Hardware action when the corresponding
12
axis is enabled. They stop all motion and activate EStop hardware state.IRQ is also generated when one of these is activated (if enabled.)
xHome Home Switch inputs for x Axis (XYZABC) when the correspondingAxis is enabled in MACH_CONFIG register. MACH_IDX register forcorresponding axis is frozen when this signal is activated so exact hit posi-tion can be read. Actual Index Counters are NOT a�ected so the currentposition information is not lost. MACH_IDX registers are transparentlatches that mirror Index Counters all the time but latch the last read-ing when Probe or Home Switch is hit thus giving the exact hit position.Once read they resume their normal operation if the corresponding switchis not active or not enabled any more. Home Switch freezes only the cor-responding axis Index while Probe Switch freezes ALL Indexes. IRQ isgenerated when one of these switches is activated so the Driver softwarecan take appropriate action immediately.
PROBE_SW Digital Probe Switch input for probing. Its state can be readfrom a corresponding bit but it also performs some hardware actions whenactivated. ALL MACH_IDX registers are frozen when this signal is acti-vated so exact hit position can be read. Actual Index Counters are NOTa�ected so the current position information is not lost. MACH_IDX reg-isters are transparent latches that mirror Index Counters all the time butlatch the last reading when Probe or Home Switch is hit thus giving theexact hit position. Once read they resume their normal operation if thecorresponding switch is not active or not enabled any more. Home Switchfreezes only the corresponding axis Index while Probe Switch freezes ALLIndexes. IRQ is generated when this switch is activated so the Driversoftware can take appropriate action immediately.
ESTOP_SW Emergency Stop Switch input. That can NOT be disabledor recon�gured to other polarity (not �Negated�) and it MUST be anormally closed switch. If it is OPEN i.e. there is no current through itsoptocoupler hardware will be in EStop hardware mode and there is NOway to get it out of this state until this switch is closed. In other words thisswitch is ABSOLUTELY required and itMUST be a �Push-To-Break�type.
SP_TIMING Multiple pulse per revolution Spindle rotation sensor input.This is used for reporting Spindle RPM and for Z Axis motion controlwhen lathe threading or rigid tapping. On every transition on this in-put (rising or faling depending on con�guration bit in MACH_CONFIG2register) the internal counter contents is transferred to MACH_SPCNTregister, counter is reset, and then incremented on each and every PCIclock pulse. IRQ is generated on SP_TIMING transition so software canread MACH_SPCNT register and act appropriately by calculating actualSpindle RPM and displaying it or adjusting Z Axis speed thus gearing itto the Spindle. There is also a debouncing counter that is loaded with a
13
value set in MACH_CONFIG2 register and started decrementing every15 μS on a transition at this input. Input state is ignored until this countercounted down to zero. This cycle repeats on all consecutive transitions,both low-to-high and high-to-low.
SP_INDEX Single pulse per revolution Spindle Index sensor. This is usedin lathe threading to start Z Axis motion at exactly the same spot oneach consecutive threading pass. This is done in hardware by holdingstep output until SP_INDEX pulse detected. To do this software shouldwrite '1' in MACH_CTL register WAIT4PULSE bit. This will put allstep output (except Spindle) on hold and will restart it when SP_INDEXis detected. FIFO will be still taking step data while this hold is in ef-fect until it is full. Then, when Index pulse comes the very �rst FIFOentry will be output immediately. This input also performs all the func-tions of SP_TIMING if that is not enabled. There is a separate de-bouncing counter for SP_INDEX working in exactly the same fashion asSP_TIMING. IRQ is also generated on each SP_INDEX pulse.
2.2.3 DAC, O�set 0x08
X X X X X X X X
X X X X X X X X
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
Table 2.4: DAC Register
D0..15 SPI Transmit Holding Register (THR.) Once written data is transferredbit-by-bit to TLV5617A 2-channel 0-10V output DAC on the BRK board.Each write to DAC register clears corresponding bit in IRQ_RAW registerand that bit goes back to '1' once that written data is transferred tothe DAC. This register is Write-Only. Please read TLV5617A datasheetand Mach3 Driver source to learn how to use this register. Please notethat despite only 16 bits are used all writes MUST be done as 32-bitinstructions.
X Don't care.
14
2.2.4 ADC, O�set 0x0c
X X X X X X X X
X X X X X X X X
X X X X X X D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
Table 2.5: ADC Register
D0..9 SPI Transmit Holding Register (THR) on write, Receive Holding Regis-ter (RHR) on read. This is a second SPI controller, separate from DACSPI. Once written data is transferred bit-by-bit to TLV1544 4-channel0-10V input ADC on the BRK board. At the same time ADC data isreceived into RHR. Each write to ADC register clears corresponding bitin IRQ_RAW register and that bit goes back to '1' once that written datais transferred to the ADC (and ADC data is received into RHR.) ReadingADC register (RHR) does not have any e�ect on SPI controller and IRQstate, only write starts a new SPI cycle. Please read TLV1544 datasheetand Mach3 Driver source to �nd out how to use this register. Please notethat despite only 10 bits are used all reads and writes MUST be done as32-bit instructions.
X Don't care on write, '0' on read.
2.2.5 IRQ_RAW, O�set 0x10
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 MACH_SP_TIM MACH_SP_IDX MACH_HomeC
MACH_HomeB MACH_HomeA MACH_HomeZ MACH_HomeY
MACH_HomeX MACH_PROBE MACH_FOVF MACH_FAULT
MACH_DONE MACH_TMR ADC DAC
Table 2.6: IRQ_RAW Register
DAC DAC SPI Controller is Idle and ready to take new data to be sent toTLV5617A DAC on the BRK board. This bit is always set when DACSPI Controller is Idle. Write data to its THR and write '1' to this bit toreset it. It will get set again when transfer is complete.
15
ADC ADC SPI Controller is Idle and ready to take new data to be sent toTLV1544 ADC on the BRK board. This bit is always set when ADC SPIController is Idle. Write data to its THR and write '1' to this bit to resetit. It will get set again when transfer is complete.
MACH_TMR Mach3 timer interrupt. Periodic interrupt every 5th cyclewhen the board in is RUN condition. Cycle period is determined byCYCLE setting in MACH_CTL register. Write '1' to this bit to clear.
MACH_DONE All data in FIFO were sent out and last cycle has ended soboard got idle. Write '1' to this bit to clear.
MACH_FAULT Fault interrupt. Raised when any of Limit Switches hit, orEmergency Stop (EStop from now on) button is activated. Cleared bywriting '1' in this bit if the condition that caused it is cleared. Will notreset if condition is still present. FIFO is purged on this event, periodictimer stays ticking. It can be also activated by Watchdog over�owif it is enabled by setting a bit in MACH_CONFIG3 register.
MACH_FOVF FIFO over�ow. Theoretically should not happen becausehardware ignores all FIFO writes when it is full but anyways... Write'1' to clear.
MACH_PROBE Probe Switch hit. Write '1' to clear. Will not reset if theswitch is still activated. All axes indexes are frozen on this event untilthey are read, PROBE_HIT bit in MACH_STAT register is written with'1,' and this IRQ is acknowledged by writing '1' to its bit. The freeze isdone by stopping transparent latches between actual index counters andIDX registers so they keep the last data while index counters continuecounting so the running position is not lost.
MACH_HOMEx Home Switch for x Axis (XYZABC) is hit. Write '1' toclear. Will not reset if the switch is still activated. The corresponding axisindex is frozen on this event until it is read, corresponding HOME_HIT bitin MACH_STAT register is written with '1,' and this IRQ is acknowledgedby writing '1' to its bit. The freeze is done by stopping transparent latchesbetween actual index counters and IDX registers so they keep the last datawhile index counters continue counting so the running position is not lost.
MACH_SP_IDX Spindle Index Pulse detected. This is single pulse perrevolution Index sensor that is used for starting lathe threading pass. Itdoubles at Spindle Timing if no Timing sensor installed. Write '1' to thisbit to clear.
MACH_SP_TIM Spindle Timing Pulse detected. This is multiple pulseper revolution Timing sensor that is used for measuring Spindle RPM forMach DRO and gearing Z Axis to the Spindle while threading or rigidtapping. See DATA_IN register for Spindle Index and Timing operationdescription. Write '1' to clear.
16
2.2.6 IRQ_MASK, O�set 0x14
X X X X
X X X X
X X X X
X X X X
X MACH_SP_TIM MACH_SP_IDX MACH_HomeC
MACH_HomeB MACH_HomeA MACH_HomeZ MACH_HomeY
MACH_HomeX MACH_PROBE MACH_FOVF MACH_FAULT
MACH_DONE MACH_TMR ADC DAC
Table 2.7: IRQ_MASK Register
X Don't care. Those bits can be written to and read back but they don't haveany e�ect for now. They might be used in the future when additionalfunctionality is implemented and add-on boards are out.
Rest Remaining bits are used to mask corresponding IRQ_RAW interrupt bits.Default to all '0' on powerup so no IRQs to PCI bus is generated.
2.2.7 IRQ_STAT, O�set 0x18
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 MACH_SP_TIM MACH_SP_IDX MACH_HomeC
MACH_HomeB MACH_HomeA MACH_HomeZ MACH_HomeY
MACH_HomeX MACH_PROBE MACH_FOVF MACH_FAULT
MACH_DONE MACH_TMR ADC DAC
Table 2.8: IRQ_STAT Register
0 Unused, read as '0.'
Rest Remaining bits are a result of bitwise AND on IRQ_RAW and IRQ_MASKregisters. PCI IRQ signal is an OR on all bits of this register. That meansthat it is only raised when the corresponding bit is set in both IRQ_RAWand IRQ_MASK. All bits are read-only. To reset (acknowledge) a partic-ular IRQ '1' should be written to a bit in IRQ_RAW register.
17
2.2.8 MACH_IDX_[XYZABC], O�sets 0x1c, 0x20, 0x24,0x28, 0x2c, 0x30
D31 D30 D29 D28 D27 D26 D25 D24
D23 D22 D21 D20 D19 D18 D17 D16
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
Table 2.9: MACH_IDX_[XYZABC] Registers
D0..31 Current Axis position, R/W. Incremented/Decremented on each andevery step output to the Axis depending on step direction. Signed (2-complement) 32-bit INT. Actual counters are connected to these registersthrough transparent latches. Those latches are open most of the timeso registers show the current positions. They are frozen when Home orProbe Switch event occurs so the exact hit position can be read. Tounfreeze them the Switch Hit event should be cleared. This is done bywriting '1' to a corresponding bit in MACH_STAT register. To preventthis condition from reoccuring if a switch is still activated one can �rstdisable that switch in MACH_CONFIG register and then write '1' toMACH_STAT bit.
2.2.9 MACH_CONFIG, O�set 0x34
PROBE_EN PROBE_NO C_HOME_EN C_HOME_NO
C_LIMS_NO C_DIR_REV C_EN B_HOME_EN
B_HOME_NO B_LIMS_NO B_DIR_REV B_EN
A_HOME_EN A_HOME_NO A_LIMS_NO A_DIR_REV
A_EN Z_HOME_EN Z_HOME_NO Z_LIMS_NO
Z_DIR_REV Z_EN Y_HOME_EN Y_HOME_NO
Y_LIMS_NO Y_DIR_REV Y_EN X_HOME_EN
X_HOME_NO X_LIMS_NO X_DIR_REV X_EN
Table 2.10: MACH_CONFIG Register
x_EN Axis x (XYZABC) enable. Enables corresponding axis hardware. Axisx(Plus,Minus,Home) signals are connected to the corresponding DATA_INbits, x(DIR/STEP) outputs switched from DATA_OUT bits to corre-sponding FIFO outputs, Limit Switches logic is enabled so MACH_FAULTIRQ will be generated.
18
x_DIR_REV Axis x (XYZABC) Direction Signal will be inverted. In Mach3'0' means �move to PLUS side.� That is what is stu�ed in FIFO for eachand every Axis. Actual drives might treat direction signals di�erently.To accomodate all of them DIR output is inverted if these bits are set to'1.' It is only the actual physical output line that is inverted, all internalsignals are still the same and MACH_IDX registers are Incremented onevery step when corresponding DIR bit is '0.'
x_LIMS_NO Axis x (XYZABC) Limit Switch is Normally Open (NO.) Usu-ally it is recommended that Limit/Home/Probe/EStop switches BREAKthe connection when activated, i.e. they are Normally Closed (NC) untilactivated. That ensures the machine will be saved from damage even ifthe switch cable is cut or otherwise disconnected. If the switch is NO itsactivation will not be detected if it is disconnected and the machine canbe damaged. If it is necessary to use NC switches this bit should be setto invert the default logic. It can also be used to make the switch signalalways inactive if there is no particular switch on the machine insteadof shorting that pin (all axes signals are �xed in hardware and there isno way to disable a Limit Switch or use its pin for something else if anAxis is enabled.) There is only ONE LIMS_NO bit per axis so BOTH ofswitches must be either NO or NC, mix is not allowed.
x_HOME_NO Axis x (XYZABC) Home Switch is Normally Open. Every-thing from x_LIMS_NO applies here.
x_HOME_EN Axis x (XYZABC) Home Switch Enable. To avoid unneces-sary interrupts and to provide for resetting HOME_HIT conditions HomeSwitches are only enabled brie�y during Homing cycles. These are per-axisEnable bits.
PROBE_NO Probe Switch is Normally Open. Everything written aboutNO/NC switches above applies.
PROBE_EN Probe Switch Enable. It is only enabled when probing, disabledall other time to provide for PROBE_HIT condition reset and eliminameunnecessary interrupts.
19
2.2.10 MACH_CONFIG2, O�set 0x38
SP_TIM_INV SP_TIM_EN TIM_DB[8..7]
TIM_DB[6..3]
TIM_DB[2..0] IDX_DB[9]
IDX_DB[8..5]
IDX_DB[4..1]
IDX_DB[0] SP_DIR_INV SP_STEP_INV SP_DIRSTEP
SP_IDX_INV SP_IDX_EN C_STEP_INV B_STEP_INV
A_STEP_INV Z_STEP_INV Y_STEP_INV X_STEP_INV
Table 2.11: MACH_CONFIG2 Register
x_STEP_INV Axis x Step signal Inverted. Usually Step Signal is outputas a pulse that turns the drive Step input optocoupler ON. Some drivesmay require inverted signal. These bits invert STEP outputs when set,per axis.
SP_IDX_EN Spindle Index signal Enable.
SP_IDX_INV Spindle Index signal is Inverted i.e. turns CENTIPEDE op-tocoupler OFF to indicate Index pulse.
SP_DIRSTEP Enables Dir/Step Spindle when set.
SP_STEP_INV Spindle Step signal Inverted i.e. drive Step input optocou-pler ON to OFF transition is used to make a step.
SP_DIR_INV Spindle Dir signal Inverted. Set this if your Spindle rotatesin the wrong direction.
IDX_DB[0..9] Spindle Index signal debounce time in 15 μS units. Indexsignal state is ignored for this number of 15 μS intervals after initial tran-sition. Write '0' to disable debouncing.
TIM_DB[0..8] Spindle Timing signal debounce time in 15 μS units. Indexsignal state is ignored for this number of 15 μS intervals after initial tran-sition. Write '0' to disable debouncing.
SP_TIM_EN Spindle Timing signal Enable.
SP_TIM_INV Spindle Timing signal is Inverted i.e. turns CENTIPEDEoptocoupler OFF to indicate Timing pulse.
20
2.2.11 MACH_CTL, O�set 0x3c
WAIT4PULSE FIFO_PURGE X X
X X X X
X X X X
X X X X
MACH_CYCLE[10..7]
MACH_CYCLE[6..3]
MACH_CYCLE[2..0] RESET
RUN NO_LIMITS ESTOP_REQ SIMULATE
Table 2.12: MACH_CTL Register
SIMULATE When set to '1' motor control outputs are kept at '0' state, noSteps output. Everything else works as usual so this is the most preciseDry Run simulation possible.
ESTOP_REQ Programmatic Emergency Stop (EStop.) Stops the CEN-TIPEDE FSM, purges FIFO. Board goes in EStop state; only periodictimer IRQs are generated.
NO_LIMITS Makes the board to ignore any of Limit Switches. Normally,when this bit is not set CENTIPEDE immediately goes into EStop state,FIFO purged, FSM stopped, FAULT IRQ generated, only periodic timeris ticking. Board will NOT go out of EStop until the condition is removedi.e. machine is moved out of Limit Switches. Setting this bit overridesthis behaviour thus allowing to jog o� the switch.
RUN Setting this bits allows the Finite State Machine (FSM) to run so theactual Mach3 work can be done.
RESET Setting this bit generates board RESET signal � most registers areset to all zero, FSM stopped, FIFO purged, periodic timer is also stoppedso no IRQs. This is self-clearing bit because reset sets all the registersto their initial state (almost always all zeroes) thus resetting this very bitamong others.
MACH_CYCLE[0..10] Mach3 Cycle Period, 11 bit. This �eld determineskernel frequency or Engine frequency as it is called in Mach3. Every Mach3cycle will be this number of PCI clocks long. PCI Clock is roughly 30 nSthat corresponds to standard 33.333 MHz PCI Frequency (the exact valueis measured by the Mach Driver.) For 100 KHz, e.g. the value is 333 (33.3MHz / 333 = 100 KHz.)
FIFO_PURGE Writing '1' to this bit will purge the FIFO � FIFO pointer(internal) will be set to the �rst element, i.e. FIFO will become empty.
21
This bit is not sticky i.e. action is only taken once on the write operationand its value is not saved. That means there is no need to write '0' thereafter writing '1.'
WAIT4PULSE Writing '1' to this bit will make CENTIPEDE put all stepdata on hold until Spindle Index Pulse. This is used for lathe threadingto start each consecutive thread pass at exactly the same spot. This bitis not sticky i.e. action is only taken once on the write operation and itsvalue is not saved. That means there is no need to write '0' there afterwriting '1.'
X Don't care.
Please note that there is no Step Pulse settings any more. It did not make senceto have them at all because ALL stepper/servo drives we are aware of only stateMINIMUM pulse width. They all make step on Step input TRANSITION,either low-to-high or high-to-low. That is why CENTIPEDE step generationhas changed.
Now we generate step pulses as transitions from inactive to active stateexactly in the middle of each Mach Cycle period and resetting it back to inac-tive at the very end of that cycle. The exact meaning of �active� depends onx_STEP_INV bits in MACH_CONFIG2 register. All Step signals are exactlyone Mach Cycle wide with actual Step transition happening at the middle of it.In Mach terms (Motor Tuning dialog) that means that both Dir and Step Pulseare ALWAYS half of Mach Cycle period i.e. half of Kernel Frequency period.For 100KHz Kernel Frequency they are both 5 μS. Mach3 settings are ignoredby the driver.
That allowed to simplify our hardware implementation a little bit thus free-ing CPLD resources for other purposes and gave us some additional bene�ts.One of those is that step is ALWAYS taken at the middle of Mach Cycle thatreduces step jitter when lathe threading or rigid tapping.
2.2.12 MACH_STAT, O�set 0x40
RUNNING ESTOP BUSY SP_STOPPED
WD_OVF X FIFO_FULL FIFO_EMPTY
FIFO_ROOM[4..1]
FIFO_ROOM[0] ProbeHit CHomeHit CMinusHit
CPlusHit BHomeHit BMinusHit BPlusHit
AHomeHit AMinusHit APlusHit ZHomeHit
ZMinusHit ZPlusHit YHomeHit YMinusHit
YPlusHit XHomeHit XMinusHit XPlusHit
Table 2.13: MACH_STAT Register
22
xPlusHit Axis x (XYZABC) Plus side Limit Switch hit. This is NOT a switchstate but the indicator it's been hit. This event generates FAULT inter-rupt and forces board into EStop. Writing '1' to these bits will clear thecondition if the Limit Switch is no longer activated. If the switch is stillactive it will have no e�ect unless NO_LIMITS bit is set in MACH_CTLregister.
xMinusHit Same as above for Minus side Limit switch.
xHomeHit Axis x (XYZABC) Home Switch hit. Freezes the IDX register forthe a�ected axis, stays set until cleared with writing '1' to a particularbit. Such a write will have no e�ect if condition still exists. Recom-mended action is read the frozen value (hit point,) disable the switchin MACH_CONFIG, reset with writing '1.' Usually Home Switches areonly enabled brie�y on Homing forward pass and disabled right after theswitch is hit. Resetting a particular bit unfreezes the corresponding axisIDX register so it starts giving the actual position.
FIFO_ROOM[0..4] Current free space left in FIFO. Used by the driver tomake a decision on how many steps it can push in FIFO.
FIFO_EMPTY Set when FIFO is empty. Indicator bit, R/O. Resets auto-matically if there is at least one entry in FIFO and its cycle is not �nished.
FIFO_FULL No more room in FIFO. R/O, self-resets when the �rst entry ispopped.
WD_OVF Watchdog timer over�ow. MACH_FAULT interrupt is generatedon this event and system goes in EStop. This bit allows to check ifMACH_FAULT has been caused by Watchdog event. Watchdog oper-ation is detailed in MACH_CONFIG3 register desctription. Will notself-reset until Watchdog is reset.
SP_STOPPED Spindle stopped. Either Dir/Step Spindle is stopped (if en-abled) or no Spindle Index/Timing pulses detected for more than 8 sec-onds.
BUSY CENTIPEDE is busy i.e. FIFO is not empty and there are still cyclesto do. R/O, self-clearing.
ESTOP Board is in EStop state � Limit Switch hit, EStop button activated,connection to BRK board lost, or ESTOP_REQ bit set in MACH_CTLregister. Writing '1' to this bit will clear EStop if the condition that forcedCENTIPEDE in that state is no longer active. Write will have no e�ectif condition persists. Will not go away by itself when condition removed;writing '1' to reset is required.
RUNNING Indicator bit, R/O meaning the board is up and running. Run-ning means board was con�gured properly and RUN bit set in MACH_CTL.
23
EStop does NOT a�ect this bit � board can be running but in EStop con-dition. '0' in this bit means FSM is stopped and board is not active, eventhe periodic timer is stopped.
X Don't care.
2.2.13 MACH_FIFO, O�set 0x44
X X X X X X X X
X X X X X X X X
X X X X CStep CDir BStep BDir
AStep ADir ZStep ZDir YStep YDir XStep XDir
Table 2.14: MACH_FIFO Register
xDir Axis x (XYZABC) Direction for current step. '0' means move to the Plusdirection. FIFO is 20 entries deep. That number is chosen because Mach3outputs Planned Motion points in sets of 5 so FIFO is made a multipleof 5. The �rst entry written to FIFO will be automatically output to themotors by CENTIPEDE hardware on the next cycle. Then it will removeit automatically and pop the next one from FIFO until no more entriesleft. It pops one entry each CENTIPEDE cycle. Periodic timer interruptis generated every 5th cycle so the driver ISR can load another set of 5steps to FIFO.
xStep Axis x (XYZABC) Step signal. Step pulse will be generated if it is '1'.Everything from xDir also applies here. As usual only 32-bit writes shouldbe used. This is a W/O register, reads are not guaranteed to return anyparticular value.
2.2.14 MACH_ENC, O�set 0x48
ENC4_CNTR[7..0]
ENC3_CNTR[7..0]
ENC2_CNTR[7..0]
ENC1_CNTR[7..0]
Table 2.15: MACH_ENC Register
ENCx_CNTR[7..0] 8-bit counter for Encoder x (1..4.) Signed (2-complement)CHAR. Increments/Decrements on Quadrature Encoder rotation depend-ing on direction. Registers are R/O and they are reset to zero after eachread. That is done to save on CPLD resources � the main 32-bit counter
24
is in the software driver and these 8-bit counters are used as �Change fromlast read.� Every periodic timer tick driver reads all these counters andadds them to the main 32-bit counters. Decoder logic for quadrature en-coders is all-hardware, x4 multiplying i.e. every transition is detected sothe actual resolution is 4 times of encoder stated one. That means thate.g. 2500 CPR encoder will give 10000 steps per revolution.
2.2.15 MACH_SPCNT, O�set 0x4c
X X X X SP_CNT[27..24]
SP_CNT[23..16]
SP_CNT[15..8]
SP_CNT[7..0]
Table 2.16: MACH_SPCNT Register
SP_CNT[0..27] Spindle Count. Number of PCI Clock pulses between last 2Spindle Timing (or Spindle Index if Timing is not enabled) pulses. Read-Only.
X Don't care.
2.2.16 MACH_SPCTL, O�set 0x50
X X X X FAKE_PULSE SP_RUN SP_DIR SP_DIV[24]
SP_DIV[23..16]
SP_DIV[15..8]
SP_DIV[7..0]
Table 2.17: MACH_SPCTL Register
SP_DIV[0..24] Dir/Step Pulse Frequency Divisor. Steps are generated by di-viding PCI clock. This is a value that determines resulting step frequencye.g. Dir/Step Spindle RPM. Every time internal counter decrements tozero Step output is inverted and counter is reloaded with SP_DIV value(this is all done by the hardware; SP_DIV is stored in a register whenwritten so it only needs to be written once for particular RPM.) For a fullstep pulse 2 such transitions needed so this value must be calculated to geta frequency twice the desired RPM multiplied by steps per rotation. E.g.if we want to get 300 RPM from a motor with 1000 steps per revolutionwe should feed it with 300(RPM) / 60(sec/min) * 1000(steps/rev) = 5KHz pulse rate. We need 2 transitions per step so we should program our
25
divisor for 5 KHz * 2 = 10 KHz frequency. PCI clock is usually 33.333MHzso to get 10 KHz we should use 33.333(MHz) / 10(KHz) = 3333 divisorvalue.
SP_DIR Dir signal for Dir/Step Spindle.
SP_RUN Go signal. Set this to '1' to actually start the Spindle, set to '0' tostop it.
FAKE_PULSE This bit imitates Spindle Timing pulse. It is only used onDriver startup to measure actual PCI clock frequency. This is Write-Onlybit.
X Don't care. No e�ect on write, read back as '0.'
Please note that there is no Step Pulse settings. It did not make sence to havethem at all because ALL stepper/servo drives we are aware of only state MIN-
IMUM pulse width. They all make step on Step input TRANSITION, eitherlow-to-high or high-to-low. Our Step Pulses are actually a constant 50% DutyCycle square wave. This is generated in hardware without any need for sot-ware intervention once SP_DIV is programmed and SP_RUN is set. Softwareonly has to intervene when Spindle RPM or some other state (e.g. Direction orRun/Stop) needs to be changed.
2.2.17 MACH_CONFIG3, O�set 0x54
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X WD_ENABLE CPUMP_INV
CPUMP_5KHZ CPUMP_ALWAYS CPUMP_ENABLE SEQ_ENABLE
Table 2.18: MACH_CONFIG3 Register
SEQ_ENABLE Setting this bit to '1' inserts a step sequencer between inter-nal Step/Dir signals and Step/Dir outputs for all axes. That means therewill be steady state on Step/Dir pairs changing with each step taken andkept until the next step instead of Step pulses. This sequencer is madefor particular machines - Bridgeport Series II BOSS 6 Mill. It allows tomake a quick retro�t by keeping its existing motors and drives, just by dis-connecting its ZDI board from Axis Drives and connecting CENTIPEDEoutputs to those drives. Step sequence consists of 4 states. Changing
26
state to the next one makes existing Drives/Motors make a step in onedirection; for opposite direction state should be changed to a previous one.State table wraps around after the �rst step (if going backwards) to thelast one and vice versa for forward direction. Here is the state table:
Pin13 Pin19
L LH LH HL H
CPUMP_ENABLE Enable ChargePump. Setting this bit to '1' enables50% duty cycle signal output on Out14 output. It is used as indicationthat Mach3 itself, the driver, and hardware is alive and well. Usually usedwith cheap Parallel Port breakout boards but it is also here if somebodyreally needs it. Unlike those cheap boards this signal is generated andcontrolled by CENTIPEDE �rmware, no Mach3 cooperation required. Ifnot con�gured to output constantly (see below) it will be only output ifMach3 is running and CENTIPEDE is not in EStop state.
CPUMP_ALWAYS ChargePump output will not stop in EStop state. How-ever it WILL stop if Mach3 is not running.
CPUMP_5KHZ If this bit is set to '1' ChargePump will output signal ofabout 5kHz frequency. Otherwise it is about 12.5kHz.
CPUMP_INV Invert ChargePump signal if set to '1.' It doesn't make anydi�erence when signal is running but a�ects the ChargePump output pin(Out14) state when signal is stopped. It will stop at LOW state if thispin is not set otherwise that pin will be kept HIGH when ChargePumpsignal is stopped.
WD_ENABLE Write '1' to enable watchdog timer. Watchdog is 4-bit binarycounter incremented on every timer interrupt request (doesn't matter iftimer IRQ is enabled or not) and reset on every timer interrupt acknowl-edgement. When it over�ows MACH_FAULT interrupt is generated, allMach3 activity stops (except timer interrupts) and watchdog timer getsfrozen in over�own state. There is only one way to get out of this state- disable and reenable watchdog.
X Don't care.
27
Chapter 3
Appendix A - Hardware
di�erences between rev.1.0
and rev.1.1
There are some di�erences between rev.1.0 and rev.1.1 CENTIPEDE-PCI boards.They are not all that signi�cant but there some caveats.
� First of all, there were 4 unpopulated footprints for optional oscillator onrev.1.0 board (elements R4, C15, U2, and R5) close to the boards center.Those were removed completely from rev.1.1 PCB. There is absolutely noimpact because those elements were never used.
� Rev.1.0 board has 4 out of 8 fast optocouplers on di�erent input lines(see section 2.2.2.) It is not very likely somebody would use that featurebut if he would one should take care to assign data lines properly withapplication software (e.g. con�guration editor or whatever it's called) forhis particular board revision.
� As a result of the above CPLD project �le di�ers between those 2 revi-sions. VHDL code is absolutely identical between the two but there aresome changes in pin assignments in centipede_pci.qsf �le and resultingcentipede_pci.pof �le is di�erent. Changes are minimal but please becareful anyway. All future CPLD �rmware will be released in versionsfor both rev.1.0 and rev.1.1 PCI boards. There is no di�erences betweenthose revisions from software point of view.
� IMPORTANT! Rev.1.0. PCI board had PCI bus GROUND con-nected to pins 69 and 78 of the External Connector, NOT +5V power. Ithad 2 +5V power pins (51 and 60) and 2 GROUND pins (69 and 78.) Onrev.1.0 CENTIPEDE-BRK board pins 69 and 78 of the mating connec-tors are NOT CONNECTED to anything so it works OK with rev.1.0
28
CENTIPEDE-PCI board. Rev.1.1 PCI board will also work just �ne withrev.1.1 BRK board though 2 +5V conductors in the cable will not beused. But rev.1.0 PCI board can NOT be used with rev.1.1 BRKboard because the latter has pins 51, 60, 69, and 78 all con-nected together that will make a short circuit between PC +5Vand ground.
� Other than that those boards absolutely identical and fully compatiblewith each other.
29
Chapter 4
Appendix B -
CENTIPEDE-PCI rev.1.0
Schematics
30
FIL
E:
RE
VIS
ION
:
DR
AW
N B
Y:
PA
GE
OF
TIT
LE
IO3_
1P
14
IO3_
2N
13
IO3_
3P
15
IO3_
4M
14
IO3_
5N
14
IO3_
6M
13
IO3_
7N
15
IO3_
8L1
4
IO3_
9N
16
IO3_
10L1
3
IO3_
11M
15
IO3_
12L1
2
IO3_
13M
16
IO3_
14L1
1
IO3_
42F
12
IO3_
41E
15
IO3_
40F
11
IO3_
39E
16
IO3_
38G
14
IO3_
37F
15
IO3_
36G
13
IO3_
35F
16
IO3_
33G
15
IO3_
32G
12
IO3_
31G
16
IO3_
30H
14
IO3_
29H
15
IO3_15L15
IO3_16K14
IO3_17L16
IO3_18K13
IO3_19K15
IO3_20K12
IO3_21K16
IO3_23J15
IO3_24J14
IO3_25J16
IO3_26J13
IO3_27H16
IO3_28H13
IO_GCLK3H12
IO_GCLK2J12
IO3_49C15
IO3_48E12
IO3_47D14
IO3_46F14
IO3_45D15
IO3_44F13
IO3_43D16
EP
M22
10 F
BG
A25
6
BA
NK
3
VC
CIO
3 I/O
PO
WE
R
IO3_53D13
IO3_52E14
IO3_51C14
IO3_50E13
U1
−12
VB
1
TC
KB
2
GN
DB
3
TD
OB
4
+5V
B5
+5V
B6
INT
BB
7
INT
DB
8
PR
SN
T1
B9
RS
VD
2B
10
PR
SN
T2
B11
RS
VD
4B
14
GN
DB
15
CLK
B16
GN
DB
17
RE
QB
18
+V
_IO
B19
AD
31B
20
AD
29B
21
GN
DB
22
AD
27B
23
AD
25B
24
+3.
3VB
25
C/B
E3
B26
AD
23B
27
GN
DB
28
AD
21B
29
AD
19B
30
+3.
3VB
31
AD
17B
32
C/B
E2
B33
GN
DB
34
IRD
YB
35
+3.
3VB
36
DE
VS
EL
B37
PC
IXC
AP
B38
LOC
KB
39
PE
RR
B40
+3.
3VB
41
SE
RR
B42
+3.
3VB
43
C/B
E1
B44
AD
14B
45
GN
DB
46
AD
12B
47
AD
10B
48
M66
EN
B49
AD
8B
52
AD
7B
53
+3.
3VB
54
AD
5B
55
AD
3B
56
GN
DB
57
AD
1B
58
+V
_IO
B59
AC
K64
B60
+5V
B61
+5V
B62
TR
ST
A1
+12
VA
2
TM
SA
3
TD
IA
4
+5V
A5
INT
AA
6
INT
CA
7
+5V
A8
RS
VD
1A
9
+V
_IO
A10
RS
VD
3A
11
3.3V
_AU
XA
14
RS
TA
15
+V
_IO
A16
GN
TA
17
GN
DA
18
PM
EA
19
AD
30A
20
+3.
3VA
21
AD
28A
22
AD
26A
23
GN
DA
24
AD
24A
25
IDS
EL
A26
+3.
3VA
27
AD
22A
28
AD
20A
29
GN
DA
30
AD
18A
31
AD
16A
32
+3.
3VA
33
FR
AM
EA
34
GN
DA
35
TR
DY
A36
GN
DA
37
ST
OP
A38
+3.
3VA
39
SD
ON
EA
40
SB
OA
41
GN
DA
42
PA
RA
43
AD
15A
44
+3.
3VA
45
AD
13A
46
AD
11A
47
GN
DA
48
AD
9A
49
C/B
E0
A52
+3.
3VA
53
AD
6A
54
AD
4A
55
GN
DA
56
AD
2A
57
AD
0A
58
+V
_IO
A59
RE
Q64
A60
+5V
A61
+5V
A62
3.3V
Key
3.3V
Key
SOLDER
COMPONENT
5V K
ey5V
Key
P1
PC
I Edg
e C
onne
ctor
1A1
3
1A2
4
1A3
7
1A4
8
1A5
11
2A1
14
2A2
17
2A3
18
2A4
21
2A5
22
1OE
1
2OE
13
1B1
2
1B2
5
1B3
6
1B4
9
1B5
10
2B1
15
2B2
16
2B3
19
2B4
20
2B5
23
VC
C24
GN
D12
U4
SN
74C
BT
D33
84C
DB
Q
1A1
3
1A2
4
1A3
7
1A4
8
1A5
11
2A1
14
2A2
17
2A3
18
2A4
21
2A5
22
1OE
1
2OE
13
1B1
2
1B2
5
1B3
6
1B4
9
1B5
10
2B1
15
2B2
16
2B3
19
2B4
20
2B5
23
VC
C24
GN
D12
U5
SN
74C
BT
D33
84C
DB
Q
1A1
3
1A2
4
1A3
7
1A4
8
1A5
11
2A1
14
2A2
17
2A3
18
2A4
21
2A5
22
1OE
1
2OE
13
1B1
2
1B2
5
1B3
6
1B4
9
1B5
10
2B1
15
2B2
16
2B3
19
2B4
20
2B5
23
VC
C24
GN
D12
U6
SN
74C
BT
D33
84C
DB
Q
1A1
3
1A2
4
1A3
7
1A4
8
1A5
11
2A1
14
2A2
17
2A3
18
2A4
21
2A5
22
1OE
1
2OE
13
1B1
2
1B2
5
1B3
6
1B4
9
1B5
10
2B1
15
2B2
16
2B3
19
2B4
20
2B5
23
VC
C24
GN
D12
U7
SN
74C
BT
D33
84C
DB
Q
1A1
3
1A2
4
1A3
7
1A4
8
1A5
11
2A1
14
2A2
17
2A3
18
2A4
21
2A5
22
1OE
1
2OE
13
1B1
2
1B2
5
1B3
6
1B4
9
1B5
10
2B1
15
2B2
16
2B3
19
2B4
20
2B5
23
VC
C24
GN
D12
U3
SN
74C
BT
D33
84C
DB
Q
P_A
D1
P_A
D3
P_A
D5
P_A
D7
P_A
D8
P_A
D10
P_A
D12
P_A
D14
P_C
/BE
1#
P_S
ER
R#
P_P
ER
R#
P_D
EV
SE
L#
P_I
RD
Y#
P_C
/BE
2#P
_AD
17
P_A
D19
P_A
D21
P_A
D23
P_C
/BE
3#
P_A
D25
P_A
D27
P_A
D29
P_A
D31
P_R
EQ
#
P_C
LK
P_I
NT
A#
P_R
ST
#
P_A
D0
P_A
D2
P_A
D4
P_A
D6
P_C
/BE
0#
P_A
D9
P_A
D11
P_A
D13
P_A
D15
P_P
AR
P_S
TO
P#
P_T
RD
Y#
P_F
RA
ME
#
P_A
D16
P_A
D18
P_A
D20
P_A
D22
P_I
DS
EL#
P_A
D24
P_A
D26
P_A
D28
P_A
D30
P_G
NT
#
P_A
D30
P_A
D28
P_G
NT
#P
_RS
T#
P_I
NT
A#
P_C
LKP
_RE
Q#
P_A
D31
P_A
D29
P_A
D27
P_A
D20
P_A
D22
P_I
DS
EL#
P_A
D24
P_A
D26
P_A
D25
P_C
/BE
3#P
_AD
23P
_AD
21P
_AD
19
P_S
TO
P#
P_T
RD
Y#
P_F
RA
ME
#P
_AD
16P
_AD
18
P_A
D17
P_C
/BE
2#P
_IR
DY
#P
_DE
VS
EL#
P_P
ER
R#
P_A
D9
P_A
D11
P_A
D13
P_A
D15
P_P
AR
P_S
ER
R#
P_C
/BE
1#P
_AD
14P
_AD
12P
_AD
10
P_A
D0
P_A
D2
P_A
D4
P_A
D6
P_C
/BE
0#
P_A
D8
P_A
D7
P_A
D5
P_A
D3
P_A
D1
+5V
+5V
+5V
+5V
PC
IEN
#
LAD
3
LAD
28LA
D30
LGN
T#
LRS
T#
LIN
TA
#
LCLK
LRE
Q#
LAD
31LA
D29
LAD
27
LAD
20LA
D22
LID
SE
L#LA
D24
LAD
26
LAD
25LC
/BE
3#LA
D23
LAD
21LA
D19
LST
OP
#LT
RD
Y#
LFR
AM
E#
LAD
16LA
D18
LAD
17LC
/BE
2#LI
RD
Y#
LDE
VS
EL#
LPE
RR
#
LAD
9LA
D11
LAD
13LA
D15
LPA
R
LSE
RR
#LC
/BE
1#LA
D14
LAD
12LA
D10
LAD
0LA
D2
LAD
4LA
D6
LC/B
E0#
LAD
8LA
D7
LAD
5
LAD
1
LAD1
LAD0LAD5LAD2
LAD3
LAD4LAD8LAD6
LC/B
E0#
LAD
9LA
D14
LAD
11LA
D12
LAD
13
LAD
15LP
ER
R#
LPA
RLS
ER
R#
LST
OP
#
LC/BE1#LTRDY#
LDEVSEL#LIRDY#
LAD19LFRAME#LAD17LAD16
LAD18LC/BE2#LAD20LAD23LAD22LAD21LIDSEL#
LRS
T#
LAD
24LI
NT
A#
LAD
26LA
D25
LAD
28
LAD
30LA
D29
LAD
31LA
D27
LGN
T#
LRE
Q#
LCLK
IO1_
1D
3
IO1_
2C
2
IO1_
3E
3
IO1_
4C
3
IO1_
5E
4
IO1_
6D
2
IO1_
7E
5
IO1_
8D
1
IO1_
9F
3
IO1_
10E
2
IO1_
11F
4
IO1_
12E
1
IO1_
13F
5
IO1_
14F
2
IO1_
42M
3
IO1_
41L5
IO1_
40M
2
IO1_
39K
3
IO1_
38M
1
IO1_
37K
4
IO1_
36L2
IO1_
35K
5
IO1_
34L1
IO1_
32K
2
IO1_
31J3
IO1_
30K
1
IO1_
29J4
IO1_15F6
IO1_16F1
IO1_17G3
IO1_18G2
IO1_19G4
IO1_20G1
IO1_21G5
IO1_22H2
IO1_24H1
IO1_25H3
IO1_26J1
IO1_27H4
IO1_28J2
TDOM5
TCKP3
TDIL6
TMSN4
IO_GCLK1J5
IO_GCLK0H5
IO1_49P2
IO1_48N3
IO1_47M4
IO1_46N2
IO1_45L3
IO1_44N1
IO1_43L4
EP
M22
10 F
BG
A25
6
BA
NK
1
VC
CIO
1 I/O
PO
WE
R
U1
IO2_
1C
13
IO2_
2B
16
IO2_
3C
12
IO2_
4A
15
IO2_
5D
12
IO2_
6B
14
IO2_
7C
11
IO2_
8B
13
IO2_
9D
11
IO2_
10A
13
IO2_
11E
11
IO2_
12B
12
IO2_
13C
10
IO2_
14A
12
IO2_
42A
4
IO2_
41C
7
IO2_
40B
5
IO2_
39D
7
IO2_
38A
5
IO2_
37E
7
IO2_
36B
6
IO2_
34A
6
IO2_
33C
8
IO2_
32B
7
IO2_
31D
8
IO2_
30A
7
IO2_
29E
8
IO2_15D10
IO2_16B11
IO2_17E10
IO2_18A11
IO2_20B10
IO2_21C9
IO2_22A10
IO2_23D9
IO2_24B9
IO2_25E9
IO2_26A9
IO2_27A8
IO2_28B8
IO2_51D5
IO2_50A2
IO2_49C5
IO2_48B3
IO2_47C6
IO2_46C4
IO2_45D6
IO2_44B4
IO2_43E6
EP
M22
10 F
BG
A25
6
BA
NK
2
VC
CIO
2 I/O
PO
WE
R
IO2_52B1
IO2_53D4
U1
IO4_
1P
4
IO4_
2R
1
IO4_
3P
5
IO4_
4T
2
IO4_
5N
5
IO4_
6R
3
IO4_
7P
6
IO4_
8R
4
IO4_
9N
6
IO4_
10T
4
IO4_
11M
6
IO4_
12R
5
IO4_
13P
7
IO4_
14T
5
IO4_
42T
13
IO4_
41N
11
IO4_
40R
12
IO4_
39M
11
IO4_
38T
12
IO4_
37P
10
IO4_
36R
11
IO4_
35N
10
IO4_
34T
11
IO4_
33M
10
IO4_
32R
10
IO4_
30T
10
IO4_
29P
9
IO4_15N7
IO4_16R6
IO4_17M7
IO4_18T6
IO4_20R7
IO4_21P8
IO4_22T7
IO4_23N8
IO4_24R8
IO4_25N9
IO4_26T8
IO4_27T9
IO4_28R9
IO_DEV_CLRnM9
IO_DEV_OEM8
IO4_49P12
IO4_48T15
IO4_47N12
IO4_46R14
IO4_45M12
IO4_44R13
IO4_43P11
EP
M22
10 F
BG
A25
6
BA
NK
4
VC
CIO
4 I/O
PO
WE
R
IO4_51P13
IO4_50R16
U1
VC
CIO
1C
1
VC
CIO
1H
6
VC
CIO
1J6
VC
CIO
1P
1
VC
CIO
2A
3
VC
CIO
2A
14
VC
CIO
2F
8
VC
CIO
2F
9
VC
CIO
3C
16
VC
CIO
3H
11
VC
CIO
3J1
1
VC
CIO
3P
16
VC
CIO
4L8
VC
CIO
4L9
VC
CIO
4T
3
VC
CIO
4T
14
VC
CIN
TH
8
VC
CIN
TH
10
VC
CIN
TJ7
VC
CIN
TJ9
GN
DIO
A1
GN
DIO
A16
GN
DIO
B2
GN
DIO
B15
GN
DIO
G7
GN
DIO
G8
GN
DIO
G9
GN
DIO
G10
GN
DIO
K7
GN
DIO
K8
GN
DIO
K9
GN
DIO
K10
GN
DIO
R2
GN
DIO
R15
GN
DIO
T1
GN
DIO
T16
GN
DIN
TH
7
GN
DIN
TH
9
GN
DIN
TJ8
GN
DIN
TJ1
0
VC
CIN
TF
10
VC
CIN
TG
11
VC
CIN
TK
6
VC
CIN
TL7
GN
DIN
TF
7
GN
DIN
TG
6
GN
DIN
TK
11
GN
DIN
TL1
0
U1
+3.
3V
EX
40E
X38
EX
36E
X34
EX
32E
X30
EX
28E
X26
EX
24E
X22
EX
20E
X18
EX
16E
X14
EX
12E
X10
EX
8E
X6
EX
4E
X2
C1
10nF
C2
0.1u
F
C3
10nF
C4
0.1u
F
C5
10nF
C6
0.1u
F
C7
10nF
C8
0.1u
F
C9 10nF
C10 10nF
C11 0.1uF
C12 0.1uF
+3.
3V
10 8 6 4 213579
J2JT
AG
EN
A1
VCC4 GND 2
OU
T3
U2
66M
Hz
R2 10K
R1 10K
R3
10K
R4 10K
+3.
3V
C15 10nF
+3.
3V
TD
I
TM
S
TC
KT
DO
66M
HZ
1 2
C13
33uF10V
1 2
C1433uF10V
+3.
3V+
5V
TDO
TCK
TDI
TMS
66MHZ
R5
33
+3.
3V
LC/B
E3#
LAD10
LAD7
PC
I
LOS
I2LS
S22
LSS
11I1
8LP
CK
1LS
S13
LOS
I1LS
S12
LSS
21
LPC
K2
I7I5
I12I3
I10I1
I2I23
I15
I21
I16
I25
I14
I28
I19
I26
I17
I24
I20 I8 I6
I9I11
I13I4
I27LSS23
I31LISO2
I29
I32I22I30
LISO1
IN, S
PI
O17O29O18
O1
O30 O9
O31 O2
O10 O3
O32
O11
O19
O4O28
O20O5
O13
O6O27O14O21O7
O24
O23
O25
O22
O16
O26
O8
O15
O12
OU
T
EX
32E
X40
EX
41E
X28
EX
38E
X30
EX
39
EX
36E
X24
EX
37
EX26EX34
EX35
EX33EX20EX31EX22EX29
EX27EX25EX23
EX
9E
X14
EX
11E
X12
EX
13
EX
15
EX
17E
X18
EX
19E
X16
EX
21
EX1
EX3
EX5
EX7
EX0
EX4
EX6
EX10EX2EX8
EX
PA
NS
ION
EX
0
EX
41E
X39
EX
37E
X35
EX
33E
X31
EX
29E
X27
EX
25E
X23
EX
21E
X19
EX
17E
X15
EX
13E
X11
EX
9E
X7
EX
5E
X3
EX
1
30 28 26 4 213252729
24 222123
20 181719
16 141315
12 10911
8 657
34 323133
38 363537
42 403941
46 444345
50 484749
J1+
5V
PC
IEN
#
CE
NT
IPE
DE
−P
CI
PC
I CN
C In
terf
ace
Boa
rd
12
1.0
Ser
gey
Kub
ushy
n <
ksi@
koi8
.net
>
31
FIL
E:
RE
VIS
ION
:
DR
AW
N B
Y:
PA
GE
OF
TIT
LE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 100
999897969594939291
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 50494847464544434241J3
1 2 4 3
7 6
8 5
FO
D05
3L
U28
1 2 4 3
7 6
8 5
FO
D05
3L
U29
1 2 4 3
7 6
8 5
FO
D05
3L
U30
1 2 4 3
7 6
8 5
FO
D05
3L
U31
1 2 3 4
8 7 6 5U
17
MO
CD
207M
1 2 3 4
8 7 6 5
U19
MO
CD
207M
1 2 3 4
8 7 6 5
U22
MO
CD
207M
1 2 3 4
8 7 6 5
U23
MO
CD
207M
1 2 3 4
8 7 6 5
U16
MO
CD
207M
1 2 3 4
8 7 6 5
U18
MO
CD
207M
1 2 3 4
8 7 6 5
U20
MO
CD
207M
1 2 3 4
8 7 6 5U
21
MO
CD
207M
Q32
Q25
Q31
Q26
Q30
Q27
Q29
Q28
RP2330
RP1330
RP44.7K
RP34.7K
I2I4I6I8I9I11
I13
I15
+3.
3V
V+
IN2
V+
IN1
I16
I14
I12
I10 I7 I5 I3 I1
+3.
3V
IN2
IGN
D
IN4
IN6
IN8
IN9
IN11
IN13
IN15
IN1
IN3
IN5
IN7
IN10
IN12
IN14
IN16
V+
IN1
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
V+
IN2
IN9
IN10
IN11
IN12
IN13
IN14
IN15
IN16
V+
IN3
IN17
IN18
IN19
IN20
IN21
IN22
IN23
IN24
V+
IN4
IN25
IN26
IN27
IN28
IN29
IN30
IN31
IN32
IVC
CM
ISO
1+M
ISO
1−M
OS
I1+
MO
SI1
−S
PC
K1+
SP
CK
1−N
SS
11+
NS
S11
−N
SS
12+
NS
S12
−N
SS
13+
NS
S13
−IG
ND
OU
T1
OU
T2
OU
T3
OU
T4
OU
T5
OU
T6
OU
T7
OU
T8
OU
T9
OU
T10
OU
T11
OU
T12
OU
T13
OU
T14
OU
T15
OU
T16
OU
T17
OU
T18
OU
T19
OU
T20
OU
T21
OU
T22
OU
T23
OU
T24
OU
T25
OU
T26
OU
T27
OU
T28
OU
T29
OU
T30
OU
T31
OU
T32
IVC
CM
ISO
2+M
ISO
2−M
OS
I2+
MO
SI2
−S
PC
K2+
SP
CK
2−N
SS
21+
NS
S21
−N
SS
22+
NS
S22
−N
SS
23+
NS
S23
−
RP6330
RP84.7K
V+
IN4
+3.
3V
I31
I29
I27
I25
I24
I22
I20
I18
IN31
IN29
IN27
IN25
IN24
IN22
IN20
IN18
1 2 3 4
8 7 6 5
U25
MO
CD
207M
1 2 3 4
8 7 6 5
U27
MO
CD
207M
1 2 3 4
8 7 6 5
U24
MO
CD
207M
1 2 3 4
8 7 6 5
U26
MO
CD
207M
RP5330
RP74.7K
+3.
3V
I32
I30
I28
I26
I23
I21
I19
I17
V+
IN3
IN32
IN30
IN28
IN26
IN23
IN21
IN19
IN17
C_I
N[1
:32]
, p.1
OU
T1
OU
T2
OU
T3
OU
T4
OU
T5
OU
T6
OU
T7
OU
T8
R38
100
R39
100
R40
100
R41
100
R42
100
R43
100
R44
100
R45
100
O1
O2
O3
O4
O5
O6
O7
O8
Q24
Q17
Q23
Q18
Q22
Q19
Q21
Q20
OU
T9
OU
T10
OU
T11
OU
T12
OU
T13
OU
T14
OU
T15
OU
T16
R30
100
R31
100
R32
100
R33
100
R34
100
R35
100
R36
100
R37
100
O9
O10
O11
O12
O13
O14
O15
O16
Q16
Q9
Q15
Q10
Q14
Q11
Q13
Q12
OU
T17
OU
T18
OU
T19
OU
T20
OU
T21
OU
T22
OU
T23
OU
T24
R22
100
R23
100
R24
100
R25
100
R26
100
R27
100
R28
100
R29
100
O17
O18
O19
O20
O21
O22
O23
O24
Q8
Q1
Q7
Q2
Q6
Q3
Q5
Q4
OU
T29
OU
T31
OU
T30
OU
T32
OU
T28
OU
T27
OU
T26
OU
T25
R14
100
R15
100
R16
100
R17
100
R18
100
R19
100
R20
100
R21
100
O29
O31
O30
O32
O28
O27
O26
O25
Vcc
11
GN
D1
2
INA
3
INB
4
OU
TC
5
NC
6
EN
17
GN
D1
8G
ND
29
EN
210
NC
11IN
C12
OU
TB
13O
UT
A14
GN
D2
15V
cc2
16
ISO
7231
U8
Vcc
11
GN
D1
2
INA
3
INB
4
OU
TC
5
NC
6
EN
17
GN
D1
8G
ND
29
EN
210
NC
11IN
C12
OU
TB
13O
UT
A14
GN
D2
15V
cc2
16
ISO
7231
U11
C_O
UT
[1:3
2], p
.1
1A1
2A7
3A9
4A15
G4
G12
1Y2
1Z3
2Y6
2Z5
3Y10
3Z11
4Y14
4Z13
VCC16
GND8
U9
SN
75A
LS19
2D
1Y3
2Y5
3Y11
4Y13
G4
G12
1A2
1B1
2A6
2B7
3A10
3B9
4A14
4B15
GN
D8
VC
C16
U10
SN
75A
LS19
3D
C21 0.1uF
C27
0.1u
FC
260.
1uF
C25
0.1u
F
C28
0.1u
F
C20 0.1uF
1 2
C1733uF10V
R7 10K
R10 10K
NS
S13
+N
SS
13−
NS
S12
+N
SS
12−
NS
S22
+N
SS
22−
NS
S23
+N
SS
23−
MIS
O1+
MIS
O1−
MIS
O2+
MIS
O2−
IVcc
IVcc
IGN
DIG
NDIV
ccIV
cc
IGN
D
IGN
D
IVC
C
IGN
D
1A1
2A7
3A9
4A15
G4
G12
1Y2
1Z3
2Y6
2Z5
3Y10
3Z11
4Y14
4Z13
VCC16
GND8
U15
SN
75A
LS19
2D
NS
S11
+N
SS
11−
SP
CK
1+S
PC
K1−
MO
SI1
+M
OS
I1−
IGN
DIG
ND
IGN
DIG
ND
R13 10K
IVcc
+3.
3V
LSS
11LP
CK
1LO
SI1
C24
0.1u
FC
230.
1uF
C22
0.1u
F
1A1
2A7
3A9
4A15
G4
G12
1Y2
1Z3
2Y6
2Z5
3Y10
3Z11
4Y14
4Z13
VCC16
GND8
U13
SN
75A
LS19
2D
NS
S21
+N
SS
21−
SP
CK
2+S
PC
K2−
MO
SI2
+M
OS
I2−
IGN
DIG
ND
IGN
DIG
ND
R12 10K
IVcc
+3.
3V
LSS
21LP
CK
2LO
SI2
SP
I[1:2
], p.
1
IS1
IS2
SS
13S
S12
SS
22S
S23
IVcc
R11 10K IGN
D
LSS
13LS
S12
LIS
O1
R9
10K
R6 10K
R8 10K
C18
0.1u
F+
3.3V
C19 0.1uF
SS
22S
S23
IS2
C16 0.1uF+3.
3V
LSS
22LS
S23
LIS
O2
SS
13S
S12
IS1
Vcc
11
GN
D1
2
INA
3
INB
4
INC
5
NC
6
NC
7
GN
D1
8G
ND
29
EN
10N
C11
OU
TC
12O
UT
B13
OU
TA
14G
ND
215
Vcc
216
ISO
7230
AU
12
Vcc
11
GN
D1
2
INA
3
INB
4
INC
5
NC
6
NC
7
GN
D1
8G
ND
29
EN
10N
C11
OU
TC
12O
UT
B13
OU
TA
14G
ND
215
Vcc
216
ISO
7230
AU
14
+5V
Q1−
Q32
FD
V30
1N
R47 12
0
R46
120
MIS
O1+
MIS
O1−
MIS
O2+
MIS
O2−
CE
NT
IPE
DE
−P
CI
PC
I CN
C In
terf
ace
Boa
rd
22
1.0
Ser
gey
Kub
ushy
n <
ksi@
koi8
.net
>
32
Chapter 5
Appendix C -
CENTIPEDE-PCI rev.1.1
Schematics
33
FIL
E:
RE
VIS
ION
:
DR
AW
N B
Y:
PA
GE
OF
TIT
LE
IO3_
1P
14
IO3_
2N
13
IO3_
3P
15
IO3_
4M
14
IO3_
5N
14
IO3_
6M
13
IO3_
7N
15
IO3_
8L1
4
IO3_
9N
16
IO3_
10L1
3
IO3_
11M
15
IO3_
12L1
2
IO3_
13M
16
IO3_
14L1
1
IO3_
42F
12
IO3_
41E
15
IO3_
40F
11
IO3_
39E
16
IO3_
38G
14
IO3_
37F
15
IO3_
36G
13
IO3_
35F
16
IO3_
33G
15
IO3_
32G
12
IO3_
31G
16
IO3_
30H
14
IO3_
29H
15
IO3_15L15
IO3_16K14
IO3_17L16
IO3_18K13
IO3_19K15
IO3_20K12
IO3_21K16
IO3_23J15
IO3_24J14
IO3_25J16
IO3_26J13
IO3_27H16
IO3_28H13
IO_GCLK3H12
IO_GCLK2J12
IO3_49C15
IO3_48E12
IO3_47D14
IO3_46F14
IO3_45D15
IO3_44F13
IO3_43D16
EP
M22
10 F
BG
A25
6
BA
NK
3
VC
CIO
3 I/O
PO
WE
R
IO3_53D13
IO3_52E14
IO3_51C14
IO3_50E13
U1
−12
VB
1
TC
KB
2
GN
DB
3
TD
OB
4
+5V
B5
+5V
B6
INT
BB
7
INT
DB
8
PR
SN
T1
B9
RS
VD
2B
10
PR
SN
T2
B11
RS
VD
4B
14
GN
DB
15
CLK
B16
GN
DB
17
RE
QB
18
+V
_IO
B19
AD
31B
20
AD
29B
21
GN
DB
22
AD
27B
23
AD
25B
24
+3.
3VB
25
C/B
E3
B26
AD
23B
27
GN
DB
28
AD
21B
29
AD
19B
30
+3.
3VB
31
AD
17B
32
C/B
E2
B33
GN
DB
34
IRD
YB
35
+3.
3VB
36
DE
VS
EL
B37
PC
IXC
AP
B38
LOC
KB
39
PE
RR
B40
+3.
3VB
41
SE
RR
B42
+3.
3VB
43
C/B
E1
B44
AD
14B
45
GN
DB
46
AD
12B
47
AD
10B
48
M66
EN
B49
AD
8B
52
AD
7B
53
+3.
3VB
54
AD
5B
55
AD
3B
56
GN
DB
57
AD
1B
58
+V
_IO
B59
AC
K64
B60
+5V
B61
+5V
B62
TR
ST
A1
+12
VA
2
TM
SA
3
TD
IA
4
+5V
A5
INT
AA
6
INT
CA
7
+5V
A8
RS
VD
1A
9
+V
_IO
A10
RS
VD
3A
11
3.3V
_AU
XA
14
RS
TA
15
+V
_IO
A16
GN
TA
17
GN
DA
18
PM
EA
19
AD
30A
20
+3.
3VA
21
AD
28A
22
AD
26A
23
GN
DA
24
AD
24A
25
IDS
EL
A26
+3.
3VA
27
AD
22A
28
AD
20A
29
GN
DA
30
AD
18A
31
AD
16A
32
+3.
3VA
33
FR
AM
EA
34
GN
DA
35
TR
DY
A36
GN
DA
37
ST
OP
A38
+3.
3VA
39
SD
ON
EA
40
SB
OA
41
GN
DA
42
PA
RA
43
AD
15A
44
+3.
3VA
45
AD
13A
46
AD
11A
47
GN
DA
48
AD
9A
49
C/B
E0
A52
+3.
3VA
53
AD
6A
54
AD
4A
55
GN
DA
56
AD
2A
57
AD
0A
58
+V
_IO
A59
RE
Q64
A60
+5V
A61
+5V
A62
3.3V
Key
3.3V
Key
SOLDER
COMPONENT
5V K
ey5V
Key
P1
PC
I Edg
e C
onne
ctor
1A1
3
1A2
4
1A3
7
1A4
8
1A5
11
2A1
14
2A2
17
2A3
18
2A4
21
2A5
22
1OE
1
2OE
13
1B1
2
1B2
5
1B3
6
1B4
9
1B5
10
2B1
15
2B2
16
2B3
19
2B4
20
2B5
23
VC
C24
GN
D12
U4
SN
74C
BT
D33
84C
DB
Q
1A1
3
1A2
4
1A3
7
1A4
8
1A5
11
2A1
14
2A2
17
2A3
18
2A4
21
2A5
22
1OE
1
2OE
13
1B1
2
1B2
5
1B3
6
1B4
9
1B5
10
2B1
15
2B2
16
2B3
19
2B4
20
2B5
23
VC
C24
GN
D12
U5
SN
74C
BT
D33
84C
DB
Q
1A1
3
1A2
4
1A3
7
1A4
8
1A5
11
2A1
14
2A2
17
2A3
18
2A4
21
2A5
22
1OE
1
2OE
13
1B1
2
1B2
5
1B3
6
1B4
9
1B5
10
2B1
15
2B2
16
2B3
19
2B4
20
2B5
23
VC
C24
GN
D12
U6
SN
74C
BT
D33
84C
DB
Q
1A1
3
1A2
4
1A3
7
1A4
8
1A5
11
2A1
14
2A2
17
2A3
18
2A4
21
2A5
22
1OE
1
2OE
13
1B1
2
1B2
5
1B3
6
1B4
9
1B5
10
2B1
15
2B2
16
2B3
19
2B4
20
2B5
23
VC
C24
GN
D12
U7
SN
74C
BT
D33
84C
DB
Q
1A1
3
1A2
4
1A3
7
1A4
8
1A5
11
2A1
14
2A2
17
2A3
18
2A4
21
2A5
22
1OE
1
2OE
13
1B1
2
1B2
5
1B3
6
1B4
9
1B5
10
2B1
15
2B2
16
2B3
19
2B4
20
2B5
23
VC
C24
GN
D12
U3
SN
74C
BT
D33
84C
DB
Q
P_A
D1
P_A
D3
P_A
D5
P_A
D7
P_A
D8
P_A
D10
P_A
D12
P_A
D14
P_C
/BE
1#
P_S
ER
R#
P_P
ER
R#
P_D
EV
SE
L#
P_I
RD
Y#
P_C
/BE
2#P
_AD
17
P_A
D19
P_A
D21
P_A
D23
P_C
/BE
3#
P_A
D25
P_A
D27
P_A
D29
P_A
D31
P_R
EQ
#
P_C
LK
P_I
NT
A#
P_R
ST
#
P_A
D0
P_A
D2
P_A
D4
P_A
D6
P_C
/BE
0#
P_A
D9
P_A
D11
P_A
D13
P_A
D15
P_P
AR
P_S
TO
P#
P_T
RD
Y#
P_F
RA
ME
#
P_A
D16
P_A
D18
P_A
D20
P_A
D22
P_I
DS
EL#
P_A
D24
P_A
D26
P_A
D28
P_A
D30
P_G
NT
#
P_A
D30
P_A
D28
P_G
NT
#P
_RS
T#
P_I
NT
A#
P_C
LKP
_RE
Q#
P_A
D31
P_A
D29
P_A
D27
P_A
D20
P_A
D22
P_I
DS
EL#
P_A
D24
P_A
D26
P_A
D25
P_C
/BE
3#P
_AD
23P
_AD
21P
_AD
19
P_S
TO
P#
P_T
RD
Y#
P_F
RA
ME
#P
_AD
16P
_AD
18
P_A
D17
P_C
/BE
2#P
_IR
DY
#P
_DE
VS
EL#
P_P
ER
R#
P_A
D9
P_A
D11
P_A
D13
P_A
D15
P_P
AR
P_S
ER
R#
P_C
/BE
1#P
_AD
14P
_AD
12P
_AD
10
P_A
D0
P_A
D2
P_A
D4
P_A
D6
P_C
/BE
0#
P_A
D8
P_A
D7
P_A
D5
P_A
D3
P_A
D1
+5V
+5V
+5V
+5V
PC
IEN
#
LAD
3
LAD
28LA
D30
LGN
T#
LRS
T#
LIN
TA
#
LCLK
LRE
Q#
LAD
31LA
D29
LAD
27
LAD
20LA
D22
LID
SE
L#LA
D24
LAD
26
LAD
25LC
/BE
3#LA
D23
LAD
21LA
D19
LST
OP
#LT
RD
Y#
LFR
AM
E#
LAD
16LA
D18
LAD
17LC
/BE
2#LI
RD
Y#
LDE
VS
EL#
LPE
RR
#
LAD
9LA
D11
LAD
13LA
D15
LPA
R
LSE
RR
#LC
/BE
1#LA
D14
LAD
12LA
D10
LAD
0LA
D2
LAD
4LA
D6
LC/B
E0#
LAD
8LA
D7
LAD
5
LAD
1
LAD1
LAD0LAD5LAD2
LAD3
LAD4LAD8LAD6
LC/B
E0#
LAD
9LA
D14
LAD
11LA
D12
LAD
13
LAD
15LP
ER
R#
LPA
RLS
ER
R#
LST
OP
#
LC/BE1#LTRDY#
LDEVSEL#LIRDY#
LAD19LFRAME#LAD17LAD16
LAD18LC/BE2#LAD20LAD23LAD22LAD21LIDSEL#
LRS
T#
LAD
24LI
NT
A#
LAD
26LA
D25
LAD
28
LAD
30LA
D29
LAD
31LA
D27
LGN
T#
LRE
Q#
LCLK
IO1_
1D
3
IO1_
2C
2
IO1_
3E
3
IO1_
4C
3
IO1_
5E
4
IO1_
6D
2
IO1_
7E
5
IO1_
8D
1
IO1_
9F
3
IO1_
10E
2
IO1_
11F
4
IO1_
12E
1
IO1_
13F
5
IO1_
14F
2
IO1_
42M
3
IO1_
41L5
IO1_
40M
2
IO1_
39K
3
IO1_
38M
1
IO1_
37K
4
IO1_
36L2
IO1_
35K
5
IO1_
34L1
IO1_
32K
2
IO1_
31J3
IO1_
30K
1
IO1_
29J4
IO1_15F6
IO1_16F1
IO1_17G3
IO1_18G2
IO1_19G4
IO1_20G1
IO1_21G5
IO1_22H2
IO1_24H1
IO1_25H3
IO1_26J1
IO1_27H4
IO1_28J2
TDOM5
TCKP3
TDIL6
TMSN4
IO_GCLK1J5
IO_GCLK0H5
IO1_49P2
IO1_48N3
IO1_47M4
IO1_46N2
IO1_45L3
IO1_44N1
IO1_43L4
EP
M22
10 F
BG
A25
6
BA
NK
1
VC
CIO
1 I/O
PO
WE
R
U1
IO2_
1C
13
IO2_
2B
16
IO2_
3C
12
IO2_
4A
15
IO2_
5D
12
IO2_
6B
14
IO2_
7C
11
IO2_
8B
13
IO2_
9D
11
IO2_
10A
13
IO2_
11E
11
IO2_
12B
12
IO2_
13C
10
IO2_
14A
12
IO2_
42A
4
IO2_
41C
7
IO2_
40B
5
IO2_
39D
7
IO2_
38A
5
IO2_
37E
7
IO2_
36B
6
IO2_
34A
6
IO2_
33C
8
IO2_
32B
7
IO2_
31D
8
IO2_
30A
7
IO2_
29E
8
IO2_15D10
IO2_16B11
IO2_17E10
IO2_18A11
IO2_20B10
IO2_21C9
IO2_22A10
IO2_23D9
IO2_24B9
IO2_25E9
IO2_26A9
IO2_27A8
IO2_28B8
IO2_51D5
IO2_50A2
IO2_49C5
IO2_48B3
IO2_47C6
IO2_46C4
IO2_45D6
IO2_44B4
IO2_43E6
EP
M22
10 F
BG
A25
6
BA
NK
2
VC
CIO
2 I/O
PO
WE
R
IO2_52B1
IO2_53D4
U1
IO4_
1P
4
IO4_
2R
1
IO4_
3P
5
IO4_
4T
2
IO4_
5N
5
IO4_
6R
3
IO4_
7P
6
IO4_
8R
4
IO4_
9N
6
IO4_
10T
4
IO4_
11M
6
IO4_
12R
5
IO4_
13P
7
IO4_
14T
5
IO4_
42T
13
IO4_
41N
11
IO4_
40R
12
IO4_
39M
11
IO4_
38T
12
IO4_
37P
10
IO4_
36R
11
IO4_
35N
10
IO4_
34T
11
IO4_
33M
10
IO4_
32R
10
IO4_
30T
10
IO4_
29P
9
IO4_15N7
IO4_16R6
IO4_17M7
IO4_18T6
IO4_20R7
IO4_21P8
IO4_22T7
IO4_23N8
IO4_24R8
IO4_25N9
IO4_26T8
IO4_27T9
IO4_28R9
IO_DEV_CLRnM9
IO_DEV_OEM8
IO4_49P12
IO4_48T15
IO4_47N12
IO4_46R14
IO4_45M12
IO4_44R13
IO4_43P11
EP
M22
10 F
BG
A25
6
BA
NK
4
VC
CIO
4 I/O
PO
WE
R
IO4_51P13
IO4_50R16
U1
VC
CIO
1C
1
VC
CIO
1H
6
VC
CIO
1J6
VC
CIO
1P
1
VC
CIO
2A
3
VC
CIO
2A
14
VC
CIO
2F
8
VC
CIO
2F
9
VC
CIO
3C
16
VC
CIO
3H
11
VC
CIO
3J1
1
VC
CIO
3P
16
VC
CIO
4L8
VC
CIO
4L9
VC
CIO
4T
3
VC
CIO
4T
14
VC
CIN
TH
8
VC
CIN
TH
10
VC
CIN
TJ7
VC
CIN
TJ9
GN
DIO
A1
GN
DIO
A16
GN
DIO
B2
GN
DIO
B15
GN
DIO
G7
GN
DIO
G8
GN
DIO
G9
GN
DIO
G10
GN
DIO
K7
GN
DIO
K8
GN
DIO
K9
GN
DIO
K10
GN
DIO
R2
GN
DIO
R15
GN
DIO
T1
GN
DIO
T16
GN
DIN
TH
7
GN
DIN
TH
9
GN
DIN
TJ8
GN
DIN
TJ1
0
VC
CIN
TF
10
VC
CIN
TG
11
VC
CIN
TK
6
VC
CIN
TL7
GN
DIN
TF
7
GN
DIN
TG
6
GN
DIN
TK
11
GN
DIN
TL1
0
U1
+3.
3V
EX
40E
X38
EX
36E
X34
EX
32E
X30
EX
28E
X26
EX
24E
X22
EX
20E
X18
EX
16E
X14
EX
12E
X10
EX
8E
X6
EX
4E
X2
C1
10nF
C2
0.1u
F
C3
10nF
C4
0.1u
F
C5
10nF
C6
0.1u
F
C7
10nF
C8
0.1u
F
C9 10nF
C10 10nF
C11 0.1uF
C12 0.1uF
+3.
3V
10 8 6 4 213579
J2JT
AG
R2 10K
R1 10K
R3
10K
+3.
3V
TD
I
TM
S
TC
KT
DO
1 2
C13
33uF10V
1 2
C1433uF10V
+3.
3V+
5V
TDO
TCK
TDI
TMS
+3.
3V
LC/B
E3#
LAD10
LAD7
PC
I
LOS
I2LS
S22
LSS
11I2
6LP
CK
1LS
S13
LOS
I1LS
S12
LSS
21
LPC
K2
I7I5
I12I3
I10I1
I2I20
I15
I18
I16
I29
I14
I22
I19
I21
I17
I28
I25 I8 I6
I9I11
I13I4
I30LSS23
I32LISO2
I31
I24I27I23
LISO1
IN, S
PI
O17O29O18
O1
O30 O9
O31 O2
O10 O3
O32
O11
O19
O4O28
O20O5
O13
O6O27O14O21O7
O24
O23
O25
O22
O16
O26
O8
O15
O12
OU
T
EX
32E
X40
EX
41E
X28
EX
38E
X30
EX
39
EX
36E
X24
EX
37
EX26EX34
EX35
EX33EX20EX31EX22EX29
EX27EX25EX23
EX
9E
X14
EX
11E
X12
EX
13
EX
15
EX
17E
X18
EX
19E
X16
EX
21
EX1
EX3
EX5
EX7
EX0
EX4
EX6
EX10EX2EX8
EX
PA
NS
ION
EX
0
EX
41E
X39
EX
37E
X35
EX
33E
X31
EX
29E
X27
EX
25E
X23
EX
21E
X19
EX
17E
X15
EX
13E
X11
EX
9E
X7
EX
5E
X3
EX
1
30 28 26 4 213252729
24 222123
20 181719
16 141315
12 10911
8 657
34 323133
38 363537
42 403941
46 444345
50 484749
J1+
5V
PC
IEN
#
CE
NT
IPE
DE
−P
CI
PC
I CN
C In
terf
ace
Boa
rd
12
1.1
Ser
gey
Kub
ushy
n <
ksi@
koi8
.net
>
34
FIL
E:
RE
VIS
ION
:
DR
AW
N B
Y:
PA
GE
OF
TIT
LE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 100
999897969594939291
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 50494847464544434241J3
1 2 4 3
7 6
8 5
FO
D05
3L
U28
1 2 4 3
7 6
8 5
FO
D05
3L
U29
1 2 4 3
7 6
8 5
FO
D05
3L
U30
1 2 4 3
7 6
8 5
FO
D05
3L
U31
1 2 3 4
8 7 6 5U
17
MO
CD
207M
1 2 3 4
8 7 6 5
U19
MO
CD
207M
1 2 3 4
8 7 6 5
U22
MO
CD
207M
1 2 3 4
8 7 6 5
U23
MO
CD
207M
1 2 3 4
8 7 6 5
U16
MO
CD
207M
1 2 3 4
8 7 6 5
U18
MO
CD
207M
1 2 3 4
8 7 6 5
U20
MO
CD
207M
1 2 3 4
8 7 6 5U
21
MO
CD
207M
Q32
Q25
Q31
Q26
Q30
Q27
Q29
Q28
RP2330
RP1330
RP42.2K
RP32.2K
I2I4I6I8I9I11
I13
I15
+3.
3V
V+
IN2
V+
IN1
I16
I14
I12
I10 I7 I5 I3 I1
+3.
3V
IN2
IGN
D
IN4
IN6
IN8
IN9
IN11
IN13
IN15
IN1
IN3
IN5
IN7
IN10
IN12
IN14
IN16
V+
IN1
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
V+
IN2
IN9
IN10
IN11
IN12
IN13
IN14
IN15
IN16
V+
IN3
IN17
IN18
IN19
IN20
IN21
IN22
IN23
IN24
V+
IN4
IN25
IN26
IN27
IN28
IN29
IN30
IN31
IN32
IVC
CM
ISO
1+M
ISO
1−M
OS
I1+
MO
SI1
−S
PC
K1+
SP
CK
1−N
SS
11+
NS
S11
−N
SS
12+
NS
S12
−N
SS
13+
NS
S13
−IG
ND
OU
T1
OU
T2
OU
T3
OU
T4
OU
T5
OU
T6
OU
T7
OU
T8
OU
T9
OU
T10
OU
T11
OU
T12
OU
T13
OU
T14
OU
T15
OU
T16
OU
T17
OU
T18
OU
T19
OU
T20
OU
T21
OU
T22
OU
T23
OU
T24
OU
T25
OU
T26
OU
T27
OU
T28
OU
T29
OU
T30
OU
T31
OU
T32
IVC
CM
ISO
2+M
ISO
2−M
OS
I2+
MO
SI2
−S
PC
K2+
SP
CK
2−N
SS
21+
NS
S21
−N
SS
22+
NS
S22
−N
SS
23+
NS
S23
−
RP6330
RP82.2K
V+
IN4
+3.
3V
I32
I31
I30
I29
I28
I27
I25
I26
IN32
IN31
IN30
IN29
IN28
IN27
IN25
IN26
1 2 3 4
8 7 6 5
U25
MO
CD
207M
1 2 3 4
8 7 6 5
U27
MO
CD
207M
1 2 3 4
8 7 6 5
U24
MO
CD
207M
1 2 3 4
8 7 6 5
U26
MO
CD
207M
RP5330
RP72.2K
+3.
3V
I24
I23
I22
I21
I20
I18
I19
I17
V+
IN3
IN24
IN23
IN22
IN21
IN20
IN18
IN19
IN17
C_I
N[1
:32]
, p.1
OU
T1
OU
T2
OU
T3
OU
T4
OU
T5
OU
T6
OU
T7
OU
T8
R38
100
R39
100
R40
100
R41
100
R42
100
R43
100
R44
100
R45
100
O1
O2
O3
O4
O5
O6
O7
O8
Q24
Q17
Q23
Q18
Q22
Q19
Q21
Q20
OU
T9
OU
T10
OU
T11
OU
T12
OU
T13
OU
T14
OU
T15
OU
T16
R30
100
R31
100
R32
100
R33
100
R34
100
R35
100
R36
100
R37
100
O9
O10
O11
O12
O13
O14
O15
O16
Q16
Q9
Q15
Q10
Q14
Q11
Q13
Q12
OU
T17
OU
T18
OU
T19
OU
T20
OU
T21
OU
T22
OU
T23
OU
T24
R22
100
R23
100
R24
100
R25
100
R26
100
R27
100
R28
100
R29
100
O17
O18
O19
O20
O21
O22
O23
O24
Q8
Q1
Q7
Q2
Q6
Q3
Q5
Q4
OU
T29
OU
T31
OU
T30
OU
T32
OU
T28
OU
T27
OU
T26
OU
T25
R14
100
R15
100
R16
100
R17
100
R18
100
R19
100
R20
100
R21
100
O29
O31
O30
O32
O28
O27
O26
O25
Vcc
11
GN
D1
2
INA
3
INB
4
OU
TC
5
NC
6
EN
17
GN
D1
8G
ND
29
EN
210
NC
11IN
C12
OU
TB
13O
UT
A14
GN
D2
15V
cc2
16
ISO
7231
U8
Vcc
11
GN
D1
2
INA
3
INB
4
OU
TC
5
NC
6
EN
17
GN
D1
8G
ND
29
EN
210
NC
11IN
C12
OU
TB
13O
UT
A14
GN
D2
15V
cc2
16
ISO
7231
U11
C_O
UT
[1:3
2], p
.1
1A1
2A7
3A9
4A15
G4
G12
1Y2
1Z3
2Y6
2Z5
3Y10
3Z11
4Y14
4Z13
VCC16
GND8
U9
SN
75A
LS19
2D
1Y3
2Y5
3Y11
4Y13
G4
G12
1A2
1B1
2A6
2B7
3A10
3B9
4A14
4B15
GN
D8
VC
C16
U10
SN
75A
LS19
3D
C21 0.1uF
C27
0.1u
FC
260.
1uF
C25
0.1u
F
C28
0.1u
F
C20 0.1uF
1 2
C1733uF10V
R7 10K
R10 10K
NS
S13
+N
SS
13−
NS
S12
+N
SS
12−
NS
S22
+N
SS
22−
NS
S23
+N
SS
23−
MIS
O1+
MIS
O1−
MIS
O2+
MIS
O2−
IVcc
IVcc
IGN
DIG
NDIV
ccIV
cc
IGN
D
IGN
D
IVC
C
IGN
D
1A1
2A7
3A9
4A15
G4
G12
1Y2
1Z3
2Y6
2Z5
3Y10
3Z11
4Y14
4Z13
VCC16
GND8
U15
SN
75A
LS19
2D
NS
S11
+N
SS
11−
SP
CK
1+S
PC
K1−
MO
SI1
+M
OS
I1−
IGN
DIG
ND
IGN
DIG
ND
R13 10K
IVcc
+3.
3V
LSS
11LP
CK
1LO
SI1
C24
0.1u
FC
230.
1uF
C22
0.1u
F
1A1
2A7
3A9
4A15
G4
G12
1Y2
1Z3
2Y6
2Z5
3Y10
3Z11
4Y14
4Z13
VCC16
GND8
U13
SN
75A
LS19
2D
NS
S21
+N
SS
21−
SP
CK
2+S
PC
K2−
MO
SI2
+M
OS
I2−
IGN
DIG
ND
IGN
DIG
ND
R12 10K
IVcc
+3.
3V
LSS
21LP
CK
2LO
SI2
SP
I[1:2
], p.
1
IS1
IS2
SS
13S
S12
SS
22S
S23
IVcc
R11 10K IGN
D
LSS
13LS
S12
LIS
O1
R9
10K
R6 10K
R8 10K
C18
0.1u
F+
3.3V
C19 0.1uF
SS
22S
S23
IS2
C16 0.1uF+3.
3V
LSS
22LS
S23
LIS
O2
SS
13S
S12
IS1
Vcc
11
GN
D1
2
INA
3
INB
4
INC
5
NC
6
NC
7
GN
D1
8G
ND
29
EN
10N
C11
OU
TC
12O
UT
B13
OU
TA
14G
ND
215
Vcc
216
ISO
7230
AU
12
Vcc
11
GN
D1
2
INA
3
INB
4
INC
5
NC
6
NC
7
GN
D1
8G
ND
29
EN
10N
C11
OU
TC
12O
UT
B13
OU
TA
14G
ND
215
Vcc
216
ISO
7230
AU
14
+5V
Q1−
Q32
FD
V30
1N
R47 12
0
R46
120
MIS
O1+
MIS
O1−
MIS
O2+
MIS
O2−
CE
NT
IPE
DE
−P
CI
PC
I CN
C In
terf
ace
Boa
rd
22
1.1
Ser
gey
Kub
ushy
n <
ksi@
koi8
.net
>
35