Ch. 6 Sequential Circuits

• Sequential Circuit Definitions• Latches• Flip-Flops• Sequential Circuit Analysis• Sequential Circuit Design• Summary

Outline

• Sequential operations – Requires storage elements that can store information between

operations.

• Implementation of sequential operations by combinational circuits – Requires cascading many structures together.– Very costly and inflexible.

• Sequential circuit design – Flip-flops + combinational logic– Behavior of sequential circuits State tables and state diagram

Sequential Circuit Definitions• Block diagram

– 조합회로 : 입력및출력변수, Logic gate의상호연결로구성 : Fig. 3-1

– 순서회로 : 조합회로 + 기억장치(Flip/Flop) : Fig. 6-1• 기억장치 : 2진정보저장, 즉주어진시간에서순서회로의상태(state) 저장

• Two main types of sequential circuits– Asynchronous sequential circuit

• 임의의연속된시간에서입력값과입력의순서에따라정의– Synchronous sequential circuit

• 불연속적인어떤시점에서동작신호가어떤값인가에따라정의• 시간의어떤시점에서기억장치요소에영향을주는신호필요

– Clock generator : Clock의주기적순서(train) 생성기– Synchronous clocked sequential circuit : Fig. 6-3

Latches• Latch

– Basic primitive for constructing storage elements.– 입력신호에의해출력이결정되고입력상태가변하지않는한유지되는요소

• SR Latch with NOR gates– Logic diagram and function table : Fig. 6-4

– Logic simulation of SR Latch behavior : Fig. 6-5

• SR Latch with NAND gates– Logic diagram and function table : Fig. 6-6

• SR Latch with control input– Logic diagram and function table : Fig. 6-7

• D Latch– Logic diagram and function table : Fig. 6-8

– D Latch with transmission gates : Fig. 6-9

Flip-Flops• Flip-Flops

– 클럭형순서회로에서사용하는기억장치요소• 제어입력에있는값의순간적인변화(trigger)에의해활성화됨.

– D, SR, JK, T Flip-Flops : Table 6-7

– Master-Slave Flip-Flop • Clock pulse가 F/F의상태를제어하고있을때동작하는 Latch와 Clock

pulse가없을때동작하는 Latch를결합시킨 F/F.

• SR Master-Slave Flip-Flop – Logic diagram : Fig. 6-10, page 250 (or 265)

• 제어입력을갖는 2개의 latch(clocked SR latch)와 1개의 inverter로구성

– Logic simulation of a Master-Slave Flip-Flop : Fig. 6-11, page 251(265)

• Edge-Triggered Flip-Flop– Clock pulse가전이(transition)되는순간에만동작하는 F/F– Negative-edge triggered F/F : Fig. 6-12

– Positive-edge triggered F/F : Fig. 6-13

• D Flip-Flop with direct set and reset : Fig. 6-15

• Standard Graphics Symbols– Standard graphic symbols for Latches and Flip-Flops : Fig. 6-14

Sequential Circuit Analysis• Sequential Circuit Analysis

– 순서회로의동작 회로의입력, 출력, 현재상태에의해결정– 출력과다음상태 입력과현재상태의함수.– 주어진요구사항에따른입력, 출력그리고상태의변화분석

• Input Equations– F/F의입력에들어가는신호에대한 Boolean 함수관계식– A sequential circuit implemented by two D-type flip-flops : Fig. 6-17

( )

A

B

D AX BX

D AX

Y A B X

= +

=

= +

• State Table– 순서회로의입력, 출력, F/F의현재상태및다음상태를정의한표– State table for Fig. 6-17. ( 1)

( 1)( )

A

B

A t D AX BXB t D AXY A B X

+ = = +

+ = =

= +

– Two-dimensional state table for the circuit in Fig. 6-17.

– Mealy Model 회로 : Fig. 6-17• 출력이현재상태뿐만아니라입력에의존하는순서회로

– Moore Model 회로 : Fig. 6-18• 출력이현재상태에만의존하는순서회로

AD A X YZ A

= ⊕ ⊕=

• State Diagram– 상태표에나타난정보, 즉입력과출력에의한상태변화를그림으로표현

– State diagram : Fig. 6-19(a)• For the sequential circuit in Fig. 6-17.• For the state table in Table 6-2

– State diagram : Fig. 6-19(b)• For the state table in Fig. 6-18(b).

Sequential Circuit Design• Design Procedure

– Specification– Formulation : 주어진문제에대한상태도및상태표작성– State assignment : 상태에 2진코드할당– Filp-Flop input equation determination : 인코드된상태표에서상태변화에따른 F/F입력식유도

– Output equation determination : 상태표의출력엔트리에대한출력식유도

– Optimization : F/F의입력식과회로의출력식간략화– Technology mapping : 논리도구성– Verification : 확인

• Finding State Diagrams and State Tables – Example 6-2 : A sequence recognizer (See page 270 (or 286))

• Find a state diagram that recognize the occurrence of the sequence of bits 1101 on X by making Z equal to 1 when the previous three inputs to the circuit were 110 and current input is a 1. Otherwise, Z equals 0.

– State table for Example 6-2

• Designing with D Flip-Flops – Given task : A sequence recognizer (Ex. 6-2 : See page 270 (or 286))

– Table 6-5

( 1) ( , , ) (3,6,7)

( 1) ( , , ) (1,3,5,7)

( , , ) (5)

A

B

A t D A B X m

B t D A B X m

Z A B X m

+ = =

+ = =

=

∑∑

∑

– Maps for input equations and output Z

( 1) ( , , ) (3,6,7)

( 1) ( , , ) (1,3,5,7)

( , , ) (5)

A

B

A t D A B X m

B t D A B X m

Z A B X m

+ = =

+ = =

=

∑∑

∑

– Logic diagram for sequential circuit with D flip-flop

– Verification by simulation : Fig. 6-30

• Homework #6– 6-5, 6-14 (a) D F/F이용, (b) JK F/F이용

Ch. 6 Sequential CircuitsOutlineSequential Circuit DefinitionsLatchesFlip-FlopsSequential Circuit AnalysisSequential Circuit Design