1 sequential circuits definition of sequential circuit synchronous sequential circuit asynchronous...

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SEQUENTIAL CIRCUITS

DEFINITION OF SEQUENTIAL CIRCUIT SYNCHRONOUS SEQUENTIAL CIRCUIT ASYNCHRONOUS SEQUENTIAL CIRCUIT

MEMORY ELEMENTS CLASSIFICATION: LATCHES AND FLIP-FLOPS LATCHES

BASIC LATCH GATED LATCH

EFFECT OF PROPAGATION DELAYS FLIP-FLOPS

ASYNCHRONOUS SEQUENTIAL CIRCUIT ASYNCHRONOUS BEHAVIOR ANALYSIS OF ASYNCHROUNOUS CIRCUITS

__________________________________________________ECSE-323/Department of Electrical and Computer Engineering/McGill University/ Prof. Marin. Revised 2005-02-14.Figures taken from Fundamentals of Digital Logic with VHDL Design, S. Brown and Z. Vranesic, 2nd Edition, McGraw Hill.

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DEFINITION OF SEQUENTIAL CIRCUIT CIRCUITS IN WHICH THE VALUES OF THE OUTPUTS

DEPENT ON: THE PRESENT VALUES OF THE INPUTS THE PAST BEHAVIOR OF THE CIRCUITARE CALLED SEQUENTIAL CIRCUIT. IN SUCH CIRCUITS STORAGE ELEMENTS STORETHE VALUES OF THE SIGNALS. THE CONTENTS OF THESTORAGE ELEMENTS REPRESENT THE STATE OF THECIRCUIT.THERE ARE TWO TYPES:

SYNCHRONOUS, AND ASYNCHRONOUS

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DEFINITION OF SEQUENTIAL CIRCUIT

SYNCHRONOUS SEQUENTIAL CIRCUITS: ARE SEQUENTIAL CIRCUITS CONTROLLED BY A CLOCK

SIGNAL

Combinational circuit

Flip-flops

Clock

Q

W Z

Combinational circuit

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DEFINITION OF SEQUENTIAL CIRCUIT

ASYNCHRONOUS SEQUENTIAL CIRCUITS:ARE SEQUENTIAL CIRCUITS:

WITH NO CLOCK SIGNALS, NO FLIP-FLOPS TO STORE STATE VARIABLES

Feedback signal Gate-delay

R

S Q Y y

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MEMORY ELEMENTS

EXAMPLES OF MEMORY ELEMENTS:

A B

A B OutputData

Load

TG1

TG2

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MEMORY ELEMENTS

CLASSIFICATION: LATCHES AND FLIP-FLOPS

BASIC LATCH: is a feedback connection of two NOR gates or two NAND gates.

GATED LATCH: is a basic latch that includes input gating and a control input signal.

FLIP-FLOPS: is a storage element based on the gated latch principle which can have its output state changed only at the edge of the controlling clock signal.

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MEMORY ELEMENTS

CLASSIFICATION: LATCHES AND FLIP-FLOPS (Continues)

The state of the LATCH keeps changing according to the values of the input signals during the period when the clock is active.

The state of the FLIP-FLOP changes only at the edge of the controlling clock signal.

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MEMORY ELEMENTS

LATCHES: BASIC LATCH

S R Qa Qb

0 00 11 01 1

0/1 1/00 11 00 0

(a) Circuit (b) Truth table

Time

1

0

1

0

1

0

1

0

R

S

Qa

Qb

Qa

Qb

?

?

(c) Timing diagram

R

S

t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

(no change)

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MEMORY ELEMENTSLATCHES: GATED RS LATCH

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MEMORY ELEMENTS

LATCHES: GATED D LATCH

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MEMORY ELEMENTS

EFFECT OF PROPAGATION DELAYS: Latch Setup and hold times.

SETUP TIME: Minimum time that the D input signal must be stable prior to the negative (positive) edge of the Clk (clock) signal.

HOLD TIME: Minimum time that the D input signal must remain stable after the negative (positive) edge of the Clk (clock) signal

t sut h

Clk

D

Q

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MEMORY ELEMENTS FLIP-FLOPS:They are storage elements that can change their state no

more thanonce during one clock cycle. Two types: Master-Slave and Edge-triggered. Master-Slave Flip-flop:

D

Clock

Q m

Q Q s =

(b) Timing diagram

D Q

Q

(c) Graphical symbol

D Q

Q

Master Slave

D Q

Q

D Q

Q

Q m Q s

(a) Circuit

Clk Clk

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MEMORY ELEMENTS

FLIP-FLOPS (Continues). Edge-triggered Flip-flop

D

Clock

P4

P3

P1

P2

5

6

1

2

3

(a) Circuit

D Q

Q

(b) Graphical symbol

Clock

Q

Q

4

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MEMORY ELEMENTS

INPUT/OUTPUT BEHAVIOR OF LATCHES AND FLIP-FLOPS*

_______________________________________* Contemporary Logic Design by R.H. Katz, Benjamin Cummings, 1994, page 290.

TYPES WHEN INPUTS ARE SAMPLED WHEN OUTPUTS ARE VALID

UNCLOCKED LATCH(Basic latch)

ALWAYS PROPAGATION DELAY FROM INPUT CHANGE

LEVEL-SESITIVE LATCH(Gated latch)

CLOCK HIGHtsu , th around falling clock edge

PROPAGATION DELAY FROM INPUT CHANGE

POSITIVE-EDGE FLIP-FLOP CLOCK LOW-TO-HIGH TRANSITIONtsu , th around rising clock edge

PROPAGATION DELAY FROM RISING EDGE OF CLOCK

NEGATIVE-EDGE FLIP-FLOP CLOCK HIGH-TO-LOW TRANSITIONtsu , th around falling clock edge

PROPAGATION DELAY FROM FALLING EDGE OF CLOCK

MASTER-SLAVE FLIP-FLOP CLOCK HIGH-TO-LOW TRANSITIONtsu , th around falling clock edge

PROPAGATION DELAY FROM FALLING EDGE OF CLOCK

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MEMORY ELEMENTS

LEVEL-SENSITIVE VERSUS EDGE-TRIGGERED STORAGE ELEMENTS

D Q

Q

D Q

Q

D Q

Q

D

Clock Q a

Q b

Q c

Q c

Q b

Q a

Clk

D

Clock

Q a

Q b

(b) Timing diagram

Q c

(a) Circuit

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MEMORY ELEMENTSFLIP-FLOPS (Continues)

CHARACTERISTIC AND EXCITATION EQUATIONS OF D, T AND J-K FLIP-FLOPS

Type Symbol Characteristic

Excitation

D-type D Q+ 0 01 1

Q Q+ D0 0 00 1 11 0 01 1 1

T-type T Q+ 0 Q1 !Q

Q Q+ T0 0 00 1 11 0 11 1 0

Q

!QD

>Clk

Q

Clk !Q

T

>

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MEMORY ELEMENTS FLIP-FLOPS (Continues)

CHARACTERISTIC AND EXCITATION EQUATIONS OF D, T AND J-K FLIP-FLOPS

Type Symbol Characteristic Excitation

J-K-type J K Q+ 0 0 Q0 1 01 0 11 1 !Q

Q Q+ J K0 0 0 x0 1 1 x1 0 x 11 1 x 0

SR-type(not in use;shown here for completeness)

S R Q+ 0 0 Q0 1 01 0 1 1 1

Forbidden

Q Q+ S R0 0 0 x0 1 1 01 0 0 11 1 x 0

Q

!Q

J

>

K

Clk

S

RQ

!QClk>

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MEMORY ELEMENTS

FLIP-FLOPS (Continues) FLIP-FLOP CONVERSIONS : Given a flip-flop as a buiding

block, produce another type of flip-flop. APPROACH: Determine the input logic to the given flip-

flop by satisfying the condition that both flip-flops must have identical logic behavior (their outputs are the same)

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MEMORY ELEMENTS FLIP-FLOP CONVERSIONS (Continues): Example: Produce the circuit of a J-K-type flip-flop using a T-type

flip-flop as a building block and NAND gates as needed

The corresponding circuit is shown on next slide

J K Q Q+JK Q+

T T

0 00 00 10 11 01 01 11 1

01010101

01001110

01001110

00011011

T = J !Q + K Q

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MEMORY ELEMENTS

FLIP-FLOP CONVERSIONS: Example (Continues): Circuit of a J-K flip-flop using a T

flip-flop

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ASYNCHRONOUS SEQUENTIAL CIRCUIT

IN SYNCHRONOUS SEQUENTIAL CIRCUITS A CLOCK SIGNAL CONSISTING OF PULSES, CONTROLS THE STATE VARIABLES WHICH ARE REPRESENTED BY FLIP-FLOPS. THEY ARE SAID TO OPERATE IN PULSE MODE.

IN ASYNCHRONOUS CIRCUITS STATE CHANGES ARE NOT TRIGGERED BY CLOCK PULSES. THEY DEPEND ON THE VALUES OF THE INPUT AND FEEDBACK VARIABLES.TWO CONDITIONS FOR PROPER OPERATION:

1.-INPUTS TO THE CIRCUIT MUST CHANGE ONE AT A TIME AND MUST REMAIN CONSTANT UNTIL THE CIRCUIT REACHES STABLE STATE.

2.-FEEDBACK VARIABLES SHOULD CHANGE ALSO ONE AT A TIME. WHEN ALL INTERNAL SIGNALS STOP CHANGING, THEN THE CIRCUIT IS

SAID TO HAVE REACHED STABLE STATE.WHEN THE INPUTS SATISFY CONDITION 1 ABOVE, THEN THE CIRCUIT ISSAID TO OPERATE IN FUNDAMENTAL MODE.

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ASYNCHRONOUS BEHAVIORConsider the Set-Reset latch. The gates shown below have no delay. Their delay

(twice one-gate delay) is represented by the square. R

S Q Y y

(a) Circuit with modeled gate delay

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ASYNCHRONOUS BEHAVIOR: Set-Reset latch (continues) The circuit behavior is represented by a State-assigned table or

Flow table which show every possible transition of the circuit for each input value. Stable-states are those circled in the table because, while the inputs are stable, present state is equal to next state (internal variables stop changing). Columns with no circled sates indicate circuit oscillation for that particular input value.

Figure 9.1. Analysis of the S-R latch.

(b) State-assigned table

Present Nextstate

state SR = 00 01 10 11y Y Y Y Y

0 0 0 1 0

1 1 0 1 0

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ASYNCHRONOUS BEHAVIOR: Set-Reset latch (continues) FINITE-STATE-MACHINE MODEL: MOORE MODEL

Figure 9.2. FSM model for the SR latch. MOORE MODEL

(a) State table

(b) State diagram

Present Next state Outputstate SR = 00 01 10 11 Q

A A A B A 0 B B A B A 1

1000

110100

10

A 0 B 1

1101

SR

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ASYNCHRONOUS BEHAVIOR: Set-Reset latch (continues) FINITE-STATE-MACHINE MODEL: MEALY MODEL

(a) State Table

(b) State Diagram

Present Nextstate Output, Q

state SR = 00 01 10 11 00 01 10 11

A A A B A 0 0 0

B B A B A 1 1–

–

–

10/100/1

11/001/000/0

10/ –

A B

01 –11 –

SR/Q

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ANALYSIS OF ASYNCHROUNOUS CIRCUITSPROCEDURE: CUT ALL FEEDBACK PATHS AND INSERT A DELAY

ELEMENT AT EACH POINT WHERE CUT WAS MADE INPUT TO THE DELAY ELEMENT IS THE NEXT STATE

VARIABLE Yi WHILE THE OUTPUT IS THE PRESENT VALUE yi.

DERIVE THE NEXT-SATE AND OUTPUT EXPRESSIONS FROM THE CIRCUIT

DERIVE THE EXCITATION TABLE DERIVE THE FLOW TABLE DERIVE A STATE-DIAGRAM FROM THE FLOW TABLE

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ANALYSIS OF ASYNCHROUNOUS CIRCUITS: EXAMPLE

D

C

Q Y y

(a) Circuit

Present Next state

state CD = 00 01 10 11y Y Y Y Y Q

0 0 0 0 1 0

1 1 1 0 1 1

(b) Excitation table

Present Next state

state CD = 00 01 10 11 Q

A A A A B 0

B B B A B 1

(c) Flow table

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ASYNCHRONOUS SEQUENTIAL CIRCUIT ANALYSIS OF ASYNCHROUNOUS CIRCUITS: EXAMPLE CONTINUES

Present Next state

state CD = 00 01 10 11 Q

A A A A B 0

B B B A B 1

(c) Flow Table

(d) State Diagram: Moore Model

x10x

x00x

11

A 0 B 1

10

CD

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SYNTHESIS OF ASYNCHROUNOUS CIRCUITS THIS TOPIC IS NOT COVERED IN THIS COURSE. IT BELONGS

TO A MORE ADVANCED LOGIC DESIGN COURSE. THIS SUBJECT IS VERY IMPORTANT IN TODAYS DIGITAL

SYSTEMS DESIGN BECAUSE CLOCKS ARE SO FAST THAT THEY PRESENT PROPAGATION DELAYS MAKING SUBSYSTEMS TO OPERATE OUT OF SYNCHRONIZATION.

TECHNIQUES FOR SYNTHESIS OF ASYNCHRONOUS CIRCUITS INCLUDE

THE HOFFMAN OR CLASSIC SYNTHESIS APPROACH HANDSHAKING SIGNALING FOR TWO SUBSYSTEMS TO

COMMUNICATE ASYNCHRONOUSLY