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Dept. of Info. & Comm.Chap. 8 Integrated-Circuit Logic Families

8-1Chap. 8 Integrated-Circuit Logic Families

Introduction Digital IC technology has advanced rapidly(Chap 4)

Moore’s Law» The number of components that can be packed on a computer chip doubles every 18

months while price stays the same.

Most of the reasons that modern digital systems use integrated circuits Integrated circuits pack a lot more circuitry in a small package

» the overall size of any digital system is reduced the cost is dramatically reduced because of the economies of mass-producing large volumes of

similar devices

Integrated circuits have made digital systems more reliable by reducing the number of external interconnections

» Discrete components(transistor, diode, resistor, etc.) are protected from poor soldering, breaks or shorts in connecting paths on a circuit board

Complexity Number of Gates

Small-scale integration(SSI) Fewer

Medium-scale integration(MSI) 12 to 99(102 - 10

3)

Large-scale integration(LSI) 100 to 9,999(103 - 10

5)

Very large-scale integration(VLSI) 10,000 to 99,999(105 - 10

7)

Ultra large-scale integration(ULSI) 100,000 to 999,999(107 - 10

9)

Giga-scale integration(GSI) 1,000,000 or more(109 - 10

11)

Tera-scale integration(TSI) (1012 or more)



8-2

Integrated circuits have drastically reduced the amount of electrical power needed to perform a given function

» Integrated circuitry typically requires less power than their discrete counterparts the saving in power supply costs does not require much cooling

There are some things that Integrated Circuits cannot do Integrated circuits can not handle very large currents or voltages (because the

heat generated in such small spaces would cause temperatures to rise beyond acceptable limits)

Integrated circuits can not easily implement certain electrical devices such as inductors, transformers, and large capacitors

For these reason Integrated circuits are principally used to perform low-power circuit operations

that are commonly called information processing The operations that require high power levels or devices that can not be

integrated are still handled by discrete components

Various Logic Families Bipolar transistors : TTL and ECL Unipolar MOSFET transistors : NMOS, PMOS, and CMOS

* Transistor의 작용은 carrier로서1) Electron 과 Hole, 모두의 이동

을 이용하는 Bipolar2) Electron 또는 Hole 중 하나만

의 이동을 이용하는 Unipolar



8-3

In this chapter We will present the important characteristics of each of IC families You will be much better prepared to do analysis, troubleshooting, and some

design of digital circuits

8-1 Digital IC Terminology Current and Voltage Parameters : Fig. 8-1

VIH (min) : high- level input voltage VIL (max) : low- level input voltage VOH (min) : high- level output voltage VOL (max) : low- level output voltage IIH : high- level input current IIL : low- level input current IOH : high- level output current IOL : low- level output current

» Actual current direction : Fig. 8-5 Fan-Out( = Loading Factor )

maximum number of standard logic inputs that an output can drive reliably» Fan-Out = 10 : one logic gate can drive 10 standard logic inputs

min, max 는 Fig. 8-4 참조



8-4

Propagation Delays : Fig. 8-2 (INVERTER) tPLH : delay going from LOW to HIGH tPHL : delay going from HIGH to LOW

Power Requirements Every IC requires a certain amount of electrical power to operate. Power supply terminal on a chip : VCC (for TTL), VDD (for MOS) Current drain ICC on the VCC supply : Fig. 8-3

» ICCH : Current drain when all of the gate outputs are HIGH» ICCL : Current drain when all of the gate outputs are LOW

Average Current» ICC(avg) = ( ICCH + ICCL ) / 2

Average Power» PD(avg) = ICC(avg) X VCC

Speed-Power Product Digital IC families have historically been characterized for both speed and power

» shorter gate propagation delays (higher speed)» lower values of power dissipation

Multiply the gate propagation delay by the gate power dissipation



8-5

예제) average propagation delay = 10 ns, average power dissipation = 5 mW» Speed-Power Product = 10 ns X 5 mW = 50 X 10 -12 watt-second

= 50 Pico-joules (pJ)

Noise Immunity Stray electric and magnetic fields can induce voltages on the connecting wires

between logic circuits» These unwanted, spurious signals are called noise

Noise Immunity» Circuit’s ability to tolerate noise without causing spurious changes in the output voltage

Noise Margin : Fig. 8-4» Quantitative measure of noise immunity

High-state noise margin : VNH = VOH (min) - VIH (min) Low-state noise margin : VNL = VIL (max) - VOL (max)

Exam. 8-1) Determine the following by using Tab. 8-1 (a) The maximum-amplitude noise spike that can be tolerated when a HIGH

output is driving an input : VNH = VOH (min) - VIH (min) = 2.4 V - 2.0 V = 0.4 V (b) The maximum-amplitude noise spike that can be tolerated when a LOW

output is driving an input : VNL = VIL (max) - VOL (max) = 0.8 V - 0.4 V = 0.4 V



8-6

•Fig. 8-4 dc noise margins



8-7

Invalid Voltage Levels Invalid Voltage Level : Input voltage between 0.8 and 2.0 V

» produce an unpredictable output response In normal operation, a logic input voltage will not fall into the invalid region

(because it comes from a standard logic output) Invalid Input Voltage Level 의 원인

» 1) Output is overloaded (= its fan-out is exceeded) » 2) Power-supply voltages are outside the acceptable range

Current Sourcing/ Current Sinking Action Current Sourcing Action : Fig. 8-5(a)

» When the output of gate 1 is in the HIGH state the output of gate 1 is acting as a source of current for the gate 2 input

Current Sinking Action : Fig. 8-5(b)» When the output of gate 1 is in the LOW state

the output of gate 1 is acting as a sink of current for the gate 2 input

IC Packages Common IC Packages : Fig. 8-6

» DIP : Leads are inserted through holes in the board (또는 socket 사용)» QFP, SOIC (gull-wing) : surface mount technology places an IC onto conductive pads

on the surface of the board



8-8

High

Low

•Fig. 8-5 current sourcing and sinking



8-9

» PLCC (J-lead) : socket or surface mount Package Dimensions : Tab. 8-2

» Lead pitch : space between pins mil = 1 / 1000 inch

8-2 The TTL Logic Family Basic TTL NAND gate : Fig. 8-7(a)

Tr. Q1 has two emitters» Multiple-emitter input transistor can have up to

eight emitters for an eight-input NAND gate Totem-Pole arrangement : Tr. Q3 and Q4

» Either Q3 or Q4 will be conducting (ON)

Diode equivalent of the multiple-emitter Tr. Q1 : Fig. 8-7(b) DTL Diodes D2 and D3 : two E-B junctions of Q1 Diode D4 : C-B junction of Q1

Circuit Operation - LOW output state : Fig. 8-8(a) D1 is needed to keep Q3 off ( = Level Shift Diode )

» Base Voltage (Q3) = 0.8 V = VBE (Q4) + VCE (Q2) = 0.7 V + 0.1 V 그러나 Q3가 ON 되려면 VCE (Q4) + VD1 + VBE (Q3) = 0.1 V + 0.7 V + 0.7 V = 1.5 V 가 필요

하지만 0.8 V 밖에 안되어 Q3는 항상 OFF

VBE(on) = 0.7 VVCE(sat) = 0.1 V - Ge

0.2 V - Si

VCE

IC

Transistor Characteristic

IB

Saturate Region

ActiveRegion

VCE(sat)

ON

OFFCut-offRegion



8-10

•‘1’

•‘1’•‘0’

•NAND Gate : Low output

x

x

•0.1 V •0.7 V

•0.1 V

•Leakage current

•= = 0.8 V•→ Q3 = off

•Fig. 8-8(a) Low output



8-11•NAND Gate : High output

•‘1’

•‘0’•‘1’

x

x

•VD1 0.7 V•VBE 0.7 V

• ? VR2

Emitter-follower : Q3-Input = Base-Output = Emitter

•Fig. 8-8(b) High output



8-12

Circuit Operation - HIGH output state : Fig. 8-8(a) VOH will be around 3.4 to 3.8 V (typically 3.6 V)

» 5 V (Vcc) - VBE (Q3) - VD1 – VR2 = 5 V - 0.7 V - 0.7 V - VR2 3.6 V IIL = V / R = ( Vcc - VD3) / R1 = ( 5 V - 0.7 V ) / 4 K = 1.075 mA

R1, R2, R3, and R4 in Fig. 8-8(b) R1 : A 와 B 중에서 어느 한쪽이 “0” 일 때, R1 이 없으면 Vcc가 그대로 Ground로

연결되어 전원이 Short 된다

R2 : R2 가 없으면 Q2의 ON/OFF 에 관계없이 Q3의 Base에는 항상 Vcc가인가되어 Q3는 항상 ON 된다.

R3 : R3 가 없으면 Q2 와 Q4 가 Darlington 접속이 되어 hFE = hFE (Q2) X hFE (Q4) 로 매우 크게 되어 발열이 심하여 동작이 불안하다.

R4 : Q3 가 ON 일 때 전류 제한용으로 사용된다. Current-Sinking Action : Fig. 8-9(a)

Q4 : Current-sinking transistor or Pull-down transistor Current-Sourcing Action : Fig. 8-9(b)

Q3 : Current-sourcing transistor or Pull-up transistor IIH : small reverse-bias leakage current (typically 10 A)

» Fig. 8-8(a) 참고



8-13

Totem-Pole Output Circuit Totem-Pole을 사용하는 이유

» Q3 와 Q4 가 교대로 동작하여 열 방출을 감소시킬 수 있다. Q3 가 없을 때는 Q4 가 ON 되면 아주 큰 전류(5 V / 130 = 40 mA)가 흘러서 많은 열 발생.

» Output HIGH state에서 Q3 가 낮은 출력 Impedance(10 )를 갖는 Emitter Follower로동작한다.

This low output impedance provides a short time constant for charging up any capacitive load on the output

효율적인 신호 전송을 위해서는 출력단의 출력 impedance는 적을 수록, 그리고 입력단의 입력impedance는 클 수록 좋다(전압 분배의 법칙).

Totem-Pole의 단점 : Current Transients, Fig 8-18» During the transition from LOW to HIGH, Q4 turns off more slowly than Q3 turns on.

So there is a period of a few nanoseconds during both transistors are conducting (ON) 이때 Relatively large current (30 to 40 mA) will be drawn from the power supply.

TTL NOR Gate : Fig. 8-10 Multiple-emitter transistor is not used

» each input is applied to the emitter of a separate transistor The same totem-pole arrangement as the NAND gate is used Output HIGH : Input A = B = 0

» Q1 = Q2 = ON, Q3 = Q4 = OFF, Q5 = ON, Q6 = OFF Output LOW : Input A = B = 1

» Q1 = Q2 = OFF, Q3 = Q4 = ON, Q5 = OFF, Q6 = ON

Fig. 8-8에서 Q3 와 D1을 제거하고R4와 Q4를 연결해도 NAND gate 가능



8-14

A B X

LOW LOW HIGH

LOW HIGH LOW

HIGH LOW LOW

HIGH HIGH LOW

•0 1

•0 1

•on•off

•on•off

•on•off

•off•on

•off•on

•off•on

•Fig. 8-10 TTL NOR gate



8-15

8-3 TTL Data Sheets TTL Series Characteristics

Manufacturers use same numbering system Manufacturers attach unique prefix

» Texas Instruments - SN (SN7402)» National Semiconductor - DM (DM7402)» Signetics - S (S7402)

74 and 54 Series basically the same» 54 series can operate over

Wider temperature range Power- supply voltage

Original Standard Series» 74, 74LS, 74S

No longer recommended by the manufacturers for use in new design Still enough demand in the market to keep them in production

Advanced and Fast TTL Series » 74AS, 74ALS, 74F

Manufacturer’s Data Sheets Data Sheet for 5400/7400 NAND gate : Fig. 8-11

» Recommended operating conditions, Electrical characteristics, and Switching Characteristics are shown

다음 Paragraph 부터 Data Sheet의 내용을 하나 씩 설명함



8-16

Supply Voltage and Temperature Range 74 and 54 have nominal supply voltage VCC = 5 V Supply Voltage

» Standard 74 operate reliably from 4.75 to 5.25 V» Standard 54 operate reliably from 4.5 to 5.5 V» 74/54 ALS operate reliably from 4.5 to 5.5 V

Temperature Range : TA» 74 operates from 0 to 70 C» 54 operates from -55 to +125 C

54 series more expensive : Military or Space application Voltage Levels (74ALS) : Tab. 8-3

LOW state noise margin = 300 mV» VNL = VIL (max) - VOL (max) = 0.8 V - 0.5 V = 0.3 V

HIGH state noise margin = 500 mV» VNH = VOH (min) - VIH (min) = 2.5 V - 2.0 V = 0.5 V

Maximum Voltage Ratings Voltages applied to any input of a standard 74 ALS series

» HIGH : never exceed +5.5 7.0 V not shown in Fig. 8-11» LOW : never be smaller than –0.5 V generally given at the top of a data sheet

Input Clamp Diode(Shunt Diode) : to clamp negative input ringing (the most negative voltage at an input)

VIK (MAX) : 1.2 1.5 V in Fig. 8-11Refer to Fig. 8-12



8-17

Power Dissipation(ALS) ICC (avg) = ( ICCH + ICCL ) / 2 = ( 0.85 mA + 3 mA ) / 2 = 1.93 mA

» Fig. 8-11에서 ICCH = 0.85 mA, ICCL = 3 mA PD (avg) = 1.93 mA X 5 V = 9.65 mW : 한 개 IC에 4 개 NAND gate의 전력 소모량

» 따라서 한 개의 Standard TTL NAND gate 전력 소모량 = 2.4 mW power (1/4)

Propagation Delays tpd (avg) = ( tPLH + tPHL ) / 2 = 6 ns

» tPLH = 7 ns, tPHL = 5 ns (중간 값 in Fig. 8-11)

Exam. 8-2) Determine the maximum average power dissipation and the maximum average propagation delay of a single gate (74ALS00 in Fig. 8-11) PD (max) = ICC (max) X Vcc(max) = 1.93 mA X 5.5 V = 10.45 mW

따라서 4 로 나누면 PD (max) = 2.6 mW per gate» ICC (max) = [ ICCH (max) + ICCL (max) ] / 2 = ( 0.85 mA + 3 mA ) / 2 = 1.93 mA

tpd (max) = [ tPLH (max) + tPHL(max) ] / 2 = ( 11 ns + 8 ns ) / 2 = 9.5 ns» tPLH(max) = 11 ns, tPHL(max) = 8 ns



8-18

8-4 TTL Series Characteristics (= TTL Subfamilies) 74 : Standard TTL

No longer a reasonable choice for new designs 74L : Low-power TTL

Low-power (1 mW) Longer propagation delay (33 ns)

74H : High-speed TTL High-speed (6 ns) Higher-power (23 mW)

74S : Schottky TTL 74S series reduces a storage-time delay by not allowing

the transistor to go as deeply into saturation 74S00 NAND gate : Fig. 8-12(b)

» High-speed (3 ns)» Power dissipation (20 mW)» Darlington pair (Q3 and Q4)

shorter output rise time when switchingfrom ON to OFF

* Standard TTLPower Dissipation : 10 mWPropagation Delays : 9 ns

Pt Si

Schottky Barrier Diode

0.2 0.4 0.6V

i

Forward Bias* Schottky Barrier Diode(SBD)

금속과 반도체를 연결하면 ECL 보다는 느리지만 동작속도가 빨라짐(0.25 - 0.4 Volt에서 동작) Schottky Transistor

Forward Bias V 가 증가하면서 Off 에서On 된 후, 다시 Forward Bias V 가 감소하면서 On에서 Off 되는 시간

=



8-19

74LS : Low-power Schottky TTL Lower-power (2 mW) Slower-speed (9.5 ns)

74AS : Advanced Schottky TTL Fastest TTL series (1.7 ns) 74AS compare with 74S : Tab. 8-4

74ALS : Advanced Low-power Schottky TTL Lowest speed-power product (4.8 pJ = 4 ns x 1.2mW) Lowest gate power dissipation (1.2 mW) 74ALS compare with 74LS : Tab. 8-5

74F : Fast TTL Propagation delay (3 ns) Power dissipation (6 mW)

Comparison of TTL Series Characteristics : Tab. 8-6 Exam. 8-3) Calculate the dc noise margins for a 74LS IC, and compare with the

standard TTL noise margins. 74LS : VNH = VOH (min) - VIH (min) = 2.7 V - 2.0 V = 0.7 V (Standard = 0.4 V)

VNL = VIL (max) - VOL (max) = 0.8 V - 0.5 V = 0.3 V (Standard = 0.4 V)

1980 년대 74LS TTL series가 주류를 이루었으나 현재는 CMOS series 74HC 와74HCT series가 주류를 이루고 있음.

74AS 와 74ALS 사이의성능을 갖고 있음



8-20

Exam. 8-4) Which TTL series can drive the most device inputs of the same series? 각각의 Series 마다 Fan-out이 다르며 같은 series에서는 Tab. 8-6과 같다. 따라서

가장 많은 input을 drive 할 수 있는 series는 74AS series로 40개 이다. 만약 다른series와 혼용해서 사용하는 경우는 각각 series의 IOL, IIL, IOH , IIH 에 따라 다르며Sec.8-5에서 공부함.

8-5 TTL Loading and Fan-Out Fan-Out : Load drive capability of an IC output

LOW state ( Q3 = OFF ) : Fig. 8-13(a)» Q4 = ON : acting as current sink = IOL

IOL : sum of IIL currents from each input» Q4 = ON : collector-emitter resistant is very small

But not zero : produce a voltage drop VOL

VOL must not exceed VOL(max) : 0.4 Volt 이하

HIGH state ( Q4 = OFF ) : Fig. 8-13(b)» Q3 = ON : acting as current source = IOH

IOH : sum of IIH currents from each input» Q3 = ON, Q4 = OFF : VOH = Vcc - IOH• (R2 + emitter-base resistant + D1 resistant)

VOH must not be lower than VOH(min) : 2.4 Volt 이상

Determining the Fan-Out An IC output can drive how many different inputs

* 전류의 방향+ : 전류가 외부에서 흘러 들어옴- : 전류가 외부로 흘러 나감



8-21

•Low IOL ≥ IIL + IIL + ….. •High IOH ≥ IIH + IIH + …..

•0.1 V •≤ 0.4 V •= 5 – 0.7 – 0.7 – VR2

• ≤ 3.6 V•Typ. ≥ 2.4 V

•0.7 V

•0.7 V



8-22

Must Know IOL(max), IOH(max), IIL (max) , IIH (max)» presented in the manufacturer’s IC data sheet

Exam. 8-5) How many 74ALS00 NAND gate inputs can be drive by a 74ALS00 NAND gate output? Refer to the data sheet in Fig. 8-11

» Fan-out(LOW) : Fig. 8-14 IOL(max) / IIL (max) = 8 mA / 0.1 mA = 80

» Fan-out(HIGH) IOH(max) / IIH (max) = 400 A / 20 A = 20

Overall Fan-Out = 20» Lower of the two values ( 80 and 20 )

Exam. 8-6) How many 74AS20 NAND gate inputs can be drive by the output of another 74AS20 NAND gate? Refer to the data sheet in Tab. 8-7

» Fan-out(LOW) IOL(max) / IIL (max) = 20 mA / 0.5 mA = 40

» Fan-out(HIGH) IOH(max) / IIH (max) = 2000 A / 20 A = 100




8-23

Fan-Out in Combination of various logic families Method for determining the loading of any digital output

» Step 1 : Fan-Out (HIGH) Add up the IIH for all inputs connected to an output. This sum must be less than the output’s IOH specification

» Step 2 : Fan-Out (LOW) Add up the IIL for all inputs connected to an output. This sum must be less than the output’s IOL specification

Specifications for input/output current : Tab. 8-7» IOH = IIL = negative : current flows out of the output (sourcing current)» IOL = IIH = positive : current flows into the output (sinking current)

Exam. 8-7) Determine if there is a loading problem (when A 74ALS00 NAND gate outputs is driving three 74S gate inputs and one 7406 gate input). Refer to the data sheet in Tab. 8-7

» Step 1 : Fan-Out (HIGH) Add all IIH = Total IIH = 3 •( IIH for 74S ) + 1 •(IIH for 74 ) = 3 •( 50 A ) + 1•( 40A ) = 190 A This sum 190 A < 400 A ( IOH ) : No Problem

» Step 2 : Fan-Out (LOW) Add all IIL = Total IIL = 3 •( IIL for 74S ) + 1 •(IIL for 74 ) = 3 •( 2 mA ) + 1•( 1.6 mA ) = 7.6 mA This sum 7.6 mA < 8 mA ( IOL ) : No Problem



8-24

Exam. 8-8) The output could drive how many additional 74ALS inputs without being overloaded in Exam. 8-7 ? Refer to the data sheet in Tab. 8-7

» Additional current in LOW = IOL - IIL(sum of load) = 8 mA - 7.6 mA = 0.4 mA IIL = 0.1 mA, 따라서 drive up to four more 74ALS inputs

» Additional current in HIGH = IOH - IIH (sum of load) = 400 A - 190 A = 210 A IIH = 20 A, 따라서 drive up to ten more 74ALS inputs

This output can drive up to four more 74ALS inputs» Lower of the two values ( 10 and 4 )

Exam. 8-9) What is the maximum number of F/F CLR inputs that this gate can drive? The output of a 74AS04 inverter is providing the CLR signal to a parallel register(74AS74 D F/F) Refer to the 74AS74 data sheet (not in Tab. 8-7 )

* PRE and CLR input of 74AS74 : IIL = 1.8 mA, IIH = 40 A* Output of 74AS04 : IOL = 20 mA, IOH = 2 mA (Tab. 8-7 )» Maximum number of inputs(LOW)

IOH / IIH = 2 mA / 40 A = 50» Maximum number of inputs(HIGH)

IOL / IIL = 20 mA / 1.8 mA = 11.11




8-25

8-6 Other TTL Characteristics Several other characteristics of TTL logic must be understood

Intelligently use TTL in a digital system application Unconnected Inputs (Floating)

Unconnected TTL inputs act like a logical “1” Floating : input is left unconnected

» Diode D2 and D3 will not be forward-biased : D2 and D3 는 모두 OFF 따라서 A 와 B 에 모두 “1” 이 입력된 것과 같음

Unused Inputs 3 가지 처리 방법

» 1) Unconnected (Floating) : Fig. 8-15(a) act as a logical “1”

» 2) Connected to +5 V through a 1 k resistor : Fig. 8-15(b) 1 k resistor is for current protection of the emitter-base

junctions in case of spikes on the power supply line.

» 3) Tied to a used input : Fig. 8-15(c) This technique can be used for any type of gate Tied input do not exceed fan-out current : Exam. 8-10

Tied-Together Inputs Two (or more) TTL inputs on the same gate are connected together

Fig. 8-8(a) 참조

NAND, AND gate에만 적용되며 NOR, OR에는 출력이 항상 “1”이 되어 사용 불가능

NAND, AND gate에만 적용되며 NOR, OR에는 출력이 항상 “1”이 되기 때문에GND에 연결해야 함



8-26

Generally act as each individual input for fan-out counting» Only Exception : NAND and AND gates in LOW state

Act as single input regardless of number tied together The reason for this characteristics : Fig. 8-8(b) p. 499

This situation is different for OR and NOR gates : Fig. 8-10 p. 502

If input A and B are tied together and grounded, IIL is not changed (IILis only limited by the R1)

OR and NOR gates do not use multiple-emitter transistor(OR and NOR gates have separate input transistor for each input) R1/R2

Exam. 8-10) Determine the load current at the output X in Fig. 8-16. ( Each gate is a 74LS, IIL = 0.4 mA, IIH = 20 A )

HIGH : gate 2 NAND 는 2 개 Input으로 계산 ( 40 A = 2 X 20 A ) LOW : gate 2 NAND 는 1 개 Input으로 계산 ( 0.4 mA )

Biasing TTL Inputs Low One-shot trigger on a positive transition : Fig. 8-17

» Resistor R serves to keep the T input LOW while switch is open IIL will not exceed VIL(max) : the largest value of R

» IIL X Rmax = VIL(max), 따라서 Rmax = VIL(max) / IIL



8-27

Exam. 8-11) Determine an acceptable value for R( OS gate is a 74LS TTL, IIL = 0.4 mA )

Rmax = VIL(max) / IIL = 0.8 V / 0.4 mA = 2000 Standard resistor value for a good choice = 1.8 k

Current Transients : Fig. 8-18 Whenever a totem-pole TTL output goes from LOW to HIGH, a high amplitude

current spike is drawn from the Vcc supply.» 원 인 :

Q4 가 saturated (ON) 상태에 있기 때문에 Q3 보다 switching time이 늦어서 순간적으로 Q3 와Q4 가 동시에 ON이 되는 순간 (about 2 ns) 이 존재.

이때 load capacitance에 의해 비교적 큰 surge current (30 to 50 mA) 발생. 이와 동시에 Power Supply Line (PCB Pattern Line) 의 distributed inductance가 미분기의

역할을 하여 surge current 에 의해 Voltage spike 가 발생함

This spike can cause serious malfunctions » 해결책 : Power-Supply Decoupling

Connect a 0.01 F or 0.1 F ceramic (low inductance) capacitor between Vcc and Ground near each TTL IC to short out high frequency spikes

Connect single large capacitor ( 2 to 20 F ) between Vcc and Ground on each board to filter out relatively low frequency variations in Vcc

The Capacitor leads are kept very short to minimize series inductance

v=L(di/dt) 에서 dt = 2 ns 임으로 v가 커진다.

•Bypass Capacitor

i=C(dv/dt) 에서 dt = 2 ns 임으로 i가 커진다.



8-28

•Q4 on off

•Vout 0 1

•Q4 ON → OFF time > Q3 OFF→ ON time• * 원인 : Q4 saturated, capacitive load



8-29

8-7 MOS Technology MOS digital ICs = MOSFET

Metal Oxide Semiconductor Field Effect Transistor Advantages

Relatively simple and inexpensive to fabricate» 1/ 3 as complex as the fabrication of bipolar ICs (TTL, ECL, etc.)

Less space on a chip (Small)» Do not use the IC resistor elements that take up so much of chip area» Suited for complex ICs such as microprocessor and memory chips

Consumes very little power MOS ICs are faster than 74, 74LS, and 74ALS TTL

» 74AS TTL family is still as fast as the best MOS(but much greater power dissipation)

Disadvantage Susceptibility to static-electricity damage

» TTL devices are used in education (more durable for laboratory experimentation)

The MOSFET 2 types of MOSFET

» Depletion MOSFET» Enhancement MOSFET : MOS digital ICs use enhancement MOSFETs exclusively

* Comparison-Fig. 8-8: TTL NAND-Fig. 8-21: NMOS Inverter-Fig. 8-23: CMOS NAND

NormalClosedOpen

•TTL 74AS : 1.7 ns•CMOS 74AVC : 1.9~2.0 ns•ECL 0.3 ns

•TTL mW per gate•CMOS nW per gate



8-30

•+ •- •- •+

•VDD

•VDD•GND

•GND

Schematic symbols for enhancement MOSFETs : Fig. 8-19 N-channel/P-channel : Gate, Drain, Source

Basic MOSFET Switch N-channel MOSFET switching state : Fig. 8-20

» OFF state : VGS = 0 Volt (ROFF = 1010 = open circuit)» ON state : VGS = + 5 Volt (RON = 1 k) : acts as load resistor

Threshold voltage (VT) 1.5 V : VGS -1.5V(P), VGS +1.5V(N) N- and P-channel switching characteristics : Tab. 8-8

» Bias Voltage VDD : opposite polarity Drain is connected to VDD (N), Source is connected to VDD (P)

P-channel MOSFET switching state : Fig. 8-21 8-8 Complementary MOS(CMOS) Logic

Three categories : N-MOS, P-MOS, CMOS N-MOS

» Uses only N- channel enhancement MOSFETs P-MOS

» Uses only P- channel enhancement MOSFETs CMOS (Complementary MOS) : Sec. 8-9

» Uses both P- and N- channel devices» - Complexity of the IC fabrication (lower packing density)» + High speed and Low power

FET On Condition



8-31

CMOS Inverter : Fig. 8-22 VIN = + VDD : VOUT = 0 V

» ROFF (Q1 = OFF) = 1010 » RON (Q2 = ON) = 1 k

VIN = 0 V : VOUT = + VDD» RON (Q1 = ON) = 1 k» ROFF (Q2 = OFF) = 1010

CMOS NAND gate : Fig. 8-23 Both A = B = HIGH, X = LOW

» Q1 = Q3 = OFF, Q2 = Q4 = ON

CMOS NOR gate : Fig. 8-24 Both A = B = LOW, X = HIGH

» Q1 = Q3 = ON, Q2 = Q4 = OFF

A B X

LOW LOW HIGH

LOW HIGH HIGH

HIGH LOW HIGH

HIGH HIGH LOW

A B X

LOW LOW HIGH

LOW HIGH LOW

HIGH LOW LOW

HIGH HIGH LOW



8-32

•off

•on•1

•1

•0

•off •off

•on

•on

•0

•0

•1•on

•off

•NAND gate •NOR gate



8-33

CMOS Flip-Flops Two CMOS NOR gates or NAND gates can be cross-coupled Additional gating circuitry (Edge detector/Pulse steering) is used : Fig. 5-25(p. 229)

8-9 CMOS Series Characteristics Compared with TTL

Slower Lower power Better noise margin Greater supply voltage range Higher fan-out More dense

Replacement Rules for Different Families/Series Pin-compatible

» pin configuration must be same (pin 7 = GND, pin 14 = Vcc) Functionally equivalent

» logic function must be same (6 D F/F with positive edge clock) Electrically compatible

» two ICs can be connected directly to each other (without taking any special measures to ensure proper operation)

Fig. 5-6Fig. 5-10



8-34

4000/ 14000 series Oldest series (RCA) Very low power dissipation 3 to 15 V power- supply voltages Very slow Very low output current capability Not pin-compatible with any TTL series Not electrically-compatible with any TTL series

74C series Pin-compatible and functionally equivalent to TTL with same number Performance much like 4000 series

74HC/ HCT (high- speed CMOS) 10 times faster than 74C series Pin-compatible and functionally equivalent to TTL with same number 74HCT devices electrically compatible with TTL 74HC devices not electrically compatible with TTL



8-35

74AC/ ACT (advanced CMOS) Functionally equivalent to TTL Not pin-compatible with TTL 74AC not electrically compatible with TTL 74ACT is electrically compatible with TTL Faster than HC series Device numbering different : 5 digit number (beginning with the digits 11)

» 74AC11004 = 74HC04» 74ACT11293 = 74HCT293

74AHC (advanced high-speed CMOS) Newest series Three times faster than HC series Direct replacement for HC series

BiCMOS logic (Bipolar + CMOS) Low-power of CMOS (75 % reduction over 74F family) + High-speed of Bipolar Pin-compatible with TTL and standard 5 V logic 74ABT : Advanced BiCMOS (second generation of BiCMOS)

» high speed and 3.3 V low voltage



8-36

Power- supply voltage (VDD) 4000/ 14000 and 74C : from 3 to 15 V 74HC/HCT, 74AHC/74AHCT and 74AC/ACT : from 2 to 6 V

Logic Voltage Levels : Tab. 8-9 Voltage Levels of CMOS Logic

» VOL is very close to 0 V » VOH is very close to 5 V

74ACT, 74AHCT and 74HCT» Electrically compatible with TTL

Noise Margins CMOS devices have greater noise margins than TTL

» High-state noise margin : VNH = VOH (min) - VIH (min) = 4.9 – 3.5 = 1.4 v 74HC» Low-state noise margin : VNL = VIL (max) - VOL (max) = 1.0 – 0.1 = 0.9 v 74HC

Power Dissipation Low power dissipation in static state (not changing)

» Typically 2. 5 nW per gate with VDD = 5 V

Refer to next slide

Standard TTL0.4 v



8-37

Low power dissipation because of large resistances : Fig. 8-22» VIN = 0 V

RON (Q1) = 1 k, ROFF (Q2) = 1010 : always OFF MOSFET in the current path between VDD and GND

ID = 0. 5 nA : leakage current from VDD supply ( 5 V / 1010 = 0.5 nA ) PD = 5 V x 0. 5 nA = 2. 5 nW

PD increases with Frequency : Fig. 8-25 Current spike : Each time a output switches from LOW to HIGH (same as Fig. 8-18)

» this is due mainly to the charging current of the load capacitance» a transient charging current (ID) must be supplied by VDD

As switching frequency increases, PD will increase in proportion to the frequency» at higher frequencies, CMOS begins to lose its advantage over other logic families» at frequency near 2 to 3 MHz, CMOS gate will have the same average PD as a 74LS gate

Fan-out - Gate output drives a total CLOAD of N X 5 pF : Fig. 8-26» capacitance load will increase the output switching time (proportion to the # of load N)» typically N = 50 fan-out for low frequency operation ( 1 MHz)» fan-out would have to be less for higher-frequency operation

Switching Speed 4000 series NAND : tpd = 50 ns at VDD = 5 V

» large ROUT and CLOAD (5 pF) serve to increase switch time» ROUT N-MOS 100 K fig.8-20 > CMOS (P-MOS) 1 K fig. 8-22 : CMOS speed up

74HC/ HCT series NAND : tpd = 8 ns

Time-constant 증가



8-38

74AC/ ACT series NAND : tpd = 4.7 ns 74AHC series NAND : tpd = 4.3 ns

Unused inputs Never leave unconnected

» Unconnected CMOS input is susceptible to noise and static chargesBoth P-channel and N-channel MOSFETs in the conductive state

» Resulting in increased power dissipation and possible overheating

Tied either to a fixed voltage level (GND or VDD) or to another input

Static Sensitivity Static charge damage breaks down thin oxide film’s dielectric insulation Precautions to protect from ESD (ElectroStatic Discharge)

1) Connect the chassis of all test instruments, soldering-iron tips, and your work bench to earth ground2) Connect yourself to earth ground with a special wrist strap3) Keep ICs in conductive foam or aluminum foil4) Avoid touching IC pins, and insert the IC into the circuit immediately after removing it from the protective carrier5) Place shorting straps across the edge connectors of PC boards when the boards are being carried or transported6) Do not leave any unused IC inputs unconnected, because open inputs tend to pick up stray static charges



8-39

Latch-Up 원 인 :

» Unavoidable existence of parasitic (unwanted) PNP and NPN transistors embedded in the substrate of MOS ICs

» These parasitic transistors on a CMOS chip are triggered into conduction.» Latch-up can be triggered by high-voltage spikes or ringing at the device inputs and

outputs» Device’s maximum voltage ratings are exceeded (surge from power supply)

증 상 : Turn permanently ON (Latch-Up)» Large current may flow and Destroy the IC

해결책 : » Modern CMOS ICs are designed with protection circuitry (to prevent Latch-up)» Well regulated power supply » Clamping diode can be connected externally to protect against such transients

- industrial environments where high-voltage/high-current load(motor, relay,…)- refer to Fig. 8-12(b) and Fig. 8-40(d) : clamp the overshoot(+)/undershoot(-)

» Unused inputs must be connected to GND or VDD

•due to Line RLCand Delay time



8-40

8-10 Low-Voltage Technology Low-Voltage Technology의 필요성

Increase the Chip Density » Increase the overall chip power dissipation

Raise the chip temperature above the maximum level allowed for reliable operation

해결책 : Chip operated at lower voltage level (1.2 ~ 3.5 V instead of 5 V) CMOS Family

74LVC, 74ALVC, 74LV, 74AVC, 74CBT, 74GTLP, 74TVC BiCMOS Family

74LVT, 74ALVT, 74ALB, 74VME Example of Texas Instrument : Tab. 8-10 Logic Family Life Cycle : Fig. 8-27

8-11 Open-collector/Open-drain Outputs Wired OR / Wired AND : connecting output together

Connect the outputs of two or more logic gates 장점 : 출력단의 AND 또는 OR gate의 수를 줄일 수 있다.

Valuable for battery operated equipment



8-41

Connecting CMOS Outputs Together : Fig. 8-28 Pull-up and Pull-down resistance would be the same ( 1 K ) Voltage on the common wire will be about half the supply voltage ( VOUT = VDD / 2 ) This voltage is in the indeterminate range and unacceptable for driving a CMOS

input Connecting TTL totem pole Outputs Together : Fig. 8-29

Suppose that the Gate A output = HIGH and the Gate B output = LOW» One gate output is trying to go LOW while another gate output is trying to go HIGH

Very low resistance load on Q3A ( 130 ) will draw a far greater current than rated to handle ( IOH = IOL : as high as 50 mA)

Overheating and Device failure

Open-Collector/Open-Drain Outputs Open-Collector TTL : Fig. 8-30(a)

» Eliminate the Q3, D1, R4 : refer to Fig. 8-8» Output : taken at Q4’s collector (Open = Unconnected) » External pull-up register Rp (= 4.7 ~10 K) should be connected : Fig. 8-30(b)

HIGH (= Q4 OFF) : VOH ≈ 5 V LOW (= Q4 ON ) : VOL ≤ 0.4 V

Open-Drain CMOS : Fig. 8-22» Remove the active pull-up transistor(Output : taken at the drain of Pull-down TR)

Conventional CMOS/Totem-pole TTL outputs should not be tied together

* Rated Standard TTL CurrentIOH = 0.4 mA, IOL = 16 mA

Rp = 5 V / 16 mA 3.1 K

Refer to Fig. 8-38



8-42

Wired-AND Connection Wired-AND operation using open collector/drain gates : Fig. 8-31

» Devices with OC/OD Outputs can be connected together safely» Dotted AND gate symbol eliminates the need for an actual AND gate» 단 점 : much slower switching speed

pull-up TR (Q3) to change up load capacitance rapidly(but no pull-up TR in OC/OD circuit) OC/OD circuits should not be used where speed is a principal consideration

Open-Collector Buffer/Drivers Buffer, Driver or Buffer/Driver

» Greater output current and/or voltage capability than an ordinary logic circuit Open-Collector buffer/driver IC : 7406 (Fig. 8-32, 8-33)

» contain 6 INVERTER» sink up to 40 mA in the LOW state ; IOL = 8-20 mA in Totem pole

» handle output voltage up to 30 V Output TR can be connected to a voltage greater than 5 V

예제 1) Drive a high-current, high-voltage load : Fig. 8-32» Q = 1 Output TR = ON 7406 output = LOW

Output TR sinks the 25 mA of lamp current, LAMP = ON» Q = 0 Output TR = OFF 7406 output = Open

Output TR turns off, no path for current, LAMP = OFF



8-43

예제 2) Drive a LED indicator(OC)/Relay(OD) : Fig. 8-33(a),(b)» Q = 1 Output TR = ON 7406 output = LOW

Output TR provide a current path to ground, forward biased, LED/Relay = ON» Q = 0 Output TR = OFF 7406 output = Open

Output TR turns off, no path for current, LED/Relay = OFF

8-12 Tristate Logic Outputs Tristate : A third type of TTL/CMOS output configuration

Three possible output states : HIGH, LOW, High-Impedance» High-impedance (= Hi-Z)

both transistor are turned off in the totem-pole arrangement output terminal is an open or floating (neither a LOW not a HIGH)

Utilize the high-speed operation of the totem-pole arrangement Permit outputs to be connected together

Tristate INVERTER Obtained by modifying the basic totem-pole circuit

» 1) Enabled State ( OE = 1) : Fig. 8-35(a),(b) Output = Inverse of logic input A

» 2) Disabled State ( OE = 0 ) : Fig. 8-35(c) Output = Hi-Z ( both TR OFF )

1) Totem-pole2) Open-collector/Drain3) Tristate

(a) Rs = 330 : LED에 흐르는 전류 (Is) 제한, (b) D = 역기전력에 의한 Reverse Current 방지



8-44

Advantage of Tristate Outputs can be connected together (paralleled) without sacrificing switching

speed.» When Enabled, Totem-pole outputs have a high-speed characteristic

주의 사항 : Only one of output should be enabled at one time (Fig. 8-37)» 2 Output contention Fig. 8-28 and Current damage Fig. 8-29

Tristate Buffers Tristate noninverting buffers : Fig. 8-36

» Control the passage of a logic signal from input to output» Two commonly used tristate buffer ICs : 74LS125, 74LS126

Differ only in the active state of ENABLE input ( E) Contain four noninverting tristate buffers (14 pin)

Tristate buffers used to connect several signals to a common bus : Fig. 8-37» Transmit any one of A, B, and C signals over the bus line to other circuits by enabling

the appropriate buffer» No more than one output should be enabled at one time : Only signal B is enabled

Bus Contention : A signal on bus is a combination of more than one signal (Fig. 8-38)

Tristate ICs : 74LS374 (Octal D-type FF with tristate output) 8-bit register made up of D-type FFs Outputs are connected to tristate buffers

Refer to Fig. 8-28



8-45

Active LOW

•74LS374



8-46

8-13 High-speed Bus Interface Logic Bus wire distance 4 inches

Viewed as “a transmission line” Have inductance, capacitance, and resistance ( line impedance )

Transmission Line Theory Travel time down the wire : Delay time Reflected wave : Echoes Ringing : Line RLC and Delay time

5 Bus Termination Techniques Resistance Termination : Fig. 8-40(a)

» Terminated with about 50 ( line impedance )» Not feasible : require too much current to maintain logic level voltages across such a

low resistance Resistance/Capacitance Termination : Fig. 8-40(b)

» Block the DC current when the line is not changing» But just same as resistor when the line is changing( = pulse )

Voltage Divider Termination : Fig. 8-40(c)» With resistances larger than the line impedance : reduce reflections» But with hundreds of bus lines : make heavy load on the power supply

*CapacitorAC: PassingDC: Blocking



8-47

Diode Termination : Fig. 8-40(d)» Simply clips off or clamp the overshoot/undershoot of the ringing

Series Resistance Termination : Fig. 8-40(e)» At the source, slows down the switching speed

None of above methods are ideal IC manufacturers are designing new series of logic circuits that overcome many

of these problems Texas Instruments’ Bus Interface Logic Series

BTL(Backplane Transceiver Logic)» Specially designed to drive the relatively long busses that connect modules of a large

digital system GTL(Gunning Transceiver Logic)

» More suitable for high-speed busses within a single circuit board or between boards in small enclosures like a personal computer case

» Voltage swing : 0.4 v / 1.2 v lower than TTL or CMOS» The bus used in the Pentium : GTL+ GTL Plus (= GTLP) by Fairchild

LVDS(Low-Voltage Differential signaling)» Use two wires for each signal» Responds to the difference between two wires



8-48

Forward Bias V 가 증가하면서 Off 에서On 된 후, 다시 Forward Bias V 가 감소하면서 On에서 Off 되는 시간

8-14 ECL Digital IC Family ECL (Emitter-Coupled Logic)

ECL operates on the principle of current switching» TTL operates on the principle of voltage switching in the saturated mode

Voltage switching speed is limited by the storage delay time

ECL increases overall switching speed by preventing transistor saturation ECL is referred to as current-mode logic (CML)

Basic ECL Circuit : Fig. 8-41 Supply voltage : VEE and VBB

» produce an fixed current IE (remains around 3 mA in normal operation) Two logic levels

» - 1.7 V : logic 0 for ECL» - 0.8 V : logic 1 for ECL

IE flows through either Q2 or Q1 depending on VIN» VIN = 0 ( -1.7 V ) : Q2 = ON, Q1 = OFF ( IE 가 Q1으로 흐르지 않고 Q2로 흐름 )

Vc1 = 0 V Vc2 = - 0.9 V : R2의 전압 강하 = 300 x 3 mA (IE) = -0.9 V

» VIN = 1 ( -0.8 V ) : Q2 = OFF, Q1 = ON ( IE 가 Q2로 흐르지 않고 Q1으로 흐름 ) Vc1 = - 0.9 V : R1의 전압 강하 = 300 x 3 mA (IE) = -0.9 V Vc2 = 0 V



8-49

•-1.7 v Logic 0 •off •on•-0.8 v Logic 1 •on •off

•VE (Q1) = -5.2 – IE * R3 = -5.2 – (- 3) = - 2.2 V•• 0 : - 1.7 V•VB(Q1) = VIN = • 1 : - 0.8 V• 0 : -2.2 – (- 1.7) = - 0.5 V OFF•VBE(Q1) = • 1 : -2.2 – (- 0.8) = - 1.4 V ON

• * 전위차 : - 1.4 V > - 0.5 V

•3 mA * 1 K

•-1.7 v Logic 0 •off •on

•VC1 = 0 V•VC2 = 300 Ω X 3 mA = 0.9 V

• * ECL Inverter Circuit : Fig. 8-41(b)• Emitter follower addition : Q3 / Q4

•VOUT1 = 0 + (– 0.8 ) = -0.8 V•VOUT2 = -0.9 + (– 0.8 ) = - 1.7 V•0 V

•-0.9 V

•-0.8 V

•-0.8 V

•-1.7 V Logic 0

•-0.8 V Logic 1

•Fig. 8-41 (a) Basic ECL Circuit (b) with addition of emitter followers



8-50

Vc1 and Vc2 are the complements of each other Output voltage levels are not the same as input voltage level

» 해결책 : Fig. 8-41(b) addition of emitter follower Emitter follower subtracts 0.8 V from Vc1 and Vc2 :

Vc1 - 0.8 V : 0 V+( - 0.8 V) = - 0.8 V (logic 1), (- 0.9 V)+ (- 0.8 V) =-1.7 V (logic 0) Emitter follower provides a very low output impedance ( 7 ) for large fan-out and fast charging

of load capacitance Emitter follower produces two complementary output :

VOUT1 = VIN, VOUT2 = VIN

ECL OR/NOR Gate : Fig. 8-42 Basic circuit (Fig. 8-41) can be expanded to more than one input by paralleling

transistor (Q1 and Q3) ECL characteristics

Transistors never saturate» Very high switching speed ( ~ 1 ns )

Logic levels» -0.8 V for logical 1» -1.7 V for logical 0

Low noise margins ( ~ 250 mV)» Unreliable for use in heavy industrial environment

Input = -1.7 VOutput (Vc2) = -0.9 V

VC1 + VBE



8-51

Generates normal output and its complement output» Eliminate the need for INVERTER

Fan- out around 25 25 mW power dissipation

» Higher than with other logic families No noise spikes

» Current switching

ECL comparison with other logic families : Tab. 8-11 High speed (short propagation delay) : high clock rate High power dissipation Low noise margin

Disadvantage of ECL Not a wide range of general-purpose logic devices

» only special purpose ICs : high-speed data transmission, high-speed memory, high-speed arithmetic units

Relatively low noise margins and high power dissipation 2 Negative power supply voltage ( VEE and VBB ) Difficult to use ECL devices with TTL or CMOS ICs

» Logic levels are not compatible with other logic families



8-52

8-15 CMOS Transmission Gate(Bilateral Switch) CMOS Bilateral Switch : Fig. 8-43

Pass signals in both directions » CONTROL = HIGH : Both MOSFET = ON (Switch = closed)» CONTROL = LOW : Both MOSFET = OFF (Switch = open)

Input can be either digital or analog signals 4016/74HC4016 Quad bilateral switch : Fig. 8-44

» Independently controlled : CONTA, CONTB, CONTC, CONTD

» Bi-directional : IN/OUTA, OUT/INA

Exam. 8-12) Describe the operation of the circuit of Fig. 8-45 OUTPUT SELECT = HIGH : upper s/w = open, lower s/w = closed (Y = VIN) OUTPUT SELECT = LOW : upper s/w = closed, lower s/w = open (X = VIN) 4316/74HC4316 : second power supply ( -VEE), VOUT = from - VEE to + VDD

» - VEE = 0 V → VOUT = 0 ~ + VDD

» - VEE = - X V → VOUT = - VEE ~ + VDD = - X ~ + VDD



8-53

8-16 IC Interfacing Interface

Connecting the output(s) of one circuit or system to the input(s) of another circuit or system

Interfacing Logic ICs : Fig. 8-46» (a) no interface is needed (direct connect) : H is high enough, and L is low enough» (b) interface circuit is required : H is not high enough, or L is not low enough

Input / Output currents with a supply voltage of 5 V : Tab. 8-12 Different families have different characteristics

» Checking the device data sheets for values of input and output current/voltageparameters

Interfacing 5 V TTL and CMOS : Fig. 8-47 no problem in low output 1) CMOS input current requirement : No problem

» TTL output current (74LS : IOH = 0.4 mA) > CMOS input current (4000B : IIH = 1 A) 2) CMOS input voltage requirement : Problem

» TTL output voltage (74LS : VOH = 2.4 V) < CMOS input voltage (4000B : VIH = 3.5 V) » Pull-up register : Fig. 8-47

TTL output to rise to approximately 5 V

Refer to Tab. 8-12

Refer to Tab. 8-9

* Low statecurrent / voltage : No problem

* High state current : No problem – 1)voltage : Problem – 2)



8-54

•Voltage requirements• Driver Load•VOH (min) > VIH (min) + VNH

• VOL (max) + VNL < VIL (max)

•Current requirements• Driver Load• IOH (max) > IIH Total sum• IOL (max) > IIL Total sum

•VOL



8-55

CMOS Driving TTL CMOS Driving TTL in the HIGH State : Fig. 8-48(a)

» CMOS output voltage(4000B : VOH = 4.95 V) > TTL input voltage (74LS : VIH = 2.0 V)

» CMOS output current(4000B : IOH = 0.4 mA) > TTL input current (74LS : IIH = 20 A)

CMOS Driving TTL in the LOW State : Fig. 8-48(b)» CMOS output voltage(4000B : VOL = 0.05 V) < TTL input voltage (74LS : VIL = 0.8 V)

» CMOS output current(4000B : IOL = 0.4 mA) = TTL input current (74LS : IIL = 0.4 mA)

* A CMOS driver cannot supply enough current to the TTL load.» 따라서 1 개 이상의 74LS를 구동하려면 74LS125 Buffer IC 사용 : Fig. 8-49(a)

4000B (IOL = 0.4 mA) can not drive even one input of 74 (IIL = 1.6 mA), and 74AS (IIL = 0.5 mA)

» 또는 the load is divided up among multiple 4001 parts: Fig. 8-49(b)

Refer to Tab. 8-12Refer to Tab. 8-9

No problem in the HIGH state

No problem in the HIGH state

min

No problem in the LOW state max

No problem in driving a single TTL load

4001B CMOS (IOL = 0.4 mA) can drive four 74ALS TTL (IIL = 100 uA)



8-56

Exam. 8-13) A 74HC output is driving 3 7406 inputs. Is this a good design ?. IOL = 4 mA (74HC) , IIL = 1.6 mA (7406) 1.6 mA x 3 = 4.8 mA, too much load current

Exam. 8-14) A 4001B is driving 3 74LS inputs. Is this a well-designed circuit? IOL = 0.4 mA (4001B) , IIL = 0.4 mA (74LS) : fan-out = 1 개 0.4 mA x 3= 1.2 mA, too much load current

8-17 Mixed-Voltage Interfacing Low-voltage outputs driving high-voltage loads

Using open drain with pullup : 74LVC07 Fig. 8-50(a) Using a voltage-level translator : 74AVC1T45 Fig. 8-50(b)

High-voltage outputs driving low-voltage loads Using 5 V tolerant inputs as buffer : 74LVC07A Fig. 8-51

8-18 Analog Voltage Comparators Analog Voltage Comparator : LM339 OP. Amp.

Output = HIGH : + voltage input > - voltage input Output = LOW : - voltage input > + voltage input

HIGH state voltage / current : No problemLow state voltage : No problemLow state current : Problem



8-57

Exam. 8-15) Design a circuit to interface the temperature sensor to the digital circuit.- The digital system alarm must sound when the temperature exceeds 100 °F- The output voltage of LM34 temperature sensor goes up 10 mV per degree F Voltage output of the LM34 at 100 °F = 100 °F X 10 mV/ °F = 1 V Choose a bias current = 500 A, 따라서 R = 5 V / 500 A = 10 K Voltage divider 1 V : 4 V = 2 K : 8 K , Fig. 8-52

8-19 Troubleshooting Logic Pulser : Fig. 8-53

Logic pulser generates a short-duration pulse by pressing a pushbutton Logic pulser senses the existing voltage level at the node and produces a voltage

pulse in the opposite direction» if node = LOW : produce a narrow positive-going pulse» if node = HIGH : produce a narrow negative-going pulse

Logic pulser has a very low output impedance (2 or less), so that it can overcome the NAND gate’s output and can change the voltage at the node.

Logic pulser can not produce a voltage pulse at a node that is shorted directly to ground or Vcc.

Using Logic Pulser and Probe to Test a Circuit : Fig. 8-54 Logic pulser manually injects a pulse into a circuit Logic probe monitors the circuit’s response Logic pulser is applied to the circuit node without disconnecting the output of

NAND gate

Vref = - voltage input

almost shorted circuitto Vcc or GND



8-58

Finding Shorted Nodes Press the logic pulser button (when you touch a logic pulser and a logic probe

to the same node)» if the probe = constant LOW and Pulse LED not flash : Fig. 8-54(a)

the node is shorted to ground

» if the probe = constant HIGH and Pulse LED not flash : Fig. 8-54(b) the node is shorted to Vcc



8-59

8-20 Characteristics of an FPGA Consider the electrical and timing characteristics for the Altera Cyclone™ II

family of devices. A subcategory of PLD devices referred to as field programmable gate arrays

(FPGAs). Power-Supply Voltage

Two different power-supply voltages must be applied to a Cyclone II chip. VCCINT provides power for the internal logic of the chip. The nominal value is 1.2

V A separate supply voltage, VCCIO , will power the input and output buffers of the

Cyclone chips. This value will be dependent on the desired output logic level(3.3/2.5/1.8/1.5 V)

Logic Voltage Levels Cyclone devices support a variety of input/output standards that gives flexibility

in system design Altera Cyclone II characteristics using general-purpose I/O standards: Tab. 8-13



8-60

Power Dissipation The Cyclone II devices use CMOS, so power consumption will be low—power will

be dependent on voltage level, frequencies & I/O signal loads. The Quartus II software has two tools to estimate the amount the power usage for

an application.» The PowerPlay Early Power Estimator is typically used during the early stages of

design.» The PowerPlay Power Analyzer is often used with sample test vectors, for more

accurate estimate.

Maximum Input Voltage and Output Current Ratings The Max. DC Input Voltage : 4.6 V Each output pin can sink up to 40mA / source up to 25 mA

Switching Speed The speed of an application will be dependent upon the application and how it is

implemented in the programmable device : Tab. 8-14 Cyclone II chips are available in three different speed grades ( –6 , –7, and –8 )

chap. 8 integrated-circuit logic familiesmicrocom.koreatech.ac.kr/course...

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