CHAPTER 1 Basic VLSI Design

+ DRAIN Vdd - n Type Silicon SOURCE Figure 1.1: The beginning of the n-channel JFET

Figure 1.3 : p-channel JFET

Figure 1.2

Fig.1.4 Schematic Symbols .

Figure 1.5 Physical structure of MOS transistors and their schematic icons

p+ p+

n substrate

channel

Source Drain

p transistor

G

S

D

SB

Polysilicon Gate SiO2

Insulator L W

G

substrate connected to V DD

Source

n transistor substrate connected

Polysilicon Gate SiO2 Insulator

n+ n+

p substrate channel

Drain G

S

D

SB

L W

G

S

D

to GND

Figure 1.6(a): NMOS-transistor

Figure 1.6(b): P-transistor .

Figure 1.6 (c ): C-switch .

N

D

S

G

D

S

G

P

D

S

G

D

S

G

C D S

-G

G

.

Figure 1.7: Transistor schematic of a static complementary inverter.

vdd

a b

vdd

a o/p

a o/p

b b

vss

a b

vss Fig. 19. NAND gate schematic

Fig 1.8 NOR gate schematic

VDD

Out

Gnd

In

Inverter

Figure 1.10: A dynamic latch circuit.

.

Figure 1.11(a): Wires and wire segments.

Figure 1.11(b): Schematic symbols for transistors

D

F 1

F

Cg

Q1

Wire segments

n-type p-type

Figure 1.12: General CMOS Layout structure, Circuit and the Layout diagram of CMOS Inverter.

VDD

Out

Gnd

VDD

Out

Gnd

Pullup Network

(p-transistors)

Pulldown Network

(n-transistors)

InInputs

Inverter

Figure 1.13: Stick diagram

Table 1.1 Rules for possible interactions between layers.

Figure 1.15: The inverter circuit used for delay analysis

VDD In VSS

Out

Metal p-diff n-diff poly

Figure 1.14: Stick diagram symbols

VDD

CL

Gnd

In

Inverter

t

Input voltage

Figure 1.16: Circuit used for power consumption analysis

Figure 1.17: A pseudo-nMOS NOR gate

Figure 1.18: A circuit model for stuck-open faults.

VDD

t1

t2 b a CL

VDD

CL

Gnd

In

Inverter

t

VDD

CL

Gnd

Id,p IL

Id,n

a b

output

Figure1.19: Testing for combinational faults.

A

B

E

G

C

F

D

i1

i2

i3 i4

i5

i6 i7

i8

W1

W2 O1

O2

Fig. 1.20 Commercially available FPGA architectures

1 PO 2 PO 3 PO

4 PI 5 PI 6 7

8 PI 9PI 10PI 11PI

Fig 1.21 Initial 3-restricted DAG

1 2 3

Symmetrical Array Row-based Interconnect

Interconnect

Logic Block

Logic Block

Interconnect

Interconnect Overlayed on Logic Blocks

Sea-of-Gates Hierarchical PLD

4 5 10 11

8 9

Fig. 1.22 Mapping of the 3-restricted DAG by four 3-LUTs connection between wire segments in x and y axes and also vias.

Fig.1.23 3-D FPGA architecture

CHAPTER 2 VLSI CAD

Figure 2.1: Y-chart

System

Register transfer

Logic

Circuit

BEHAVIOR

Algorithms, flowcharts

Register Transfer

Boolean expression

Transfer function

STRUCTURAL

Processors, Memories

Registers, flipflops, MUX

Gates

Transistors

Cell layout

Modules

Boards

PHYSICAL

CHAPTER 3

Partitioning in High Level Synthesis

Figure: 3.1 Example: Behavioral description of a 4 bit Shift multiplier

.

A_PORT B_PORT Architecture SHIFT_MULT of MULT is begin START begin process variable A,B,M: BIT_VECTOR CLK variable COUNT: INTEGER begin M_OUT DONE wait until (START =1) A:= A_PORT; COUNT :=0; Entity MULT is B:=B_PORT; DONE<=’ 0 ’ Port (A_PORT, M:=B”0000”; B_PORT: in bit _ vector(3 down to 0); while (COUNT <4) loop M_PORT: out bit _vector (7 down to 0); if (A(0)=’1’) then M:=M+B; CLK: in BIT end if; START: in BIT A:=SHR(A,M(0)); DONE: out BIT; M:=SHR(M,’0’); ); COUNT:=COUNT+1 end MULT; end loop; M_OUT <=M & A; DONE <=’1’; End process; End SHIFT_MULT;

Figure: 3.2 CDFG for the shift-multiplier example

0 1

B1

0 1

B4 0 1

B2

0 1

B3

Control-flow graph

Read START ‘1’

=

Read A_PORT Read B_PORT ‘0’

Write A Write B Write COUNT

‘0’

Write DONE

B”0000”

Write A

Read A[0] ‘1’

=

Read COUNT ‘4’

<

Read M Read A

&

Write M_OUT

‘1’

Write DONE

Read M Read B

+

Write M

Read A Read M[0]

Write A

Write COUNT

‘1’

Write M

Read M SHR Read

COUNT

+

‘0’

SHR

Figure : 3.3 Scheduled CDFG for the shift multiplier

START=1

A=A_PORT; COUNT=0; B=B_PORT; DONE <= 0 M=B” 0000” ;

COUNT <4

A(0) = ‘1’

M = M + B;

ENDIF

M_OUT <= M & A; DONE <=’1’;

A=SHR(A,M(0)); COUNT=COUNT + 1; M=SHR(M,’0’);

S0

S1

S2

S3

0

1

1

B10

0 B4

0 B2

B3

1

Figure: 3.4 Initial unit selection for the shift-multiplier design

Mult Count_Reg B_Reg A_Reg

Shift1 Shift2 Compar Adder

A_PORT B_PORT

START

CLK

DONE M_OUT

Concat enator

Figure 3.5 Synthesized design for the shift-multiplier example

A= S0 & START=1 B= S0 & ~(START=1) C= S1 & COUNT < 4 D= S1 & ~(COUNT < 4) E= S2 & A(0)=1 F= S2 & ~ (A(0)=1) G= S3 Control Unit A B C D E F G Mux1 - - - - 1 - 0

Mux2 1 - - - - - 0

Mux3 - - - - 0 - 0

Mux4 - - - - 0 - 1

Load A_Reg 1 - - - - - 1

Load B_Reg 1 - - - - - -

Clear Count_Reg

1 - - - - - -

Load Count_Reg

- - - - - - 1

Clear Multiplier

1 - - - - - -

Load Multiplier

- - - - 1 - 1

Adder - - - - 1 - 1

Shift1 - - - - - - 1

Shift2 - - - - - - 1

DONE 0 - - 1 - - -

Next State S1 S0 S2 S0 S3 S3 S1

Multiplier Count_Reg

B_Reg A_Reg

Mux1

Comp

Adder

A_PORT B_PORT

START

CLK DONE M_OUT

Mux2

Shift2 Shift1

0

Mux3 Mux4

0001

0100

State Reg

A_Reg(0)

Comp LT

Concat

3.2 PARTITIONING

Figure 3.6 Circuit Partitioning: (a) an example (b) graph and its physical representations

FF1

REG

FF2 Chip1

Chip2

a b d e f g

c

nj ni

a b

a

b

G1

G2 v

G

c v

d v

e f

g

a

e25

e24 v

e36 v

v1 v2 v3

v4 v5

V6

ni nj

c

d e f g

(a) (b)

(b)

Cutline

3

V(24135)

5

1

3

5

1

3

4

3

V1 V1 V2 V3 V4 V5

Graphical Representation Closeness measurement Cluster Tree Representation

V5

V2413

V2413 V5

V2413 -- --

V5 3 --

V(24)

V(241)

V(2413)

3

V1 V2 V4 V3 V5

V3

V5

V2

V4

4

6

V1 -- -- -- -- -- V2 5 -- -- -- -- V3 4 1 -- -- -- V4 0 6 0 -- -- V5 0 3 0 0 --

V1 V2 V4 V3 V5

V(24)

V1

V3

V5

4

V24

V1 V24 V3 V5

V1 -- -- -- -- V24 5 -- -- -- V3 4 1 -- -- V5 0 3 0 --

V1 V2 V4 V3 V5

V(24)

V(241)

V3

V5

V241 V241 V3 V5

V241 -- -- -- V3 4 -- -- V5 3 0 --

V1 V2 V4 V3 V5

V(24)

V(241)

V(2413)

(a)

(b)

(c)

3 4 1 2 5

c e f b a d b

Criterion B a b c 3

2 1 5 4

Figure 3.7 : Cluster tree formation a b c f c a e d b

(d)

d e f

First cutline

(a)

d e f

(b)

{ f, c}

{ d }

{ b }

{ a, e}

5

3

2

1

{ a, e}

{ f,c}

{ b }

{ d}

(c)

f c a e d b

Figure 3.8 Clustering based on a) criterion A only, b) criterion B only, c) Criterion A below the first cut-line, then criterion B, d) criterion B below the first cut-line, then criterion A e) criterion A below the second cut-line, then criterion B

{ c, e}

{ a, d }

{ b }

{f }

5

4

1

{ c, e}

{ f }

{a ,d}

{ b }

(d)

Second Cutline

{f, c}

{a,e,d}

{ b}

5

3 2

{a,e,d}

{f, c}

{ b}

(e)

1 2 3 4 5 6 7 8 9 10

40 20 10 10

Figure 3.9 Two-way partition

Figure 3.10 Interconnection reduction by node interchanging: a)before interchanging vi and vj, b) after interchanging vi and vj

Figure 3.11: Kernigham-Lin Search Strategy

vi G1

vj G2

Cutline

vj G1

vj G2

Cutline

Figure 3.12 (a) two cluster partition

Figure 3.12 (b) three cluster partition

G1

O2

(+) o1 (+)

O3 (*)

a b c

G3

e13 e23

O2

(+) o1 (+)

O3 (*)

a b c

G3

e13 e23

o1 (+)

o2 (+)

e13 e23

mult1 G2

add1 G1

e13 e23

mult1 G3

add1 G1

add2 G2

e10,11

v4 e4,9 v9

v2 e2,5

v5 e5,7

v7 v8

v3 e3,6 v6 e6,8

CHAPTER 4 Scheduling in High level Synthesis

Figure 4.1(a) Text description

Figure 4.1 (b) DFG (Data Flow Graph)

While (x<a) do { x1:= x + dx; u1:= u – (3 * x * u * dx) – (3 * y * dx); y1:= y + (u * dx); x:= x1; u:=u1; y:=y1; }

u dx 3 x u dx x dx

* * * +

* * +

y y

* -

-

dx u

<

c

a

v10

v11

v1

e1,5

e7,8

V1 V2 V3 V4 V10 E=1 E=2 V5 V6 V9 V11 E=3 V7 E=4 V8 (a)

V1 V2 L=1 L=2 V5 V3 L=3 V7 V6 V4 V10 L=4 V8 V9 V11 (b)

1 2 3 4 5 6 7 8 9 10 11 S1 S2 S3 S4 (a)

V1 V2 S1 S2 V5 V3 V10 S3 V7 V6 V4 S4 V8 V9 V11 (b)

Figure 4.2: (a) ASAP schedule, (b) ALAP schedule.

Figure 4.3: An ILP scheduling example: (a) ranges for operations, (b) final schedule,

* * *

+

*

*

+

*

-

-

<

* *

* +

* *

+

* -

- <

* *

*

+ * *

+

* -

- <

S1 2.33 1 2

S2 2.33 5 3 S3 1.33 7 6 4 10 S4 0.00 8 9 11 (c) (d)

-------------------------------------------------------- ---------------------------------------

S1 1 2 3 4 10 2.83

S2 5 2.33

S3 7 6 0.83

S4 8 9 11 0.00

(a) (b)

Figure 4.4: Force-directed scheduling example: (a) probability of scheduling operations into control steps, (b) operator cost for multiplications in a, (c) probability of scheduling operations into control steps after operation o3 is scheduled to step s2, (d) operator cost for multiplications in 4.4c. '

* *

*

+

*

*

+

*

-

-

<

* *

*

+

* *

+

*

-

-

<

S1 S2 S3 S4

S1 S2 S3 S4

* * - + < S1 1 2 10 S2 5 3 11 S3 6 4 7 S4 8 9

Figure 4.5: Rescheduling: (a) initial schedule where three operations are movable to five control steps (dashed arrows), (b) after operation 6 is moved and locked.

Plist* = 1<0>, 2<0>,3<1>, 4<2>

<0> <0> <2> <2> Plist+ =10<2> Plist- = NIL <0> <1> <2> <2> Plist< =NIL (b) <0> <1>

Resources* = 2 Resources+ = 1 <0> Resources- = 1 Resources< = 1 (c) Figure 4.6: List scheduling: (a) a DFG with mobility labeling (inside < > ), (b) the list of ready operations for control state s1, (c) the resource constraints, (d) the scheduled .DFG

1 2 3 4 10

5 6 9 11

7

8

(a)

1 2 3 4 10

5 6

9 11

7

8

(b)

* * * +

*

* + < *

-

-

(a)

* *

*

+

*

*

+

< *

-

-

(d)

2 4 10 1 5 3 9 11

7 6 8 (a) (b) 2 1 10 S1 2 1 10 3 5 S2 3 5 11

S3 4 6 7 S4 8 9 (c ) (d) Figure 4.7: Static-list scheduling: (a) a DFG (b) priority list, (c) partial schedule of five nodes, (d) the final schedule.

Node 8 9 11 7 6 4 10 5 3 1 2

ALAP 1 1 1 2 2 2 2 3 3 4 4 ASAP 4 2 2 3 2 1 1 2 1 1 1 Priority 1 2 3 4 5 6 7 8 9 10 11

*

*

-

-

*

*

*

+

+

+

<

*

*

*

*

+

<

*

-

*

+

-

* *

* *

*

S1 S2 (a)

S1 S2 (b)

S1 (c)

S1 S2 S3 (d)

Figure 4.8: Scheduling with arbitrary-delay units

Figure 4.9: CDFG for a behavioral description with a conditional construct.

a:=a+1; if(a>100) then b:=a/c; else b:=d/c; endif c:=c-g;

+

* -

+ *

-

+ *

-

*

*

ALU1 ALU2 ALU3 S1 S2 S3 (a) ALU1 ALU2 ALU3 S1 S2 S3 (b)

v1=v2+v3 v4= v2*v3 v5=v1+v4 v6=v4/v1 v2=v4*v5

v4=v2*v3 v1= v2+v3 v5=v1+v4 v6=v4/v1 v2=v4-v5

1 2 3 4 5 7 8 12 11 10 9 6

b

time

10,11, 12 7, 8, 9 4, 5, 6 1, 2, 3

u

(a)

(b)

1

2

3

4

5

7 10

8 11

6 9 12

m

p

(c)

ALU1 ALU2 ALU3 S1 S2 S3 ( c ) Figure 4.11: Scheduling using simulated annealing : (a) an initial schedule, (b) after swapping two operations, (c) after displacing an operation.

v4=v2*v3 v1= v2+v3 v5=v1+v4 v2=v4-v5 v6=v4/v1

Figure 4.12: Path-based scheduling: (a) an example CDFG, (b) a path in the CDFG with constraint intervals, (c) scheduled CDFG.

4.5.3 DFG Restructuring

2

3

1

9

8

5 4

10

7

6

ipp<=pc ipo<=oldpc outbus,=inbus + 8 if( jump = ‘1’) then pc<= jumppc endif wait until (cond=’T’) oldpc<= pc pc< = pc + 8

2

3

1

9

8

5 4

10

7

6

2

3

1

9

8

5 4

10

7

6

write

jump

loop

write

i1

i2

Figure 4.13: DFG restructuring : (a) DFG (b) DFG after tree-height reduction

+

+

+

+

+

a b c d e f

1

2

3

4

5

(((a + b) + c) + d) + (e + f) (a)

+

+

+

+

+

a b c d e f

1

2 3

4

5

((a + b) + c) + (d + (e + f)) (b)

Figure 4.13: DFG restructuring: (c) DFG (d) DFG after redundant operation insertion.

+

+

+

+

a b d c

1

2

3

4

5

d (a + b + c) + (a+b) + (a+b) (c)

*

+

+ +

+

a b d c

1

2

3

45

d (a + b + c) + 2(a+b) (d)

*

+ 6

CHAPTER 5 Data Path Allocation in High Level Synthesis

a b c d o1 o2 r1 r2 r3 r4 S1 e f S2 o3 o4 g h Add1 Add2 Figure 5.1: Mapping of behavioral objects into RT components.

+ +

+ +

a b ,e, g c ,f, h d

+1 +3 +2 +4

+

+

+

+

O1

O2

O3

O4

a b c d

e f

g h

S1

S2

r1 r2 r3 r4

+1 +4 +2 +3

a b, e, g c, f, h d

ADD1 ADD2

r1 r2 r3 r4

+1 +3 +2 +4

a ,g b, e c, f d,h

ADD1 ADD2

r1 r2 r3 r4

+1 +4 +2 +3

a ,g b, e c, f d,h

ADD1 ADD2

(a) (b)

(c)

(d)

S1 S2 Edge Common Neighbor e1

1,3 1 e1

1,4 1 e1

2,3 0 S3 S4 S5 e1

2,5 0 e1

3,4 1 e1

4,5 0 (b)

S13 S2 Edge Common Neighbor e1

13,4 0 e1

2,5 0 e1

4,5 0 S4 S5 (c)

S134 S2 Edge Common Neighbor e1

2,5 0 S5 (d)

v2

v5

S134 S25 Cliques: S134 = { V1, V3, V4 } S25 = { V2, V5} (e) (f)

v1

v3 v4

Figure 5.2: Interdependence of functional-unit and storage binding

(a)

Figure 5.3: Clique partitioning example

v1 v2

v3 v4 v5

v1 v2

v3 v4 v5

v1

v3 v4

v2

v5

v1

v3 v4

v2

v5

V1 V2

S1 V6 V4

V3 S2 V10 V5

V7 S3

V11 V8 V9 S4

V1 V2 (a)

V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 R W R W R W R W (b)

Cliques: {v1,v8}=r1 {v2,v3,v9}=r2 {v4,v5,v11}=r3 {v6,v7}=r4 {v10}=r5 (d)

*

/ +

* - -

- +

(c)

v3

v8

v10 v1

v9 v2

v7

v5

v6 v4

v11

V1 V10 V4 V6 V2 V3 V5 V7 V8 V9 V11 V11 V1

2 S1

S2

S3 S4

Cluster 1 Cluster 2 Cluster 3 Cluster 4 (a)

Figure 5.4: Register allocation using clique partitioning: (a) a scheduled DFG, (b) lifetime intervals of variables, (c) the graph model for register allocation, (d) a clique-partitioning solution

V1 V10 V4 V6 V2 V3 V5 V7 V8 V9 V11 V1’ V2’ r1 r2 r3 r4 r5

S1 V1 V10 V4 V6 V2 V3 S2 V5 V7 S3 S4 V8 V9 V11 V1 V2 Figure 5.5: Register allocation using the left-edge algorithm: (a) sorted variable lifetime intervals, (b) five-register allocation result.

r1 v3

r1 = { v1 , v8 , v11}

r2 r2 = { v9 , v10 } r3 = { v4 , v5 , v11} v5 r4 = { v6 , v7 }

r3 r5 = { v2 , v3 , v12}

r4 v7

r5

Set R Set V (b) (c)

Figure 5.6: Weighted bipartite-matching for register allocation: (a) sorted lifetime intervals with clusters, (b)

bipartite graph for binding of variables in Cluster2 after Cluster1 has been assigned to the registers, (c)

final binding of all variables to the set of registers.

v1

v10

v4

v6

v2

CHAPTER 6 LOGIC SYNTHESIS

(a) (b)

( c) Figure 6.1 Cubic representation of a boolean function of (a) one variable (b) two variables and ( c) three

variables.

10

00

11

01

0 1

001 m1

011 m3

010 m2

110 m6

100 m4

101 m5

000 m0

111 m7

FIGURE 6.2 A cubic representation of the function F(A, B, C) = ? m(0, 2, 3, 4, 7).

FIGURE 6.3 A cubic representation of the function G(A, B, C) = A1C1 + B1C1 + ABC.

m3

m2

m4

m0

m7

A

C

B

m2

m4

m0

m7

A

C

B

x00

0x0

A m6 X1X m7 m2 B m3 C Figure 6.4: A cubic representation of the function H(A, B, C) = B.

F(xi) xi F= xi F(xi) + x1

i F(x1i)

F(x1i)

x1

i (a) F1(xi) x1

i F= [x1i + F1(xi)][ xi +F1(x1

i)] F1(x1

i)

xi (b)

Figure 6.5 An expanded function F, represented (a) in NAND-NAND logic, and (b) in NOR-NOR

logic.

Figure 6.6: A binary tree representation of the function F = A(BD + B1C1) + A1( BC1 + B1CD).

(a) (b)

(c) Figure 6.7 Binary decision diagram of the functions (a) AB (b) A+B and (c) A(+) B.

A

B B

C C C D

D

F

0

0 0

1

1

1

1

A

B

Y=AB

0

0

1

1

Y=0

Y=0 Y=1

A

B

Y=A+B

0

0

1

Y=0

Y=1

Y=1 Y=

1

A

B

Y

0

0

1

Y=0 Y=1

B

0

1 0 1

0

1 1 0 0

1 0

0 0

0 0

1 1

1 1

2 3

4,7 5,6

(a) (b) FIGURE 6.9: Realization of the function Y = A (+) B (+) C (a) The binary tree; (b) the tree reduced to the

BDD,

B

C

0

0

1

1

m0 m1 m2 m3 m4 m5 m6 m7

C0

1 1

B

C

0

0

1

1 C

0

A 1 0

1 2 3

7 6 5 4

B

C

0

0

1

1

0 1 1 0 1 0 0 1

C0

1 1

B

C

0

0

1

1 C

0

A 1 0

1 2 3

7 6 5 4

A

B B

C C

0 1

(a)

B

C

0

0

1

1

1 0 1 0 0 0 1 1

C0

1 1

B

C

0

0

1

1 C

0

A 1 0

1 2 3

7 6 5 4

B

C

0

0

1

1

1 0 1 0 1 0 (b)

C0

1 4,5

B

0

1

C

A0

Y

2

5 4

A

Y

0

C

A

Y

0

01

1 0

(c) Figure 6.10 Realization of the function, Y(A, B, C) = ? m(0, 2, 6, 7) (a) The binary tree (b) reducing the tree(c) the BDD.

B

A

D

F

E

C

0 (a) 1

1

1

0

1

1

1

1

0

0

0 0

0

F

BC

A

Y

0 1

0

1 1 0 0

0 1 1

Figure 6.11: BDD illustrating (a) Advantages of a good ordering, (b) Drawbacks of a bad ordering

C

A

D

F

E

C

0 (b) 1

F

E E E

B B B B

D

B

D

0

0

1

1

0 1 0 1 0 1 1 1 (a)

D0

1 1

B

D

0

0

1

1 D

0

A 1 0

1 2 3

7 6 5 4

Y

Y (c) (d) FIGURE 6.12: Realization of the function Y = AB + D. (a) The binary tree; (b) reducing the tree; (c) the

BDD; (d) counting the paths to an output.

B

0 1

0 1 0 1 (b)

D0

1 1

B

0 1

1 D

0

A 1 0

1

1

B

0 1

0-

D

0

A 1

Y

0 1 1

B

1 1

1-

D

0

A 1

Y

2 2

1 0

0

1

0

1

0 1

1 1

2

1

1

2

2 2

(a) (b)

FIGURE 6.13: The BDD for the function Y = AB + D, with D the most significant bit. (a) The binary tree; (b) BDD.

(a) (b)

FIGURE 6.14: Realization of the function Y = AB + CD. (a) The BDD; (b) the number of paths to an

out put.

B

D

0

0

1

1

0 0 0 1 1 1 1 1

D0

1 1

B

D

0

0

1

1 D

0

A 1 0

1 2 3

7 6 5 4

Y

A

B

0

0

1

1 0 0

D 1

1

Y

1

A

B C

D

0 1

A

B C

D

0 1

THEN ELSE

ELSE

FIGURE 6.15: If-then-else diagrams of (a) AB, (b) A + B, and (c) A (+) B. FIGURE 6.16: If-then-else diagrams of (a) AB + A1C and (b) ABD

B

A

0

THEN ELSE

IF

B

A

1

THEN ELSE

IF

B

ATHEN ELSE

IF

B

B

ATHEN ELSE

IF

A

1

IF

D

THEN

B C

IF

0

b

a BTHEN

ELSE

F

THEN ELSE

1 0

1 c

a CTHEN

ELSE

G

THEN ELSE

1 0

0

d

b DTHEN

ELSE

H

THEN ELSE

1 0

1 b

a THEN

ELSE

I

THEN ELSE

0 D

C

F 2 F 1

Inputs Outputs

AND plane

OR plane

Register Register

VDD VDD GND GND VDD GND P0

P1 P2 P3 GND VDD F 2 F 2 F 1 F 1 I0 I1 I2 Y0 Y1 Y2

FIGURE 6.18: The basic floor plan of a PLA structure.

FIGURE 6.19: A stick drawing of an NMOS NOR-NOR PLA realization.

A A1 B B1 C1 C D1 D Y1 Y2 Y3 P1=A1BC Y1=P1+P2

Y2=P1+P3+P4 P2=AB1D1 Y3=P2+P3 Y4=P4+P5 P3=A1C1D1 Y5=P5+P6 Y6=P4+P6 P4=CD1E P5=CEF1

P6=E1FG1

E1 E F1 F G1 G D1 D Y4 Y5 Y6

Inputs Outputs Inputs I1 I2 I3 Y1 Y2 Y3 Y4 I7 I8 I9 I10 P1 P5 P2 P6 P3 P7 P4 P8 I1 I4 I5 I6 Y5 Y6 Y2 Y7 Y3 Y8 I11 I12 I9 I10 AND Plane OR Plane AND Plane

FIGURE 6.20: A column custom-folded PLA. (a) AND-plane column-folding; (b) OR-plane column-

folding.

FIGURE 6.21: A row or product-line folded PLA.

. .

1 2 3 4 5 6 7 8 9 10 P1 AB1

P2 AC

P3 D P4 A1B

P5 B1C A1 A B1 B C1 C D1 D Y1 Y2 (a)

A B1 C D P1 AB1

P2 AC P3

D P5 B1C P4 A1B A1 B C D Y1 Y2

(b)

Figure 6.22: A simple PLA implemented (a) directly, and (b)optimized

A B1

C D E1

2i 3i

(b) FIGURE 6.23 (a): Multilevel NOR diagram of the function Y = A’B’ + C’(D + E’) (b) a typical NMOS NOR gate.

?

d ? ß

V (a)

W X

Y

1i

VDD

GND

Figure 6.25 An FSM with redundant states and its minimized version.

0/0

0/0

1/1

0/0

1/0

1/1

1/1 0/0

1/1

0/0

0/0

0/0

0/0

1/1

CHAPTER 7

PHYSICAL SYNTHESIS

Figure 7.1: Physical design cycle

Circuit Design

Partitioning

Floorplanning & Placement

Routing

Compaction

Extraction & Verification

Fabrication

(a)

(b)

(c )

A

D

E

B 8 C

F G

H I

6 1 7

2

5 4

3

1

2 3

4 7 5 6

F G H I D E A

B C

H

V

H

V V V V

H

F G H I D E A

B C

( d) Figure 7.2: Floorplan with slicing tree and a non— slicing floorplan.

Figure 7.3: Interconnection topologies.

Figure 7.4: Phases of routing.

(a) Global Routing (b) Detailed Routing

A a

D d

b B

c C

Fig 7.3 (a) Steiner tree (b) minimum spanning tree (c) complete graph

Figure 7.5: A net routed by Lee’s algorithm. obstacle T S Figure 7.6: A net routed by Mikami-Tabuchi’s Algorithm obstacle T S Figure 7.7: A net routed by Hightower’s Algorithm

6 5 4 3 4 5 6 7

5 4 3 2 3 4 5 6

4 3 2 1 2 3 4 5

5 4 3 2 3 4 5 6

6 5 4 3 4 5 6 7

7 6 5 4 5 6 7 8

8 7 6 5 6 7 8 9

9 8 7 6 7 8 9 10

1 Switchbox 1

2 2 (c) (d)

1 3 3 4 2 2 1 (a) (b)

Figure 7.8: Channels and Switchboxes 7.4.2.1 Problem Formulation

(a) (b)

Figure 7.9: (a) Grid-based. (b) Gridless

Layer1 Layer2 Track 1 Layer3 Via Unreserved Layer Model

1 4 2 0 2 1 1 0 3 4 0 upper boundary lower boundary Terminal 3 0 1 2 0 3 4 0 0 2 3 Net list: 1 4 2 0 2 1 1 0 3 4 0 3 0 1 2 0 3 4 0 0 2 3

Track2 Track 3 Track1 Track 2 Track 1 Figure 7.10: A comparison between HVH, VHV, and unreserved layer models.

Figure 7.11: A channel and its associated net list.

upper boundary terminals via Tracks Dogleg Lower boundary trunks branches

1 5 2 0 2 1 1 0 3 4 0 3 0 1 2 0 3 4 0 0 2 3 (a) 1 5 2 4 3 (b)

Figure 7.12: Terminology for channel routing problems.

Figure 7.13: A routing problem and its HCG .

1 5 2 0 2 1 1 0 3 4 0 3 0 1 2 0 3 4 0 0 2 3 (a) 1 5 2 4 3 (b)

4 1 2 3 1 2 3 4 (c)

Figure 7.14: A channel routing problem and its VCG.

. The figure 7.15 (a) shows a channel routing problem with a vertical constraint

cycle while figure 7.15 (b) shows how a dogleg can be used to break a vertical constraint cycle. Figure 7.15(c) shows vertical constraint cycle involving four nets. In figure 7.15(d), we show one possible routing for the example in figure 7.15(c).

1 2 1 2 2 1 2 1 (a) (b)

4 1 2 3 1 2 3 4 (d)

Figure 7.15: A cyclic vertical constraint.

1 5 2 4 3 Figure 7.16: A combined constraint graph (CCG) 7.4.2.5 Left-edge Channel Routing Algorithm

7.5 Compaction

Figure 7.17: Constraint graph generation

v3 ? 1 v2 ? 1 5 ? v4 2

v0 ? 4 1 v1 ? 2 ? v5 Fig 7.18: Input DAG

Q P1 P2 P3 P4 P5 x1 x2 x3 x4 x5 “not initialized”

{v0} {v1}

{v2,v5} {v3,v5}

{v5} {v4}

1 2 1 2 1 0 1 1 2 1 0 0 1 2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 1 5 0 0 0 1 5 0 0 3 1 5 6 6 3 1 5 6 6 3 1 5 6 7 3 1 5 6 7 3

Table 7.2:Results of Longest Path algorithm

A

B

C

D

F

E

A

C

F

B D

E

. v3 ?

1 v2 ? -1 1 5 ? v4 2 -3

v0 ? 4 -4 1 v1 ? 2 v5 ?

Fig 7.19: DAG with a few backward edges

Step x1 x2 x3 x4 x5

Initialize Forward 1

Backward 1 Forward 2

Backward 2 Forward 3

Backward 3

-8 -8 -8 -8 -8 1 5 6 7 3 2 5 6 7 3 2 5 6 8 4 2 5 7 8 4 2 5 7 8 4 2 5 7 8 4

Table 7.3:Results of Liao-Wong algorithm

APPENDIX A VHDL BASICS

Figure A.1(a) (b) Figure A.1: Example of structural description.

A Y

F B

?

?

?

F A Y

G B

?

?

?

A Y

H B

?

?

?

A Y

I B

?

?

?

?

?

?

Figure A.2 Structure of count2 .

Graph Theory Basics

A B C D E Fig. B.1 A graph 0 1 0 0 1 1 0 1 1 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 Fig. B.2 Adjacency matrix representation

COUNT2 BIT_0 Q0 CLK FF0 BIT_1 INV Q1 INV_FF0 FF1

T_FLIPFLOP CLK Q

? ?

INVERTER A Y

T_FLIPFLOP CLK Q

?

A B E NULL B A C D NULL C B E NULL D B E NULL E A C D NULL Fig.B.3 Adjacency list representation

V5 V2 V3 V2 V4 V5 V4

V1 V3 V3

(a) (b) Fig B.4: A directed graph (a) and its adjacency list representation(b). When this algorithm is applied on graph shown in Fig B.4, the algorithm takes different steps as shown in table BT.2

Q W Edges processed (V1) (V1 , V2)

(V3 , V4, V5 )

(V4, V5 )

(V5)

V1

V2

V3

V4

V5

(V1 , V2) ,(V1 , V3) (V2, V4) ,(V2 , V5) NULL (V4 , V3)

NULL

V1

V2

V3

V4

V5

Table BT.2: The different steps of the breadth-first search algorithm applied to the graph of figure B.4 V1 2 V6 6 1 3 1 V2 V5 2 1 1

1 V4 V3 5 Fig B.5 : An edge-weighted directed graph.

Iteration T vi .distance, for i = 1 2 3 4 5 6

1 2 3 4 5 6

{ V1} { V1 , V4}

{ V1 , V4, V5} { V1 , V4 ,V5 ,V6}

{ V1 ,V4 ,V5 ,V6 ,V2} { V1 ,V4 ,V5 ,V6 ,V2 ,V3}

6 8 1 3 8 6 6 2 8 6 6 3 4 6 5

Table BT.3: The evolution of the distance attributes in Dijkstra’s algorithm when applied to the graph with vs = v1 and vt=v2 . 2 V2 2 V2 1 5 1 V1 4 V3 2 V5 2 V1 V3 2 V5 2 1 1 3 V4 V4 Fig B.6 An edge-weighted undirected graph(a) and its minimum spanning tree (b).

Iteration U Vi .distance, vi .via_edge, for i =

1 2 3 4 5 0 1 2 3 4

V1 V2

V3 V4

V5

2, (V1 ,V2) 4, (V1, V3) 3, (V1, V4 ) +8 ,? 1, (V2, V3 ) 2, (V2, V4 ) 5, (V2, V5 ) 1, (V3, V4 ) 2, (V3, V5 ) 2, (V3, V5 )

Table BT.4: The evolution of Prim’s algorithm when applied to the graph of figure B.6a.