chapter 10 operational-amplifier circuitsb97032/electronics_ch10.pdfchapter 10 operational-amplifier...

CHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS

Chapter Outline10.1 The Two-Stage CMOS Op Amp10.2 The Folded-Cascode CMOS Op Amp10.3 The 741 Op-Amp Circuit10.4 DC Analysis of the 74110.5 Small-Signal Analysis of the 74110.6 Gain, Frequency Response, and Slew Rate of the 74110.7 Modern Techniques for the Design of BJT Op Amp

NTUEE Electronics – L.H. Lu 10-1

10.1 The Two-Stage CMOS Op Amp

Multi-stage amplifiersPractical transistor amplifiers usually consist of a number of stages connected in cascadeInput stage: High input resistance to avoid signal loss due to high-resistance source Voltage gain Large CMRR for differential amplifiers

Middle stages: Voltage gain Shifting of the dc level for required voltage swing Differential to single-ended conversion if necessary


Differential to single ended conversion if necessaryOutput stage: Low output resistance to avoid loss of gain due to low-resistance load Current supply required by the load Sufficient voltage swing required by the load Small-signal approximation may not apply

Circuit ConfigurationMost widely used op amp in VLSI circuitsBias circuit: IREF and Q8

Input stage: Q1-Q5

Active-loaded MOS differential pair Differential input and single-ended output Provides voltage gain and high input resistance

Output stage: Q6-Q7

Active-loaded common-source amplifier Provides voltage gain Provides voltage gain High output resistance (not suitable for low-impedance loads)

DC arrangement: The bias current of the input differential pair is provided by Q5

The bias current of the second stage is provided by Q7

To avoid systematic (predictable) offset:


5

7

4

6

)/()/(2

)/()/(

LWLW

LWLW

Input common-mode range and output swingThe transistors are supposed to be in saturation for proper circuit operationICMR: Output swing:

Voltage gainLow-frequency small-signal gain:

513 OVOVtpDDICMtptnOVSS VVVVVVVVV

76 OVDDOOVSS VVvVV

)||(||

62

421111

421

211

mm

oomm

oo

mmm

gGrrgRGA

rrRggG

Amplifier prototype: Input resistance: Output resistance: Transconductance:

Common-mode rejection ratio:


)||()||()||(

||

76642121

766222

762

62

oomoomv

oomm

oo

mm

rrgrrgAAArrgRGA

rrRg

6421 )||( moomm grrgG

iR

76 || ooo rrR

SSmoom RgrrgCMRR 3421 2)||(

Frequency responsePoles and zeros

C

mZ

mP

CmP

Lgddbdb

gsdbgddbgd

CGf

CGf

CRGRf

CCCCC

CCCCCC

21

2

22

2211

7762

644221

2121

121

fP2 decreases for a capacitive loadMay result in stability issue

Unity-gain frequency for a dominant pole case

and

Phase margin


C

mPvt C

GfAf 11 2

1

21 mm GG 2

21

CG

CG m

C

m

)/(tan)/(tan90180

)/(tan)/(tan90

)/(tan

)/(tan

12

1

12

1

12

12

ZtPttotal

ZtPttotal

ZtZ

PtP

ffffPM

ffff

ff

ff

Phase margin improvement technique Adding a series resistance in the feedback path The zero is defined by

The zero can be moved toward higher frequencies for better phase marginSlew rateSlew rate is defined as the maximum voltage change rate at outputAssociated with charging/discharging time of C

222

1 imi VG

sCR

V

R

GC

s

mC

2

11

Associated with charging/discharging time of CC

Extreme cases: Limited by bias current of Q5 (typical case): SR = I/CC

Limited by bias current of Q7: SR = I7/CC

Relationship between SR and ft

SR = 2 ftVOV = tVOV

Slew rate is determined by the overdrive voltagefor a given unity-gain frequency

PMOS devices are preferred for the differential pair with a fixed current I at the cost of lower gain


Power-supply rejection ratio (PSRR)PSRR is defined as the ratio of the amplifier differential gain to the gain from the supply voltage

Design trade-offsCMOS two-stage op amp performance is determined by The channel length of the MOSFETs The overdrive voltage of the MOSFETs

sso

idod

ddo

idod

vvvv

AAPSRR

vvvv

AAPSRR

////

The overdrive voltage of the MOSFETsPerformance benefit for a larger channel length: gain, CMRR, PSRRPerformance benefit for a smaller overdrive voltage: gain, CMRR, PSRR, ICMR, output swing and offsetPerformance benefit for a larger overdrive voltage: high-frequency characteristics (gain)

For modern submicron CMOS technologies: Typical VOV between 0.1 to 0.3 V Channel length is at least 1.5 to 2 times minimum length (Lmin)


2

5.121

21

LV

CCgf OVn

gdgs

mT

10.2 The Folded-Cascode CMOS Op Amp

Circuit ConfigurationCascode topology to increase the gain of the input differential pairFolded topology to improve the ICMR and to reduce the required supply voltageIs generally considered a single-stage amplifierAlso called operational transconductance amplifier (OTA)

DC bias: Bias current for Q1-Q2 is I/2 Bias current for Q3-Q8 is I/2 IB

IB can be realized by MOS current mirrors


Input common-mode range and output swingICMR:Output swing:

Voltage gain

High voltage gain due to increased output resistanceNot desirable for applications where low output resistance is needed for the op amp

F

tnOVDDICMtnOVOVSS VVVVVVVV 9111

41075 OVOVDDOtnOVOVSS VVVvVVVV

)}(||)]||({[)(||)]||([||

866102442

8661024464

21

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oomooomooo

mmm

rrgrrrggRGArrgrrrgRRR

ggG

Frequency responseDominant pole at the output nodeExcellent high-frequency response

Slew rateThe slew rate is limited by the bias current I and the load CLSlew rate SR = I/CL = 2 ftVOV1 for IB > ITypically IB is set 10% ~ 20% larger than I


oL

om

id

o

RsCRG

VV

1 L

mt C

Gf21

Increasing the ICMR: rail-to-rail input operationNMOS and PMOS differential pairs in parallelICMR exceeds the power supply voltageDifferential output voltage providedICM in the middle: Both pairs operate simultaneously Av = 2GmRo

ICM near supply voltage: Only one of the pairs is operational Gain drops to half Gain drops to half

Increasing the output voltage range: wide-swing current mirrorModified cascode current mirrorOutput swing increased by Vt

Output resistance remains the sameA proper dc bias voltage VBIAS is needed


The BJT DeviceHigh-frequency hybrid- model: The base-charging or diffusion capacitance Cde:

The base-emitter junction capacitance Cje:

The collector-base junction capacitance C:

T

CFmFde V

IgC

02 jje CC

m

c

CB

VV

CC

0

0

1

The cutoff (unity-gain) frequency:


cV 0

T

CmT

mfe

m

b

cfe

bb

mc

VCCI

CCgf

rCCsrCCsrgh

CCsrsCg

IIh

sCsCrICCrIV

VsCgI

)(21

21

)(1)(1

)(/1

/1)||||(

)(

0

8.3 The 741 Op-Amp Circuit

741 Op-AmpDevice parameters: npn: IS = 10-14 A, = 200, VA = 125 V pnp: IS = 10-14 A, = 50, VA = 50 V


Bias circuit: Reference current generated by Q11, Q12 and R5

Bias for input stage: Widlar current source (Q10, Q11 and R4) and current mirror Q8, Q9

Bias for second stage: current mirror Q12, Q13B (Q13 is a two-output current source) Bias for output stage: current mirror Q12, Q13A /Q18-Q19 provides 2VBE drop between VB14 and VB20

Input stage: (Q1-Q7, R1-R3) Input emitter follower (Q1-Q2): high input resistance Current-mirror load (Q5-Q7, R1-R3):high output resistance and differential to single-ended conversion Level shifting (Q3 and Q4): for required voltage swing and dc level at the input of the second stage

Second stage: (Q16-Q17, Q13B, R8-R9)Second stage: (Q16 Q17, Q13B, R8 R9) Emitter follower Q16 for high input resistance Common-emitter Q17 for voltage gain Miller compensation technique by CC

Output stage: (Q14, Q20) Complementary pair Q14 and Q20

Low output resistance Relatively large load current without dissipating a large amount of power Emitter follower Q23 to increase input resistance of the output stage

Short-circuit protection circuitry Q15, Q21, Q24, Q22, R6, R7, R11


10.4 DC Analysis of the 741

Reference bias currentProvided by Q11, Q12 and R5

IREF = 0.73 mA (for VCC = VEE = 15 V)Input-stage biasWidlar current source Q11, Q10 and R4:

I = 19 A

5

1112 )(R

VVVVI EEBEEBCCREF

41010

ln RIIIV C

C

REFT

IC10 = 19 ACurrent mirror Q8 and Q9:

IC1 = IC2 IC3 = IC4 = 9.5 AQ1-Q4 and Q8-Q9 form a negative feedback loopBias current can be stabilized by the negative feedback


102

/212

CPP

III

Current-source load Q5-Q7 and R1-R3

IC7 = 10.5 AInput bias current and offset currents Input bias current:

IB = 47.5 nA I ff

3

2

3

2677

65

)/ln(22R

IRIIVIR

IRVIII

III

ST

N

BE

NEC

CC

N

BBB

IIII

2

21

Input offset current:

Non-zero input offset due to mismatches in the valueInput common-mode range: Input common-mode voltage over which the input stage remains in the linear active mode The upper end limited by saturation of Q1 and Q2

The lower end limited by saturation of Q3 and Q4


21 BBOS III

Second-stage bias

IC17 IC13B = 550 AVEB17 = 618 mV and IC16 = 16.2 A

Output-stage biasDC for Q23:

S

CTBE

REFBCC

IIVV

III

1717

1317

ln

75.0

9

17817171616 R

VRIIII BEEBEC

IC23 180 A (IB23 3.6 A negligible for IC17)DC for Q18-Q19:

IC18 165 A and IC19 VBE18/R10 + IB18 = 15.8 A DC for Q14 and Q20:

VBB = VBE18 + VBE19 = 588 mV + 530 mV = 1.118 VIC14 = IC20 = 154 A (for IS14 = IS20 = 310-14 A)


REFEC III 25.02323

S

CTBE

BEREFC

IIVV

RVII

1818

101818

ln

/25.0

10.5 Small-Signal Analysis of the 741

The input stageDifferential input resistance:

re = 2.63 k and Rid = 2.1 MTransconductance:

Gm1 = 0.19 mA/VOutput resistance:

eNid

eie

rRrvi

)1(4)4/(

11 21

22

mei

e

i

om g

rvi

viG

Output resistance:

Ro4 = ro4[1 + gm4(re4||r2)] = 10.5 MRo6 = ro6[1 + gm6(R2||r6)] = 18.2 MRo1 = Ro4||Ro6 = 6.7 M

Equivalent circuit for the input stage:


)]||(1[ rRgrR emoo

The second stageInput resistance

Ri2 4 MTransconductance

)]})(1(||[){1( 81717916162 RrRrR eei

179172

1796

179217

817

1717

||||

||||

icm

ie

iib

e

bc

RRrRR

RrviG

RRrRRvv

Rrvi

Gm2 = 6.5 mA/VOutput resistance

Ro2 = 81 kEquivalent circuit for the second stage:


17968172 || ieei RRrRrv

)]}||(1[{|||| 81717171317132 RrgrrRRR moBooBoo

The output stageOutput voltage limits

approximately 1 V below VCC and 1.5 V above –VEE

Input resistance (for RL = 2 k, IC20 = 5 mA and IC14 =0)

Rin3 3.7 MOpen-circuit voltage gain

2023min

14max

EBEBCEsatEEO

BECEsatCCO

VVVVvVVVv

)||()||)(1()1(

132023132023233

20202020

AoiAoiin

LLi

rRrRrRRRrR

Open circuit voltage gain

Transconductance


12

3 LRo

ovo v

vG

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03

3

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1m

eR

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om

bebi

grv

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Output resistance

Rout 34 Equivalent circuit for the output stage

11||1

20

2320

20

132320

23

22323

oe

Aooeout

oeo

RrrRrR

RrR

Output short-circuit protection One of the two output transistors could conduct

a large amount of current if output is short-circuited Short-circuit protection is adopted in the 741 op amp For current source case (IC14 > 20 mA)VBE15 > 540 mAQ15 turns on and takes away the base current of Q14

IC14 is limited as the base current is reduced Similar case for current sink case (IC20 >20 mA)


10.6 Gain, Frequency Response and Slew Rate of the 741

Small-signal gain

Av = 243147 V/V = 107.7 dBFrequency response

outL

Lvoomiom

o

o

i

o

i

i

i

ov RR

RGRGRRGvv

vv

vv

vvA

322211

22

22 ))(||(

Pt

tinP

iot

Cin

fAfRC

f

RRRACC

0

21

2

121

|||)|1(

fP = 4.1 Hzft = 1 MHz

Slew rate

SR = 0.63 V/sRelationship between ft and slew rate

Slew rate of MOS opamp with same ft is 2~3 times higher than the 741Gm-reduction method: total bias current is kept constant with reduced Gm1


CCISR 2

tTVSR 4

chapter 10 operational-amplifier circuitsb97032/electronics_ch10.pdfchapter 10 operational-amplifier...

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