chapter 11 verilog hdl
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Chapter 11 VERILOG HDL - PowerPoint PPT PresentationTRANSCRIPT
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11-1Dr. Chiang’s ASIC Class NotesMixed Operating Signal Group of TKU
Chapter 11 VERILOG HDL
Key terms and concepts: syntax and semantics operators hierarchy procedures and assignments timing controls and delay tasks and functions control statements logic-gate modeling modeling delay altering parameters other Verilog features: PLI
History: Gateway Design Automation developed Verilog as a simulation language Cadence purchased Gateway in 1989 Open Verilog International (OVI) was created to develop the Verilog language as an IEEE standard Verilog LRM, IEEE Std 1364-1995 problems with anormative LRM
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11-2Dr. Chiang’s ASIC Class NotesMixed Operating Signal Group of TKU
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