chapter 2 - 國立臺灣大學access.ee.ntu.edu.tw/course/vlsi_design_92first/ppt/...2003/04/07 ·...
TRANSCRIPT
![Page 1: Chapter 2 - 國立臺灣大學access.ee.ntu.edu.tw/course/VLSI_design_92first/ppt/...2003/04/07 · EE141 5 Manufacturing Patterning of SiO2 Si-substrate Si-substrate Si-substrate](https://reader036.vdocuments.net/reader036/viewer/2022071112/5fe8f49bc6343e6cb8535fb3/html5/thumbnails/1.jpg)
EE1411
Manufacturing
Chapter 2Chapter 2ManufacturingManufacturingProcess Process and and CMOS CircuitCMOS CircuitLayoutLayout
1st rev. : March 7, 20032nd rev. : April 10, 2003
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EE1412
Manufacturing
CMOS ProcessCMOS Process
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EE1413
Manufacturing
A Modern CMOS ProcessA Modern CMOS Process
p-well n-well
p+
p-epi
SiO2
AlCu
poly
n+
SiO2
p+
gate-oxide
Tungsten
TiSi2
DualDual--Well TrenchWell Trench--Isolated CMOS ProcessIsolated CMOS Process
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EE1414
Manufacturing
The Manufacturing ProcessThe Manufacturing Process
For a great tour through the IC manufacturing process and its different steps, check
www.fullman.com/semiconductors/semiconductors.html
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EE1415
Manufacturing
Patterning of SiO2Patterning of SiO2Si-substrate
Si-substrate Si-substrate
(a) Silicon base material
(b) After oxidation and depositionof negative photoresist
(c) Stepper exposure
PhotoresistSiO2
UV-lightPatternedoptical mask
Exposed resist
SiO2
Si-substrate
Si-substrate
Si-substrate
SiO2
SiO2
(d) After development and etching of resist,chemical or plasma etch of SiO2
(e) After etching
(f) Final result after removal of resist
Hardened resist
Hardened resist
Chemical or plasmaetch
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EE1416
Manufacturing
oxidation
opticalmask
processstep
photoresist coatingphotoresistremoval (ashing)
spin, rinse, dryacid etch
photoresist
stepper exposure
development
Typical operations in a single photolithographic cycle (from [Fullman]).
PhotoPhoto--Lithographic ProcessLithographic Process
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EE1417
Manufacturing
Recurring Process StepsRecurring Process StepsDiffusion and Ion Implantation: change dopant concentration of some parts of the material.
Deposition: Silicon Nitride Si3N4 (CVD, chemical vapor deposition, Polysilicon (polycrystalline silicon), Aluminum
Etching: Si2O (acid), Plasma etching (dry etching)
Planarization: Chemical-mechanical planarization (CMP) on top of Si2O before deposition of an extra metal layer.
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EE1418
Manufacturing
CMOS Process at a GlanceCMOS Process at a GlanceDefine active areasEtch and fill trenches
Implant well regions
Deposit and patternpolysilicon layer
Implant source and drainregions and substrate contacts
Create contact and via windowsDeposit and pattern metal layers
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EE1419
Manufacturing
CMOS Process WalkCMOS Process Walk--ThroughThrough
p+
p-epi (a) Base material: p+ substrate with p-epi layer
p+
(c) After plasma etch of insulatingtrenches using the inverse of the active area mask
p+
p-epi SiO2
3SiN
4(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)
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EE14110
Manufacturing
CMOS Process WalkCMOS Process Walk--ThroughThroughSiO2
(d) After trench filling, CMPplanarization, and removal of sacrificial nitride
(e) After n-well and VTp adjust implants
n
(f) After p-well andVTn adjust implants
p
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EE14111
Manufacturing
CMOS Process WalkCMOS Process Walk--ThroughThrough
(g) After polysilicon depositionand etch
poly(silicon)
(h) After n+ source/drain andp+source/drain implants. These
p+n+
steps also dope the polysilicon.
(i) After deposition of SiO2insulator and contact hole etch.
SiO2
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EE14112
Manufacturing
CMOS Process WalkCMOS Process Walk--ThroughThrough
(j) After deposition and patterning of first Al layer.
Al
(k) After deposition of SiO 2insulator, etching of via’s,deposition and patterning ofsecond layer of Al.
AlSiO2
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EE14113
Manufacturing
Advanced MetallizationAdvanced Metallization
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EE14114
Manufacturing
Advanced MetallizationAdvanced Metallization
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EE14115
Manufacturing
Design RulesDesign Rules
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EE14116
Manufacturing
33D PerspectiveD Perspective
Polysilicon Aluminum
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EE14117
Manufacturing
Circuit Under DesignCircuit Under Design
VDD VDD
Vin Vout
M1
M2
M3
M4
Vout2
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EE14118
Manufacturing
Its Layout ViewIts Layout View
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EE14119
Manufacturing
CMOS Process LayersCMOS Process LayersLayer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
RedBlue
MagentaBlack
BlackBlack
Select (p+,n+) Green
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EE14120
Manufacturing
Layers in 0.25 Layers in 0.25 µµm CMOS processm CMOS process
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EE14121
Manufacturing
CMOS Inverter LayoutCMOS Inverter Layout
A A’
np-substrate Field
Oxidep+n+
In
Out
GND VDD
(a) Layout
(b) Cross-Section along A-A’
A A’
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EE14122
Manufacturing
Sticks DiagramSticks Diagram
1
3
In Out
VDD
GND
Stick diagram of inverter
• Dimensionless layout entities• Only topology is important• Final layout generated by “compaction” program
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EE14123
Manufacturing
Design RulesDesign Rules
Interface between designer and process engineerGuidelines for constructing process masksUnit dimension: Minimum line width
scalable design rules: lambda parameterabsolute dimensions (micron rules)
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EE14124
Manufacturing
IntraIntra--Layer Design RulesLayer Design Rules
Metal2 4
3
10
90
Well
Active3
3
Polysilicon2
2
Different PotentialSame Potential
Metal1 3
32
Contactor Via
Select2
or6
2Hole
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EE14125
Manufacturing
Transistor Rules (DRC)Transistor Rules (DRC)
1
2
5
3
Tran
sist
or
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EE14126
Manufacturing
ViasVias and Contactsand Contacts
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
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EE14127
Manufacturing
Select LayerSelect Layer
1
3 3
2
2
2
WellSubstrate
Select3
5
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EE14128
Manufacturing
Layout Editor (Cadence, Magic,..)Layout Editor (Cadence, Magic,..)
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EE14129
Manufacturing
Design Rule Checker (onDesign Rule Checker (on--line check)line check)
poly_not_fet to all_diff minimum spacing = 0.14 um.
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EE14130
Manufacturing
CMOS Layout ofCMOS Layout ofComplexeComplexe Gate:Gate:From Chapter 6 From Chapter 6 Slides and Insert DSlides and Insert D
Designing CombinationalDesigning CombinationalLogic CircuitsLogic Circuits
March 28, 2003
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EE14131
Manufacturing
Example Gate: NANDExample Gate: NAND
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EE14132
Manufacturing
Example Gate: NORExample Gate: NOR
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EE14133
Manufacturing
Complex CMOS GateComplex CMOS Gate
OUT = D + A • (B + C)
DA
B C
D
AB
C
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EE14134
Manufacturing
Constructing a Complex GateConstructing a Complex Gate
C
(a) pull-down network
SN1 SN4
SN2
SN3D
FF
A
DB
C
D
F
A
B
C
(b) Deriving the pull-up networkhierarchically by identifyingsub-nets
D
A
A
B
C
VDD VDD
B
(c) complete gate
OUT = D + A • (B + C)
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EE14135
Manufacturing
Stick DiagramsStick Diagrams
Contains no dimensionsRepresents relative positions of transistors
In
Out
VDD
GND
Inverter
A
Out
VDD
GNDB
NAND2
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EE14136
Manufacturing
Stick DiagramsStick Diagrams
C
A B
X = C • (A + B)
B
AC
i
j
j
VDDX
X
i
GND
AB
C
PUN
PDNABC
Logic Graph
PUN: Pull-up Network, PDN: Pull-down Network
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EE14137
Manufacturing
Two Versions of C Two Versions of C •• (A + B)(A + B)
X
CA B A B C
X
VDD
GND
VDD
GND
Two Strips Line of Diffusions One Strip Line of Diffusions
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EE14138
Manufacturing
Consistent Consistent EulerEuler Path Path (Insert D of textbook)(Insert D of textbook)
j
VDDX
X
i
GND
AB
C
A B C
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EE14139
Manufacturing
OAI22 Logic GraphOAI22 Logic Graph
C
A B
X = (A+B)•(C+D)
B
A
D
VDDX
X
GND
AB
C
PUN
PDN
C
D
D
ABCD
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EE14140
Manufacturing
Example: x = Example: x = abab++cdcd
GND
x
a
b c
d
VDDx
GND
x
a
b c
d
VDDx
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
a c d
x
VDD
GND
(c) stick diagram for ordering {a b c d}b
Euler PathsFor both PUDand PDN
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EE14141
Manufacturing
Cell DesignCell Design
Standard Cells (gate collection)General purpose logicCan be synthesizedSame height, varying width
Datapath CellsFor regular, structured designs (arithmetic)Includes some wiring in the cellFixed height and width
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EE14142
Manufacturing
Standard Cell Layout Methodology Standard Cell Layout Methodology ––1980s1980s
signals
Routingchannel
VDD
GND
VDD
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EE14143
Manufacturing
Standard Cell Layout Methodology Standard Cell Layout Methodology ––1990s1990s
M2
No Routingchannels VDD
GNDM3
VDD
GND
Mirrored Cell
Mirrored Cell
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EE14144
Manufacturing
Standard CellsStandard Cells
Cell boundary
N WellCell height 12 metal tracksMetal track is approx. 3λ + 3λPitch = repetitive distance between objects
Cell height is “12 pitch”
2λ
Rails ~10λ
InOut
VDD
GND