chapter 3 - processor

8/11/2019 Chapter 3 - Processor

1/69

Chng3: Bxl

Khiiukhinvng

dliu


2/69

Nidung

Thnh phncbncabxl

Lnhtruy cp

Cc ton tALU

Ton tbnh

Ktnicc thnh phn

Cc tn hiuiukhinv bnknh MUXesCc chthgiim lnh


3/69

Material that is not in this lecture

Readings from the book

ALU Function field (fig.4.13 in 4.4)Some data path details

The book has excellent descriptions of this topic.

Please read the book before watching thislecture.

The reading assignment is on the website.


4/69

Thcthi cbncaMIPS (fromthe book)

Xem licc tplnhcbntrong MIPSMemory: lw, swArithmetic: add,sub

Logic: and, orBranch: beq

cthm:Multiply, divideA bunch of logic operationsjumpjr and jal


5/69

Cc hotngchnh cabxl?

Nplnh: tm ra lnhv tilnh

Tnh ton trn ALU: tm ra ton tv thcthi

Truy nhpbnh: tm ra achv truy nhp


6/69

Thitknxung nhp

Thitkutin sxl mtlnhtrong mtchu kngh. Chia lnhthnh cc phav thchintrong mtchu kngh.

Nhclivthitkmclogic: Thpcc mclogic tora trngthi ktip

Bnh(cc mchcht, RAM) lutrtrngthi Bnghchuynitrngthi ktip

Quy trnh nplnh

Trngthi ktip: PC+4 (ngoitrcc lnhnhy)

Trngthi: Program Counter (lnhhinti)


7/69

Thitknxung nhp

Thitkxl mtlnhtrong mtchu kngh Cc khixl cbn:Combinational logic tora next state

Memories (latches, RAM) lutrtrngthiClockchuyninext state thnh current state.


8/69

Skhi

HUST-FET, 02/10/2014 8

Trinkhai cc lnh

Lnhtruy cpbnh: lw, sw

Lnhshcv logic: add, sub, and, or, slt

Lnhiukhindng chngtrnh: beq, j

Trinkhai cc pha hotng Dng thanh ghi PC luachlnh

clnhtbnh, v cpnhtgi trPC

Giim lnhv ccc thanh ghi

Thchinlnh

Luktqu

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction

Fetch

PC = PC+4

DecodeExec, Store


9/69

Nplnh

Theo di achlnhhintitn thanh PC.TngPC ln 4 trong michu kTilnhtiachcxc nhbiPC


10/69

Nplnh

HUST-FET, 02/10/2014 10

clnhtiach(lutrong) PC tbnhlnh(eng. InstructionMemory)

Cpnhtgi trPC tiachcalnhktip

Read

AddressInstruction

Instruction

Memory

Add

PC

4

PC ccpnht michu kkhng cntn hiuiukhinghi PC.

ctbnhlnhcthchinbnglogic thp

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction


11/69

Giim lnh

HUST-FET, 02/10/2014 11

Chuyncc bit thuctrngm lnhv trngm chcnngtikhiiukhin

Instruction

Control

Unit

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction


12/69

Giim lnh(lnhR)


13/69

Giim lnh(Lnhtrctip)


14/69

Giim lnh(cc tn hiuiukhin)


15/69

Giim lnh(R-format)


16/69

Giim lnh(load)


17/69

Npton hng

HUST-FET, 02/10/2014 17

c2 gi trton hngngunttpthanh ghi

Chscc thanh ghi nmtrong lnhMrngducho ton hngtrctipI

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read

Data 1

Read

Data 2

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction


18/69

Thchinlnh

HUST-FET, 02/10/2014 18

Thchinphp ton (m ha biopv funct) trn gi trton hngopA v opB Cc php ton calnhR v I Php ton tnh achtrong lnhlw, sw Php ton so snh trong lnhbeq, bne

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

InstructionopB

ALU

overflow

zero

ALU control

opA

result


19/69

Tnh ton trn ALU (cc chthlnhdngR-type)

Cc bcthchin?cdliuttpthanh ghi(specify rsand rt)Thcthi tnh ton ALU

Ghi dliuvtpthanh ghi (specify rd)


20/69

Tnh ton trn ALU

Cc bcthchin?

cdliuttpthanh ghi (xcnhr rsv rt)

Thchintnh ton ALUGhi dliutrlitpthanh ghi (xcnhr rd)


21/69

Ghi ktqu

HUST-FET, 02/10/2014 21

TALU vicc lnhtnh tonTbnhvicc lnhtruy cpbnh

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read

Data 1

Read

Data 2

RegWriteInstruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction


22/69

Truy cpbnh

HUST-FET, 02/10/2014 22

MemWrite

MemRead

Data

Memory

Address

Write Data

Read Data

a ch theo byteD liu t thanh ghi rt InstructionFetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction


23/69

Truy cpbnh

Cc bcthchin?Tnh ton achGiachnbnhdliu(write: data)

c: nhnktqutrvv avo tpthanh ghiQ:iug xyra nucghi vo bnhcng mtthiim1/ khng thxyra2/ dliusbsai lchhockhng hpl3/ khng c vng cv c ura cdliuv uvo ghi dliu

A: 2

HotngcaRAM: kch hotmthngc/ghi dliu. Nuthchinc2 cnglc slm cc bit bxo trn. Ngoi racnphi2 achcho qu trnh ghi c


24/69

Ktnicc thnh phn Btnh ton ALU

tilnhtnh ton gi trtiptheo caPCcttpthanh ghithcthi tnh tonghi litpthanh ghi

Truy nhpbnh(load/store)tilnh

tnh ton gi trtiptheo caPCcttpthanh ghitnh ton achRead/Write dliubWrite dliuvo tpthanh ghi

Nplnh(branch)tilnh

tnh ton gi trtiptheo caPCcttpthanh ghi

Tnh ton achrnhnh: khng sdngALU cho php ton sosnh v tnh ton achcng mtthiim.

thcthi cc nhnh so snhcpnhtligi trcaPC


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KtniRF v ALU


26/69

KtniALU vibnh


27/69

Ktnigi trtcthitnhton ach


28/69

Thm vo bdnknh

Lachntn hiubngBdnknh MUX


29/69

nhtuyntnh hiu(control)

MUX lachnALU input (tpthanh ghi hoccc gi trhngsc dutcthi) MUX lachntpthanh ghi ghi dliu(ktqutnh ton ctiALU hocdliutbnh)


30/69

Cc tn hiuiukhinxc nhhotng: Lnhaddi

nhnghavtn hiuiukhin: ALUSrc(ALU source) v MemtoReg(Memory to Register File)


31/69

Cc tn hiuiukhinxc nhhotng: lnhadd


32/69

Xy dngcc khirnhnh ciukin

Cc bcthchin?Mcnh: PC= PC + 4Trnghpc iukin: PC= PC+ 4+[Sign-extended immediate


33/69

Tn hiuPCSrc

Cc bcthchin?Mcnh: PC= PC + 4Trnghpc iukin: PC= PC+4+[Sign-extended immediate


34/69

ngtn hiunxung nhptrong MIPS


35/69

Cc dliungun(dliulyra u?)


36/69

Cc dliuch(dliuinu?)


37/69

V d: addi


38/69

Lpliqu trnh


39/69

ThchinlnhloiR v ghi ktqu

HUST-FET, 02/10/2014 39

LnhnhdngR (add, sub, slt, and, or)

Thchinphp ton (m ha biopv funct) trn gi trtonhngtrong rsv rt

Ghi ktquvo tpthanh ghi (tivtr rd)

Instruction

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read

Data 1

Read

Data 2

ALU

overflow

zero

ALU controlRegWrite

R-type:

31 25 20 15 5 0

op rs rt rd functshamt

10

Tpthanh ghi khng cghi michu kcntn hiuiukhinghi ring bit.

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction


40/69

cghi bnh

HUST-FET, 02/10/2014 40

achbnhtnh bcEX: cngthanh ghi cs(cttpthanh ghi khi giim lnh) vigi troffset

ghi (sw) gi tr(ccttpthanh ghi khi giim lnh) vo bnhdliu

c(lw) gi trtbnhdliuvo tpthanh ghi

Instruction

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read

Data 1

Read

Data 2

ALU

overflowzero

ALU controlRegWrite

Data

Memory

Address

Write Data

Read Data

Sign

Extend

MemWrite

MemRead

16 32

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction

Lnh r nhnh c i kin


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Lnhrnhnh c iukin

HUST-FET, 02/10/2014 41

So snh ton hngcttpthanh ghi khi giim Tnh achchbngcch cnggi trPC (sau khi cpnht) vi

trngoffset 16 bit cmrngdu.

Instruction

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read

Data 1

ReadData 2

ALU

zero

ALU control

Sign

Extend16 32

Shift

left 2

Add

4Add

PC

Branch

target

address

(to branch

control logic)

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction

Lnh nh khn i kin


42/69

Lnhnhykhng iukin

HUST-FET, 02/10/2014 42

Thay 28 bit thpcaPC bng26 bt thpcalnhcnpv 2 bt 0

Read

AddressInstruction

Instruction

Memory

Add

PC

4

Shift

left 2

Jump

address

26

4

28

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

NextInstruction


43/69

ngdliu: LnhR, I, lw,sw

HUST-FET, 02/10/2014 43

MemtoReg

Read

AddressInstruction

Instruction

Memory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read

Data 1

Read

Data 2

ALU

ovf

zero

ALU controlRegWrite

Data

Memory

Address

Write Data

Read Data

MemWrite

MemReadSign

Extend16 32

ALUSrc

d li L h h h


44/69

ngdliu: Lnhrnhnh

HUST-FET, 02/10/2014 44

Instr[5-0]

Read

AddressInstr[31-0]

Instruction

Memory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read

Data 1

Read

Data 2

ALU

ovf

zero

RegWrite

Sign

Extend16 32

ALUSrc

Shift

left 2

Add

PCSrc

RegDst

ALU

control

1

1

0

0

0

1

ALUOp

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15-11]

Control

UnitInstr[31-26]

Branch

ng d liu: Lnh R I lw sw beq bne


45/69

ngdliu: LnhR,I, lw, sw, beq, bne

HUST-FET, 02/10/2014 45

Read

AddressInstr[31-0]

Instruction

Memory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read

Data 1

Read

Data 2

ALU

ovf

zero

RegWrite

Data

Memory

Address

Write Data

Read Data

MemWrite

MemRead

Sign

Extend16 32

MemtoReg

ALUSrc

Shift

left 2

Add

PCSrc

RegDst

ALU

control

1

1

1

0

00

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15

-11]

Control

UnitInstr[31-26]

Branch

B x l n xung nhp (2) Lnh R


46/69

Bxl nxung nhp(2) LnhR

HUST-FET, 02/10/2014 46

Read

AddressInstr[31-0]

Instruction

Memory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read

Data 1

Read

Data 2

ALU

ovf

zero

RegWrite

Data

Memory

Address

Write Data

Read Data

MemWrite

MemRead

Sign

Extend16 32

MemtoReg

ALUSrc

Shift

left 2

Add

PCSrc

RegDst

ALU

control

1

1

1

0

00

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15

-11]

Control

UnitInstr[31-26]

Branch

BXL n xung nhp (3) Lnh lw sw


47/69

BXL nxung nhp(3) Lnhlw, sw

HUST-FET, 02/10/2014 47

Read

AddressInstr[31-0]

Instruction

Memory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read

Data 1

Read

Data 2

ALU

ovf

zero

RegWrite

Data

Memory

Address

Write Data

Read Data

MemWrite

MemRead

Sign

Extend16 32

MemtoReg

ALUSrc

Shift

left 2

Add

PCSrc

RegDst

ALU

control

1

1

1

0

00

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15

-11]

Control

UnitInstr[31-26]

Branch

BXL n xung nhp (3) Lnh lw sw


48/69

BXL nxung nhp(3) Lnhlw, sw

HUST-FET, 02/10/2014 48

Read

AddressInstr[31-0]

Instruction

Memory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read

Data 1

Read

Data 2

ALU

ovf

zero

RegWrite

Data

Memory

Address

Write Data

Read Data

MemWrite

MemRead

Sign

Extend16 32

MemtoReg

ALUSrc

Shift

left 2

Add

PCSrc

RegDst

ALU

control

1

1

1

0

00

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15

-11]

Control

UnitInstr[31-26]

Branch

BXL n xung nhp (4) Lnh r nhnh


49/69

BXL nxung nhp(4) Lnhrnhnh

HUST-FET, 02/10/2014 49

Read

AddressInstr[31-0]

Instruction

Memory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read

Data 1

Read

Data 2

ALU

ovf

zero

RegWrite

Data

Memory

Address

Write Data

Read Data

MemWrite

MemRead

Sign

Extend16 32

MemtoReg

ALUSrc

Shift

left 2

Add

PCSrc

RegDst

ALU

control

1

1

1

0

00

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15

-11]

Control

UnitInstr[31-26]

Branch

BXL n xung nhp (4) Lnh r nhnh


50/69

BXL nxung nhp(4) Lnhrnhnh

HUST-FET, 02/10/2014 50

Read

AddressInstr[31-0]

Instruction

Memory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read

Data 1

Read

Data 2

ALU

ovf

zero

RegWrite

Data

Memory

Address

Write Data

Read Data

MemWrite

MemRead

Sign

Extend16 32

MemtoReg

ALUSrc

Shift

left 2

Add

PCSrc

RegDst

ALU

control

1

1

1

0

00

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15

-11]

Control

UnitInstr[31-26]

Branch

BXL nxung n pT m n n y


51/69

n u g n p n n y

HUST-FET, 02/10/2014 51

Read

AddressInstr[31-0]

Instruction

Memory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read

Data 1

Read

Data 2

ALU

ovf

zero

RegWrite

Data

Memory

Address

Write Data

Read Data

MemWrite

MemRead

Sign

Extend16 32

MemtoReg

ALUSrc

Shift

left 2

Add

PCSrc

RegDst

ALU

control

1

1

1

0

0

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15-11]

Control

UnitInstr[31-26]

Branch

Shift

left 2

0

1

Jump

32

Instr[25-0]

26PC+4[31-28]

28


52/69

Thitkngbtheo ngh

HUST-FET, 02/10/2014

Mchngbtheo ngh: 1 phnt trngthi l hplv nnhcquy nhbixung ngh

- Phnt trngthi - phnt nh- VD. thanh ghi, bnhlnh, bnhdliu.- Kch hottheo sncc trngthi thay ikhi c xnxung

cnidung caphnt trngthi tnh gi trbnglogic thp ghi ktquvo phnt trngthi

Cc phnttrngthi cghi ttccc chu kngh.

State

element1

State

element2

Combinational

logic

clock

one clock cycle


53/69

nghu?


54/69

Lnh addi thcthi nhth

no?

Khi t hi h bi


55/69

Khi c tn hiungh, binmiclutr


56/69

Lpliqu trnh


57/69

V dlnh: addi


58/69

Cc tuynlogic v cc btr

Tc x l xc nh nh th


59/69

Tcxl xc nhnhthno?


60/69

Tnh chu ky nghTc

ngdi nht

HUST-FET, 02/10/2014

Instr. I Mem Reg Rd ALU Op D Mem Reg Wr Total

R-type 2 1 2 1 6nsload 2 1 2 2 1 8ns

store 2 1 2 2 7ns

beq 2 1 2 5ns

jump 2 2ns

Tnh chu knghtrong trnghpbqua tr bghp, khiiukhin, khimrngdu, khicPC, khidch2, dy dn, thigian thitlpv gi. Cho bittr:

- Truy cpbnhlnhv bnhdliu(2ns)

- Khishclogic v bcng(2 ns)

- Truy cptpthanh ghi (chocghi) (1 ns)


61/69

Hiunngthitknxungnhp

HUST-FET, 02/10/2014

trlogic khiTruy cplnh 2 nscthanh ghi 1 nsHotngALU 2 ns

Truy cpbnhDL 2 nsGhi thanh ghi 1 ns

Tng 8 ns

Tcngh= 125 MHz

Cc loilnh:

R-type 44% 6 nsLoad 24% 8 ns

Store 12% 7 ns

Branch 18% 5 ns

Jump 2% 4 ns

Thigian trung bnh6.38 ns

CPI = 1.

PC

P

C

PC

PC

PC

ALU-type

Load

Store

Branch

Jump

Notused

Notused

Notused

Notused

Notused

Notused

Notused

Notused

Notused

(and jr)

(exceptjr&jal)

Thit k n xung nhp u


62/69

Thitknxung nhpunhcim

HUST-FET, 02/10/2014 62

Sdngchu knghkhng hiuquchu knghcttheo lnhchmnht.

Cc lnhphctpnhlnhnhn duphyng: Tndintch thitkv cnnhn imtskhichcnng(VD. bcng) v chng khngthcchia strong cng 1 chu kngh

nginv dhiu

Clk

lw sw Waste

Cycle 1 Cycle 2


63/69

Thitkaxung nhp

HUST-FET, 02/10/2014 63

Chia lnhthnh cc pha thchin: IF, ID, EX, MEM, WB. Mipha thchintrong1 chu kxung nhp

Thigian thchin(= spha) camilnhciuchnhty thucphctpcalnh

Cc khichcnngcchia sgiacc pha khc nhau calnhdo mtkhichcnngcthkhng cntrong ton bcc pha thchincalnh

Clock

Clock

Instr 2Instr 1 Instr 3 Instr 4

3 cycles 3 cycles 4 cycles5 cycles

Timesaved

Instr 1 Instr 4Instr 3Instr 2

Timeneeded

Timeneeded

Time

allotted

Timeallotted

Hi thit k


64/69

Hiunngthitkaxungnhp

HUST-FET, 02/10/2014

Cc loilnhsdngschu kkhc nhauR-type 44% 4 cycles

Load 24% 5 cycles

Store 12% 4 cycles

Branch 18% 3 cyclesJump 2% 2 cycles

nggp vo schu ktrung bnh cncho mtlnh:

R-typeLoad

Store

Branch

Jump_____________________________

CPI trung bnh

PC

PC

PC

PC

PC

ALU-type

Load

Store

Branch

Jump

Notused

Notused

Notused

Notused

Notused

Notused

Notused

Notused

Notused

(and jr)

(exceptjr&jal)

Hiunngthi tk axung


65/69

Hiu nng thi t k a gnhp

HUST-FET, 02/10/2014 65

Cc loilnhsdngschu kkhc nhauR-type 44% 4 cycles

Load 24% 5 cycles

Store 12% 4 cycles

Branch 18% 3 cycles

Jump 2% 2 cycles

Tnh schu ktrung bnhcncho mtlnh:R-type 0.444 = 1.76

Load 0.245 = 1.20

Store 0.124 = 0.48Branch 0.183 = 0.54

Jump 0.022 = 0.04_____________________________

CPI trung bnh 4.02

PC

P

C

PC

PC

PC

ALU-type

Load

Store

Branch

Jump

Notused

Notused

Notused

Notused

Notused

Notused

Notused

Notused

Notused

(and jr)

(exceptjr&jal)


66/69

Thitknxung nhp

HUST-FET, 02/10/2014 66

/

ALU Datacache

Instr

cache

Next addr

Reg

file

op

jta

fn

inst

imm

rs (rs)

(rt)

Dataaddr

Datain0

1

ALUSrc

ALUFunc DataWrite

DataRead

SE

RegInSrc

rt

rd

RegDst

RegWrite

32/

16

Register input

Dataout

Func

ALUOvfl

Ovfl

31

012

Next PC

Incr PC

(PC)

Br&Jump

ALUout

PC

012

Clock rate = 125 MHz

CPI = 1 (125 MIPS)


67/69

Thitkaxung nhp

HUST-FET, 02/10/2014 67

Clock rate = 500 MHz

CPI4 (125MIPS)

/16

rs

01

012 ALUCache Reg

file

op

jta

fn

(rs)

(rt)

Address

Data

Inst Reg

Data Reg

xReg

yReg

zRegPC

4

ALUSrcX ALUFuncMemWrite

MemRead

RegInSrc

4

rd

RegDst RegWrite

/32

Func

ALUOvfl

Ovfl

31

PCSrc

PCWrite IRWrite

ALU out

01

01

0123

0123

InstData

ALUSrcY

SysCallAddr

/26

4rt

ALUZero

Zero

xMux

yMux

01

JumpAddr

4 MSBs/

30

30

SEimm

2

So snh nh gi thit k n


68/69

So snh nhgi thitknxung nhp

HUST-FET, 02/10/2014

Instruction access 2 ns

Register read 1 ns

ALU operation 2 ns

Data cache access 2 ns

Register write 1 ns

Total 8 nsSingle-cycle clock = 125 MHz

nghtc125 MHz l bnh thng

So snh trthchin1 lnh:

Mtbxl 2.5 GHz vi20 giai onpipeline c trkhong:

0.4 ns/cycle

20 cycles = 8 nsLulngcabxl c pipeline tthnrtnhiu:

Tthnti20 lnvicc bxl pht hnh nlnh

Tthnti100 lnvicc bxl pht hnh alnh


69/69

So snh nhgi thitka

xung nhpR-type 44% 4 cycles

Load 24% 5 cycles

Store 12% 4 cycles

Branch 18% 3 cyclesJump 2% 2 cycles

Contribution to CPI

R-type 0.444 = 1.76

Load 0.245 = 1.20

Store 0.124 = 0.48

Branch 0.183 = 0.54

Jump 0.022 = 0.04_____________________________

Average CPI 4 02

Cycle time = 2 nsClock rate = 500 MHz

So snh trthchin1 lnh:

Mtbxl 2.5 GHz vi20 giai onpipelinec trkhong: 0.4 ns/cycle 20 cycles = 8 ns

Lulngcabxl c pipelinetthnrtnhiu:- Tthnti20 lnvicc bxl pht

hnh nlnh- Tthnti100 lnvicc bxl pht

hnh alnh

chapter 3 - processor

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