chapter 4 combinational logic

Princess Sumaya Univ.Computer Engineering Dept.

Chapter 4:Chapter 4:

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Combinational CircuitsCombinational Circuits

Output is function of input only

i.e. no feedback

When input changes, output may change (after a delay)

•••

•••

n inputs m outputsCombinational

Circuits

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Combinational CircuitsCombinational Circuits

Analysis

● Given a circuit, find out its function

● Function may be expressed as:

♦ Boolean function

♦ Truth table

Design

● Given a desired function, determine its circuit

● Function may be expressed as:

♦ Boolean function

♦ Truth table

CBA

CBA

BA

CA

CB

F1

F2

?

?

?

4 / 65

Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Analysis ProcedureAnalysis Procedure

Boolean Expression Approach

CBA

CBA

BA

CA

CB

F1

F2

ABCA+B+C

AB+AC+BC

(A’+B’)(A’+C’)(B’+C’)

AB'C'+A'BC'+A'B'C

F1=AB'C'+A'BC'+A'B'C+ABCF2=AB+AC+BC

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.

CBA

CBA

BA

CA

CB

F1

F2

Analysis ProcedureAnalysis Procedure

Truth Table Approach A B C F1 F2

0 0 0= 0 = 0= 0

= 0= 0= 0

= 0= 0

= 0= 0

= 0= 0

0

0

0

0

0

0

1

0

00 0

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CBA

CBA

BA

CA

CB

F1

F2


Truth Table Approach= 0 = 0= 1

= 0= 0= 1

= 0= 0

= 0= 1

= 0= 1

0

1

0

0

0

0

1

1

1

A B C F1 F2

0 0 0 0 00 0 1 1 0

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CBA

CBA

BA

CA

CB

F1

F2



= 0= 1= 0

= 0= 1

= 0= 0

= 1= 0

0

1

0

0

0

0

1

1

1

A B C F1 F2

0 0 0 0 00 0 1 1 00 1 0 1 0

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CBA

CBA

BA

CA

CB

F1

F2



= 0= 1= 1

= 0= 1

= 0= 1

= 1= 1

0

1

0

0

1

1

0

0

0

A B C F1 F2

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 1

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CBA

CBA

BA

CA

CB

F1

F2



= 1= 0= 0

= 1= 0

= 1= 0

= 0= 0

0

1

0

0

0

0

1

1

1

A B C F1 F2

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 0

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CBA

CBA

BA

CA

CB

F1

F2



= 1= 0= 1

= 1= 0

= 1= 1

= 0= 1

0

1

0

1

0

1

0

0

0

A B C F1 F2

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 1

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CBA

CBA

BA

CA

CB

F1

F2



= 1= 1= 0

= 1= 1

= 1= 0

= 1= 0

0

1

1

0

0

1

0

0

0

A B C F1 F2

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 1

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CBA

CBA

BA

CA

CB

F1

F2



= 1= 1= 1

= 1= 1

= 1= 1

= 1= 1

1

1

1

1

1

1

0

0

1

A B C F1 F2

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

B

0 1 0 1

A 1 0 1 0C

B

0 0 1 0

A 0 1 1 1C

F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Design ProcedureDesign Procedure

Given a problem statement:

● Determine the number of inputs and outputs

● Derive the truth table

● Simplify the Boolean expression for each output

● Produce the required circuit

Example:

Design a circuit to convert a “BCD” code to “Excess 3” code

4-bits 0-9 values

4-bits Value+3

?

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BCD-to-Excess 3 ConverterA B C D w x y z

0 0 0 0 0 0 1 10 0 0 1 0 1 0 00 0 1 0 0 1 0 10 0 1 1 0 1 1 00 1 0 0 0 1 1 10 1 0 1 1 0 0 00 1 1 0 1 0 0 10 1 1 1 1 0 1 01 0 0 0 1 0 1 11 0 0 1 1 1 0 01 0 1 0 x x x x1 0 1 1 x x x x1 1 0 0 x x x x1 1 0 1 x x x x1 1 1 0 x x x x1 1 1 1 x x x x

C

1 1 1 BA

x x x x1 1 x x

D

C

1 1 11 B

Ax x x x

1 x x

D

C

1 11 1 B

Ax x x x1 x x

D

C

1 11 1 B

Ax x x x1 x x

D

w = A+BC+BD x = B’C+B’D+BC’D’

y = C’D’+CD z = D’

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BCD-to-Excess 3 ConverterA B C D w x y z

0 0 0 0 0 0 1 10 0 0 1 0 1 0 00 0 1 0 0 1 0 10 0 1 1 0 1 1 00 1 0 0 0 1 1 10 1 0 1 1 0 0 00 1 1 0 1 0 0 10 1 1 1 1 0 1 01 0 0 0 1 0 1 11 0 0 1 1 1 0 01 0 1 0 x x x x1 0 1 1 x x x x1 1 0 0 x x x x1 1 0 1 x x x x1 1 1 0 x x x x1 1 1 1 x x x x

w

x

D

C

z

y

B

A

w = A + B(C+D)

x = B’(C+D) + B(C+D)’

y = (C+D)’ + CD

z = D’

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Seven-Segment DecoderSeven-Segment Decoder

a

b

c

g

e

d

f?

w

x

y

z

abcdefg

w x y z a b c d e f g

0 0 0 0 1 1 1 1 1 1 00 0 0 1 0 1 1 0 0 0 00 0 1 0 1 1 0 1 1 0 10 0 1 1 1 1 1 1 0 0 10 1 0 0 0 1 1 0 0 1 10 1 0 1 1 0 1 1 0 1 10 1 1 0 1 0 1 1 1 1 10 1 1 1 1 1 1 0 0 0 01 0 0 0 1 1 1 1 1 1 11 0 0 1 1 1 1 1 0 1 11 0 1 0 x x x x x x x

1 0 1 1 x x x x x x x1 1 0 0 x x x x x x x1 1 0 1 x x x x x x x1 1 1 0 x x x x x x x1 1 1 1 x x x x x x x

y

1 1 11 1 1 x

wx x x x1 1 x x

z

BCD code

a = w + y + xz + x’z’ b = . . .c = . . .d = . . .

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Binary AdderBinary Adder

Half Adder

● Adds 1-bit plus 1-bit

● Produces Sum and Carry

HAx

yS

C

x y C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

x+ y───C S

x

y

S

C

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Full Adder

● Adds 1-bit plus 1-bit plus 1-bit

● Produces Sum and Carry

x y z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

x+ y+ z───C S

FAxyz

S

C

y

0 1 0 1

x 1 0 1 0z

y

0 0 1 0

x 0 1 1 1z

S = xy'z'+x'yz'+x'y'z+xyz = x y z

C = xy + xz + yz

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Full Adder

x

y

z

S

C

xy

xz

yz

xyzxyzxyzxyz

xyzx

y

z

xy

xz

yz

S

C

S = xy'z'+x'yz'+x'y'z+xyz = x y z

C = xy + xz + yz

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Full Adder

x

y

z

S

C

HAxy

z

HAS

C

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c3 c2 c1 .+ x3 x2 x1 x0

+ y3 y2 y1 y0

────────Cy S3 S2 S1 S0

FA

x3 x2 x1 x0

FAFAFA

y3 y2 y1 y0

S3 S2 S1 S0

C4 C3 C2 C1

0

Binary Adder

x3x2x1x0 y3y2y1y0

S3S2S1S0

C0Cy

Carry Propagate Addition

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Carry Propagate Adder

CPA

A3 A2 A1 A0 B3 B2 B1 B0

S3 S2 S1 S0

C0CyCPA

A3 A2 A1 A0 B3 B2 B1 B0

S3 S2 S1 S0

C0Cy

x3 x2 x1 x0y3 y2 y1 y0

x7 x6 x5 x4y7 y6 y5 y4

S3 S2 S1 S0S7 S6 S5 S4

0

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.BCD AdderBCD Adder

4-bits plus 4-bits

Operands and Result: 0 to 9

+ x3 x2 x1 x0

+ y3 y2 y1 y0

────────Cy S3 S2 S1 S0

X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0

0 + 0 0 0 0 0 0 0 0 0 = 0 0 0 0 0 00 + 1 0 0 0 0 0 0 0 1 = 1 0 0 0 0 10 + 2 0 0 0 0 0 0 1 0 = 2 0 0 0 1 0

0 + 9 0 0 0 0 1 0 0 1 = 9 0 1 0 0 11 + 0 0 0 0 1 0 0 0 0 = 1 0 0 0 0 11 + 1 0 0 0 1 0 0 0 1 = 2 0 0 0 1 0

1 + 8 0 0 0 1 1 0 0 0 = 9 0 1 0 0 11 + 9 0 0 0 1 1 0 0 1 = A 0 1 0 1 02 + 0 0 0 1 0 0 0 0 0 = 2 0 0 0 1 0

9 + 9 1 0 0 1 1 0 0 1 = 12 1 0 0 1 0

Invalid Code

Wrong BCD Value0001 1000

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X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0 Required BCD Output Value

9 + 0 1 0 0 1 0 0 0 0 = 9 0 1 0 0 1 0 0 0 0 1 0 0 1 = 99 + 1 1 0 0 1 0 0 0 1 = 10 0 1 0 1 0 0 0 0 1 0 0 0 0 = 169 + 2 1 0 0 1 0 0 1 0 = 11 0 1 0 1 1 0 0 0 1 0 0 0 1 = 179 + 3 1 0 0 1 0 0 1 1 = 12 0 1 1 0 0 0 0 0 1 0 0 1 0 = 189 + 4 1 0 0 1 0 1 0 0 = 13 0 1 1 0 1 0 0 0 1 0 0 1 1 = 199 + 5 1 0 0 1 0 1 0 1 = 14 0 1 1 1 0 0 0 0 1 0 1 0 0 = 209 + 6 1 0 0 1 0 1 1 0 = 15 0 1 1 1 1 0 0 0 1 0 1 0 1 = 219 + 7 1 0 0 1 0 1 1 1 = 16 1 0 0 0 0 0 0 0 1 0 1 1 0 = 229 + 8 1 0 0 1 1 0 0 0 = 17 1 0 0 0 1 0 0 0 1 0 1 1 1 = 239 + 9 1 0 0 1 1 0 0 1 = 18 1 0 0 1 0 0 0 0 1 1 0 0 0 = 24

+ 6

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Correct Binary Adder’s Output (+6)

● If the result is between ‘A’ and ‘F’

● If Cy = 1

S3 S2 S1 S0 Err

0 0 0 0 0

1 0 0 0 01 0 0 1 01 0 1 0 1

1 0 1 1 11 1 0 0 11 1 0 1 11 1 1 0 11 1 1 1 1

S1

S2S3

1 1 1 11 1

S0

Err = S3 S2 + S3 S1

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Binary AdderA3 A2 A1 A0 B3 B2 B1 B0

S3 S2 S1 S0

CiCy

Binary AdderA3 A2 A1 A0 B3 B2 B1 B0

S3 S2 S1 S0

CiCy

0 0

0

0

S3 S2 S1 S0Cy

x3 x2 x1 x0 y3 y2 y1 y0

Err

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Binary SubtractorBinary Subtractor

Use 2’s complement with binary adder

● x – y = x + (-y) = x + y’ + 1

Binary Adder A 3 A 2 A1 A0 B3 B2 B1 B0

S3 S2 S1 S0

CiCy 1

x3 x2 x1 x0 y3 y2 y1 y0

F3 F2 F1 F0

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Binary Adder/SubtractorBinary Adder/Subtractor

Binary Adder A3 A 2 A1 A0 B3 B2 B1 B0

S3 S2 S1 S0

CiCy

Mx3 x2 x1 x0 y3 y2 y1 y0

F3 F2 F1 F0

M: Control Signal (Mode)

● M=0 F = x + y

● M=1 F = x – y

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.OverflowOverflow

Unsigned Binary Numbers

2’s Complement Numbers

FA

x3 x2 x1 x0

FAFAFA

y3 y2 y1 y0

S3 S2 S1 S0

C4 C3 C2 C1

0

Carry

FA

x3 x2 x1 x0

FAFAFA

y3 y2 y1 y0

S3 S2 S1 S0

C4 C3 C2 C1

0

Overflow

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Magnitude ComparatorMagnitude Comparator

Compare 4-bit number to 4-bit number

● 3 Outputs: < , = , >

● Expandable to more number of bits

Magnitude Comparator

A3A2A1A0 B3B2B1B0

A<B A=B A>B

33333 BABAx

22222 BABAx

11111 BABAx

00000 BABAx

0123)( xxxxBA

00123112322333)( BAxxxBAxxBAxBABA

00123112322333)( BAxxxBAxxBAxBABA

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A 3

(A<B)

B 3

A 2

B 2

A 1

B 1

A 0

B 0

(A>B)

(A=B)

x3

x2

x1

x0

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MagnitudeComparator

A3 A2 A1 A0 B3 B2 B1 B0

A<B A=B A>B

I(A>B)

I(A=B)

I(A<B)

x3 x2 x1 x0y3 y2 y1 y0

x7 x6 x5 x4y7 y6 y5 y4

A<B A=B A>B

MagnitudeComparator

A3 A2 A1 A0 B3 B2 B1 B0

A<B A=B A>B

I(A>B)

I(A=B)

I(A<B)

010

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.DecodersDecoders

Extract “Information” from the code

Binary Decoder

● Example: 2-bit Binary Number

BinaryDecoder

x1

x0

Only one lamp will turn on

0

0

1000

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2-to-4 Line Decoder

I1 I0 Y3 Y2 Y1 Y0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

Bin

ary

Dec

oder I1

I0

y3

y2

y1

y0

I1

I0

Y3

Y2

Y1

Y0

013 IIY 012 IIY

011 IIY 010 IIY

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3-to-8 Line Decoder

Bin

ary

Dec

oder

I2

I1

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

I2

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

I1

012 III

012 III

012 III

012 III

012 III

012 III

012 III

012 III

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“Enable” Control

Bin

ary

Dec

oder I1

I0

E

Y3

Y2

Y1

Y0

E I1 I0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

EI0

Y3

Y2

Y1

Y0

I1

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Expansion

I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 1 0 00 1 1 0 0 0 0 1 0 0 01 0 0 0 0 0 1 0 0 0 01 0 1 0 0 1 0 0 0 0 01 1 0 0 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0

I2 I1 I0

Bin

ary

Dec

o der I0

I1

E

Y3

Y2

Y1

Y0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Bin

ary

Dec

oder I0

I1

E

Y3

Y2

Y1

Y0

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Active-High / Active-Low

I1 I0 Y3 Y2 Y1 Y0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

I1 I0 Y3 Y2 Y1 Y0

0 0 1 1 1 0

0 1 1 1 0 1

1 0 1 0 1 1

1 1 0 1 1 1

Bin

ary

Dec

o der I1

I0

Y3

Y2

Y1

Y0

I1

I0

Y3

Y2

Y1

Y0

Bin

ary

Dec

oder I1

I0

Y3

Y2

Y1

Y0

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Implementation Using DecodersImplementation Using Decoders

Each output is a minterm

All minterms are produced

Sum the required minterms

Example: Full Adder

S(x, y, z) = ∑(1, 2, 4, 7)

C(x, y, z) = ∑(3, 5, 6, 7)

I2

I1

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

BinaryDecoder

xyz

S C

40 / 65

Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Implementation Using DecodersImplementation Using Decoders

I2

I1

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

BinaryDecoder

xyz

S C

I2

I1

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

BinaryDecoder

xyz

S C

41 / 65

Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.EncodersEncoders

Put “Information” into code

Binary Encoder

● Example: 4-to-2 Binary Encoder

x3 x2 x1 y1 y0

0 0 0 0 0

0 0 1 0 1

0 1 0 1 0

1 0 0 1 1

BinaryEncoder

y1

y0

x1

x2

x3

Only one switch

should be activated at a time

42 / 65

Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.EncodersEncoders

Octal-to-Binary Encoder (8-to-3)

I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0

0 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 1 0 0 0 10 0 0 0 0 1 0 0 0 1 00 0 0 0 1 0 0 0 0 1 10 0 0 1 0 0 0 0 1 0 00 0 1 0 0 0 0 0 1 0 10 1 0 0 0 0 0 0 1 1 01 0 0 0 0 0 0 0 1 1 1

Bin

ary

En

cod

er Y2

Y1

Y0

I7

I6

I5

I4

I3

I2

I1

I0

13570

23671

45672

IIIIY

IIIIY

IIIIY

I7

I6

I5

I4

I3

I2

I1

I0

Y2

Y1

Y0

43 / 65

Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Priority EncodersPriority Encoders

4-Input Priority Encoder

I3 I2 I1 I0 Y1 Y0 V

0 0 0 0 0 0 0

0 0 0 1 0 0 1

0 0 1 x 0 1 1

0 1 x x 1 0 1

1 x x x 1 1 1

Pri

orit

yE

nc o

der V

Y1

Y0

I3

I2

I1

I0

I0

I1

I2

I3

Y1

Y0

V0123

1230

231

IIIIV

IIIY

IIY

Y1

I1

1 1 1 1 I2I3

1 1 1 11 1 1 1

I0

44 / 65

Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Encoder / Decoder PairsEncoder / Decoder Pairs

Y2

Y1

Y0

I7

I6

I5

I4

I3

I2

I1

I0

I2

I1

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

BinaryEncoder

BinaryDecoder

45 / 65

Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.MultiplexersMultiplexers

MUX Y

I0

I1

I2

I3 S1 S0

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

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2-to-1 MUX

4-to-1 MUX

MUX YI0

I1 S I1

I0

S

Y

MUX Y

I0

I1

I2

I3 S1 S0

I1

I0

S1

YI2

I3

S0

47 / 65


Quad 2-to-1 MUX

MUX YI0

I1 S

MUX YI0

I1 S

MUX YI0

I1 S

MUX YI0

I1 S

x3

x2

x1

x0

y3

y2

y1

y0

S

Y3

Y2

Y1

Y0

S E

A3

A2

A1

A0

B3

B2

B1

B0

MUX

A3

A2

A1

A0

S E

Y3

Y2

Y1

Y0

B3

B2

B1

B0

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Quad 2-to-1 MUX

Y3

Y2

Y1

Y0

S E

A3

A2

A1

A0

B3

B2

B1

B0

MUX

A3

A2

A1

A0

S E

Y3

Y2

Y1

Y0

B3

B2

B1

B0

Extra Buffers

49 / 65

Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Implementation Using MultiplexersImplementation Using Multiplexers

MUX Y

I0

I1

I2

I3 S1 S0

x y F

0 0 1

0 1 1

1 0 0

1 1 1

ExampleF(x, y) = ∑(0, 1, 3)

x y

F

1101

50 / 65


x y z F

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 1

ExampleF(x, y, z) = ∑(1, 2, 6, 7)

MUX Y

I0

I1

I2

I3 I4

I5

I6

I7S2 S1 S0

x y z

01100011

F

51 / 65


MUX Y

I0

I1

I2

I3 S1 S0

x y z F

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 1

ExampleF(x, y, z) = ∑(1, 2, 6, 7)

x y

FF = zz

F = z

z

F = 0

0

F = 1

1

52 / 65


MUX Y

I0

I1

I2

I3 I4

I5

I6

I7S2 S1 S0

Implementation Using MultiplexersImplementation Using Multiplexers

A B C D F0 0 0 0 00 0 0 1 10 0 1 0 00 0 1 1 10 1 0 0 10 1 0 1 00 1 1 0 00 1 1 1 01 0 0 0 01 0 0 1 01 0 1 0 01 0 1 1 11 1 0 0 11 1 0 1 11 1 1 0 11 1 1 1 1

ExampleF(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)

A B C

F

F = DD

F = DD

F = D

D

F = 0

0

F = 0

F = D

F = 1

F = 1

0

D

1

1

53 / 65


Y

I0

I1

I2

I3

I4

I5

I6

I7

S2 S1 S0

Multiplexer ExpansionMultiplexer Expansion

8-to-1 MUX using Dual 4-to-1 MUX

MUX Y

I0

I1

I2

I3 S1 S0

MUX Y

I0

I1

I2

I3 S1 S0

MUX YI0

I1 S

0 01

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.DeMultiplexersDeMultiplexers

DeMUXI

Y3

Y2

Y1

Y0S1 S0

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

I

Y3

Y2

Y1

Y0

S0

S1

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Multiplexer / DeMultiplexer PairsMultiplexer / DeMultiplexer Pairs

Y

I7

I6

I5

I4

I3

I2

I1

I0

I

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

MUX DeMUX

S2 S1 S0 S2 S1 S0

x2 x1 x0 y2 y1 y0

Synchronize

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.DeMultiplexers / DecodersDeMultiplexers / Decoders

Bin

ary

Dec

oder I1

I0

E

Y3

Y2

Y1

Y0

E I1 I0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

DeMUXI

Y3

Y2

Y1

Y0S1 S0

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.Three-State GatesThree-State Gates

Tri-State Buffer

Tri-State InverterA Y

C

C A Y

0 x Hi-Z

1 0 0

1 1 1

A Y

C

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A

YC

B

D

C D Y

0 0 Hi-Z

0 1 B

1 0 A

1 1 ?

Not Allowed

Y=

A

C

B

A if C = 1

B if C = 0

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I0

Y

E

S1

I1

I2

I3

Bin

ary

Dec

o der I1

I0

E

Y3

Y2

Y1

Y0

S0

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Princess Sumaya UniversityPrincess Sumaya University 4241 – Digital Logic Design 4241 – Digital Logic Design Computer Engineering Computer Engineering Dept.Dept.HomeworkHomework

Mano

● Chapter 4

♦ 4-2

♦ 4-3

♦ 4-5

♦ 4-11

♦ 4-13

♦ 4-27

♦ 4-28

♦ 4-31

♦ 4-32

♦ 4-33

♦ 4-35

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Mano4-2 Obtain the simplified Boolean expressions for output F

and G in terms of the input variables in the circuit:

A

BC

D

F

G

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4-3 For the circuit shown in the “Quad 2-to-1 MUX”:

(a) Write the Boolean functions for the four outputs in terms of the input variables

(b) If the circuit is listed in a truth table, how many rows and columns would there be in the truth table?

4-5 Design a combinational circuit with three inputs, x, y, and z, and three outputs, A, B, and C. When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When the binary input is 4, 5, 6, or 7, the binary output is one less than the input.

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4-11 Design a 4-bit combinational circuit incrementer. (A circuit that adds one to a 4-bit binary number.) The circuit can be designed using four half-adders.

4-13 The adder-subtractor circuit has the following values for mode input M and data inputs A and B. In each case, determine the values of the four SUM outputs and the carry C.

M A B

(a) 0 0111 0110(b) 0 1000 1001(c) 1 1100 1000(d) 1 0101 1010(e) 1 0000 0001

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4-27 A combinational circuit is specified by the following three Boolean functions:

F1(A, B, C) = ∑(2, 4, 7)

F2(A, B, C) = ∑(0, 3)

F3(A, B, C) = ∑(0, 2, 3, 4, 7)

Implement the circuit with a decoder constructed with NAND gates and NAND or AND gates connected to the decoder outputs. Use a block diagram for the decoder. Minimize the number of inputs in the external gates.

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4-28 A combinational circuit is defined by the following three Boolean functions:

F1 = x’ y’ z’ + x z

F2 = x y’ z’ + x’ y

F3 = x’ y’ z + x y

Design the circuit with a decoder and external gates.

4-31 Construct a 16 1 multiplexer with two 8 1 and one2 1 multiplexers. Use block diagrams.

4-32 Implement the following Boolean function with a multiplexer:

F(A, B, C, D) = ∑(0, 1, 3, 4, 8, 9, 15)

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4-33 Implement a full adder with two 4 1 multiplexers:

4-35 Implement the following Boolean function with a 4 1 multiplexer and external gates. Connect inputs A and B to the selection lines. The input requirements for the four data lines will be a function of variables C and D. These values are obtained by expressing F as a function of C and D for each of the four cases when AB = 00, 01, 10, and 11. These functions may have to be implemented with external gates.

F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)

chapter 4 combinational logic

Documents

function function

b c f1 f20

circuit function

desired function

abc abc abc abcf2

input onlyi

ab ac bc5

feedbackwhen input changes