chapter - 6 capacitor placement for power loss...
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127
CHAPTER - 6
Capacitor Placement for Power Loss Minimization
6.1 Introduction:
Capacitors are used in the unbalanced radial distribution systems
(URDS) for reactive power compensation; many constructions deferral
and enhance quality service. The volumes of benefits vary with placement
and sizing of capacitors and for unbalanced systems, unbalanced
switching of capacitors may be necessary to enhance these benefits.
Optimum shunt capacitor values are obtained using simulated
annealing method [39]. H. Kim and S.K You [61] proposed optimal shunt
capacitor bank values using genetic algorithm. They are handled the
capacitors as constant reactive power loads. These solutions mainly
utilize the positive sequence network model and the associated power
flows in formulating the problem. Hence, the results do not directly apply
for URDS.
This chapter presents a simple approach to identify the best
locations for capacitor and the optimal sizing of the capacitor bank in
URDS.Energy cost, capacitor installation cost and purchase cost are
considered in such a way that the objective function should be maximum
for the net cost saving. In the proposed method, two algorithms are
developed for the optimal sizing and location of capacitors in URDS.
128
Finally, the approach proposed is implemented successfully on the 25-
bus URDS and the IEEE 37-bus URDS.
6.2 Mathematical Formulation for Capacitor Placement
In the present work, the objective function is to decide the optimal
size of the capacitors that gives maximum net cost profit with capacitor
placement, satisfying the system constraints. The problem may be stated
as,
n
jCcIE KnKPTLTLPTKMaximize
1
]u(j)[][ (6.1)
Subjected to
Voltage constraint
In order to have quality supply, Voltage profile of complete network
is to be maintained in permissible range
maxminqqq VVV (6.2)
Current constraint
All the branch currents are to be maintained in permissible range
maxpqpq II (6.3)
Source constraint
The source capacity should be more than or equal to total load
maxpqpq PP (6.4)
maxpqpq QQ (6.5)
129
Where
KE = Energy Cost (Rs.3/kWh)
T = Time Period (8760 hrs)
TLP = Total active power loss before capacitor placement in kW
PTL = Total active power loss after capacitor placement in kW
= Depreciation factor is 0.2
nc = number of capacitor nodes
KI = Installation cost (Rs. 50,000/each location)
KC = Cost of the installation of the capacitor (Rs. 200/kVAr)
)( ju = Capacitor bank rating in kVAr of jth Capacitor
minqV Is 0.95 p.u.,
maxqV is 1.05 p.u
6.3 Algorithm for Candidate Nodes Identification
The algorithm for identifying the best candidate nodes for capacitor
placement is:
Step 1: Read the given data for unbalanced radial distribution system.
Step 2: Perform the load flows and calculate the total real power losses of
base case.
Step 3: Reactive power injections (QC) are made (except at source node)
in all the phases, load flows are run and real power losses are
computed.
Step 4: Calculate reduction in real power losses and associated
realpower loss indices (PLI) using eqn. (6.6)
130
Step 5: Select the best candidate nodes whose PLI > Tolerance.
Step 6: Stop.
The flow chart of the proposed method is shown in Appendix F as
Fig. F.2.
6.4 Proposed Candidate Nodes Identification Method for Capacitor
Placement
The proposed candidate node identification method for capacitor
placement is explained with the 25- bus unbalanced radial distribution
system [127] whose single line diagram is given Fig. 6.1 and system data
given at Appendix E in Table E1. The impedances of the lines are given in
Table E2.
Fig. 6.1 Single line diagram for 25-bus URDS [127]
The candidate nodes for the placement of capacitors are found in
this section. In the base case of three phase load flow, total active power
loss obtained is 150.12 kW. At each node, reactive power injections are
131
made in all the phases equal to local reactive load at that particular
node, load flows are performed and the total active power loss and loss
reduction in each case recorded are shown in Table 6.1
The power loss indices (PLI) are calculated as
reductionMinreductionMax
reductionMinireductionLossiPLI
..
.][.][
(6.6)
The power loss indices (PLI) for 25 bus URDS are given in Table
6.2. The suitable capacitor placement locations are identified using the
systematic PLI approach. The proposed approach reduces the system
resource capacity required and the optimization space search procedure.
The PLI approach is the systematic process to select the capacitor
best locations which are sensitive with considerable effect on the active
power loss reduction. Maximum PLI at each bus is taken to represent the
entire network PLI. In the present example, from Table 6.2, the nodes
with considerable effect on the active power loss reduction are observed
as 15, 14, 12 and 9.
132
Table 6.1 Power Loss Reductions for 25 bus URDS
Bus
no.
Real Power loss(kW)
with reactive power
injection Qc at each
bus in all the phases
equal to local reactive
load at that particular
bus
Loss
Reduction
(kW)
2 150.1225 0
3 147.8025 2.3200
4 146.6871 3.4354
5 147.4755 2.6470
6 146.8649 3.2576
7 150.1225 0
8 146.6567 3.4658
9 143.3385 6.7839
10 144.7280 5.3945
11 144.5633 5.5592
12 142.4946 7.6279
13 144.5035 5.6189
14 143.3311 6.7914
15 134.1132 16.0093
16 145.4619 4.6606
17 145.0712 5.0512
18 147.2179 2.9046
19 145.9406 4.1818
20 147.1387 2.9837
21 147.0366 3.0859
22 145.8084 4.3141
23 146.3854 3.7370
24 147.2501 2.8724
25 146.4120 3.7104
133
Table 6.2 Power Loss Indices for 25 bus URDS
Bus No Power loss Index (PLI)
2 0
3 0.1449
4 0.2146
5 0.1653
6 0.2035
7 0
8 0.2165
9 0.4238
10 0.3370
11 0.3472
12 0.4765
13 0.3510
14 0.4242
15 1.0000
16 0.2911
17 0.3155
18 0.1814
19 0.2612
20 0.1864
21 0.1928
22 0.2695
23 0.2334
24 0.1794
25 0.2318
The most suitable nodes for the capacitor placement are chosen
based on the condition that PLI to be greater than a PLI tolerance value
that lies between ‘0’ and ‘1’. The PLI tolerance value for a chosen system
is selected by verifying it with the highest net cost profit obtained with its
different values. The best PLI tolerance value gives the highest net profit
with capacitor placement, satisfying the system constraints.
134
0 5 10 15 20 250
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Bus Number
Pow
er
Loss
Index
Fig. 6.2 Plot between Bus Number and Power Loss Index (PLI)
Fig. 6.2 illustrates power loss index for 25 bus URDS. From
experimentation the best value of PLI tolerance is observed as 0.4.Hence
it can be concluded that the nodes 15, 12, 14, 9 with considerable effect
on the active power loss reduction are best candidate nodes for the
capacitor placement that gives the highest net profit satisfying the
system constraints.
6.5 Variational Technique Algorithm for the Capacitor Sizing
Step 1: Read the system data and the best candidate nodes for capacitor
placement.
Step 2: Set candidate node place as k
Step 3: At bus k, keep the capacitor with available standard sizes in
practice (50 kVAr per phase)and change them step wise.
Perform the Unbalanced power flow and Select Qc at bus k that
135
has got the highest cost saving using Eqn. (6.1) without
violating the constraints.
Step 4: Repeat step 3 for all the m buses in step1, suitable for capacitor
placement
Step 5: First capacitor is adjusted in steps with other capacitor sizes
fixed. Without violating constraints, for 1st capacitor, choose Qc
for maximum net cost saving and repeat step 5 for all the
capacitors
Step 6: Repeat step 5 till maximum savings are increased without
violating the constraints.
Step 7: Stop
The flow chart of the proposed method is shown in Appendix F as
Fig. F.3.
6.6 Simulation Results and Analysis
6.6.1 Case Study I : 25 - Bus URDS
Fig. 6.1 illustrates 4.16 kV, 25-bus URDS on which proposed
approach is implemented. System data is at Appendix E in Table E1,
whose line impedance values are given in Table E2. In the base case of
three phase load flow, total active power loss obtained is 150.12 kW and
reactive power loss is 131.63 kVAr. The voltages at base case are given in
Table 4.4 in chapter 4.
136
Table 6.3 Voltage profile for 25-bus URDS after capacitor placement
Bus
No
Phase- a Phase- b Phase- c
|Va|
p.u.
Va
deg.
|Vb|
p.u.
Vb
deg.
|Vc|
p.u.
Vc
deg.
1 1.0000 0.00 1.0000 -120.00 1.0000 120.00
2 0.9799 -0.93 0.9797 -120.79 0.9845 119.07
3 0.9730 -1.06 0.9731 -120.90 0.9789 118.91
4 0.9696 -1.12 0.9699 -120.95 0.9765 118.83
5 0.9685 -1.12 0.9689 -120.95 0.9755 118.83
6 0.9711 -1.42 0.9704 -121.24 0.9766 118.61
7 0.9645 -1.91 0.9633 -121.70 0.9704 118.16
8 0.9690 -1.41 0.9683 -121.23 0.9747 118.61
9 0.9617 -2.17 0.9601 -121.94 0.9680 117.93
10 0.9581 -2.22 0.9560 -121.97 0.9645 117.88
11 0.9564 -2.25 0.9541 -122.00 0.9630 117.85
12 0.9559 -2.29 0.9534 -122.04 0.9624 117.81
13 0.9557 -2.25 0.9533 -122.00 0.9622 117.85
14 0.9617 -2.17 0.9604 -121.93 0.9676 117.93
15 0.9608 -2.25 0.9594 -122.02 0.9668 117.84
16 0.9634 -1.91 0.9622 -121.70 0.9695 118.15
17 0.9606 -2.16 0.9594 -121.93 0.9663 117.93
18 0.9671 -1.06 0.9673 -120.88 0.9734 118.90
19 0.9623 -1.05 0.9631 -120.87 0.9691 118.91
20 0.9647 -1.06 0.9650 -120.87 0.9712 118.90
21 0.9636 -1.05 0.9636 -120.87 0.9697 118.91
22 0.9617 -1.05 0.9612 -120.86 0.9677 118.92
23 0.9663 -1.12 0.9671 -120.95 0.9739 118.83
24 0.9643 -1.12 0.9652 -120.95 0.9722 118.83
25 0.9619 -1.12 0.9634 -120.95 0.9703 118.83
Size of the capacitor banks placed using the Variational algorithm
at buses 15, 12, 14, and 9 are 450, 150, 300 and 600 kVAr respectively.
The voltages after capacitor placement are given in Table 6.3 for 25 bus
137
URDS. Fig 6.3 illustrates the voltage variation in all the phases for the
base case and after capacitor placement for 25 bus URDS.
Table 6.4 Power flows for 25-bus URDS after Capacitor Placement
Bus
From
Bus
To
Phase a Phase b Phase c
P
(kW)
Q
(kVAr)
P
(kW)
Q
(kVAr)
P
(kW)
Q
(kVAr)
1 2 1110.71 333.38 1122.34 338.66 1112.71 339.31
2 3 511.51 382.04 516.46 378.24 509.96 377.31
2 6 582.01 -73.05 587.56 -61.75 590.77 -61.20
3 4 246.58 186.60 246.38 178.31 231.02 166.19
3 18 227.20 166.58 227.25 166.48 232.10 175.59
4 5 40.04 30.03 40.04 30.03 40.04 30.03
4 23 155.88 115.64 145.71 102.48 140.61 100.46
6 7 496.07 -137.36 496.39 -127.76 510.45 -120.40
6 8 40.09 30.06 40.09 30.06 40.08 30.06
7 9 226.87 -86.66 232.14 -76.60 226.70 -81.65
7 14 224.57 -84.07 219.55 -84.20 239.53 -72.06
7 16 40.04 30.03 40.04 30.03 40.04 30.03
9 10 165.83 67.59 181.06 82.70 175.82 82.65
10 11 130.26 42.18 140.34 52.23 130.25 50.19
11 12 50.04 -14.97 60.05 -4.97 50.03 -9.98
11 13 35.03 25.02 45.04 32.03 40.03 30.02
14 15 133.52 -49.84 133.52 -49.86 133.49 -49.85
14 17 40.05 30.03 35.04 25.03 45.06 32.04
18 20 95.40 70.29 90.32 65.21 95.33 72.25
18 21 90.43 65.29 95.53 70.36 95.49 72.34
20 19 60.15 45.11 50.10 35.07 50.11 40.07
21 22 50.10 35.07 60.15 45.11 50.11 40.07
23 24 95.35 70.25 95.27 62.18 90.25 65.18
24 25 60.15 45.11 50.09 30.06 50.10 35.07
Table 4.5 in Chapter 4 and Table 6.4 depicts the power flows for 25
bus URDS for base case and after capacitor placement respectively. Real
138
power losses in each phase for base case and after capacitor placement
for 25 bus URDS are illustrated in Fig. 6.4. Table 6.5 depicts the base
case and after capacitor placement test results summary, the total active
power losses and minimum voltages of the 25 bus URDS.With capacitor
banks installation, total active power loss and reactive power loss came
down from 150.12kW, 167.28kVAr to 105.87 kW, 118.36 kVAr
respectively and minimum voltages in phase a, phase b and phase c
increased from 0.9284, 0.9284 and 0.9366 p.u to 0.9557, 0.9533 and
0.9622 p.u respectively.
Fig. 6.3 Voltage magnitude variation in all the phases for base case and
after capacitor placement for 25 bus URDS
139
Fig. 6.4 Real power losses in all the phases for base case and after
capacitor placement for 25 bus URDS
140
Table 6.5 Test Results summary of 25- bus URDS for capacitor placement
DescriptionBase Case After Capacitor Placement
Phase- a Phase b Phase- c Phase- a Phase b Phase- c
Capacitor placed nodes
9
12
14
15
- - -
4 x 50
1 x 50
2 x 50
3 x 50
4 x 50
1 x 50
2 x 50
3 x 50
4 x 50
1 x 50
2 x 50
3 x 50
Minimum Voltage 0.9284 0.9284 0.9366 0.9557 0.9533 0.9622
Voltage regulation (%) 7.16 7.16 6.34 4.43 4.67 3.78
Improvement of Voltage regulation (%) - - - 36.55 32.96 39.27
RealPower Loss (kW) 52.83 55.45 41.87 37.42 39.05 29.41
Total Active Power Loss reduction (%) - - - 29.16 29.56 29.74
Reactive Power Loss (kVAr) 58.29 53.30 55.69 41.38 37.67 39.31
Total Reactive Power Loss reduction (%) - - - 29.05 29.31 29.41
Total Demand (kW) 1126.12 1138.74 1125.16 1110.72 1122.35 1112.71
Total Released Demand (kW) - - - 15.40 16.39 12.45
Total Reactive Power Demand (kVAr) 850.29 854.30 855.69 833.38 838.67 839.31
Total Released Reactive Power Demand (kVAr) - - - 16.91 15.63 16.38
Total Feeder Capacity (kVA) 1411.09 1423.57 1413.60 1388.72 1401.08 1393.76
Total Released Feeder Capacity (kVA) - - - 22.37 22.49 19.84
Net Saving (Rs.) - 10,92,883.77
141
6.6.2 Case Study II : IEEE 37 - Bus URDS
Fig. 6.5 illustrates 4.8 kV, IEEE 37-bus URDS [128] without
voltage regulator, on which the proposed approach is implemented. All
line segments are undergrounded with highly unbalanced loads.
Fig. 6.5 Single line diagram of IEEE 37-bus URDS [128]
The line data, load data, line impedance, line charging
admittances, substation and transformer data are given at Appendix E in
Tables E3, E4, E5 and E6 respectively. Proposed approach performance
is observed by over loading each load by 25% in all the phases. Delta
connected capacitor bank is used.149.12 kW, 131.63 kVAr are the base
case active, reactive power losses obtained.
In 3 phases, at all buses, with reactive power injections, load flows
142
performed and the total active power loss, loss reduction and power loss
indices recorded in each case, for the 37-bus system are given in Table
6.6.
Table 6.6 Power Loss Reductions and Power Loss
Bus
No
Power loss(kW) with reactive power
injection Qc at each bus in 3 phases,
equal to local reactive load at that
particular bus
Loss
Reduction
(kW)PLI
701 139.1192 10.0128 1.0000
702 149.1319 0 0
703 149.1319 0 0
730 145.4629 3.6691 0.3664
709 149.1319 0 0
708 149.1319 0 0
733 143.8993 5.2327 0.5226
734 147.0653 2.0666 0.2064
737 139.5848 9.5471 0.9535
738 140.1399 8.9921 0.8981
711 149.1319 0 0
741 147.1058 2.0261 0.2024
713 145.7922 3.3398 0.3336
704 144.5636 4.5683 0.4563
720 144.5793 4.5526 0.4547
706 149.1319 0 0
725 147.7126 1.4194 0.1418
705 149.1319 0 0
742 147.2700 1.8619 0.1860
727 147.4091 1.7228 0.1721
744 147.1512 1.9807 0.1978
729 147.1514 1.9806 0.1978
775 149.1319 0 0
731 147.3530 1.7789 0.1777
732 149.1319 0 0
710 149.1319 0 0
735 145.2422 3.8897 0.3885
Contd . . .
143
740 145.5763 3.5556 0.3551
714 147.8824 1.2495 0.1248
718 146.1851 2.9468 0.2943
707 149.1319 0 0
722 140.1873 8.9446 0.8933
724 146.0963 3.0356 0.3032
728 144.7215 4.4105 0.4405
736 148.0144 1.1176 0.1116
712 142.0570 7.0749 0.7066
700 710 720 730 740 750 760 770 7800
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Bus Number
Pow
er
Lo
ss
Index
Fig. 6.6 Plot between Buses and PLI for IEEE 37-bus URDS
Fig. 6.6 illustrates power loss index plot for 37 bus URDS. From
experimentation it is observed that the best value of PLI tolerance
observed is 0.6.Hence it is concluded that nodes 701, 737, 738, 722, 712
with considerable effect on the active power loss reduction are best
candidate nodes for the capacitor placement that gives the highest net
profit satisfying the system constraints.
144
The voltage profiles of base case and after capacitor placement for
IEEE 37 bus URDS are given in Table 6.7. Table 6.8 depicts the power
flows of base case and after capacitor placement for IEEE 37 bus URDS.
Table 6.9 depicts base case and after capacitor placement test results
summary, the total active power losses, minimum voltages for the IEEE
37-bus URDS. From results, the capacitor banks sizes obtained at buses
701, 737, 738, 722 and 712 are 600, 300, 450, 300 and 450 kVAr
respectively. With capacitor banks installation, total active and reactive
power loss came down from 149.12 kW and 131.63kVAr to 120.66 kW
and 107.79kVAr respectively and the minimum voltage in phase a, phase
b and phase c increased from 0.9334, 0.9454 and 0.9266 p.u to 0.9525,
0.9678 and 0.9500 p.u respectively.
145
Table 6.7 Voltage profile of base case and after capacitor placement for IEEE 37bus URDS
Bus
No.
Base case After Capacitor placement
Phase- a Phase- b Phase- c Phase- a Phase- b Phase- c
|Va|
p.u.
Va
deg.
|Vb|
p.u.
Vb
deg.
|Vc|
p.u.
Vc
deg.
|Va|
p.u.
Va
deg.
|Vb|
p.u.
Vb
deg.
|Vc|
p.u.
Vc
deg.
799 1.0000 30.02 1.0000 -90.05 1.0000 150.08 1.0000 30.02 1.0000 -90.05 1.0000 150.08
701 0.9819 29.76 0.9809 -90.68 0.9758 149.69 0.9886 29.36 0.9894 -91.05 0.9838 149.21
702 0.9710 29.57 0.9699 -91.01 0.9629 149.43 0.9813 28.94 0.9827 -91.57 0.9754 148.71
703 0.9615 29.44 0.9623 -91.23 0.9531 149.15 0.9743 28.66 0.9781 -91.91 0.9687 148.27
730 0.9540 29.44 0.9559 -91.27 0.9455 149.08 0.9686 28.47 0.9736 -92.13 0.9632 148.01
709 0.9516 29.44 0.9538 -91.28 0.9433 149.06 0.9668 28.40 0.9721 -92.19 0.9617 147.92
708 0.9480 29.44 0.9511 -91.28 0.9401 149.00 0.9641 28.30 0.9704 -92.28 0.9596 147.77
733 0.9447 29.47 0.9498 -91.27 0.9374 148.92 0.9614 28.27 0.9697 -92.33 0.9577 147.63
734 0.9400 29.54 0.9478 -91.29 0.9330 148.80 0.9577 28.22 0.9687 -92.45 0.9545 147.41
737 0.9354 29.58 0.9464 -91.25 0.9301 148.67 0.9543 28.13 0.9685 -92.52 0.9530 147.16
738 0.9339 29.60 0.9459 -91.26 0.9286 148.62 0.9530 28.13 0.9682 -92.55 0.9518 147.09
711 0.9335 29.64 0.9457 -91.29 0.9273 148.61 0.9526 28.16 0.9680 -92.58 0.9505 147.08
741 0.9334 29.65 0.9456 -91.30 0.9269 148.61 0.9525 28.17 0.9679 -92.59 0.9501 147.08
713 0.9687 29.55 0.9668 -91.04 0.9599 149.44 0.9794 28.88 0.9801 -91.64 0.9729 148.68
704 0.9656 29.51 0.9626 -91.06 0.9567 149.47 0.9769 28.77 0.9766 -91.72 0.9704 148.63
720 0.9639 29.46 0.9581 -91.13 0.9534 149.56 0.9761 28.62 0.9731 -91.87 0.9682 148.62
706 0.9638 29.44 0.9575 -91.13 0.9532 149.57 0.9760 28.61 0.9725 -91.88 0.9680 148.64
725 0.9636 29.43 0.9571 -91.13 0.9531 149.59 0.9758 28.60 0.9720 -91.87 0.9679 148.65
Contd . . .
146
705 0.9684 29.56 0.9665 -90.98 0.9605 149.48 0.9794 28.79 0.9801 -91.67 0.9738 148.61
742 0.9679 29.53 0.9654 -90.97 0.9602 149.51 0.9789 28.77 0.9790 -91.66 0.9736 148.64
727 0.9600 29.46 0.9614 -91.21 0.9518 149.14 0.9728 28.68 0.9773 -91.90 0.9674 148.26
744 0.9590 29.46 0.9609 -91.20 0.9513 149.12 0.9719 28.68 0.9768 -91.88 0.9669 148.24
729 0.9585 29.47 0.9608 -91.19 0.9511 149.11 0.9714 28.69 0.9767 -91.87 0.9667 148.23
775 0.9516 29.44 0.9538 -91.28 0.9433 149.06 0.9668 28.40 0.9721 -92.19 0.9617 147.92
731 0.9513 29.41 0.9526 -91.28 0.9429 149.09 0.9665 28.37 0.9710 -92.19 0.9614 147.95
732 1.0000 30.02 1.0000 -90.05 1.0000 150.08 1.0000 30.02 1.0000 -90.05 1.0000 150.08
710 0.9394 29.57 0.9463 -91.33 0.9309 148.84 0.9571 28.25 0.9673 -92.48 0.9525 147.44
735 0.9392 29.59 0.9461 -91.35 0.9302 148.84 0.9569 28.27 0.9671 -92.50 0.9517 147.45
740 0.9334 29.66 0.9454 -91.31 0.9266 148.62 0.9525 28.18 0.9678 -92.60 0.9500 147.08
714 0.9652 29.51 0.9625 -91.05 0.9566 149.46 0.9765 28.77 0.9765 -91.71 0.9703 148.63
718 0.9635 29.52 0.9622 -91.00 0.9560 149.41 0.9748 28.79 0.9762 -91.66 0.9697 148.58
707 0.9615 29.33 0.9510 -91.08 0.9513 149.76 0.9748 28.27 0.9673 -92.04 0.9674 148.60
722 0.9612 29.32 0.9503 -91.08 0.9510 149.78 0.9747 28.23 0.9667 -92.06 0.9673 148.59
724 0.9611 29.30 0.9497 -91.07 0.9510 149.80 0.9744 28.24 0.9660 -92.03 0.9671 148.63
728 0.9585 29.47 0.9604 -91.20 0.9507 149.13 0.9714 28.69 0.9763 -91.88 0.9664 148.24
736 0.9386 29.52 0.9441 -91.31 0.9305 148.90 0.9564 28.20 0.9651 -92.46 0.9520 147.51
712 0.9671 29.57 0.9653 -90.97 0.9592 149.49 0.9786 28.72 0.9794 -91.75 0.9731 148.54
147
Table 6.8 Power flows of base case and after capacitor placement for IEEE 37-bus URDS
Bus
From
Bus
To
Base Case After Capacitor Placement
Phase a Phase b Phase c Phase a Phase b Phase c
P
(kW)
Q
(kVAr)
P
(kW)
Q
(kVAr)
P
(kW)
Q
(kVAr)
P
(kW)
Q
(kVAr)
P
(kW)
Q
(kVAr)
P
(kW)
Q
(kVAr)
799 701 1280.22 736.39 141.09 1348.49 1236.01 924.88 1269.83 - 26.60 751.12 -986.85 618.31 -1270.10
701 702 973.15 489.31 114.24 1125.47 968.86 622.91 972.86 0.61 542.17 881.94 549.14 870.95
702 703 614.86 286.28 18.31 613.66 463.69 353.11 614.45 50.15 193.01 493.54 260.93 478.17
703 730 464.50 232.94 8.60 486.01 395.29 282.97 468.22 2.65 220.87 370.05 195.19 410.68
730 709 421.85 172.76 7.87 482.92 360.80 217.14 428.91 60.52 217.85 369.17 161.75 345.68
709 708 420.76 173.20 31.02 422.62 290.64 213.46 428.20 59.04 180.19 308.54 92.38 344.19
702 705 116.50 52.94 43.91 188.02 171.87 71.06 121.61 93.92 173.70 119.44 47.83 148.78
702 713 228.19 149.03 80.66 313.32 326.28 184.30 228.60 53.59 163.11 268.23 245.95 231.05
703 727 142.80 54.66 30.29 123.54 68.09 63.47 141.06 58.65 33.45 122.70 69.94 61.68
709 731 0.01 0.55 38.71 59.23 69.62 3.03 0.04 0.57 36.72 60.30 69.76 0.71
709 775 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
708 733 409.43 160.28 112.65 291.74 131.85 193.45 411.75 28.04 12.36 220.14 15.90 273.85
708 707 9.59 12.98 81.39 129.72 158.56 18.91 15.37 85.38 166.47 88.17 77.56 69.25
733 734 337.88 165.07 81.16 228.12 132.53 192.54 340.29 30.77 45.76 157.96 17.14 273.09
734 737 279.06 78.01 102.00 198.93 49.25 95.64 286.33 -57.11 25.31 -128.37 69.49 -180.12
734 710 38.41 57.08 20.58 29.00 66.57 64.64 35.47 58.62 19.42 29.70 69.47 61.77
737 738 161.03 83.38 47.20 93.89 50.10 94.93 160.44 -42.05 6.31 -69.73 13.79 -121.54
738 711 56.18 88.64 0.90 0.49 50.74 94.41 51.15 91.23 0.96 0.47 55.46 91.81
Contd . . .
148
711 741 18.24 29.77 0.32 0.18 17.39 31.15 16.55 30.60 0.34 0.17 18.94 30.26
711 740 37.91 59.24 0.13 0.07 33.79 62.85 34.55 61.02 0.14 0.07 36.95 61.11
713 704 188.26 90.59 79.50 312.93 294.12 120.12 190.34 5.28 161.60 268.24 212.76 167.42
704 714 84.18 6.61 27.62 90.25 16.63 1.23 84.38 4.34 29.81 89.57 16.65 0.84
704 720 49.49 69.87 103.35 160.81 225.65 85.79 52.32 29.16 188.64 117.41 144.04 134.43
720 707 9.84 13.16 82.16 131.34 159.78 20.39 14.61 86.69 168.00 88.22 76.94 70.49
720 706 0.01 0.99 19.38 29.79 34.26 1.40 0.05 1.02 18.59 30.22 34.29 0.48
706 725 0.00 0.21 18.67 30.15 34.89 1.01 0.01 0.22 17.85 30.57 34.94 0.05
705 742 6.68 0.55 35.82 65.11 69.95 3.80 6.70 0.36 34.16 65.85 70.07 2.01
705 712 109.56 53.82 7.51 122.53 101.75 66.94 114.91 -92.64 138.35 -53.94 21.70 -146.11
727 744 123.88 25.00 30.58 123.62 51.39 32.14 123.10 28.50 33.76 122.78 52.34 30.81
744 725 53.70 28.47 2.00 61.33 51.95 31.76 52.79 29.97 0.43 61.30 52.91 30.40
744 729 35.04 1.60 16.39 31.17 0.18 0.11 35.10 0.60 17.19 30.77 0.18 0.12
710 735 38.36 59.17 0.13 0.07 33.28 62.89 35.31 60.80 0.14 0.07 36.17 61.35
710 736 0.02 0.92 19.26 29.69 34.25 0.88 0.07 0.95 18.01 30.36 34.29 0.53
714 718 70.14 5.18 31.18 63.08 0.33 0.21 70.30 3.29 32.72 62.36 0.34 0.22
707 724 0.01 0.58 19.01 30.07 34.68 1.35 0.03 0.59 17.97 30.62 34.72 0.14
707 722 9.82 14.51 61.69 101.04 124.79 19.11 14.84 85.28 148.01 58.54 42.58 69.61
149
Table 6.9 Test results summary for IEEE 37 bus URDS for capacitor placement
DescriptionBase Case After Capacitor Placement
Phase a Phase b Phase c Phase a Phase b Phase c
Capacitor placed nodes
701
712
722
737
738
- - -
4 x 50
2 x 50
2 x 50
2 x 50
1 x 50
4 x 50
2 x 50
2 x 50
2 x 50
1 x 50
4 x 50
2 x 50
2 x 50
2 x 50
1 x 50
Minimum Voltage 0.9334 0.9454 0.9266 0.9525 0.9678 0.9500
Voltage regulation (%) 6.66 5.46 7.34 4.75 3.22 5.00
Improvement of Voltage regulation (%) - - - 28.68 41.02 31.88
Active Power Loss (kW) 55.00 41.22 52.90 42.80 34.57 43.29
Total Active Power Loss reduction (%) - - - 22.18 16.13 18.17
Reactive Power Loss (kVAr) 41.89 38.92 50.82 33.77 31.94 42.08
Total Reactive Power Loss reduction (%) - - - 19.38 17.93 17.20
Total Demand (kW) 1165.2 1037.02 1525.8 1153 1030.74 1516.19
Total Released Demand (kW) - - - 12.2 6.65 9.61
Total Reactive Power Demand (kVAr) 585.29 526.42 767.12 577.17 519.44 758.38
Total Released Reactive Power Demand (kVAr) - - - 8.12 6.98 8.74
Total Feeder Capacity (kVA) 1303.94 1162.98 1707.79 1289.39 1154.23 1695.28
Total Released Feeder Capacity (kVA) - - - 14.55 8.75 12.51
Net Saving (Rs.) - 6,26,135.17
150
6.7 Conclusion
A method is presented for optimal sizing and placement of
capacitor banks in unbalanced radial distribution systems to increase
voltage profile and minimizing power losses with an objective function of
maximizing net cost savings. Proposed method determines suitable
candidate nodes based on power loss indices (PLI) to place capacitors in
best locations. The capacitor-sizing problem is also addressed for loss
minimization using variational technique algorithm. The results obtained
indicate efficacy of the proposed method for capacitor placement and
sizing for 25-bus and IEEE 37-bus URDS.