chapter4 arithmetic

8/3/2019 Chapter4 Arithmetic

1/74

Chapter 4


2/74

Addition/subtraction of signed numbers

si =

ci+1 =

13

7+ Y

1

0

0

0

1

0

1

1

0

0

1

1

0

11

0

0

1

1

0

1

0

01

0

0

0

0

1

1

1

1

0

0

0

0

1

1

11

Example:

10= = 0

01 1

11 1 0 0

1

1 1 10

Legend for stage i

xi yi Carry-in ci Sumsi Carry-outci+1

X

Z

+ 6 0+xiyi

si

Carry-outci+1

Carry-inci

xiyici

xiyici

xiyici

xiyici xi yi ci =

+ + +

yici

xici

xiyi+ +

At the ith stage:

Input:

ci is the carry-in

Output:

si is the sum

ci+1

carry-out to (i+1)st

state


3/74

Addition logic for a single stage

Full adder (FA)ci

ci 1+

si

Sum Carry

yi

xi

ci

yi

xi

ci

yi

xi

xi

c

i

yi

si

ci 1+

Full Adder (FA): Symbol for the complete circuit

for a single stage of addition.


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n-bit adderCascade n full adder (FA) blocks to form a n-bit adder.

Carries propagate or ripple through this cascade, n-bit ripple carry adder.

FA c0

y1

x1

s1

FA

c1

y0

x0

s0

FA

cn 1-

yn 1-

xn 1-

cn

sn 1-

Most significant bit(MSB) position

Least significant bit(LSB) position

Carry-in c0 into the LSB position provides a convenient way to

perform subtraction.


5/74

K n-bit adderK n-bit numbers can be added by cascading k n-bit adders.

n-bit c0

yn

xn

sn

cn

y0

xn 1-

s0

ckn

sk 1- n

x0

yn 1-

y2n 1-

x2n 1-

ykn 1-

sn 1-

s2n 1-

skn 1-

xkn 1-

adder

n-bitadder

n-bitadder

Each n-bit adder forms a block, so this is cascading of blocks.Carries ripple or propagate through blocks, Blocked Ripple Carry Adder


6/74

n-bit subtractor

FA 1

y1

x1

s1

FA

c1

y0

x0

s0

FA

cn 1-

yn 1-

xn 1-

cn

sn 1-

Most significant bit(MSB) position

Least significant bit(LSB) position

RecallX Yis equivalent to adding 2s complement ofYtoX.2s complement is equivalent to 1s complement + 1.

X Y = X+ Y+1

2s complement of positive and negative numbers is computed similarly.


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n-bit adder/subtractor (contd..)Add/Subcontrol

n-bit adder

xn 1-

x1

x0

cn

sn 1-

s1

s0

c0

yn 1- y1 y0

Add/sub control = 0, addition.

Add/sub control = 1, subtraction.


8/74

Detecting overflowsy Overflows can only occur when the sign of the two operands is

the same.

y Overflow occurs if the sign of the result is different from the

sign of the operands.

y Recall that the MSB represents the sign.y xn-1, yn-1,sn-1represent the sign of operand x,operand yand result s

respectively.

y Circuit to detect overflow can be implemented by the

following logic expressions:

111111 ! nnnnnn syxsyxOverflow

1! nn ccOverflow


9/74

Computing the add timeConsider0th stage:

x0 y0

c0c1

s0

FA

c1 is available after 2 gate delays.

s1 is available after 1 gate delay.

ci

yi

xi

ci

yi

xi

xi

ci

yi

si

ci 1+

Sum Carry


10/74

Computing the add time (contd..)

x2 y2

s2

FA

x0 y0x1 y1

FA

c2FA

c1c3 c0

x3 y3

FAc4

s1 s0s3

Cascade of 4 Full Adders,ora 4-bit adder

s0 available after 1 gate delays,c1 available after 2 gate delays.

s1 available after 3 gate delays,c2 available after 4 gate delays.s2 available after 5 gate delays,c3 available after 6 gate delays.

s3 available after 7 gate delays,c4 available after 8 gate delays.

Foran n-bit adder, sn-1 isavailable after2n-1 gate delayscn isavailable after 2n gate delays.


11/74

Fast additionRecall the equations:

iiiiiii

iiii

cycxyxc

cyxs

!

!

1

Second equation can be written as:

iiiiii cyxyxc )(1 !

We can write:

iiiiii

iiii

yxPandyxGwhere

cPGc

!!

!1

Gi is called generate function and Pi is called propagate functionGi andPi are computedonlyfromxi andyi and not ci, thus they canbe computed in one gate delayafterXandYare applied to theinputsofan n-bit adder.


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Carry lookaheadci1 ! Gi Pici

ci ! Gi1 Pi1ci1

ci1 ! Gi Pi(Gi1 Pi1ci1)

continuing

ci1 ! Gi Pi(Gi1 Pi1(Gi2 Pi 2ci2 ))

until

ci1 !Gi PiGi1 PiPi1Gi2 ..PiPi1..P1G0 PiPi1...P0c0

All carries can be obtained 3 gate delaysafter X,Yand c0 are applied.-One gate delayforPi andGi

-Two gate delays in the AND-OR circuit for ci+1Allsums can be obtained 1 gate delayafter the carriesare computed.Independent ofn,n-bit addition requiresonly 4 gate delays.This is calledCarry Lookahead adder.


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Carry-lookahead adder

Carry-lookahead logic

B cell B cell B cell B cell

s3

P3

G3

c3

P2

G2

c2

s2

G1

c1

P1

s1

G0

c0

P0

s0

.c

4

x1

y1

x3

y3

x2

y2

x0

y0

G i

ci

..

.

P i s i

xi

yi

B cell

4-bit

carry-lookahead

adder

B-cell for a single stage


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Carry lookahead adder (contd..)y Performing n-bit additionin 4 gate delaysindependent ofnis good only theoretically because of fan-inconstraints.

y LastAND gate and OR gate require a fan-in of (n+1) for a n-bit adder.y For a 4-bit adder (n=4) fan-in of 5 is required.y Practicallimit for most gates.

y In order to add operandslonger than 4 bits, we cancascade4-bit Carry-Lookahead adders. Cascade of Carry-Lookaheadaddersiscalled Blocked Carry-Lookahead adder.

ci1 !Gi PiGi1 PiPi1Gi2 ..PiPi1..P1G0 PiPi1...P0c0


15/74

4-bit carry-lookahead Adder


16/74

Blocked Carry-Lookahead adder

c4 ! G3 P3G2 P3P2G1 P3P2P1G0 P3P2P1P0c0

Carry-out froma 4-bit block can be given as:

Rewrite thisas:

P0I !P3P2P1P0

G0I!G3 P3G2 P3P2G1 P3P2P1G0

SubscriptI denotesthe blockedcarrylookaheadandidentifiesthe block.

Cascade 4 4-bit adders,c16 can be expressedas:

c16 !G3I P3

IG

2

I P3

IP

2

IG1

I P3

IP

2

IP1

0G0

I P3

IP

2

IP1

0P0

0c0


17/74

Blocked Carry-Lookahead adder

Carry-lookahead logic

4-bit adder 4-bit adder 4-bit adder 4-bit adder

s15-12

P3IG3I

c12

P2IG2I

c8

s11-8

G1I

c4

P1I

s7-4

G0I

c0

P0I

s3-0

c16

x15-12 y15-12 x11-8 y11-8 x7-4 y7-4 x3-0 y3-0

.

Afterxi,yi and c0 are appliedas inputs:- Gi andPi for each stage are available after 1 gate delay.

-PI

isavailable after 2 andGI

after 3 gate delays.- All carriesare available after 5 gate delays.- c16 isavailable after 5 gate delays.- s15 which dependson c12 isavailable after 8 (5+3)gate delays

(Recall that fora 4-bit carrylookaheadadder, the last sum bit isavailable 3 gate delaysafterall inputsare available)


18/74


19/74

Multiplication of unsigned numbers

Product of 2 n-bit numbers is at most a 2n-bit number.

Unsigned multiplication can be viewed as addition of shifted

versions of the multiplicand.


20/74

Multiplication of unsigned

numbers (contd..)

y We added the partial products at end.

y Alternative would be to add the partial products at each stage.

y Rules to implement multiplication are:

y If the ith bit of the multiplier is 1, shift the multiplicand and add the

shifted multiplicand to the current value of the partial product.

y Hand over the partial product to the next stage

y Value of the partial product at the start stage is 0.


21/74

Multiplication of unsigned numbers

ith multiplier bit

carry incarry out

jth multiplicand bit

i

th

multiplier bit

Bit ofincomingpartialproduct (PPi)

Bitofoutgoingpartialproduct(PP(i+1))

FA

Typicalmultiplication cell


22/74

Combinatorial array multiplier

Multiplicand

m3 m2 m1 m00 0 0 0

q3

q2

q1

q00

p2

p1

p0

0

0

0

p3p4p5p6p7

PP1

PP2

PP3

(PP0)

,

Product is: p7,p6,..p0

Multiplicand is shifted by displacing it through an array of adders.



23/74


(contd..)y Combinatorial arraymultipliers are:

y Extremely inefficient.

y Have a high gate count for multiplying numbers of practicalsize such as 32-

bit or 64-bitnumbers.

y Perform only one function,namely,unsigned integer product.

y Improve gate efficiency by using amixture of

combinatorial array techniques and sequential

techniques requiring lesscombinationallogic.


24/74

Sequential multiplicationy Recall the rule for generating partial products:

y If the ith bit of themultiplier is 1, add the appropriately shiftedmultiplicand

to the current partial product.

y Multiplicand has beenshifted left when added to the partial product.

y However, adding a left-shiftedmultiplicand to an

unshifted partial productis equivalent to adding an

unshiftedmultiplicand to a right-shifted partial

product.


25/74

Sequential Circuit Multiplier

qn 1-

mn 1-

n-bit

Adder

Multiplicand M

Controlsequencer

Multiplier Q

0

C

Shift right

RegisterA (initially 0)

Add/Noaddcontrol

an 1-

a0

q0

m0

0

MUX


26/74

Sequential multiplication (contd..)

1 1 1 1

1 0 1 1

1 1 1 1

1 1 1 0

1 1 1 0

1 1 0 1

1 1 0 1

Initial configuration

Add

M

1 1 0 1

C

First cycle

Second cycle

Third cycle

Fourth cycle

No add

Shift

ShiftAdd

Shift

ShiftAdd

1 1 1 1

0

0

0

1

0

0

0

1

0

0 0 0 0

0 1 1 0

1 1 0 1

0 0 1 1

1 0 0 1

0 1 0 0

0 0 0 1

1 0 0 0

1 0 0 1

1 0 1 1

QA

Product


27/74


28/74

Signed Multiplicationy Considering 2s-complementsigned operands, what will happen to (-

13)v(+11) if following the samemethod ofunsignedmultiplication?

Sign extension of negative multiplicand.

1

0

11 11 1 1 0 0 1 1

110

110

1

0

1000111011

000000

1100111

00000000

110011111

13-

143-

11+( )

Sign extension isshown in blue


29/74

Signed Multiplicationy For a negativemultiplier, a straightforward solutionis

to form the 2s-complement of both the multiplier andthemultiplicand and proceed asin the case of a

positivemultiplier.

y Thisis possible because complementation of bothoperands doesnotchange the value or the sign of theproduct.

y A technique that works equally well for both negativeand positivemultipliers Booth algorithm.


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Booth Algorithmy Consider in a multiplication, themultiplier is positive

0011110, howmany appropriately shifted versions ofthemultiplicand are added in a standard procedure?

0

0 0

1 0 1 1 0 1

0

0 0 0 0 0 0

1

0

011010

1011010

1011010

10110100000000

000000

011000101010

0

00

1+ 1+ 1+ 1+


31/74

Booth Algorithmy Since 0011110 = 0100000 0000010,if we use the

expression to the right, what will happen?

0

1

0 1 0 1 1 1

0000

00000000000000

1 1 1 1 1 1 1 0 1 0 0 1

00

0

0 0 0 1 0 1 1 0 1

0 0 0 0 0 0 0 0

0110001001000 1

2's complement of

the multiplicand

0

0

0

0

1+ 1-

0

0

0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0


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Booth Algorithmy In general,in the Booth scheme, -1 times the shifted multiplicand isselected whenmoving from 0 to 1, and +1 times the shiftedmultiplicand isselected whenmoving from 1 to 0, as themultiplierisscanned from right to left.

Booth recoding of a multiplier.

001101011100110100

00000000 1+ 1-1-1+1-1+1-1+1-1+


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Booth Algorithm

Booth multiplication with a negative multiplier.

01 01 1 1 1 0 1 10 0 0 0 0 0 0 0 0

00

0110

0 0 0 0 1 1 0

1100111

0 0 0 0 0 0

01000 11111

1

10 1 1 0 1

1 1 0 1 0 6-

13+( )

X

78-

+11- 1-


34/74

Booth AlgorithmMultiplier

Bit i Bit i 1-

Version of multiplicandselected by biti

0

1

0

0

01

1 1

0 M

1+ M

1 M

0 M

Booth multiplier recoding table.

X

X

X

X


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Booth Algorithmy Bestcase a long string of 1s (skipping over 1s)y Worstcase 0s and 1s are alternating

1

0

1110000111110000

001111011010001

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0

000000000000

00000000

1- 1- 1- 1- 1- 1- 1- 1-

1- 1- 1- 1-

1-1-

1+ 1+ 1+ 1+ 1+ 1+ 1+ 1+

1+

1+1+1+

1+

Worst-case

multiplier

Ordinarymultiplier

Goodmultiplier


36/74


37/74

Bit-Pair Recoding of Multipliersy Bit-pair recoding halves the maximumnumber of

summands (versions of themultiplicand).

1+1

(a) Example of bit-pair recoding derived from Booth recoding

0

000

1 1 0 1 0

Implied 0 to right of LSB

1

0

Sign extension

1

21


38/74

Bit-Pair Recoding of Multipliers

i 1+ i 1

(b) Table of multiplicand selection decisions

selected at position i

MultiplicandMultiplier bit-pair

i

0

0

1

1

1

0

1

0

1

1

1

1

0

0

0

1

1

0

0

1

0

0

1

Multiplier bit on the right

0 0 X M

1+

1

1+

0

1

2

2+

X M

X M

X M

X M

X M

X M

X M


39/74

Bit-Pair Recoding of Multipliers

39

1-

0000

1 1 1 1 1 0

0 0 0 0 11

1 1 1 1 10 0

0 0 0 0 0 0

0000 111111

0 1 1 0 1

01 010011111

1 1 1 1 0 0 1 1

0 0 0 0 0 0

1 1 1 0 1 1 0 0 1 0

0

1

0 0

1 0

1

0 0

0

0 1

0

0 1

10

0

010

0 1 1 0 1

11

1-

6-

13+( )

1+

78-

1- 2-

Figure 6.15. Multiplication requiring only n/2 summands.


40/74

Carry-Save Addition of Summandsy

CSA

speed

su

p the addition

process.

40P7 P6 P5 P4 P3 P2 P1 P0


41/74

Carry-Save Addition ofSummands(Cont.,)

P3 P2 P1 P0P5 P4P7 P6


42/74

Carry-Save Addition ofSummands(Cont.,)

y Consider the addition ofmany summands, we can:Group the summandsin threes and performcarry-save addition on

each of these groupsin parallel to generate a set ofS and C vectorsin

one full-adder delay

Group all of the S and C vectorsinto threes, and performcarry-saveaddition on them, generating a further set ofS and C vectorsin onemore full-adder delay

Continue with this processuntil there are only two vectors remaining

They can be added in a RCA or CLA to produce the desired product


43/74

Carry-Save Addition of Summands

Figure 6.17. A multiplication example used to illustrate carry-save addition as shown in Figure 6.18.

100 1 11

100 1 11

100 1 11

11111 1

100 1 11 M

Q

A

B

C

D

E

F

(2,835)

X

(45)

(63)

100 1 11

100 1 11

100 1 11

000 1 11 111 0 00 Product

M


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Figure 6.18.The multiplication example from Figure 6.17 performed usingcarry-save addition.

00000101 0 10

10010000 1 11 1

+

1000011 1

10010111 0 10 1

0110 1 10 0

00011010 0 00

10001011 1 0 1

110001 1 0

00111100

00110 1 10

11001 0 01

100 1 11

100 1 11

100 1 11

00110 1 10

11001 0 01

100 1 11

100 1 11

100 1 11

11111 1

100 1 11 M

Q

A

B

C

S1

C1

D

E

F

S2

C2

S1

C1

S2

S3

C

3C

2

S4

C4

Product

x


45/74


46/74

M

anual Division

Longhand division examples.

1101

1

1314

26

21

274 100010010

10101

1101

1

1110

1101

10000

13 1101


47/74

Longhand Division Stepsy Position the divisor appropriately with respect to the

dividend and performs a subtraction.

y

If the rem

ainder iszero or positive, a qu

otient bit of 1is determined, the remainder is extended by another

bit of the dividend, the divisor is repositioned, and

another subtractionis performed.

y

If the rem

ainder isnegative, a qu

otient bit of 0 isdetermined, the dividend is restored by adding back

the divisor, and the divisor is repositioned for another

subtraction.


48/74

Circuit Arrangement

Figure 6.21. Circuit arrangement for binary division.

qn-1

DivisorM

Control

Sequencer

Dividend Q

Shift left

N+1 bit

adder

q0

Add/Subtract

Quotient

Setting

A

m00 mn-1

a0an an-1


49/74

Restoring Divisiony ShiftA and Q left one binary position

y Subtract M fromA, and place the answer backinA

y If the sign ofAis 1,set q0 to 0 and add M back to A(restoreA); otherwise,set q0 to 1

y Repeat these stepsn times


50/74

Examples

10111

Figure 6.22.A restoring-division example.

1 1 1 1 1

01111

0

0

0

1

000

0

0

00

0

0

0

00

0

1

00

0

0

0

1 01

11

1 1

01

0001

SubtractShift

Restore

1 00001 0000

1 1

Initially

Subtract

Shift

10111

100001100000000

SubtractShift

Restore

101110100010000

1 1

QuotientRemainder

Shift

10111

1 0000

Subtract

Second cycle

First cycle

Third cycle

Fourth cycle

00

0

0

00

1

0

1

10000

1 11 0000

11111Restore

q0Set

q0Set

q0Set

q0Set


51/74

Nonrestoring DivisionyAvoid the need for restoring A after anunsuccessfulsubtraction.

yAny idea?y Step 1: (Repeatn times)If the sign ofAis 0,shiftA and Q left one bit position andsubtract M fromA; otherwise,shiftA and Q left and add M

to A.Now,if the sign ofAis 0,set q0 to 1; otherwise,set q0 to 0.

y Step2: If the sign ofAis 1, add M to A


52/74

Examples

A nonrestoring-division example.

Add

Restore

remainder

Remainder

0 0 0 01

1 1 1 1 10 0 0 1 1

1

Quotient

0 0 1 01 1 1 1 1

0 0 0 01 1 1 1 1

Shift 0 0 0

11000

01111

Add

0 0 0 1 1

0 0 0 0 1 0 0 0

1 1 1 0 1

Shift

Subtract

Initially 0 0 0 0 0 1 0 0 0

1 1 1 0 0000

1 1 1 0 0

0 0 0 1 1

0 0 0Shift

Add

0 0 10 0 0 01

1 1 1 0 1

Shift

Subtract

0 0 0 110000

Fourth cycle

Third cycle

Second cycle

First cycle

q0Set

q0

Set

q0

Set

q0

Set


53/74


54/74

FractionsIf b isa binaryvector, then we have seen that it can be interpretedasan unsigned integer by:

V(b) = b31.231 + b30.2

30 + bn-3.229 + .... + b1.2

1 + b0.20

Thisvector hasan implicit binary point to its immediate right:

b31b30b29....................b1b0. implicit binary point

Suppose if the binaryvector is interpreted with the implicit binary point isjust left of the sign bit:

implicit binary point .b31b30b29....................b1b0

The value of b is then given by:

V(b) = b31.2-1 + b30.2

-2 + b29.2-3 + .... + b1.2

-31 + b0.2-32


55/74

Range of fractionsThe value of the unsigned binary fraction is:

V(b) = b31.2-1 + b30.2

-2 + b29.2-3 + .... + b1.2

-31 + b0.2-32

The range of the numbers represented in this format is:

In general for a n-bit binary fraction (a number with an assumed binary

point at the immediate left of the vector), then the range of values is:

9999999998.021)(032

}ee

bV

nbV

ee 21)(0


56/74

Scientific notationPrevious representations have a fixed point. Either the point is to the immediateright or it is to the immediate left. This is called Fixed point representation.

Fixed point representation suffers from a drawback that the representation can

only represent a finite range (and quite small) range of numbers.

A more convenient representation is the scientific representation, wherethe numbers are represented in the form:

x !m1.m2m3m4 v bse

Components of these numbers are:

Mantissa (m),impliedbase (b),and exponent(e)


57/74

Significant digitsA number such as the following is said to have 7 significant digits

x ! s0.m1m2m3m4m5m6m7 v bse

Fractions in the range 0.0 to 0.9999999 need about 24 bits of precision

(in binary). For example the binary fraction with 24 1s:

111111111111111111111111 = 0.9999999404

Not every real number between 0 and 0.9999999404 can be represented

by a 24-bit fractional number.

The smallest non-zero number that can be represented is:

000000000000000000000001 = 5.96046 x 10-8

Every other non-zero number is constructed in increments of this value.


58/74

Sign and exponent digitsIn a 32-bit number, suppose we allocate 2

4bits to represent a fractionalmantissa.

Assume that the mantissa is represented in sign and magnitude format,

and we have allocated one bit to represent the sign.

We allocate 7 bits to represent the exponent, and assume that the

exponent is represented as a 2s complement integer.

There are no bits allocated to represent the base, we assume that the

base is implied for now, that is the base is 2.

Since a 7-bit 2s complement number can represent values in the range

-64 to 63, the range of numbers that can be represented is:

0.0000001 x 2-64 < = | x |


59/74

A sample representation

Si gn Exponent Fractional mantissa

bit

1 7 24

24-bit mantissa with an implied binary point to the immediate left

7-bit exponent in 2s complement form, and implied base is 2.


60/74

Normalization

If the number is to be represented using only 7 significant mantissa digits,

the representation ignoring rounding is:

Consider the number: x = 0.0004056781 x 1012

x = 0.0004056 x 1012

If the number is shifted so that as many significant digits are brought into

7 available slots: x = 0.4056781 x 109 = 0.0004056 x 1012

Exponent ofx was decreased by 1 for every left shift ofx.

A number which is brought into a form so that all of the available mantissa

digits are optimally used (this is different from all occupied which may

not hold), is called a normalized number.

Same methodology holds in the case of binary mantissas

0001101000(10110) x 28 = 1101000101(10) x 25


61/74

Normalization (contd..)A floating point number is in normalized form if the most significant1 in the mantissa is in the most significant bit of the mantissa.

All normalized floating point numbers in this system will be of the form:

0.1xxxxx.......xx

Range of numbers representable in this system, if every number must benormalized is:

0.5 x 2-64


62/74

Normalization, overflow and underflow

The procedure for normalizing a floating point number is:Do (until MSB of mantissa = = 1)

Shift the mantissa left (or right)

Decrement (increment) the exponent by 1

end do

Applying the normalization procedure to: .000111001110....0010 x 2-62

gives: .111001110........ x 2-65

But we cannot represent an exponent of 65, in trying to normalize the

number we have underflowed our representation.

Applying the normalization procedure to: 1.00111000............x 263

gives: 0.100111..............x 264

This overflows the representation.


63/74

Changing the implied base

So far we have assumed an implied base of 2, that is our floating pointnumbers are of the form:

x = m 2e

If we choose an implied base of 16, then:

x = m 16e

Then:

y = (m.16) .16e-1 (m.24) .16e-1 = m . 16e = x

Thus, every four left shifts of a binary mantissa results in a decrease of 1in a base 16 exponent.

Normalization in this case means shifting the mantissa until there is a 1 in

the first four bits of the mantissa.


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Excess notationRather than representing an exponent in 2s complement form, it turns out to be

more beneficial to represent the exponent in excess notation.

If 7 bits are allocated to the exponent, exponents can be represented in the range of

-64 to +63, that is:

-64


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IEEE notationIEEE

F

loatingP

oint notation is the standard representation in use. There are tworepresentations:

- Single precision.- Double precision.

Both have an implied base of 2.

Single precision:

- 32 bits (23-bit mantissa, 8-bit exponent in excess-127 representation)

Double precision:

- 64 bits (52-bit mantissa, 11-bit exponent in excess-1023 representation)

Fractional mantissa, with an implied binary point at immediate left.

Sign Exponent Mantissa

1 8 or11 23 or52


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Peculiarities of IEEE notationFloating point numbers have to be represented in a normalized form to

maximize the use of available mantissa digits.

In a base-2 representation, this implies that the MSB of the mantissa is

always equal to 1.

If every number is normalized, then the MSB of the mantissa is always 1.

We can do away without storing the MSB.

IEEE notation assumes that all numbers are normalized so that the MSB

of the mantissa is a 1 and does not store this bit.

So the real MSB of a number in the IEEE notation is either a 0 or a 1.

The values of the numbers represented in the IEEE single precision

notation are of the form:

(+,-)1.Mx2(E- 127)

The hidden 1 forms the integer part of the mantissa.Note that excess-127 and excess-1023 (not excess-128 or excess-1024) are used

to represent the exponent.


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Exponent fieldIn the IEEE representation, the exponent is in excess-127 (excess-1023)

notation.The actual exponents represented are:

-126


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Floating point arithmeticAddition:

3.1415x108 +1.19x106 = 3.1415x108 +0.0119x108 = 3.1534x108

Multiplication:

3.1415x108 x1.19x106 = (3.1415x1.19)x10(8+6)

Division:

3.1415x10

8

/1.19x10

6

= (3.1415/1.19)x10

(8-6)

Biased exponent problem:

If a true exponent e is represented in excess-p notation, that is as e+p.

Then consider what happens under multiplication:

a. 10(x+p)*b. 10(y+p) = (a.b). 10(x+p+y+p) = (a.b). 10(x+y+2p)

Representing the result in excess-p notation implies that the exponent

should be x+y+p. Instead it is x+y+2p.

Biases should be handled in floating point arithmetic.


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Floating point arithmetic: ADD/SUB

ruley Choose the number with the smaller exponent.

y Shiftitsmantissa rightuntil the exponents of both the

number

sare eq

u

al.

y Add or subtract themantissas.

y Determine the sign of the result.

y Normalize the resultifnecessary and truncate/round

to the number ofmantissa bits.

Note: Thisdoes not consider the possibilityofoverflow/underflow.


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Floating point arithmetic: MUL ruley Add the exponents.

y Subtract the bias.

yMultiply themantissas and determine the sign of theresult.

y Normalize the result (ifnecessary).

y Truncate/round themantissa of the result.


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Floating point arithmetic: DIV ruley Subtract the exponents

y Add the bias.

yDivide the mantissas and determine the sign of theresult.

y Normalize the resultifnecessary.

y Truncate/round themantissa of the result.

Note: Multiplication anddivision does not require alignment of themantissas the wayaddition andsubtraction does.


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Guard bitsWhile adding two floating point numbers with 24-bit mantissas, we shift

the mantissa of the number with the smaller exponent to the right until

the two exponents are equalized.

This implies that mantissa bits may be lost during the right shift (that is,

bits of precision may be shifted out of the mantissa being shifted).

To prevent this, floating point operations are implemented by keeping

guard bits, that is, extra bits of precision at the least significant end

of the mantissa.

The arithmetic on the mantissas is performed with these extra bits of

precision.

After an arithmetic operation, the guarded mantissas are:

- Normalized (if necessary)

- Converted back by a process called truncation/rounding to a 24-bit

mantissa.


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Truncation/roundingy Straightchopping:

y The guard bits (excess bits of precision) are dropped.

y VonNeumann rounding:y If the guard bits are all 0, they are dropped.

y However,if any bit of the guard bitis a 1, then the LSB of the retained bitis

set to 1.

y Rounding:y If there is a 1 in the MSB of the guard bit then a 1 is added to the LSB of the

retained bits.


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Roundingy Rounding is evidently themost accurate truncation

method.

y However

,

y Rounding requires an addition operation.

y Roundingmay require a renormalization,if the addition operation de-

normalizes the truncated number.

y IEEE uses the roundingmethod.

0.111111100000roundsto 0.111111+0.000001

=1.000000 whichmustbe renormalizedto 0.100000

chapter4 arithmetic

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