Chip-Last Embedded Actives and Passives in Thin Organic Package for 1-110 GHz Multi-Band Applications

Fuhan Liu, Venky Sundaram, Sunghwan Min, Vivek Sridharan, Hunter Chan,

Nitesh Kumbhat, Baik-Woo Lee, Rao Tummala Packaging Research Center, School of Electrical and Computing Engineering, Georgia Institute of Technology, 813 Ferst Drive, Atlanta, GA 30332, USA

Dirk Baars*, Scott Kennedy*, and Sankar Paul* Rogers Corporation, One Technology Drive, Rogers, CT 06263, USA

fliu@ece.gatech.edu, vs24@mail.gatech.edu

Abstract This paper presents for the first time a novel

manufacturing-compatible organic substrate and interconnect technology using ultra-thin chip-last embedded active and passive components for digital, analog, MEMS, RF, microwave and millimeter wave applications. The architecture of the platform consists of a low-CTE thin core and minimum number of thin build up organic dielectric and conductive layers. This organic substrate is based on a new generation of low-loss and thermally-stable thermosetting polymers (RXP-1 and RXP-4). Unlike LCP- and Teflon- based materials, the RXP material system is fully compatible with conventional FR-4 manufacturing processes. Ultra-thin silicon test die (55µm thick) has been embedded in a 60µm deep cavity with a 6-metal layer RXP substrate and a total thickness of 0.22mm. The embedded IC is interconnected to the substrate by ultra-fine pitch Cu-to-Cu bonding with polymer adhesives. This novel interconnection process performed at 180°C, has passed 1,000 thermal shock cycles in reliability testing. Because of manufacturing process simplicity and unparalleled set of benefits, the chip-last technology described in this paper provides the benefits of chip-first without its disadvantages and thus enables highly miniaturized, multi-band, high performance 3D modules by stacking embedded 3D ICs or packages with embedded actives, passives and MEMS devices.

Introduction Ultra miniaturized and low-profile mobile products are

driving the need for embedded active and passive component integration technologies. Two such technologies are currently being pursued by the industry. Both are based on “chip-first” in two versions: 1) embedding by wafer-level fan-out with chip-first concept by US and European companies [1], and 2) embedding in organic substrates by chip-first by Japanese companies [2]. These technologies are based on either the chips being simultaneously mounted on detachable tape, molded by carrier or molding compound, and then interconnected using thin film package and PWB processes or being simultaneously mounted on rigid core surfaces and then interconnected using the package and PWB processes.

A third technology option has been demonstrated to overcome some of the challenges in chip-first technology. This is referred to as Embedded MEMS, Actives and Passives (EMAP) Technology with chip-last (CL) interconnection but with chip-first benefits. As seen in Figure 1, the chip-last

embedded actives and passives (EMAP-CL) technology is targeted at highly integrated systems with multiple 2D and 3D ICs for RF, digital, analog, MEMS and passive devices all in a single package or module. Ultra-thin ICs and passives are embedded in high precision cavity structures on both sides of thin core organic substrates with high I/O density vertical and horizontal interconnections.

Figure 1. Comparison of Flip-Chip, Chip-First and Chip-

Last Interconnections, and Cross-section of EMAP Chip-Last Embedded Actives

The benefits of chip-last embedding are many and include:

1. Module thickness less than 0.5mm with 3D stacked components

2. Ultra thin dielectrics, conductors and vias in an ultra-thin substrate

3. Double-side wiring and components due to through-package-vias

4. Known good substrate and known good die before assembly

5. Repairability after assembly, if necessary 6. Ultra fine-pitch and short pad-to-pad

interconnection in the long run 7. Minimal change to manufacturing infrastructure 8. Shorter time-to-market 9. Flexible testing due to the exposed dies on surface 10. Overcome TCE mismatch reliability due to the use

of ultra thin underfill 11. Precise placement of dies using current assembly

processes and tools

ICThin Core

Build-up Film Cavity

IC

IC

Substrate

Flip‐chip Chip‐Last EMAPChip‐First WL‐Fanout

758978-1-4244-6412-8/10/$26.00 ©2010 IEEE 2010 Electronic Components and Technology Conference

  

  

12. Not limited by panel or wafer size due to the post placement of ICs

13. Allow embedded dies, IPDs and discrete passives with different thicknesses and substrates (Si, GaAs, SiGe, Glass, Ceramic, Laminate) due to the multi-depth cavities

14. Top surface cavity allows MEMS devices; ideal low temperature cavity packaging option for MEMS

15. Easier heat transfer due to the exposed die 16. Embedding of TSV chips & 3D-ICs for high I/O

density 17. Low-K and ULK die embedding with low stress

interconnects This paper presents detailed results from design, materials

and processes, and package structures in three key building block technologies that make up the demonstrator test vehicle: 1) the novel RXP core and build-up dielectric materials, properties, high density wiring and thermo-mechanical reliability studies, 2) 30µm ultra-fine I/O pitch chip-last embedding, and 3) embedded RF filters and high frequency electrical characterization. The paper will conclude with a proof-of-concept demonstration of embedded actives and passives fan-out package in RXP substrates by chip-last embedding.

Chip-last Embedded IC Fan-out Package Architecture The structure of the chip-last embedded IC and passives

module consists of an ultra-thin and low loss organic substrate with high-density multi-layer routing and integrated high precision cavities in the build-up layers. Thinned ICs are embedded in the build-up layer cavities and interconnected by ultra-fine pitch copper-to-copper bonding, as shown in Figure 2. The chip-last method combines the chip-first benefits of ultra-fine I/O pitch and short connection to the IC, and flip-chip benefits of simple substrate-assembly process and supply chain flow. It addresses the chip-first concerns of known good die, yield, chip size limitation, dimensional stability of the laminate core, and disruption to existing supply chain models. Chip-last embedding also allows for pre-testing of substrate and selective site IC assembly for complex modules with embedded passives in the laminate substrate. Although this paper focuses on low loss laminate and build-up dielectrics for high frequency applications, chip-last embedding can also be implemented on FR-4 and lower cost substrate materials.

Figure 2. Scheme of fan-out chip-last embedded IC in a high performance organic substrate. High density wiring is

required for fan-out of fine pitch high I/Os actives.

The core consists of a glass fiber reinforced polymer laminate (100µm thick). Polymer thin dry film dielectric is used for build-up layers on both sides of the core. The top surface of the substrate inside the cavity has fine pitch pads to match the fine pitch I/Os on chip. In addition, ultra-fine copper lines and spaces, blind microvias and through vias are required for fine pitch and high I/O fan-out to BGA on the back side. High precision cavities are formed in the build-up layers on both sides to controlled depths as required for multiple device thickness. The ICs and passive devices are placed into the cavities using precision assembly processes for fine pitch interconnection using Cu, Au, solder or other metals. Gap filling by polymer adhesives under the ICs and around the ICs in the cavity completes the process flow.

Chip-Last EMAP Test Vehicle The first demonstrator test module consisted of six metal

layers in which four metal layers (1+2+1) were ultra-high density wiring substrate and the outside two layers were used for integrated cavities and chip embedding. Passive components such as high Q RF filters were embedded in the four-metal layer substrate. The four-layer substrate was made of a thin core (RXP-1, 100µm thick) and one build up layer on each side (RXP-4, 20µm thick). The thickness of the RXP-4 cavity layer was 60µm. The thickness of the four-layer substrate was 160µm. Fine line lithography and small filled via technologies were optimized for high routing density. Conductors of 10µm lines and spaces, core through vias of 30µm to 50µm diameter, and blind microvias of 25µm to 50µm diameter were fabricated and tested. Ultra-thin silicon test die were placed and interconnected using 30-50µm pitch peripheral Cu microbump interconnects and polymer adhesives. The total thickness of the completed module with embedded chips (55µm thick) was 220µm.

Ultra-Thin and Low Loss Polymer Dielectrics Ceramic packaging has been the dominant platform for

high frequency applications for many decades. Limitations of ceramic substrate in small panel size, low interconnection density, high process temperatures and thick substrate have driven the search for a thin, high performance and low cost organic package for high frequency applications. Although polymers such as LCP and Teflon have attracted recent attention due to their attractive electrical properties, their incompatibility with high volume manufacturing infrastructure has limited their widespread use. The objective of EMAP was to achieve the electrical performance, moisture and thermo-mechanical reliability of ceramic substrates while maintaining low-cost FR-4 process compatibility. The advantages of the EMAP organic substrates are 1) light weight and extremely low profile compared to ceramic packages, 2) low cost, 3) reliable and 4) scalable to large panel processes. Low dielectric constant was targeted for high signal speed, and low loss at GHz frequencies was targeted for RF and high frequency applications.

Two new dielectric materials, RXP-1 and RXP-4 in the RXP material system, were used for embedding high Q RF passives and ICs by chip-last method. RXP-1 is a glass reinforced hydrocarbon polymer high Tg laminate core in the

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thickness range of 50-110µm with low profile copper cladding [3]. These core materials utilize a thermosetting, hydrocarbon-based resin system, smooth ED copper foil for improved loss performance, and flat glass reinforcement to minimize the effect of the glass weave on signal propagation. The laminate material RXP-1 has excellent thermal stability and a Tg of >3000C making it ideal for lead-free solder and other high temperature interconnects. It also has X-Y CTE tailorable in the range of 10-15ppm/°C to reduce the stress on first level interconnects from Si and other ICs. Another advantage of this core laminate is low moisture uptake of <0.1% which is much lower than epoxy-based substrates and comparable to LCP. RXP-4 is a 20µm thick unreinforced build-up film available as free standing film or as resin coated copper (RCF). The advantages of this film are very low RF signal delay and very low RF power loss during signal transmission through the material. The dielectric constant Dk of RXP-4 was below 3 and the dielectric loss tangent tan ( ) was 0.005 over 1-110GHz. A summary of key properties of RXP-1 and RXP-4 is shown in Table 1. The combination of the newly developed RXP-1 and RXP-4 provides a highly reliable, high performance low cost organic platform for wide band applications.

Table 1. Properties of RXP-1 and RXP-4

Property RXP-1 RXP-4

CTE, ppm/0C 13-14 43

Tg (DMA), 0C >300 185

Dk (1~110GHz) 3.4 <3

Df (1~110GHz) <0.006 <0.005

Water Absorption, % <0.1 0.17

UL94 V-0 V-0

Solder Float Pass

(2880C/10sec) Pass

(5x30sec)

Cu Adhesion, pli 3.5-4.0 1.0-1.2

Laser Processable Yes Yes

The dielectric properties of RXP-1 and RXP-4 were characterized from 1GHz to 110GHz [4]. A numerical based extraction method using corner-to-corner probing on a cavity resonator was employed for the measurements. The extracted dielectric constant of RXP-1 was 3.41+/- 0.06 with loss tangent (tanδ < 0.006) up to 110GHz. The extracted dielectric constant of RXP-4 was 2.98+/- 0.05 with loss tangent (tanδ < 0.005) up to 110GHz. As seen in Figure 3, the dielectric constant and dielectric loss tangent were stable over the wide frequency range from 1 GHz to 110GHz. These measurements clearly demonstrate the excellent high frequency properties of RXP materials.

Figure 3. Measured values of Dk and Df for RXP-1 and RXP-4 from 1-110GHz. 

Design Rules and Substrate Routing Capacity Current leading edge area array flip-chip interconnects

have IC I/O pad pitch of 150µm, with roadmaps indicating the need for 100µm pitch in the near future [5]. Consider a high pin count fine pitch chip having 1000 I/Os with pitch of 100µm, and chip size of 10mm x10mm. In order to assemble the chip on substrate, 1,000 pads must be placed in a 10mm x 10mm area on the substrate. The maximum number of pads in the first outer row will be 400. Three rows are required for placing the 1,000 pads. For a pad size of 40µm, the channel width between adjacent pads will be 60µm. If one line is routed through the channel, a line width of 20µm or less is required. In order to route the third row, another layer with blind via interconnects is necessary. However, if the width of the routing line reduced to 12µm, two routing lines can escape through the channel. Three rows can thus be routed in one layer. Reduction of routing layers results in the reduction of materials and process cost, higher throughput and higher yields. Figure 4 shows the calculations and fabricated substrate with 40µm pads and 12µm routing copper lines and spaces for 100µm pitch interconnections.

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Figure 4. Top: Routing calculation of a fine pitch chip (10mmx10mm) having 1,000 I/Os with 100µm pitch,

Bottom: Photo of a fabricated substrate for very fine pitch area array chip. The pad size is 40µm, the pitch is 100µm,

and routing lines are 12µm. More than 1,000 I/Os on the chip can be routed on one re-distribution layer.

High Density Through Hole and Blind Via Interconnects In core and build up layers, through hole and blind via are

employed for interconnection. Through hole interconnects the front side and back side of the core, while blind via interconnects the metal on the build-up layers. Figure 5 shows a photo of thin and flexible four-metal layer RXP-4 on RXP-1 substrate with a total thickness of 160µm.

Figure 5. Photo of thin and flexible four-metal layer RXP-4/RXP-1 substrate. The total thickness is 160µm.

Figure 6 shows the cross section of four-metal layers substrate with the combinations of thin core RXP-1 and RXP-4 build-up layers. The diameter of filled through hole and blind vias are 50µm. This picture was taken after completion of the 2,000 cycles test.

Figure 6. Cross section of combinations of thin core RXP-1 and build-up that passed 2,000 cycles test. The diameter of

filled through hole and blind vias are 50µm.

Table 2 summaries the design rules of the structure of chip-last embedded actives fan-out package.

Table 2. Design Rule for Chip-Last Embedded IC Substrate

Material

Thickness (µm)

L/S (µm)

Via, (µm)

Core RXP-1 100µm 25 40 (Through

Via)

Build-up

RXP-4 20µm 10 25 (Blind

via)

Cavity RXP-4 60µm 50 100 (Blind

via)

Substrate Reliability Assessment Two batches of test vehicles were fabricated for the

thermal reliability test, with one panel from batch A and two panels from batch B. Samples from batch B were fabricated under improved process conditions compared to batch A. Sample #PTV-A-1 had both blind microvias and through holes. Samples #PTV-B-1 and #PTV-B-2 had only blind microvias. These test vehicles were subjected to MSL-3 preconditioning using accelerated conditions of 60°C/60% RH for 40 hours after which the samples were passed through 3x solder reflow with a peak temperature of 260°C according to JSTD020D-01. They were then subjected to thermal shock test at -55°C to +125°C, air- to-air, according to JESD22-A104C. Electrical continuity of the daisy chains was checked every 200 thermal cycles for assessing the reliability. Sample #PTV-A-1 had an additional test at 500 cycles. Before testing, all chains were inspected to find initial opens and near opens. Those vias which were ‘open’ and near open due to processing defects were not considered for the test. A total of 455 sub-chains consisting of 6,975 blind vias and 6,275 through holes in #PTV-A-1, and 238 sub-chains consisting of 5,998 blind-vias in #PTV-B-1 and 240 sub-chains consisting of 6,000 blind vias in #PTV-B-2 were tested.

Figure 7 shows the collected test data from 25µm blind vias on 2 TVs. Each test vehicle has 8 coupons 6,000 blind vias. Each coupon has 750 vias. One via failed on TV-B-1 after 1,000 cycles. One via was open before testing and one via was damaged by handling and five 40µm vias failed after 2,000 cycles on TV-B-2. In total, there was one 25µm via and five 40µm of 11,980 vias that failed during 2,000 thermal

10 mm

Test Chip 10mm x 10mm

Pitch

 100 µm

Max. 100 I/O per row per side

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cycles. Four of the five vias that failed, did so in the same place on TV-B-2 and at the same number of cycles.

Figure 7. Collected test data from 25µm blind vias on 2 TVs.

Figure 8. Small filled blind via Left: Top view, Right Cross section

Figure 9. Cumulative Failure Rate for RXP Substrate

The cumulative failure rate F(N) over 2,000 thermal cycles is illustrated in Figure 9 in the red curve. For comparison, the tested data on epoxy based dielectric film is also illustrated in the black curve. The dotted curve is its Weibull distribution. Figure 9 shows that the low moisture RXP material has very low failure rate compared to the conventional epoxy dielectric.

Embedded Ultra-fine Pitch Actives and Passives

Cavity Formation: High precision cavities were fabricated in the 60µm thick RXP-4 layer by plasma and laser processing. Process details and results from high precision cavity formation with chip-cavity clearance as small as 50µm have been previously reported [6]. For the current test vehicles, laser ablation was selected as the front-up approach to cavity ablation. In addition to single cavities for 3mm x 3mm and 7mm x 7mm ICs, other cavity structures evaluated include neighboring cavities for embedding two 3mm x 3mm ICs, one large cavity for embedding two 3mm x 3mm ICs, and cavities on top and bottom side of the core for embedding two 3mm x 3mm ICs. Figure 10 shows the results of CO2 laser ablated cavities in RXP-4 after laser process, and after cleaning to expose the fine-pitch metal pads inside the cavity. After process optimization, Cu pads of 30-50µm pitch were successfully demonstrated with no damage from the laser cavity process. The cavity substrates were finished with Electroless Ni, Immersion Au (ENIG) plating to protect the copper structures inside and outside the cavity.

Figure 10. Laser Ablated Cavity in RXP-4 (60µm thick) after CO2 Laser Process and after Post-Cleaning.

Ultra-fine Pitch Cu microbump chip–Last Interconnects: A novel low temperature bonding process for Cu microbumps was used to embed thin Si die (55µm thickness) inside the cavities in the RXP substrate. The details of the Cu interconnection method and reliability results have been previously reported [7]. The assembled test vehicle with 30µm pitch Cu interconnections is shown in Figure 11, which also shows the fine pitch pads on the substrate.

Figure 11. Assembled 3mm x 3mm IC on RXP substrate (left) and Closer View of 10µm Spaces between Adjacent

Pads on RXP Substrate (right).

A cross-section of the chip-last embedded IC in ultra-thin RXP substrate with a total thickness less than 300µm is shown in Figure 12. The chip-last embedded ICs (3mm and 7mm chip size) with 30µm and 50µm pitch Cu interconnects

0.00

1.00

2.00

3.00

4.00

5.00

6.00

Resistan

ce (Ohms)

Cycles

25um ViaCoupon 1

Coupon 2

Coupon 3

Coupon 4

Coupon 5

Coupon 6

Coupon 7

Coupon 8

After Laser Ablation After Post Laser Cleaning

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have demonstrated 1000 thermal cycle reliability from -55°C to 125°C.

Figure 12. Demonstrated Chip-Last Embedded Thin IC (55µm thickness) with Cu microbump interconnects

Embedded RF Filters: Lowest volume (1.2mm3) 2.4 GHz bandpass filters with size of 2.2mm x 3.0mm x 0.2mm were integrated in the four-metal layer ultra thin low-loss RXP substrate. Insertion loss of less than 2.2dB, return loss of greater than 15dB at 2.4 GHz and attenuation of greater than 30dB below 2.0 GHz and at 4.7 GHz were measured [8]. Similarly, 5 GHz filters with insertion loss of less than 1.2dB and with rejection better than 30dB were integrated, as shown in Figure 13.

Figure 13. Measured Data from 2.4GHz and 5 GHz Band Pass Filters Embedded in 1+2+1 RXP Substrates

Summary and Conclusions Chip-last embedded actives and passives (CL-EMAP) has

been demonstrated for interconnecting ultra-fine I/O pitch (30-50µm) ICs with chip-first benefits. The chip-last approach goes well beyond leading-edge flip-chip interconnections in both pitch and stand of height and beyond chip-first in ease of manufacturing for testability and yield. The chip last technology is based on advanced materials, processes such as low-loss and low-moisture uptake of RXP dielectric materials, semi-additive plating of 10µm conductors, copper filled through vias and blind vias of 30µm diameter, high precision cavities in build-up layers by laser ablation, and 30µm pitch Cu microbump interconnects with 10-15µm profile interconnected by low temperature polymer adhesive bonding. Thinned Si test chips of 55µm thickness and high quality factor RF filters at 2.4 GHz and 5 GHz were embedded in six-metal layer RXP substrates with a total

module height less than 300µm. The chip-last embedded active and passive module technology described in this paper is expected to lead to highly functional, miniaturized and low cost mixed signal systems without major changes in the manufacturing infrastructure.

Acknowledgments The authors wish to thank the PRC EMAP Consortium

Phase 1 full members: Bosch, Epcos, Infineon, Intel, TI, Sameer, and Draper Labs for their financial support; supply chain partners: Atotech, Endicott Interconnect, DuPont, AT&S, Disco, and Ibiden, for their contributions, and support from Georgia Tech faculty, students and researchers.

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industrial perspective”, i-Micronews, June 2009. http:// www.i-micronews.com

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4. S. Hwang, S. Min, M. Swaminathan, V. Venkatakrishnan, H. Chan, F. Liu, V. Sundaram, S. Kennedy, D. Baars, B. Lacroix, Y. Li, J. Papapolymerou, , “Characterization of Next Generation Thin Low-K and Low-Loss Organic Dielectrics From 1 to 110 GHz.”, IEEE Transactions on Advanced Packaging, 2008.

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6. Baik-Woo Lee, Venky Sundaram, Boyd Wiedenman, Chong K Yoon, Mahadevan Iyer and Rao R Tummala, “Chip-last Embedded Active for System-On-Package (SOP)”, Electronic Components and Technology Conference, Reno, May 2007.

7. N. Kumbhat, M. Raine, G. Mehrotra, A. Choudhury, P. M. Raj, R. Zhang, K. S. Moon, V. Sundaram, G. Meyer-Berg, CP Wong, and Rao Tummala, “Highly-Reliable, 30µm Pitch Copper Interconnects using nano-ACF/NCF”, ECTC 2009.

8. Min, Sunghwan; Hwang, Seunghyun; Chung, Daehyun; Swaminathan, Madhavan; Sridharan, Vivek; Chan, Hunter; Fuhan Liu; Sundaram, Venky; Tummala, Rao R.; “Filter integration in ultra thin organic substrate via 3D stitched capacitor,” Proc Electrical Design of Advanced Packaging & Systems Symposium, Dec. 2009, pp. 1 – 4.

300umThin Core

IC

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