chip-scale thermoelectric energy harvester for room ...m...thermoelectric n-type bismuth telluride...
TRANSCRIPT
Chip-Scale Thermoelectric Energy Harvester for Room
Temperature Applications
A Dissertation Presented
By
Samer A. Haidar
to
The Department of Electrical and Computer Engineering
in partial fulfillment of the requirements
for the degree of
Doctor of Philosophy
in the field of
Electrical Engineering
Northeastern University
Boston, Massachusetts
May 2020
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To my family.
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Abstract
Thermoelectric energy harvesters have emerged as a solution for power generation by
converting wasted heat directly into electrical energy through the Seebeck effect. As a
result, they play a critical role in the development of the Internet-of-Things (IoT) wireless
devices and sensors. High efficiency thermoelectric (TE) materials are important for
power generation and help reduce our dependence on fossil fuels and reduce greenhouse
gas emissions. Recent advances in fabrication technology have enabled these devices to
be constructed at the chip-scale level promoting the use with low power devices such as
wireless sensors and wearable applications.
Thermoelectric n-type bismuth telluride (Bi2Te3) films and p-type antimony telluride
(Sb2Te3) films are grown on SiO2/Si substrates using RF magnetron sputtering via
physical vapor deposition (PVD) process. The objective of this dissertation is to study the
crystal structure, grain size and elemental composition for 1µm and 10µm thermoelectric
films deposited using different deposition conditions and using various heat treatment
recipes. The thermoelectric properties of the films are found to be strongly dependent on
the sputtering method and deposition temperature that lead to the design and fabrication
of micro-scale thermoelectric energy generator (µTEG) based on the vertical
architecture, which is geared towards IoT and wearable applications close to room
temperature.
It is observed that high temperature single-target sputtered depositions of n-type Bi2Te3
films result in a tellurium Te-deficient of stoichiometric films (Bi:Te = 2:3) due to the
evaporation of tellurium. Two-target co-sputtered depositions using Bi2Te3 and Te targets
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at room temperature and subsequent anneal at +250°C yielded a 10µm n-type film with -
102µV/K for the Seebeck coefficient and 0.7 mW/K2.m for the power factor. Similarly,
prepared p-type Sb2Te3 film but using a single sputtering target yielded +110µV/K and
1.3 mW/K2.m for their Seebeck coefficient and power factor respectively. The design,
fabrication and characterization of the proposed vertical µTEG using separate n-type and
p-type wafers is demonstrated. Device power output as a function of the temperature
difference measured as high as 1 mW for the vertical μTEG with ~13.8 mm2 footprint
and device ΔT of ~7.5 K.
We also introduce a second-generation µTEG based on patented pyramid architecture to
overcome limitations of the vertical architecture such as thermal resistance and
manufacturing constraints. In the pyramid design, the thermoelectric elements are
deposited along a polyimide slope allowing more than 20µm of leg length for film
depositions under 5µm thick. In this architecture, the heat flows at a slight angle
compared to the top-down vertical architecture allowing for longer effective leg length
and higher output performance. We present fabrication flow of the second-generation
architecture and identify future age-related reliability stress test experiments post
characterization to assess device performance under field conditions such as high
temperature and humidity. Mechanical cross-sectioning Scanning Electron Microscopy
(SEM) and Energy Dispersive X-ray (EDX) analyses will be used for device
enhancements to achieve the desired power output performance.
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Acknowledgments
This dissertation could not be completed without the guidance and support of many
friends and colleagues who made this work possible. First, I would like to express my
gratitude to my advisor Professor Nian Sun for his support and encouragement during the
past five years. This dissertation could not be finished without his support especially
during time critical milestones. He made difficult things look easy and this is very
important for all part-time students. I still remember when we first met and discovered
his openness towards research and especially his enthusiasm to work with innovative
companies in the industry. He gave me the freedom to work on what interested me and
encouraged me throughout the research.
I’m thankful to my committee members, Dr. Baoxing Chen from Analog Devices Inc.
for all his guidance and support throughout the research, Professor Hui Fang and
Professor Yong-bin Kim from Northeastern University for their support and for their time
to review my dissertation. I greatly appreciate their efforts and feedback.
I would also thank my colleagues at Analog Devices Inc. very much specifically, Dr.
Nigel J. Coburn, Dr. Jane E. Cornett, Dr. Jean-Jacques Hajjar, Dr. Kevin Lukas, Dr.
Colm Glynn, Daniel McDaid, Arnaud Sow and my colleagues at Stanford university and
Northeastern university, Dr. Marc T. Dunham (Stanford), Dr. Yuan Gao (Northeastern,
Winchester Technologies) and Yifan He (Northeastern) in Professor Sun’s group. I
appreciate everything they’ve done for me to make this research work possible. Special
thanks to my friend James Griffin who gave me my first full-time job at Analog Devices
Inc. and believed in me.
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I also like to thank the entire product analysis group at Analog Devices Inc. for all the
support during the past five years. This group is like family and I thank everyone for all
the help.
I would like to show my deep gratitude to mom and dad for their unconditional love and
support. Finally, I would like to show my very special thanks and profound love and
appreciation to my dear wife who always supported and encouraged me to finish this
dissertation work while raising a beautiful family. I owe all my success to her and my
parents and I’m eternally grateful.
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List of Publications
• Chip-Scale Thermal Energy Harvester Using Bi2Te3, Jane Cornett, Bill Lane, Marc
Dunham, Mehdi Asheghi, Kenneth Goodson, Yuan Gao, Nian Sun, and Baoxing
Chen, IECON 2015 - Yokohama 41st Annual Conference of the IEEE Industrial
Electronics Society.
• Fabrication and Characterization of Bi2Te3-Based Chip-Scale Thermoelectric
Energy Harvesting Devices, Jane Cornett, Samer Haidar, Helen Berney, Pat
McGuinness, Bill Lane, Yuan Gao, Yifan He, Nian Sun, Marc Dunham, Mehdi
Asheghi, Ken Goodson, Yi Yuan and Khalil Najafi, Journal of Electronic Materials,
Vol. 46, No. 5, 2017.
• Experimental Characterization of Microfabricated Thermoelectric Energy
Harvesters for Smart Sensor and Wearable Applications, Marc T. Dunham, Michael
T. Barako, Jane E. Cornett, Yuan Gao, Samer Haidar, Nian Sun, Mehdi Asheghi,
Baoxing Chen, and Kenneth E. Goodson, Adv. Mater. Technol. 2018, 1700383.
• Deposition and Fabrication of Sputtered Bismuth Telluride and Antimony
Telluride for Microscale Thermoelectric Energy Harvesters, Samer A. Haidar, Yuan
Gao, Yifan He, Jane E. Cornett, Baoxing Chen, Nigel J. Coburn, Colm Glynn , Marc
T. Dunham, Kenneth E. Goodson and Nian Sun, Pending acceptance in Thin Solid
Films, 2020.
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Table of Contents
Abstract ........................................................................................................................................... 3
Acknowledgments .......................................................................................................................... 5
List of Publications ........................................................................................................................ 7
Table of Contents ........................................................................................................................... 8
List of Figures ............................................................................................................................... 11
List of Tables ................................................................................................................................ 16
Nomenclature ............................................................................................................................... 17
Chapter 1. Introduction .......................................................................................................... 18
1.1 Background .................................................................................................................... 18
1.2 Thermoelectric Effect .................................................................................................... 20
1.2.1 Seebeck Effect ........................................................................................................... 20
1.2.2 Peltier Effect .............................................................................................................. 22
1.2.3 Thomson Effect .......................................................................................................... 23
1.2.4 The Kelvin Relationships ........................................................................................... 23
1.3 Thermoelectric Materials ............................................................................................... 24
1.3.1 Bismuth Telluride ...................................................................................................... 26
1.3.2 Antimony Telluride .................................................................................................... 27
1.4 Thermoelectric Transport Properties ............................................................................. 27
1.4.1 Seebeck Coefficient ................................................................................................... 28
1.4.2 Electrical Conductivity .............................................................................................. 28
1.4.3 Thermal Conductivity ................................................................................................ 30
1.4.4 Figure of Merit (ZT) .................................................................................................. 31
1.5 Thin Film Material ......................................................................................................... 32
1.6 Applications ................................................................................................................... 33
Chapter 2. Material Deposition and Optimization ................................................................... 34
2.1 Background .................................................................................................................... 34
2.1.1 Sputtering ................................................................................................................... 35
2.1.2 Thermal Evaporation.................................................................................................. 36
2.1.3 Molecular Beam Epitaxy ........................................................................................... 37
2.1.4 Chemical Vapor Deposition ....................................................................................... 38
2.2 Optimization Methods ................................................................................................... 39
2.2.1 Doping........................................................................................................................ 39
9
2.2.2 Co-Sputtering ............................................................................................................. 39
2.2.3 Alloying ..................................................................................................................... 40
2.2.4 Nanomaterials ............................................................................................................ 40
2.2.5 Grain Boundaries ....................................................................................................... 41
2.3 Annealing ....................................................................................................................... 41
Chapter 3. Thermoelectric Film Depositions – Experimental Procedure............................... 43
3.1 Background .................................................................................................................... 44
3.2 Sputtering of Thin Films ................................................................................................ 46
3.3 X-ray Diffraction ........................................................................................................... 47
3.3.1 Bragg’s Law ............................................................................................................... 47
3.4 Experimental Details ...................................................................................................... 49
3.4.1 Seebeck and Hall Measurements ............................................................................... 52
3.5 Thin-Film Deposition and Characterization .................................................................. 53
3.5.1 High Temperature Sputtering of Bi2Te3 and Sb2Te3 Films ........................................ 53
3.5.1.1 Single Sputtering of 1µm Bi2Te3 Films ..................................................................... 53
3.5.1.2 Co-sputtering of 1µm Bi2Te3 Films @ 60W .............................................................. 58
3.5.1.3 Co-Sputtering of 1µm Bi2Te3 Films @ 90W ............................................................. 60
3.5.1.4 Co-Sputtering of 1µm Bi2Te3 Films – Vary Bi2Te3 Power ........................................ 63
3.5.1.5 Co-Sputtering of 1µm Bi2Te3 Films – Vary Temperature ......................................... 66
3.5.2 Summary of High Temperature Deposition of 1µm Bi2Te3 Films............................. 68
3.5.3 Sputtering of 1µm Sb2Te3 Films ................................................................................ 69
3.5.4 Room Temperature Sputtering and Annealing of Films ............................................ 71
3.6 Thin Film Summary ....................................................................................................... 75
Chapter 4. Fabrication and Characterization of Thermoelectric Energy Harvesting Devices
....................................................................................................................................................... 76
4.1 Fabrication of TEG Device – Vertical Architecture ...................................................... 76
4.2 Device Performance ....................................................................................................... 83
4.3 Analysis of Bond Interface ............................................................................................ 86
4.3.1 SEM Analysis and Mechanical Cross-Section ........................................................... 86
4.4 Summary of Vertical TEG ............................................................................................. 88
Chapter 5. Manufacturing Perspective of Second-Generation TE Devices and Conclusion 89
5.1 Fabrication of TEG Device – Pyramid Architecture ...................................................... 89
5.2 Process flow of the 2-Pyramid Architecture .................................................................. 91
5.3 Conclusion and Future Work ......................................................................................... 92
5.3.1 Future Work ............................................................................................................... 94
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5.3.1.1 Solder Heat Resistance............................................................................................... 94
5.3.1.2 Temperature Cycling.................................................................................................. 94
5.3.1.3 Unbiased Highly Accelerated Stress Test .................................................................. 95
5.3.1.4 Autoclave ................................................................................................................... 95
Appendix A. Fabrication and Characterization of Bi2Te3-Based Chip-Scale Thermoelectric
Energy Harvesting Devices ......................................................................................................... 96
Authors ....................................................................................................................................... 96
A.1. Introduction ........................................................................................................................ 96
A.2. Methods .............................................................................................................................. 97
A.3. Results: .............................................................................................................................. 99
A.4. Conclusion ....................................................................................................................... 101
A.5. References ........................................................................................................................ 101
Appendix B. Experimental Characterization of Microfabricated Thermoelectric Energy
Harvesters for Smart Sensor and Wearable Applications ..................................................... 102
Authors ..................................................................................................................................... 102
B.1. Introduction ...................................................................................................................... 102
B.2. Design of Microfabricated TEGs: .................................................................................... 104
B.3. μTEG Fabrication ............................................................................................................. 107
B.4. Device Characterization ................................................................................................... 110
B.4.1. Infrared Microscopy ...................................................................................................... 110
B.4.2. Thermal Resistance and Structural Imaging ................................................................. 118
B.5. Determination of material and device properties ............................................................ 120
B.5.1. Thermoelectric material thermal conductivity .............................................................. 120
B.5.2. Thermoelement/interconnect electrical contact resistance ............................................ 121
B.5.3. Material Seebeck coefficient and load power modeling ............................................... 124
B.5.3. Device ZT from thermal efficiency ............................................................................... 125
B.6. Summary and Concluding Remarks ................................................................................. 129
B.7. Acknowledgements .......................................................................................................... 129
B.8. Nomenclature ................................................................................................................... 130
B.9. References ........................................................................................................................ 131
Bibliography ............................................................................................................................... 133
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List of Figures
Figure 1.1: Thermocouple schematic. If the junctions of A and B are held at different
temperatures, an open circuit voltage, V is created 9 .........................................................21
Figure 1.2: Demonstration of thermoelectricity using the Seebeck effect. ........................21
Figure 1.3: Demonstration of thermoelectricity using the Peltier effect. ..........................22
Figure 1.4: Schematic showing dependence of electrical conductivity,
Seebeck coefficient, and power factor on the charge carrier concentration 9. ...................25
Figure 1.5: Figure of merit ZT of common bulk materials versus temperature 12. ............26
Figure 1.6: Crystal structure of Bi2Te3. Blue atoms are Bismuth (Bi),
and pink atoms are Tellirum (Te) 12. ..................................................................................27
Figure 1.7: Seebeck coefficient (α), electrical conductivity (), thermal conductivity (),
power factor (α) and figure-of-merit (ZT) as a function of the carrier concentration 20
............................................................................................................................................29
Figure 1.8: Plot of figure-of-merit (ZT) as function of temperature (K) for (a) n-type
thermoelectric materials and (b) p-type thermoelectric thermoelectric materials 21. .........32
Figure 1.9: (a) Microplet Thermogenerator TPG device, (b) High magnification
Scanning Electron Microscope (SEM) image of internal device post device uncapping
and (c) EDX layered image showing the active thermoelectric material are Bi2Te3 and
Sb2Te3. ...............................................................................................................................33
Figure 2.1: Typical representation of thermoelectric deposition deposition methods 38. ..35
Figure 2.2: Schematic of the Sputtering deposition deposition process 39. .......................36
Figure 2.3: Schematic of an evaporation deposition system 40. .........................................37
Figure 2.4: large grain with less grain boundaries (left image) verses small grain structure
with more grain boundaries (right image)47. ......................................................................41
Figure 3.1: Pysical Vapor Depostion system, manufactured by AJA International. .........46
Figure 3.2: Philips X’Pert materials X-ray Diffraction (XRD) Tool 57. ............................47
Figure 3.3: Concept of Bragg’s diffraction law 58. ............................................................48
Figure 3.4: Schematic for single target sputtering. The same method is applicable to p-
type film. ............................................................................................................................49
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Figure 3.5: Schematic for two target co-sputtering. A separate tellirum (Te) target is
added for co-sputtering deposition.....................................................................................50
Figure 3.6: Four probe measurement technique for Seebeck coefficient in an enclosed
case. ....................................................................................................................................51
Figure 3.7: Representative graph for obtaining Seebeck coefficient and Hall
measurements. ....................................................................................................................52
Figure 3.8: Cross-section image of the single target sputtered films. ................................53
Figure 3.9: SEM image of Bi2Te3 films deposited using single-sputtered target at:
(a) 25°C; (b) 150°C; (c) 200°C; (d) 250°C; (e) 300°C; and (f) 350°C. .............................54
Figure 3.10: XRD spectra taken from bismuth telluride films deposited at temperatures
between 25°C and 350°C. Bi2Te3 peaks are labeled, with vertical dashed lines marking
the locations of Bi2Te3 (0 0 3) and (0 0 9) peaks ...............................................................55
Figure 3.11: Elemental composition (EDX) atomic ratio of Bi to Te for single-target
sputtered n-type films, as a function of deposition temperature (°C). ...............................56
Figure 3.12: (a) Carrier concentration and mobility; (b) conductivity and Seebeck
Coefficient and (c) Power factor of n-type single sputtered films as a function of the
deposition temperature. ......................................................................................................57
Figure 3.13: SEM image of films deposited at 150°C by (a) single sputtering, (b) co-
sputtering with 10W power to Te target, (c) 15W power to Te target and (d) 20W power
to Te target. ........................................................................................................................58
Figure 3.14: XRD spectra taken for co-sputtered Bi2Te3 deposited with a range of Te
powers. Bi2Te3 peaks are labeled, with vertical dashed lines marking (0 0 l) family peaks.
The asterisks indicate secondary peaks attributed to a separate Te phase; ........................59
Figure 3.15: Atomic ratio Bi:Te ratio as a function of Te sputtering power for co-
sputtered films. ...................................................................................................................60
Figure 3.16: SEM image of films deposited at 150°C using 90W of power for Bi2Te3 by
(a) single sputtering, (b) co-sputtering with 10W to Te target, (c) 15W Te and (d) 20W
Te. ......................................................................................................................................61
Figure 3.17: Cross-section SEM image for (a) single sputtering film, (b) co-sputtered
with 10W of Te, (c) co-sputtered with 15W of Te and (d) co-sputtered with 20W of Te. 61
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Figure 3.18: (a) XRD spectra taken for co-sputtered Bi2Te3 films deposited at 90W with a
range of Te powers. (b) Atomic ratio Bi:Te ratio as a function of the Te sputtering
power..................................................................................................................................62
Figure 3.19: (a) Carrier concentration and mobility; (b) conductivity and Seebeck
Coefficient and (c) Power factor of co-sputtered films as a function of Te power. ..........63
Figure 3.20: SEM image of films deposited at 150°C with 10W Te by (a) co-sputtering
with 65W power to Bi2Te3 target, (b)75W, (c) 80W, and (d) 85W. .................................64
Figure 3.21: Cross- section SEM image of (a) 65W Bi2Te3, .............................................64
Figure 3.22: (a) XRD spectra taken for co-sputtered films deposited with a range of
Bi2Te3 powers. (b) Atomic ratio Bi:Te ratio as a function of Bi2Te3 sputtering power. ...65
Figure 3.23 (a) Carrier concentration and mobility; (b) conductivity and Seebeck
Coefficient and ...................................................................................................................65
Figure 3.24: SEM images of co-sputtered films deposited with 90W of Bi2Te3 and 10W
of Te at various temperatures (a) 25°C, (b) 150°C, (c) 200°C, and (d) 250°C. .................66
Figure 3.25: Cross- section SEM image of films deposited at various temperatures (a)
25°C, (b) 150°C, (c) 200°C, and (d) 250°C. ......................................................................66
Figure 3.26: (a) XRD spectra taken for co-sputtered films deposited with a fixed Bi2Te3
power and fixed Te power while varying temperature. (b) Atomic ratio Bi:Te ratio as a
function of deposition temperature using fixed Bi2Te3 powers and fixed Te power. ........67
Figure 3.27: Transport properties using fixed Bi2Te3 power and fixed Te power while
varying temperature (a) Carrier concentration and mobility; (b) conductivity and Seebeck
Coefficient and ...................................................................................................................68
Figure 3.28: SEM of p-type deposited at (a) room temperature and
150°C by (b) single sputtering and (c) co-sputtering. ........................................................69
Figure 3.29: XRD spectra taken for single target sputtered and co-sputtered Sb2Te3
deposited at 150°C. ............................................................................................................70
Figure 3.30: Annealed n-type film for 30min @250°C with 90min ramp up/ramp down,
30 PSI .................................................................................................................................71
Figure 3.31: Annealed n-type film for 30 mins @250°C with 30min ramp up/ramp
down, 50 PSI. .....................................................................................................................72
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Figure 3.32: Annealed n-type film for 30 mins @300°C with 2.5hrs ramp up/ramp down,
30 PSI. ................................................................................................................................72
Figure 3.33: Annealed n-type film for 14 hrs @225°C with 80min ramp up/ramp down,
30 PSI. ................................................................................................................................72
Figure 3.34: SEM image of room temp co-sputtered 10µm n-type films using: (a) no
anneal; (b) 30 mins anneal; (c) 1hr anneal; and (d) 2hr anneal. ........................................74
Figure 4.1: (a) SEM image of the completed TEG device after removal of the top die; (b)
Higher magnification SEM image of the individual thermoelectric legs connected in
series. (c) Layout schematic for a typical ~12mm2 vertical TEG device, showing the
metallic interconnects in orange and thermoelectric legs in purple. ..................................77
Figure 4.2: Schematic of vertical structure process flow (a) Vertical structure after Au
electroplating. (b) Double layer photo-resist (c) Deposition of active material. (d) lift-off
............................................................................................................................................78
Figure 4.3: optical image of the completed p-type wafer. .................................................80
Figure 4.4: Higher magnification SEM image of the p-type wafer. .................................80
Figure 4.5: (a) Completed n-type and p-type wafer prior to dicing, (b) Vertical device
architecture showing the individual diced die and (c) Completed die post bonding. ........81
Figure 4.6: Vertical device architecture showing (a) n-type and p-type legs are
electrically in series and (b) thermally in parallel. .............................................................82
Figure 4.7: (a) 3D X-ray image of the TEG device, (b) optical image of the TEG device.
............................................................................................................................................83
Figure 4.8: Thernal QFI image showing the ΔT drop across the TEG device. .................84
Figure 4.9: Device performance data collected for a single TEG: (a) load voltage as a
function of current and (b) power out as a function of load resistance for several
magnitudes of temperature gradient across device. Maximum power as a function of
temperature gradient is shown in (c). .................................................................................85
Figure 4.10: (a) SEM image of the TEG device post removal of top cap wafer and (b)
Higher manginfation SEM of the highlighted thermocoupe legs. .....................................86
Figure 4.11: (a) Cross-section SEM imeg of the bond interface post bond, (b) SEM image
of n-type leg including material thickness and (c) Higher magnification of the euteic bond
interface..............................................................................................................................87
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Figure 4.12: EDX map of the bond interface of the n-type leg. .......................................88
Figure 5.1: Schematic cross-section image of the patented pyramid structure 62. ............90
Figure 5.2: (a) High magnification cross-secton SEM image with labels of the individual
legs of the TEG device. (b) slope of the active material ....................................................90
Figure 5.3: Process flow for the 2-pyramid structure 62.....................................................91
Figure 5.4: Representative temperature profile for the thermal cycle condition 64. ..........95
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List of Tables
Table 3.1: Chip-scale thermoelectric material in the literatures based on Bi2Te3 and
Sb2Te3. ...............................................................................................................................45
Table 3.2: Thermoelectric, deposition of 10µm n-type and p-type films plus anneal.
Resistivity (ρ), Seebeck (S), Power Factor (PF), Carrier Concentration (CC), Mobility
(μ). ......................................................................................................................................74
Table 4.1: Measured properties for thermoelectric materials and interconnect. ................83
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Nomenclature
PF Thermoelectric power factor (mW/K2.m)
S Seebeck coefficient (μV/K)
T Temperature
ΔT Temperature gradient
ZT Thermoelectric material figure of merit
ρ Electrical resistivity (Ω-m)
Electrical conductivity (S/m)
Thermal conductivity (W/k.m)
TEG Thermoelectric Generator
μTEG Microscale Thermoelectric Generator
CC Carrier Concentration (cm-3)
μ Mobility (cm2 /v.s)
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Chapter 1. Introduction
As the demand for power increases around the globe, manufacturers and consumers
everywhere continue to look for alternative sources of clean and sustainable energy 1. In
1821 Thomas J. Seebeck discovered that a circuit made from two dissimilar metals with
junctions at different temperatures produce an electric voltage 2. A decade later, Jean
Charles Peltier learned that an electric potential creates a temperature difference at the
junction of two dissimilar metals causing heat to be either absorbed or emitted at the
junction of the materials 3.
1.1 Background
This direct conversion of temperature differences into an electric potential and vice versa
is known as the thermoelectric effect and can be used to either generate electricity
(Seebeck effect) or act as temperature controller (Peltier Effect). As the semiconductor
technology shown significant advancement in recent years, thermoelectric devices have
become more feasible. Thermoelectric generators (TEG) have emerged as a solution for
power generation through thermal energy harvesting of waste heat 1,4. They utilize the
Seebeck effect by converting a thermal gradient from external, otherwise wasted sources
of heat into an electric potential. The application of thermoelectric material for supplying
wireless smart sensors and devices, offers significant advantages to the development
of the internet-of-things (IoT) market and wearable applications 5,6. However, for
thermoelectric devices to excel in this space, their efficiency must be increased. The
efficiency is achieved by enhancing the thermal and electrical transport properties of the
materials. The performance of thermoelectric materials can be evaluated using the
19
dimensionless figure of merit, ZT, or power factor, PF. The figure of merit is defined as:
ZT = (S 2) where S (V/K) is the Seebeck coefficient, a measure of a generated
thermoelectric voltage in response to a temperature gradient in the material, (S/m) is
the material’s electrical conductivity, T (K) is the absolute temperature and (W/K·m) is
the thermal conductivity. The power factor PF (W/K2.m) is the product of the Seebeck
coefficient and the electrical conductivity: PF= S 2. Enhancing the value of ZT depends
on a bunch of factors including the material’s structure, the charge carrier concentration,
and the phonon behavior 7,8.
The objective of this dissertation is outlined in 5 chapters. Chapter 1 offers an
introduction to the thermoelectric phenomena, materials and relevant thermoelectric
transport properties and applications . Chapter 2 discusses material deposition methods
and optimization techniques used throughout the literature. Chapter 3 provides details on
the crystal orientation, crystal structure, grain size, composition ratio and temperature
effects on the thermoelectric properties for different deposition conditions and using
various heat treatment recipes. A review of an optimum deposition process for 1µm and
10µm Bi2Te3 and Sb2Te3 thin-films is included. Chapter 4 presents the design, fabrication
process flow and characterization of 10µm thermoelectric Bi2Te3 and Sb2Te3 thin film
device for micro-scale thermoelectric energy generator (µTEG) using the vertical
architecture. Chapter 5 focuses on the fabrication of a novel chip-scale commercial TEG
device using the pyramid architecture to optimize the overall performance of the device
by increasing the effective leg length and thermal resistance. It also concludes the work
and provides an overview of future work such as reliability stress testing under field
conditions such as high temperature and high humidity.
20
1.2 Thermoelectric Effect
The thermoelectric effects involve the process by which wasted heat is transformed into
electric potential or vice versa. The thermoelectric effect encompasses four separate
effects:
1.2.1 Seebeck Effect
The Seebeck effect is a phenomenon in which a temperature difference of two dissimilar
metals produce an electric voltage 2. Thomas J. Seebeck discovered this phenomenon in
1821. Figure 1.1 references a thermocouple schematic in which a circuit formed from two
dissimilar metals, a and b are connected electrically in series. He found that the voltage
produced at the junction is given by 9,
( )21 TTSV ab −= 1.1
TSV ab= 1.2
Where (T1 – T2) is the temperature gradient, T and abS is the differential Seebeck
coefficient between materials a and b, which is usually measured in volts per kelvin
( V/K ). The sign of S is positive if the electromotive force (emf) causes a current flow
in a clockwise direction around the circuit.
21
Figure 1.1: Thermocouple schematic. If the junctions of A and B are held at different
temperatures, an open circuit voltage, V is created 9
Figure 1.2 shows a demonstration on how the thermoelectric Seebeck effect works. When
heat is applied to the surface, the majority of the charged carriers (electrons and holes)
will flow from the hot side to the cold side generating a voltage drop across the device.
Figure 1.2: Demonstration of thermoelectricity using the Seebeck effect.
22
1.2.2 Peltier Effect
The Peltier effect is a phenomenon in which a potential difference applied across a
thermocouple causes a temperature difference at the junction of two dissimilar metals 3.
If the reverse situation is considered in Figure 1.1, an external potential applied across C
and D, causes a rate of heating q to occur at one junction between material a and b and
a rate of cooling - q to occur at the other junction. The amount of heat q absorbed at
the junction is given by 9,
( )Iq ba −= 1.3
Where a and b are the Peltier coefficients of material a and b. As shown in Figure 1.3,
the Peltier effect has a hot and cold side to produce a thermoelectric cooling device such
as refrigeration.
Figure 1.3: Demonstration of thermoelectricity using the Peltier effect.
23
1.2.3 Thomson Effect
The Thomson effect relates to the emission or absorption of heat q by a single current
carrying conductor exposed to a temperature difference T . The Thomson coefficient
, measured in volts per kelvin (V/K) is given by 9:
TI
q
=
. 1.4
Where q is the rate of heating or cooling and T is the temperature gradient.
1.2.4 The Kelvin Relationships
The above thermoelectric effects are related by the Kelvin relationships, which are given
by 9,10,
TS abab /= 1.4
and
TdT
dS baab −= 1.5
These relationships can be derived using irreversible thermodynamics and their validity has been
proven in thermoelectric materials and their related applications 9.
24
1.3 Thermoelectric Materials
The material used in thermoelectric devices should act as a good conductor of electricity
in order to generate the current flow, hence one of the key parameters that is used in the
classification of thermoelectric materials is the electrical conductivity ( ). As shown in
Figure 1.4, the electrical conductivity increases with an increase in charge carrier
concentration while the Seebeck coefficient decreases. The power factor (PF), the
product of the Seebeck coefficient and the electrical conductivity, is maximized at when
the carrier concentration n is between n= 1x1019/ cm3 and n= 1x1021 /cm3.
Since metals and insulators have a high and low electrical conductivity respectively,
semiconductor materials, being in the middle are well suited for thermoelectric
applications 7,9,11. Most semiconductors exhibit thermoelectricity by optimizing their
thermoelectric properties. A more meaningful measure for performance is the
dimensionless figure of merit, ZT where T is the absolute temperature. Normally the
semiconductor materials have a high carrier mobility and middle-range of carrier
concentration which signifies their ZT. Metals on the other hand have a high-range of
carrier concentration, which translates into a higher electrical conductivity but a lower
Seebeck coefficient as shown in Figure 4. Electronic thermal conductivity of metals also
increases with a temperature increase due to the high electron carrier concentration.
Hence the figure-of-merit will likely decrease above n=1x1021 3/ cm giving preference for
semiconductor materials to be used in thermometric applications.
25
Figure 1.4: Schematic showing dependence of electrical conductivity,
Seebeck coefficient, and power factor on the charge carrier concentration 9.
Commonly used thermoelectric materials are divided into different groups depending on
their performance per the temperature range as seen in Figure 1.5. Alloys such as
Bismuth Telluride (Bi2Te3) and Antimony Telluride (Sb2Te3) are reflected in this work
due to ability to work with a low temperature range under 150˚C. Lead based alloys such
as PbTe are used with an intermediate or middle temperature range (150˚C -500˚C).
Silicon germanium SiGe has a large bandgap and can operate at a much higher
temperature up to 1000 °C with application mainly in space missions 9.
26
Figure 1.5: Figure of merit ZT of common bulk materials versus temperature 12.
1.3.1 Bismuth Telluride
Bismuth Telluride (Bi2Te3) is an alloy of two metallic elements (bismuth and tellurium).
It is a narrow-gap semiconductor known as the best available thermoelastic material for
applications near room temperature. Bi2Te3 crystalizes in a layer structure with
rhombohedral-hexagonal symmetry as shown in Figure 1.6, with a space group R3m and
the lattice is stacked along the c-axis in a repeated sequence of Te-Bi-Te-Bi-Te 12.
Bismuth Telluride can be doped as either n-type material or p-type material and has been
extensively used in the construction of thermoelectric devices. It has a high Seebeck
coefficient in addition to low in-plane thermal conductivity However, one must realize
that Seebeck coefficient and electrical conductivity have a tradeoff: a higher Seebeck
coefficient results in decreased carrier concentration and decreased electrical
conductivity.
27
Figure 1.6: Crystal structure of Bi2Te3. Blue atoms are Bismuth (Bi),
and pink atoms are Tellurium (Te) 12.
1.3.2 Antimony Telluride
Similar to bismuth telluride, antimony telluride (Sb2Te3) is a p-type narrow-gap
semiconductor that possess a rhombohedral crystal structure with five covalently bonded
atoms (Te-Sb-Te-Sb-Te), i.e. one formula unit, per unit cell belonging to the space group
D5 3d (R3m) 13,14. The composition of Sb2Te3 can be manipulated to maximize the figure
of merit with optimal properties perpendicular to the c-axis are S= 83 μV/K, and κ =1.62
W/m-K, producing ZT=0.20 at 67% of Te 15,16.
1.4 Thermoelectric Transport Properties
Common thermoelectric properties include the Seebeck coefficient, electrical
conductivity, thermal conductivity. All of these properties contribute to the dimensionless
figure of merit, ZT.
28
1.4.1 Seebeck Coefficient
The Seebeck coefficient of a material is defined as the thermoelectric voltage produced by
a temperature difference across the material end. It is measured in volts per kelvin (V/K).
The sign of the Seebeck coefficient is dependent on the carrier charge. If the thermopower
is produced by electrons, the coefficient sign in negative. Similarly, a positive coefficient
is produced by holes17. The Seebeck coefficient can also be equated using the Mott’s
formula for a metal or degenerate-semiconductor with a parabolic band 18.
FEE
B
dE
Ed
e
TkS
=
−=
)](ln[
3
22 1.6
where, Bk is the Boltzmann constant, e is the electron charge, and T is the temperature.
The Seebeck coefficient is inversely proportional to the charge carrier concentration. This
interrelationship can be seen in another version of the Mott formula 19:
3/2
2
22
3*
3
8
=
nTm
eh
kS B
1.7
Where n is the carrier concentration, h is planks constant and *m is the effective mass.
1.4.2 Electrical Conductivity
Another key factor that influences the figure of merit ZT is the electrical conductivity .
It is a property of the material’s ability to conduct electricity via electron or holes or both.
The electrical conductivity (σ) and electrical resistivity (ρ) are related to n through the
carrier mobility µ:
29
σ = 1/ρ = neµ 1.8
Where n is the charge carrier concentration per unit volume, e is the electronic charge,
and µ is the carrier mobility. It is found that the charge carrier and mobility are functions
of temperature through resistivity and Hall measurements 1,7. Furthermore, it can be
seen from equation 1.8 that the electrical conductivity is a reflection of the charge
carrier concentration n. Figure 1.7 shows the compromise between the large Seebeck
coefficient (α) and high electrical conductivity in semiconductor materials that must be
maintained to maximize the figure of merit ZT. It is observed that the electrical
conductivity increases with increase in carrier concentration and the power factor for the
thermoelectric materials maximizes between n= 1x1019/ cm3 and n= 1x1021 cm3 20.
Figure 1.7: Seebeck coefficient (α), electrical conductivity (), thermal conductivity (),
power factor (α) and figure-of-merit (ZT) as a function of the carrier concentration 20
30
1.4.3 Thermal Conductivity
Thermal conductivity of a material is the ability to transfer heat under a temperature
gradient either through charge carriers, vibration of lattice (phonon) or other excitation
1,17 . The thermal conductivity of a semiconductor thermoelectric material consists of two
main components: the lattice (phonon) component lattice and the charge carrier
component carrier. The sum of the two conductivities corresponds to the total thermal
conductivity T as shown in equation 1.9.
carrierlatticeT += 1.9
Most of the carrier thermal conductivity component carrier is directly related to the
electrical conductivity via the Wiedemann-Franz law 19:
TneLTLcarrier )( == 1.10
Where is the electrical conductivity, T is the temperature and L is the Lorenz factor,
normally 2.4x10-8 V2/K2 for metals. We may express the phonon thermal conductivity
lattice in terms of the specific heat C , the speed of sound v and the mean free path l of
the phonons using the relation:
3/Cvllattice = 1.11
As shown in equation 1.11, the mean free path l is inversely proportional to the number
of excited phonons in the lattice, which is also directly proportional to T . Hence the
thermal conductivity increases as the temperature decreases.
31
1.4.4 Figure of Merit (ZT)
The quality and maximum efficiency of a thermoelectric device for both thermoelectric
power generation and refrigeration (cooling) is determined is determined primarily by the
material’s figure of merit ZT . This dimensionless figure of merit is defined as 12:
TS
ZT
=
2
1.12
where S is the Seebeck coefficient, is the electrical conductivity, is the thermal
conductivity, T is the absolute temperature. The numerator 2S is referred to as the
power factor (PF). As shown in Figure 1.4, the power factor is typically optimized in
semiconductor materials with a carrier concentration around n= 1019 or 1021 3/ cm 20.
To achieve a good thermoelectric performance, materials with high mobility carriers are
also most desirable in order to obtain the highest electrical conductivity for a given
carrier concentration. In addition, low thermal conductivity and higher Seebeck is
necessary to maintain the appropriate temperature gradient and convert heat to electric
potential. Hence achieving a high ZT value is challenging, as these requirements are
contradictory to each other as shown in eq 1.12. Figure 1.8 below shows the plot of ZT
for a variety of n-type and p-type thermoelectric materials as a function of temperature 21.
32
Figure 1.8: Plot of figure-of-merit (ZT) as function of temperature (K) for
(a) n-type thermoelectric materials and (b) p-type thermoelectric materials 21.
1.5 Thin Film Material
Several thermoelectric generation and cooling applications are used from bulk material.
However, this material is best used at the chip-scale level. In recent years the industry has
pushed for small or micro-scale process, which can be best addressed by depositing thin
films onto a silicon substrate surface. Thin-film material requires small geometries,
which are later diced and packaged. Thermoelectric bismuth telluride (Bi2Te3) and
antimony telluride (Sb2Te3) materials have received significant interest for thin-film
deposition due to their compatibility with Integrated Circuit (IC) CMOS-based
technology and deposition onto silicon substrate 22.
33
1.6 Applications
Thermoelectric generators (TEGs) are solid-state devices that have the benefit of no
moving parts and therefore offer maintenance free operation for long duration. Various
thermoelectric applications primarily from the bulk materials have been used in the
industry. For the past four decades TEGs have reliability provided power for deep space
probes such as Voyager I and Voyager II 20. Over the past few years the efficiency of the
thermoelectric devices has increased and promoted the use of thermoelectric materials in
chip-scale projects such as heat-pipe 23 , internet-of-things (IoT), wireless sensors, and
wearable applications 6,24. In addition, chip-scale TEG devices are available
commercially. Micropelt TGP-651 series uses a thin-film solid state solid state generators
in a standard package 25 . Device uncapping show the Micropelt small-scale device is
based on sputtered Bi2Te3 and Sb2Te3 active material including many leg pairs as shown
in Figure 1.9.
Figure 1.9: (a) Micropelt Thermogenerator TPG device, (b) High magnification
Scanning Electron Microscope (SEM) image of internal device post device uncapping
and (c) EDX layered image showing the active TE material are Bi2Te3 and Sb2Te3.
34
Chapter 2. Material Deposition and Optimization
In this chapter we discuss several deposition methods and optimization techniques
for n-type Bi2Te3 and p-type Sb2Te3 thermoelectric materials.
2.1 Background
Integrating thin film thermoelectric material into microsystems depends on the deposition
method, which is critical for the device operation. Thermoelectric thin films have been
prepared using a variety of technique using the physical deposition process and chemical
deposition process. These different preparation techniques are shown in Figure 2.1. The
physical deposition process encompasses a wide-range of methods where the material
goes to a vapor phase and then back to a thin-film condensed phase. This process
involves the physical ejection of material as atoms or molecules followed by the
condensation of these atoms onto substrate 26. The techniques used by physical processes
include thermal evaporation 27,28, sputtering 29–31, pulsed laser deposition 32, molecular
beam epitaxy 33–35. Additional thin-film preparation methods use the chemical deposition
process such as Metal- Organic Chemical Vapor Deposition 36 and electro-chemical
deposition 37. There are several advantages of physical process over electrodeposition or
CVD. These include 26:
• High versatility in depositing any metal, alloys and some polymeric materials
• Ability to vary the substrate temperature from subzero to very high temperatures
• Excellent bonding to the substrate
35
Figure 2.1: Typical representation of thermoelectric deposition methods 38.
2.1.1 Sputtering
Sputtering is one of the most common commercial thin film deposition technique for
various materials. It is used extensively in the semiconductor industry due to its stable
and reproducible process and sputtering efficiency 38. Sputtering utilizes magnetic and
electric fields to trap electrons to the surface of the target. Figure 2.2 presents a schematic
representation of the sputtering system. The sputtering process begins by placing a
substrate (i.e. target) in the chamber. A controlled flow of sputtering gas, typically Argon
(Ar) gas is introduced into the chamber under high vacuum (20-150 mTorr) and a high
(negative) DC bias is applied to the target material (also called the cathode) causing the
plasma to glow. Free moving electrons caused by the negatively charged voltage collide
with the argon gas atoms causing the atoms to become positively charged ions attracted
to the negatively charged target at high speed that eject the particles from the source
36
material target and get deposited as a thin material on the top of the substrate surface
after passing into the vapor phase to form a dense film. There are many different
sputtering methods under the physical vapor deposition (PVD) process 26,38. These
include:
Magnetron Sputtering
Ion Beam Sputtering
Radio Frequency Sputtering
Direct Current Sputtering
Figure 2.2: Schematic of the Sputtering deposition process 39.
2.1.2 Thermal Evaporation
Thermal evaporation is one of the simplest forms of the Physical Vapor Deposition
(PVD). It is performed by heating the target material at very high temperatures around
37
1500°C via the joule effect to evaporate a source material within the chamber 40. This
material rises in the chamber, coating the target with a thin film. Figure 2.3 shows a
schematic representation of the evaporation system. Thermal evaporation is similar to the
molecular-beam epitaxy (MBE) process because the deposition requires the thermal
energy to be used to produce the vapor of the source materials. Key advantages of
thermal evaporation include simplicity to use, high deposition rates, and relatively lower
cost of the equipment. However, thermal evaporation is not suitable for fabricating
multicomponent thin-films as some bulk materials evaporate before others due to their
different melting points.
Figure 2.3: Schematic of an evaporation deposition system 40.
2.1.3 Molecular Beam Epitaxy
Molecular-beam epitaxy (MBE) is an epitaxy technique for thin-film deposition for
single crystalline materials. Epitaxy refers to the controlled growth of one crystalline
layer on another crystalline layer 41. MBE involves building up materials by manipulating
38
atoms and molecules with a heated crystalline substrate, performed in an ultra-high
vacuum (UHV) environment (~10-10 Torr). Molecular beam epitaxy process is the most
reliable deposition process in thermal evaporation. The slow deposition rate and the ultra-
high vacuum allows for the film to grow in an epitaxial manner. However, to obtain a
pure film using MBE it is necessary to maintain a very low pressure which is difficult. In
addition, MBE is very expensive compared to other deposition processes. Bi2Te3 and
Sb2Te3 thin-films deposited using MBE yielded a Seebeck coefficient of 159–184 μV/K
and a power factor of 1.6 mW/K2.m 42.
2.1.4 Chemical Vapor Deposition
CVD is a processes where solid material is deposited from a vapor by a chemical reaction
on a heated substrate surface. The resulting solid material is in the form of a thin-film or
crystal. By varying the deposition conditions, including substrate temperature,
composition of the reaction mixture and gas flow, materials with a wide range of
physical, and chemical properties can be grown 26. There are varieties of CVD processes.
Metal Organic Chemical Vapor Deposition (MOCVD) is one of the techniques used for
growing high quality Bi2Te3 and Sb2Te3 thin-film thermoelectric materials 36 . However,
the gases used in this process are toxic and require additional safety procedures, making
the MOCVD deposition process quite expensive.
39
2.2 Optimization Methods
Efficiency of thermoelectric material is critical for a wide range of practical applications.
Various techniques are presented below to help improve the efficienty of the material, by
reducing the thermal conductivity in the materials, which is later used in the literature to
develop a chip-scale thermoelectric generator for internet-of-things (IoT) and wearable
applications near room temperature.
2.2.1 Doping
Doping is a process that intentionally alters the electrical properties of the material. This
is done by adding impurities to the atomic structure of the material to change its intrinsic
(undoped) behavior. The carrier concentration of the material can be changed using
dopants. However as shown in Figure 1.7, the electrical conductivity of the material will
increase with an increase in the carrier concentration which results in a decrease in the
Seebeck coefficient and overall power factor.
2.2.2 Co-Sputtering
Co-sputtering is a deposition method where two or more source target materials (such as
Bi/Sb and Te or Bi2Te3/Sb2Te3 and Te) are sputtered at once in a vacuum chamber and is
often used with a sputtering tool to produce high quality thin-films 39. This method is
used extensively in the literature to enhance the thermoelectric properties of bismuth-
telluride and antimony-telluride thermoelectric materials 29,43,44.
40
2.2.3 Alloying
Alloying is one of the easiet methods to reduce the lattice thermal conductivity without
degreadation to the electrical conductivity 45,46. It is used to improve efficiency of
thermoeletic material by adding an element to the material. Bismuth can be alloyed with
Antimony to yield higher mobility and reduce the thermal conductivity, thus leading to
enhanced the figure of merit , ZT. Alloying bismuth with antimony was also found to
give greater flexibility in tailoring the properties of bismuth-related nanowires for
specific thermoelectric applications 9.
2.2.4 Nanomaterials
Several methods to improve the figure-of-merit ZT can be made by reducing the lattice
contribution to the thermal conductivity. In bulk thermoelectric materials, alloying is
introduced to substitute lattice sites with different atoms but from the same grouping in
the periodic table to help scatter short wave phonons than electrons 46. By utilizing
thermoelectric material at the nanoscale level and allowing for the re-optimization of the
carrier concentration 20, the lattice thermal conductivity is reduced by exploiting different
nanostructures with the goal of harnessing phonon scattering while leaving electronic
properties unaffected 46. Ideally thermoelectric nanomaterials disrupt the phonons,
reducing their mean-free path without affecting the electrons which have shorter mean
free paths 47. Several methods for producing thermoelectric nanomaterials have been
utilized 48 .
41
2.2.5 Grain Boundaries
Another method for improving ZT is by reducing the lattice thermal conductivity. Simply
by reducing the grain size the lattice thermal conductivity is reduced and substantial
improvements in ZT have been observed 49. However decreasing grain size will decrease
electrical conductivity and ultimately the power factor as shown in Figure 1.7.
Figure 2.4: Large grain with less grain boundaries (left image) verses small grain
structure with more grain boundaries (right image)49.
2.3 Annealing
Annealing is a heat treamtment process used mostly to enhance the propeteries of a
material by alterning its physical properties to increase ductility and reduce hardness.
This change in ductility is due to the reduction of dislocations in the crystal structure 50.
During the annealing process, the atoms migrate in the crystal lattice and help increase
the grain size which increases the electrical conductivity as the charged carriers move
42
more freely. There are three main stages that causes microstructural changes during the
annealing process.
The first stage is recovery and it results in the removal of defects in the material, also
known as dislocations, which causes internal stress. This step occurs at the lower
temperature stage of the annealing process prior to the growth of new grains 51. The
second stage is recrystallization, where the new grown grains replace those deformed
grains observed in the first stage 51. The final stage is grain growth, which occurs once
the material is cooled for long duration. In grain growth stage, the microstructure of the
material is hardened and allows for faster electrical response but may lose some of its
original strength 51.
43
Chapter 3. Thermoelectric Film Depositions –
Experimental Procedure
In this chapter, we report on an optimum deposition process for 1µm and 10µm bismuth
telluride (Bi2Te3) and antimony telluride (Sb2Te3) thin films via RF magnetron sputtering
techniques on SiO2/Si substrates. The thin-film material and thermoelectric properties are
characterized for different deposition conditions and using various heat treatment recipes.
The crystal orientation is obtained using an X-ray diffraction (XRD) tool and compared to
known diffractions peaks of the same crystal material. The crystal structure and grain size
of the sputtered films are obtained via a high-resolution Scanning Electron Microscopy
(SEM) analysis for top-surface and cross-section imaging of the films. An ultra-thin layer
of platinum is deposited over the thermoelectric films to reduce the electric charge that
builds up over the top surface. The thermoelectric properties are analyzed using a Seebeck
tool and Hall measurement tool to obtain the electrical conductivity, carrier concentration
and mobility. The power factor (PF), measured in watts per meter-square Kelvin (W/K2.m),
is also recorded. The physical vapor deposition (PVD) system, which is the main tool
used in the literature for thin-film deposition is introduced in detail.
44
3.1 Background
Thin films thermoelectric materials are most suitable for micro-scale applications.
Sputtering technique is used extensively to deposit thin films. Thermoelectric n-type
bismuth telluride (Bi2Te3) films and p-type antimony telluride (Sb2Te3) films are grown
on SiO2/Si substrates via RF magnetron sputtering. The crystal structures and
thermoelectric properties are characterized for 1µm and 10µm films deposited using
different deposition conditions and using various heat treatment conditions. In this work
we demonstrate an optimum deposition process for 1µm and 10µm Bi2Te3 and Sb2Te3
thin films via RF magnetron sputtering.
The performance of thermoelectric materials can be evaluated using the figure of merit,
ZT, or power factor, PF. The figure of merit is defined as: ZT = (S2 T) / where S (V/K)
is the Seebeck coefficient, a measure of a generated thermoelectric voltage in response to
a temperature gradient in the material, (S/m) is the material’s electrical conductivity, T
(K) is the absolute temperature and (W/K·m) is the thermal conductivity. The power
factor PF (W/K2.m) is the product of the Seebeck coefficient and the electrical
conductivity: PF= S 2.
Earlier studies based on bulk thermoelectric materials show a high thermoelectric figure of
merit (ZT~1.14) at room temperature 29. However, the fabrication of microscale
thermoelectric generators (μTEG) using thin-film technology is critical for IoT and
wearable applications 6. Thermoelectric bismuth telluride (Bi2Te3) and antimony telluride
45
(Sb2Te3) thin films have been prepared using a variety of techniques, such as thermal
evaporation 27,28, sputtering 29–31, pulsed laser deposition 32, molecular beam epitaxy 33–35,
chemical deposition such as Metal- Organic Chemical Vapor Deposition (MOCVD) 36 and
electro-chemical deposition 37. A comparison summary of the deposition methods for
Bi2Te3 and Sb2Te3 is shown in Table 3.1 below:
Author Deposition
Method
N-type
Material
P-type
Material
ΔT Output
Power
Ping Fan 52 Sputtering Bi2Te3 Sb2Te3 85 K 19.13 μW
Ingo Stark 53 Sputtering Bi2Te3 Sb2Te3 60 K 203 μW
Wei Wang 54 Electrodeposition Bi2Te3 Sb2Te3 20 K 77 μW
Table 3.1: Chip-scale thermoelectrics in the literatures based on Bi2Te3 and Sb2Te3.
The magnetron sputtering method is the most common commercial thin film deposition
technique due to its stable and reproducible process and sputtering efficiency. The effects
of deposition temperature or post-annealing on the thermoelectric properties of bismuth
telluride have been reported and discussed previously 55–57,43,58. Kim et al. fabricated
400nm bismuth telluride films by co-sputtering and obtained -55µV/K and ~3 × 10-4
W/K2·m for Seebeck coefficient and power factor, respectively, with a deposition
temperature of 225ºC 29. Subsequently, they demonstrated thicker (1µm) bismuth telluride
with maximum values of S (-128µV/K) and power factor (9 × 10-4 W/K2.m) using co-
sputtering followed by a rapid thermal annealing process 55. Wang et al. coated 400nm
bismuth telluride films using the same approach and investigated the effects of normal
annealing temperature. They achieved -242µV/K for Seebeck coefficient and 2.1
mW/K2.m for the power factor 43 .
46
3.2 Sputtering of Thin Films
High quality thermoelectric thin films are deposited using magnetron sputtering
techniques via the Physical Vapor Deposition (PVD) system. Figure 2.2 shows a
schematic representation of the sputtering system. The magnetron sputtering system used
for the thin-film deposition work is manufactured by AJA International and shown in
Figure 3.1. The PVD consists of a main load chamber and a cryopump which maintains a
very low pressure below several mTorr . An ultra-high purity sputtering gas such as
Argon (Ar) or Nitrogen (N2) is provided during depositions. The sputtering tool is
equipped with 6 sputtering sources including 4 DC guns and 2 RF guns. Two (2) inch
diameter targets that can be operated independently or together are used for various
depositions throughout the literature. The tool also offers sample rotation to enable high
uniformity and high temperature capability which can heat the sample up to 1000°C for
high quality crystal material.
Figure 3.1: Physical Vapor Deposition system, manufactured by AJA International.
47
3.3 X-ray Diffraction
X-ray diffraction is used to analyze the crystal structure and phase analysis of the
thermoelectric materials used in the literature. This method is based on Bragg’s
diffraction law and is used with commercial software to aid with the analysis. A Philips
X’Pert materials research diffractometer (MRD) is used to do the XRD measurements.
Figure 3.2: Philips X’Pert materials X-ray Diffraction (XRD) Tool 59.
3.3.1 Bragg’s Law
Bragg’s law refers to the simple equation shown in equation 3.1.
nλ = 2d sin θ 3.1
θ is the angle between the incident x-ray and scatter plane. The concept of Bragg
diffraction is shown in Figure 3.3.
48
Figure 3.3: Concept of Bragg’s diffraction law 60.
XRD follows Bragg's law in that the reflected X-rays from the different crystal layers
either undergo constructive or destructive interference. Destructive interference occurs is
the x-ray waves are out of alignment, causing the signal to be destroyed. Constructive
interference takes place when the x-ray waves are in alignment. This amplifies the signal
and causes high intensity peaks in the spectrum 61.
49
3.4 Experimental Details
Bismuth telluride (Bi2Te3) and antimony telluride (Sb2Te3) films are deposited using a
physical vapor deposition (PVD) system by RF magnetron sputtering. A high purity
Bi2Te3 and Sb2Te3 targets with a diameter of 2 inches is used first as the source material
for single target deposition for n-type and p-type films respectively. A tellurium (Te)
target is added for two-target co-sputtering to optimize Bi2Te3 thin film composites and
textures. The schematic diagram of the setup is shown in Figure 3.4 and Figure 3.5. Films
are deposited on (100) silicon substrates with a thermally grown silicon-dioxide layer
(500 nm) for electrical isolation purposes. The distance between the targets and the
substrate is fixed at 20 cm and the substrates are rotated at a rate of 100 rpm for uniform
film deposition. The base pressure of the deposition chamber is below 10-7 Torr in order
to remove residual gas particles. Argon (Ar) sputtering gas is subsequently introduced
with a 4 sccm flow to achieve a pressure of 3x10-3 Torr.
Figure 3.4: Schematic for single target sputtering.
The same method is applicable to p-type film.
50
Figure 3.5: Schematic for two target co-sputtering.
A separate tellurium (Te) target is added for co-sputtering deposition.
Bismuth telluride films from a single target are deposited with a fixed power of 60W and
90W. Co-sputtering of bismuth telluride films are obtained using 60W and 90W of power
applied to the fixed Bi2Te3 target and varying the power from 10W to 20W on the Te
target. Single target deposited antimony telluride films are prepared using 60W of power.
Higher temperature n-type depositions are carried out for single target sputtering. The
temperature is varied from 150°C to 350°C and is controlled by a resistive graphite
heater, lying beneath the substrate holder. The post annealing process of room-
temperature deposited films is performed at 250°C with different anneal times; 30 mins,
1 hour, and 2 hours.
51
Step height of the deposited layer is measured with a surface profiler. In this paper, the
process is developed for 1μm and 10μm thin films, and the latter one is employed for the
final thermoelectric device fabrication. Surface morphology of bismuth telluride and
antimony telluride films is observed with a field emission scanning electron microscopy
(SEM, FEI Quanta 600F) operating at 10kV and 10mm working distance and energy
dispersive X-ray (EDX, Oxford X-max 80) is used to measure the elemental composition.
Crystallinity is characterized using an X-ray diffraction system (Philips, X'pert Pro) in the
conventional θ−2θ mode by the use of the Cu Kα1 line for the X-ray source.
Thermoelectric properties are measured using an Ecopia HMS-3000 Hall measurement
system while the Seebeck coefficient measurement is based on a 4-probe differential
measurement technique as shown in Figure 3.6.
Figure 3.6: Four probe measurement technique for Seebeck coefficient in an enclosed
case.
52
3.4.1 Seebeck and Hall Measurements
Seebeck measurements (volts per kelvin) are obtained when there is a temperature
gradient across a material. Using the four-probe measurement setup shown in Figure 3.6,
the voltage is obtained per the temperature difference and the Seebeck coefficient is
obtained using the slope of the graph as shown in Figure 3.7. Hall measurements such as
bulk concentration, mobility and conductivity are also averaged and recoded.
Figure 3.7: Representative graph for obtaining Seebeck coefficient and Hall
measurements.
Average Average -82.7
Bulk Concentration (cm-3
) -2.65E+20
Mobility (cm2 / Vs) 1.32E+01
Resistivity (Ω cm) 1.79E-03
Conductivity (Ω-1
cm-1
) 5.57E+02
Nb u rho RH RHA RHB NS SIGMA DELTA ALPHA
1mA -2.49E+20 1.40E+01 1.80E-03 -2.51E-02 -2.45E-02 -2.56E-02 -2.49E+16 5.57E+02 1.38E-02 8.56E-01
5mA -2.719E+20 12.75 0.0018 -0.02295 -0.02294 -0.02297 -2.719E+16 555.6 0.01267 0.8563
10mA -2.733E+20 12.77 0.001789 -0.02284 -0.02262 -0.02305 -2.733E+16 559 0.01261 0.8562
Average -2.65E+20 1.32E+01 1.79E-03 -2.36E-02 -2.34E-02 -2.39E-02 -2.65E+16 5.57E+02 1.30E-02 8.56E-01
Hall Data Seebeck
Power Factor
3.808E-04
Hall Data
53
3.5 Thin-Film Deposition and Characterization
In this section, the thin-film depositions and characterization are presented for the
thermoelectric n-type Bi2Te3 and p-type Sb2Te3 films using various deposition conditions
and heat treatments.
3.5.1 High Temperature Sputtering of Bi2Te3 and Sb2Te3 Films
High temperature deposition highlights different sputtering and crystal characterization
techniques for Bi2Te3 and Sb2Te3 films using different methods for optimum temperature
and composition.
3.5.1.1 Single Sputtering of 1µm Bi2Te3 Films
Bismuth telluride films are deposited via single-target sputtering for a range of substrate
temperatures between 25°C and 350°C. The target thickness for these depositions is 1µm
as shown in Figure 3.8. SEM images of the top surface of the deposited films are shown
in Figure 3.9. The room temperature film shows relatively small grain size (~75nm -
200nm) and a very smooth surface. The grain size increases with increasing deposition
temperature, with the average grain as large as ~2µm for the film deposited at 350°C.
Figure 3.8: Cross-section image of the single target sputtered films.
54
Figure 3.9: SEM image of Bi2Te3 films deposited using single-sputtered target at:
(a) 25°C; (b) 150°C; (c) 200°C; (d) 250°C; (e) 300°C; and (f) 350°C.
X-ray diffraction patterns collected for these films are shown in Figure 3.10. The XRD
spectrum taken for the room temperature film indicates a polycrystalline Bi2Te3 film with
small grains (supported by SEM analysis) and no preferential alignment. With an increase
in deposition temperature, surface diffusion of adatoms is enhanced and the temperature
55
helps the film eliminate defects and improves crystallization 29, resulting in larger and
narrower XRD peaks. For deposition temperatures above 150°C, additional peaks start to
appear. Some of these (e.g. (1 1 0), (2 0 5)) can be attributed to stoichiometric Bi2Te3. The
broad peaks close to 2=18° and 45°, however, likely indicate of presence of multiple Te-
deficient phases. A similar right-shift of the (0 0 6) and (0 0 15) Bi2Te3 peaks has been
reported previously for the Te-deficient phases that make up the (Bi2)m(Bi2Te3)n series 62.
Figure 3.10: XRD spectra taken from bismuth telluride films deposited at temperatures
between 25°C and 350°C. Bi2Te3 peaks are labeled, with vertical dashed lines marking
the locations of Bi2Te3 (0 0 3) and (0 0 9) peaks.
Deviation from stoichiometry (Bi:Te = 2:3) is confirmed via EDX in Figure 3.11. As the
deposition temperature increases, tellurium (Te) evaporates from the film and the Bi:Te
ratio increases from values close to that of stoichiometric Bi2Te3 (0.67) up to nearly 1.
56
Figure 3.11: Elemental composition (EDX) atomic ratio of Bi to Te for single-
target sputtered n-type films, as a function of deposition temperature (°C).
The measured thermoelectric properties of the films are shown as a function of deposition
temperature in Figures 3.12. The room temperature film has the lowest measured mobility
(< 7 cm2/V-s) and a relatively high carrier concentration, which is consistent with a Bi2Te3
film with small grains and a large number of grain boundary defects. The highest (negative
for n-type film) Seebeck coefficient of -55 µV/K is achieved with a deposition temperature
of 150°C resulting in a power factor of 0.65 mW/K2.m. This film also exhibits the lowest
carrier concentration of ~6.5 x 1020/cm3, indicating a better grain structure than the room
temperature film. The higher temperature depositions, which contain Te-deficient phases
in addition to Bi2Te3, exhibit poor thermoelectric properties in addition to higher carrier
concentration and lower Seebeck coefficient.
57
Figure 3.12: (a) Carrier concentration and mobility; (b) conductivity and Seebeck
Coefficient and (c) Power factor of n-type single sputtered films as a function of the
deposition temperature.
While the results indicate that 150°C is the optimal temperature for sputtering from a single
Bi2Te3 target, the properties of the 150°C film still fall short of what is expected from the
literature 57. The atomic Bi:Te ratio for this film (0.75) differs from the ideal stoichiometric
value (Bi:Te = 2:3), indicating loss of Te during deposition despite the relatively low
substrate temperature.
58
3.5.1.2 Co-sputtering of 1µm Bi2Te3 Films @ 60W
Based on the low tellurium (Te) contents and weak thermoelectric performance measured
for single-sputtered Bi2Te3 films, the co-sputtering of Te in addition to Bi2Te3 is explored.
Co-sputtered depositions are performed at 150°C, with the sputtering power for the
Bi2Te3 target set at 60W and the power to the Te target varied from 10W to 20W. Top-
surface SEM images of these films are shown in Figure 3.13. The grain size increases
with increasing power to the tellurium target. The average grain size is as large as
~500nm when deposited with 10W of power and ~1µm for 20W.
Figure 3.13: SEM image of films deposited at 150°C by (a) single sputtering, (b) co-
sputtering with 10W power to Te target, (c) 15W to Te target and (d) 20W to Te target.
59
XRD spectra collected from these co-sputtered Bi2Te3 films are shown in Figure 3.14 and
are compared with the spectrum taken from a single-sputtered Bi2Te3 film. The co-
sputtered films show more c-axis texturing, with significantly larger intensities of the (0 0
l) family peaks (marked by dashed vertical lines in Figure 3.14) than the single-sputtered
film. Also, there is no indication of the presence of Te-deficient phases as seen in higher
temperature single-sputtered depositions. While 10W and 15W Te sputtering power yield
similar spectra, additional peaks appear for the case of the 20W depositions indicating the
possible presence of a separate Te phase. This is supported by elemental composition
measurements, shown in Figure 3.15. A Te sputtering power of 10W and 15W yields a film
close to stoichiometry, while the 20W results in excess Te and a Bi:Te ratio < 0.5.
Figure 3.14: XRD spectra taken for co-sputtered Bi2Te3 deposited with a range of
Te powers. Bi2Te3 peaks are labeled, with vertical dashed lines marking (0 0 l)
peaks. The asterisks indicate secondary peaks attributed to a separate Te phase;
60
Figure 3.15: Atomic ratio Bi:Te ratio as a function of Te sputtering power for co-
sputtered films.
3.5.1.3 Co-Sputtering of 1µm Bi2Te3 Films @ 90W
Additional co-sputtered depositions using a higher power of 90W for the Bi2Te3 target is
attempted at 150°C, using three additional studies to determine the optimum sputtering
power for the Bi2Te3 and Te target. The first study uses a fixed sputtering power of 90W
for the Bi2Te3 target and vary the power to the Te target from 0 to 20W. Top-surface SEM
images of these films are shown in Fig. 3.16. Cross-section SEM images of the 1µm films
are shown in Figure 3.17. As shown via SEM analysis, the grain size increases with
increasing tellurium power, but the grain size remained smaller compared to the films
deposited using 60W of power, with the average grain ~300nm for the 10W film and as
large as ~400nm using 15W film.
61
Figure 3.16: SEM of films deposited at 150°C using 90W of power for Bi2Te3 by (a)
single sputtering, (b) co-sputtering with 10W to Te target, (c) 15W Te and (d) 20W Te.
Figure 3.17: Cross-section SEM image for (a) single sputtering film, (b) co-sputtered
with 10W of Te, (c) co-sputtered with 15W of Te and (d) co-sputtered with 20W of Te.
(a) (b)
(c) (d)
(a) (b)
(c) (d)
62
XRD spectra collected from the co-sputtered Bi2Te3 films deposited at 90W are shown in
Figure 3.18(a) and are compared with the spectrum taken from the single-sputtered Bi2Te3
film. The co-sputtered films show no indication of Te-deficient phases as seen in the higher
temperature single-sputtered depositions. while the 10W film yields a film close to
stoichiometry, the 20W film show additional peaks that may indicate the presence of a
separate Te phase. This is supported by elemental composition measurements (EDX),
shown in Figure 3.18(b). A Te sputtering power of 15W and 20W results in excess Te and
a Bi:Te ratio under 0.5.
Figure 3.18: (a) XRD spectra taken for co-sputtered Bi2Te3 films deposited at 90W with a
range of Te powers. (b) Atomic ratio Bi:Te ratio as a function of the Te sputtering power.
Measured thermoelectric properties for these films are shown as a function of Te sputtering
power in Figure 3.19. As the tellurium power is increased, co-sputtered depositions at
150°C using 10W Te target show an enhanced Seebeck coefficient of -78 µV/K compared
to the single sputtered film resulting in a power factor of 0.475 mW/K2.m The highest
Seebeck coefficient of -91 µV/K is obtained using the 15W Te target, but lower power
factor of 0.34 mW/K2.m due to lower electrical conductivity and lower mobility. Although
the Seebeck coefficient is higher in both co-sputtered films, the power factor is low due to
the higher resistivity of the films.
63
Figure 3.19: (a) Carrier concentration and mobility; (b) conductivity and Seebeck
Coefficient and (c) Power factor of co-sputtered films as a function of Te power.
3.5.1.4 Co-Sputtering of 1µm Bi2Te3 Films – Vary Bi2Te3 Power
The second study uses a fixed sputtering power of 10W for the Te target and varied the
power to the Bi2Te3 target from 65W to 85W. Top-surface SEM images of these films are
shown in Figure 3.20 and cross-section images are shown in Figure 3.21 showing an
average thickness of ~1µm . The grain size varied from 150nm to 300nm for the 85W
Bi2Te3 film. The grain size for the 90W Bi2Te3 target averaged ~350nm.
64
Figure 3.20: SEM image of films deposited at 150°C with 10W Te by (a) co-sputtering
with 65W power to Bi2Te3 target, (b)75W, (c) 80W, and (d) 85W.
Figure 3.21: Cross- section SEM image of (a) 65W Bi2Te3,
(b) 75W Bi2Te3, (c) 80W Bi2Te3 and (d) 85W Bi2Te3 power.
XRD spectra collected from these co-sputtered Bi2Te3 films are shown in Figure 3.22(a)
and are compared with the spectrum taken at 90W for the co-sputtered Bi2Te3 film. The
films show no indication of Te-deficient phases as seen in higher temperature single-
sputtered depositions. Elemental composition analysis, shown in Figure 3.22(b), confirmed
the 85W target yields a film close to ideal stoichiometry (0.667).
(b)
(d) (c)
(a)
65
Figure 3.22: (a) XRD spectra taken for co-sputtered films deposited with a range of
Bi2Te3 powers. (b) Atomic ratio Bi:Te ratio as a function of Bi2Te3 sputtering power.
Measured thermoelectric properties for these films are shown as a function of Bi2Te3
sputtering power in Figure 3.23. Co-sputtered depositions for the 80W Bi2Te3 target yield
the highest Seebeck coefficient of -98.5 µV/K and the lowest power factor of 0.237
mW/K2, while the 85W film produced the lowest Seebeck coefficient of -69.9 µV/K and
the highest power factor of 0.382 mW/K2 in addition to highest mobility due to ideal
stoichiometry composition as shown in Figure 3.22(b). It can be observed that lower
mobility in these films lowered the electrical conductivity, hence reducing the overall
power factor, PF.
Figure 3.23: (a) Carrier concentration and mobility; (b) conductivity and Seebeck
Coefficient and (c) Power factor of co-sputtered films as function of Bi2Te3 power.
66
3.5.1.5 Co-Sputtering of 1µm Bi2Te3 Films – Vary Temperature
The final study uses a combination of fixed sputtering 90W of power for the Bi2Te3 target
and fixed 10W of power for the Te target while varying the temperature rate. Top-down
SEM images of these films are shown in Figure 3.24 and cross-section images are shown
in Figure 3.25. The grain size varied from 350nm to 450nm for the films deposited at
150°C and 200°C while the grain size for the 90W Bi2Te3 target averaged ~350nm.
Figure 3.24: SEM images of co-sputtered films deposited with 90W of Bi2Te3 and 10W
of Te at various temperatures (a) 25°C, (b) 150°C, (c) 200°C, and (d) 250°C.
Figure 3.25: Cross- section SEM image of films deposited at various temperatures
(a) 25°C, (b) 150°C, (c) 200°C, and (d) 250°C.
(a) (b)
(c) (d)
67
XRD spectra collected from these co-sputtered films with fixed 90W for the Bi2Te3 target
and fixed 10W for the Te target are shown in Figure 3.26(a). As shown previously, the
room temperature film shows smooth surface and no crystallization. The 10W and 15W
films show no indication of Te-deficient phases as seen in higher temperature single-
sputtered depositions. However, EDX analysis as shown in Figure 3.26(b) show the 150°C
and 200°C films deviate away from ideal stoichiometry.
Figure 3.26: (a) XRD spectra taken for co-sputtered films deposited with a fixed Bi2Te3
power and fixed Te power while varying temperature. (b) Atomic ratio Bi:Te ratio as a
function of deposition temperature using fixed Bi2Te3 powers and fixed Te power.
Measured thermoelectric properties for these films are shown as a function of temperature
using a fixed 90W for the Bi2Te3 target and fixed 10W for the Te target are shown in Figure
3.27. Co-sputtered depositions at +200°C yielded the highest Seebeck coefficient of -89.7
µV/K and the highest power factor of 0.533 mW/K2.m. The film deposited at +250°C has
the highest mobility among the rest of the films and Seebeck of -87.6 µV/K. However, it
can be observed from the SEM analysis, the higher temperature films resulted in a different
type of grain structure, also supported by XRD analysis in Figure 3.26(a).
68
Figure 3.27: Transport properties using fixed Bi2Te3 power and fixed Te power while
varying temperature (a) Carrier concentration and mobility; (b) conductivity and Seebeck
Coefficient and (c) Power factor of co-sputtered films as function of Bi2Te3 power.
3.5.2 Summary of High Temperature Deposition of 1µm Bi2Te3 Films
To summarize this section, high temperature depositions are initially attempted using the
single-target deposition process of 1µm n-type Bi2Te3 films. While these deposition
results indicate that 150°C is the optimal temperature for sputtering, the dispositions
result in a tellurium Te-deficient of stoichiometric films due to the evaporation of
tellurium. Consequently, high temperature two-target co-sputtered deposition is
introduced to overcome the Te deficiency using the following conditions:
• Vary Te power from 10W to 20W and maintain a fixed 60W to Bi2Te3 target.
• Vary Te power from 10W to 20W and maintain a fixed 90W to Bi2Te3 target.
• Vary Bi2Te3 power from 60W to 90W and maintain a fixed 10W to Te target.
• Vary temperature and maintain a fixed 90W to Bi2Te3 and 10W to Te targets.
Based on the material analysis and characterization of the co-sputtered films, the two-
target co-sputtered deposition recipe using a fixed 60W power for the Bi2Te3 target and
10W for the Te target is chosen to deposit a thicker 10µm film to use with the micro-
scale thermoelectric energy harvester (µTEG) device.
69
3.5.3 Sputtering of 1µm Sb2Te3 Films
Given that 150°C is the optimal temperature for n-type depositions, p-type antimony
telluride (Sb2Te3) films are deposited at room temperature and 150°C using the single
sputtering process with the Sb2Te3 target set at 60W and co-sputtered process with the Te
target set at 10W in addition to the 60W power for the Sb2Te3 target. The resulting surface
structure of the synthesized films are shown in Figure 3.28. SEM analysis of the room-
temperature film shows a very smooth surface and no crystal grains. However, at 150°C
the films show higher crystalline quality and larger grains of ~500nm are observed due to
the diffusion of atoms.
Figure 3.28: SEM of p-type deposited at (a) room temperature and
150°C by (b) single sputtering and (c) co-sputtering.
70
XRD pattern analysis indicate that both 150°C films are matched as shown in Figure 3.29.
The films are well crystallized, and the structural properties are improved using the higher
substrate temperature. Both films are of rhombohedral structure that belongs to antimony
telluride and indicate no presence of a Te-deficient phase as supported by elemental
composition analysis (Sb:Te ratio is 0.65 for single sputtered film and 0.68 for the co-
sputtered film).
Figure 3.29: XRD spectra taken for single target sputtered and co-sputtered Sb2Te3 deposited at
150°C.
71
3.5.4 Room Temperature Sputtering and Annealing of Films
Fabrication of thermoelectric devices typically requires thicker films (~10µm) to achieve
optimal leg lengths and device thermoelectric resistances. Using the 150°C two-target co-
sputtering deposition recipe for n-type and single sputtering recipe for p-type as described
in the literature, 10µm thick Bi2Te3 film is attempted initially. However, due to stress in
the film, the material delaminated/peeled off and could not be further analyzed.
To achieve thick films with excellent thermoelectric properties and increased
crystallization, room temperature of 10µm deposition for n-type film followed by high
temperature annealing is investigated using various conditions. Optical inspection analysis
as shown in Figures 3.30 through Figures 3.24 post the anneal process revealed a
combination or oxidation, pitting and excessive delamination.
Figure 3.30: Annealed n-type film for 30min @250°C with 90min ramp up/ramp down,
30 PSI
72
Figure 3.31: Annealed n-type film for 30 mins @250°C with 30min ramp up/ramp down,
50 PSI.
Figure 3.32: Annealed n-type film for 30 mins @300°C with 2.5hrs ramp up/ramp down,
30 PSI.
Figure 3.33: Annealed n-type film for 14 hrs. @225°C with 80min ramp up/ramp down,
30 PSI.
73
To overcome this issue, a high temperature anneal is performed at 250°C for 30 minutes,
1 hour and 2 hours under nitrogen gas to prevent oxidation for both the n-type and p-type
films after each wafer is fabricated. SEM images of the annealed n-type films are shown
in Figure 3.34. While the non-annealed room temperature film shows small grains and
no crystallization phase, the annealed films show crystal growth resulting in larger grains
and an increase in mobility carriers. As shown in table 3.2, when the carrier concentration
for Bi2Te3 film decreases to 9.5x1019 with the annealing temperature increasing to
+250°C, the Seebeck coefficient increase. This is supported by equation 1.7 where the
Seebeck coefficient strongly depends on the charge carrier concentration 43. The highest
(most negative) Seebeck coefficient is obtained for n-type film using 30 minutes anneal
as -123 μV/K. These results correspond to a power factor (PF) of 0.829mW/K2.m.
Similarly, for p-type films, the best Seebeck coefficient and power factor are obtained
using 1hour anneal as +106 μV/K and 0.850mW/K2.m, respectively. The measured
thermoelectric properties are summarized in Table 3.2.
74
Figure 3.34: SEM image of room temp co-sputtered 10µm n-type films using: (a) no
anneal; (b) 30 mins anneal; (c) 1hr anneal; and (d) 2hr anneal.
Sample Anneal Anneal °C ρ (Ω-cm) S (μV/K) PF(mW/K2.m) CC (cm-3) μ (cm2/V-s)
Bi2Te3-sample 1 0hr 0 8.25E-04 -55.00 0.367 1.10E+21 6.85
Bi2Te3-sample 2 0.5hr 250 1.82E-03 -123 0.829 9.5E+19 36.1
Bi2Te3-sample 3 1hr 250 1.46E-03 -96 0.630 1.61E+20 26.74
Bi2Te3-sample 4 2hr 250 1.81E-03 -114 0.719 1.18E+20 29.43
Sb2Te3-sample 1 0hr 0 8.66E-01 +447 0.0231 4.67E+19 0.17
Sb2Te3-sample 2 0.5hr 250 1.61E-03 +92 0.528 1.52E+20 32.20
Sb2Te3-sample 3 1hr 250 1.31E-03 +106 0.850 1.22E+20 42.80
Sb2Te3-sample 3 2hr 250 9.80E-04 +118 0.141 8.92E+19 71.70
Table 3.2: Thermoelectric, deposition of 10µm n-type and p-type films plus anneal.
Resistivity (ρ), Seebeck (S), Power Factor (PF), Carrier Concentration (CC), Mobility (μ).
75
3.6 Thin Film Summary
Detailed deposition methods via RF magnetron sputtering are explained. Material studies
using XRD, SEM and EDX analysis show the orientation and composition of the thin-film
crystals. Thermoelectric transport properties including Seebeck measurements and power
factor were used to analyze and optimize the performance of the thin-films leading to the
fabrication of chip-scale thermoelectric energy harvester. Single-target sputtered
deposition of 1µm Bi2Te3 films above 150°C revealed a different type of grain structure.
Hexagonal crystals were formed during the deposition process and resulted in a tellurium
Te-deficient of stoichiometric films due to the evaporation of tellurium. Two-target co-
sputtered depositions with a Te sputtering power of 10W yields a film close to
stoichiometry; however co-sputtered deposition of thicker 10µm Bi2Te3 films exhibited
delamination issues due to stress in the film. For subsequent room temperature depositions,
the crystallization of the films is improved with the increasing of annealing temperature.
The resistivity of the films decreases as the mobility increases and the Seebeck coefficient
increases with the decrease in carrier concentration allowing for higher power factor for
the annealed films. Hence room temperature depositions using the two-target co-sputtering
process for Bi2Te3 film and single-target sputtering for Sb2Te3 film followed by annealing
at 250°C is chosen to fabricate a micro-scale thermoelectric energy generator (µTEG).
76
Chapter 4. Fabrication and Characterization of
Thermoelectric Energy Harvesting Devices
In this chapter we report on the fabrication and characterization of Bi2Te3 and Sb2Te3
based chip-scale thermoelectric energy harvesting devices. The thermoelectric (TE)
energy harvesters presented here are targeted towards internet of things (IoT) applications
close to room temperature. The aim is to generate enough power from a ΔT of 10°C to
power a wireless sensor. We present details on the device design, fabrication process
flow and device characterization. Finally, we provide process improvements plans for use
with second generation TE devices.
4.1 Fabrication of TEG Device – Vertical Architecture
While we have explored several different device architectures, in this work we focus on
devices based on n-type and p-type thermoelectric materials with a vertical device
architecture. The devices operate by forming a thermal pathway from a heat source to a
heat sink, thus forming a temperature gradient across the device. The thermal resistance of
the device materials establishes a temperature gradient across all thermocouples within the
device. Thus, each thermocouple will experience approximately the same temperature
gradient while being arranged electrically in series (thermally in parallel), culminating in a
large electric potential, the result of the added individual Seebeck voltages. SEM images
shown in Figure 4.1 represents the individual thermocouples connected in series within the
designed device. A single TEG device contains hundreds of thermoelectric leg pairs in a
typical 12mm2. The layout schematic is shown in Figure 4.1(c) 24.
77
Figure 4.1: (a) SEM image of the completed TEG device after removal of the top die; (b)
Higher magnification SEM image of the individual thermoelectric legs connected in
series. (c) Layout schematic for a typical ~12mm2 vertical TEG device, showing the
metallic interconnects in orange and thermoelectric legs in purple.
The optimized n-type and p-type thermoelectric materials presented in this work, are used
to design a Seebeck-based micro thermoelectric generator devices (μTEGs). The latter is
fabricated and experimentally verified utilizing a 10µm thick sputtered surface
micromachined process on 2-inch oxidized Si substrates. The oxide layer is thermally
78
grown to a thickness of 500nm to ensure both electrical and thermal isolation of the device.
Separate n-type and p-type substrates are processed in tandem in preparation for die-to-die
bonding to form the proposed micro thermoelectric generator. Figure 4.1 presents an SEM
image of a completed device after removal of the top silicon die and Figure 4.2 (a)-(d)
shows a schematic cross-sectional view of the full device process flow.
Figure 4.2: Schematic of vertical structure process flow (a) Vertical structure after Au
electroplating. (b) Double layer photo-resist (c) Deposition of active material. (d) lift-off
Approximately 4µm of gold (Au) is electroplated onto the oxidized Si substrate through
the use of both an e-beam Evaporated Ti/Au electroplating seed layer and an electroplating
photoresist mold to define and form the electric interconnect layer. The specific thickness
is chosen to allow for a low resistance path within the device and for enhancing the bonding
process. Post electroplating, the photoresist is stripped. Next, the seed layer is etched
79
through use of a standard Au etch recipe followed by a hydrofluoric (HF) etch recipe of
the base Ti. The resulting cross-section schematic is shown in Figure 4.2 (a).
Subsequently, the wafers are patterned with 15µm thick AZ9620 lift-off photoresist, in
preparation for thermoelectric material sputtering, double layer, as shown in Figure 4.2 (b).
Two layers of the photoresist are sequentially spin-coated and are subsequently patterned
to achieve the desired thickness, thus enabling an efficient lift-off of the subsequently
deposited thermoelectric materials. A physical vapor deposition (PVD) RF-sputtering
system is employed to deposit both the n-type and p-type thermoelectric materials at room
temperature. For the deposition of the n-type thermoelectric material, Bi2Te3, a co-
sputtering technique is used.
In addition, post thermoelectric material deposition, a 1μm thick film of Bi is sputtered
on top of the resulting material stack to form a bonding layer. The resulting cross-section
at this stage of device fabrication is shown in Figure 4.2 (c). Subsequently, a lift-off
process is utilized to reveal the desired device architecture. The lift-off of the
Cr/Bi2Te3/Bi and Cr/Sb2Te3/Bi stacks is performed by removing the AZ9620
photoresist in concentrated acetone for several hours. The resulting device cross-section
is shown in Figure 4.2 (d). Post lift off, both the n-type and p-type wafers are annealed
under in N2 atmosphere at 250°C to promote further crystal growth for improved
thermoelectric properties. The resulting optical image and Scanning Electron Microscopy
(SEM) image of the p-type wafer is shown in Figure 4.3 and Figure 4.4.
80
Figure 4.3: optical image of the completed p-type wafer.
Figure 4.4: Higher magnification SEM image of the p-type wafer.
81
Two individual sputtering targets are utilized concurrently inside the sputtering system.
One is a Bi2Te3 target and the other is a pure Te target. The sputtering targets are set to
60W for the Bi2Te3 and 10W for the Te. The 10W is chosen for the Te target due to the
figure of merit (CC*mobility as shown in Figure 3.12a) and elemental composition ratio
(as shown in Figure 3.15). The p-type thermoelectric material, Sb2Te3, is deposited through
the utilization of a single sputtering target set to a power of 60W. Each material type is
sputtered to a thickness of approximately 10µm to form the thermoelectric legs of the
device. Just prior to each material deposition, a 10nm thick sputtered layer of Cr is
deposited to promote adhesion between the thermoelectric materials and the Au
transmission lines.
Figure 4.5: (a) Completed n-type and p-type wafer prior to dicing, (b) Vertical device
architecture showing the individual diced die and (c) Completed die post bonding.
82
Before bonding of the substrates takes place, each wafer is diced into individual device
dies. The capping die is cut to be slightly smaller to reveal the underlying electrical contact
pads, as shown in Figure 4.5 (a). A Senta FC150 flip-chip bonder is utilized for the die-to-
die bonding through the employment of a typical thermo-compressive bonding recipe.
Specifically, the dies are ramped to 350°C under an N2 flow with the bonding force
(typically 44 MPa) being applied for 150 seconds, under which conditions, the top Bi layer
and the opposing Au surface of each die form a eutectic bond, as shown schematically in
Figure 4.5 (b)-(c). Contact resistances between Au interconnect and the thermoelectric
materials are obtained using a patterned Kelvin structures on the substrate surface. As
shown in Figure 4.6, each thermocouple, defined as one p-type leg and one n-type leg will
experience approximately the same ΔT while arranged electrically in series thermally in
parallel resulting in higher electric potential by adding all individual Seebeck voltages.
Figure 4.6: Vertical device architecture showing (a) n-type and p-type legs are
electrically in series and (b) thermally in parallel.
83
4.2 Device Performance
The thermoelectric properties of the final device are shown in Table 4.1 6 and the resulting
3D X-ray image and optical image of the final device is shown in Figure 4.7.
Material ρ (Ω-m) S (μV/K) PF (mW/K2.m) Ρcontact, Au (Ω-m2)
Bi2Te3 (Device) 1.56E-05 -102 0.7 9.42E-010
Sb2Te3 (Device) 0.90E-05 +110 1.3 3.42E-08
Au 2.6E-08
Table 4.3: Measured properties for thermoelectric materials and interconnect.
Figure 4.7: (a) 3D X-ray image of the TEG device, (b) optical image of the TEG device.
84
The device performance characterization is performed by sandwiching the TEG device
between two large copper blocks. A ΔT is generated and controlled by heating one block
and cooling the other. The magnitude of the temperature drop across the device is
determined using a Quantum Focus Instrument (QFI) infrared (IR) microscope with a
resolution of 20 μm per pixel to bypass the issue of thermal contact resistance present with
standard reference bar techniques, as shown in Figure 4.8. Thermocouples are embedded
in the copper blocks as a reference. The Current–voltage (I/V) characteristics are collected
throughout the temperature cycling in an open-circuit and variable load resistance
configurations 63.
Figure 4.8: Thermal QFI image showing the ΔT drop across the TEG device.
An example set of the data measured for a single TEG device is shown in Figure 4.9.
Measurements are performed for a set of load resistances between 10 Ω and 10 kΩ, and for
a range of cross-device temperature gradients from 1°C up to 7.5°C. Current–Voltage
characteristics are shown in Figure 4.9(a) , while the power out as a function of the load
resistance is shown in Figure 4.9(b). The open circuit voltage and power output increases
85
with ΔT across the device. In addition, the maximum power is achieved under essentially
matched load conditions, which is independent of ΔT. The maximum power, which follows
the expected quadratic dependence on ΔT, is plotted in Figure 4.9(c) 63. This maximum
power is based on an improved bonding recipe (bonding force and temperature) which
resulted in an improved power output performance.
Figure 4.9: Device performance data collected for a single TEG: (a) load voltage as a
function of current and (b) power out as a function of load resistance for several
magnitudes of temperature gradient across device. Maximum power as a function of
temperature gradient is shown in (c).
86
4.3 Analysis of Bond Interface
Following the die bonding process and performance testing of the vertical device , the
TEG is prepared for SEM analysis and mechanical cross-sectioning to expose and inspect
the individual legs for any fabrication or bonding related defects or anomalies.
4.3.1 SEM Analysis and Mechanical Cross-Section
A qualitative inspection of the top-down interface post removal of the top cap wafer is
performed. No fabrication related anomalies were observed as shown in figure 4.10.
Figure 4.10: (a) SEM image of the TEG device post removal of top cap wafer and
(b) Higher manginfation SEM of the highlighted thermocouple legs.
The TEG device is subsequently subjected for mechanical cross-sectioning analysis to
examine the bond interface. Prior to cross-sectioning, the vertical TEG device is prepared
and inserted in a mix of resin and hardener based on recommended volume per part
preceding the polishing process. Subsequently, rough grinding is performed until few
microns away from the area of interest (AOI) followed by fine polishing process and
87
SEM analysis to ensure the AOI is scratch-free and contains no chip-outs. The resulting
SEM images are shown in Figure 4.11. Cross-section SEM analysis revealed evidence of
excess force being applied during the bonding process causing some deformation of the
thermocouple legs during bond. Both n-type and p-type legs were roughly 15% wider and
shorter than the pre-bond process as shown in Figure 4.11 (a). Furthermore, the voids
shown in Figure 4.11(c) are indicative of high porosity in the bond, which contribute to
an increase in the contact resistance, which is a parasitic loss that limits the overall device
performance.
Figure 4.11: (a) Cross-section SEM image of the bond interface post bond, (b) SEM image
of n-type leg including material thickness and (c) Higher mag of the euteic bond interface.
Futher examination using elemental composition (EDX) analysis is used to analyze the
bond interface for any defects. The individual elemental maps of the bond interface are
shown in Figure 4.12. In addition to the expected active materials in the n-type Bi2Te3
device (such as bismuth, tellirum and gold), significant Oxygen (O) was present in the
interface layer indicating a likely non-optimized bond process.
88
Figure 4.12: EDX map of the bond interface of the n-type leg.
The individual elemental maps are shown on the left and superimposed on the right 63.
4.4 Summary of Vertical TEG
In this section we have demonstrated the fabrication and characterization of the chip-
scale thermoelectric generation (TEG) devices. The active materials in these devices is
based on n-type Bi2Te3 and p-type Sb2Te3 using a vertical architecture with 10 μm leg
length. The optimized 10µm films are fabricated in parallel using separate n-type and p-
type wafers and prepared using die -to-die bonding techniques to form the vertical µTEG.
SEM and EDX analysis were used to highlight any fabrication related anomalies.
Performance testing show the optimized n-type film yielded a -102µV/K for the Seebeck
coefficient and 0.7 mW/K2.m for the power factor. Similarly, optimized p-type film
yielded +110µV/K and 1.3 mW/K2.m for their Seebeck coefficient and power factor
respectively. Using the combination of novel infrared microscopy and thin-film
characterization techniques, the power output as a function of the true temperature
difference across the device are isolated. Power outputs as high as 1 mW for a μTEG with
~13.8 mm2 footprint and device ΔT of ~7.5 K are measured 6.
89
Chapter 5. Manufacturing Perspective of Second-
Generation TE Devices and Conclusion
One major limitation of the chip scale thermoelectric device based on the vertical
architecture is the thermal impedance and the manufacturing constraints. The fabrication
of the thick thermoelectric legs is performed via patterning and thin-film deposition
process; However as shown in chapter 4, the 10μm thick thermoelectric n-type and p-
type active materials are not practical using the current deposition methods due to the
slow deposition rates, higher cost and film delamination due to the internal stress/strain
on the films. These manufacturing constraints limit the leg length of the thermoelectric
materials.
5.1 Fabrication of TEG Device – Pyramid Architecture
One approach to solve these constraints is using a patented pyramid structure 64. In this
device structure the n-type bismuth telluride Bi2Te3 and p-type antimony telluride Sb2Te3
active legs are deposited along a polyimide pyramids, allowing to double the existing leg
length to more than 20μm for film depositions under 5μm thick. Polyimide is a light
weight polymer with a low thermal conductivity and provides support for the
thermoelectric legs due to its high flexibility and resistance to heat, thus reducing the
impact of the thermal shunt between the top and bottom wafer 24. Figure 5.1 shows a
cross-section image of the proposed pyramid structure. In the vertical architecture, the
heat flows from the top to bottom along the vertical legs . Hence the TE legs are
electrically in series and thermally in parallel. In the pyramid architecture, the heat flows
90
at an angle along the thermoelectric legs, while maintaining the electrical connection in
series and thermally in parallel. This provides the capability to harvest more of the
available ΔT compared to the vertical architecture. Following the fabrication process of
the pyramid device, the TEG is prepared for mechanical cross-sectioning and imaged via
high resolution SEM. The resulting cross-section image is shown in Figure 5.2.
Figure 5.1 Schematic cross-section image of the patented pyramid structure 64.
Figure 5.2: (a) High magnification cross-secton SEM image with labels of the individual
legs of the TEG device. (b) slope of the active material
91
5.2 Process flow of the 2-Pyramid Architecture
Employing the knowledge gained from the optimized n-type and p-type thermoelectric
materials detailed in this work, Seebeck-based micro thermoelectric generator devices
(μTEGs) were fabricated utilizing the polyimide architecture detailed in the previous
section. Here the TEG devices are internally fabricated on an industrial scale oxidized
silicon wafer (8 inch in diameter). The oxide layer is thermally grown to a thickness of
500nm for proper electrical and thermal isolation. The completed n-type and p-type
wafers are prepared using wafer-to-wafer bonding to form the proposed chip-scale
thermoelectric generator. As detailed previously for the vertical architecture - 10µm thick
sputtered thermoelectric devices approximately 4µm of Au is electroplated onto the
oxidized Si substrate through use of both an e-beam Evaporated Ti/Au electroplating seed
layer and an electroplating photoresist mold to define and form the electric interconnect
layer. Post electroplating, the photoresist is stripped, and the seed layer is subsequently
etched through use of first a standard Au etch followed by an HF etch of the base Ti.
Figure 5.3: Process flow for the 2-pyramid structure 64.
92
Next, polyimide is spin coated onto the wafers and is then lithographically defined to
form pyramid structures that serve as the base architecture for the thermoelectric
materials, which are subsequently thermally co-evaporated to a thickness of 5 µm. Only
one photoresist layer is required to form this thickness of thermoelectric material on each
wafer. An electroplated layer consisting of 2um of Gold (Au) and 1µm of Sn is then
formed on each substrate in preparation for eutectic bonding to form the completed
device. Differing from the previously described die-bonded devices, full 8-inch to 8-inch
bonding is performed to complete the batch fabrication of thousands of thermoelectric
devices in tandem. Wafer dicing occurs after completion of wafer bonding in order to
form the individual TEG device. Figure 5.3 depicts a schematic cross-sectional view of
the full 2-pyramid device process flow.
5.3 Conclusion and Future Work
In this work, 1µm and 10µm thermoelectric n-type bismuth telluride (Bi2Te3) and p-type
antimony telluride (Sb2Te3) thin-films are grown on SiO2/Si at room temperature and a
range of elevated temperatures using RF magnetron sputtering. The 10µm film is chosen
for the final thermoelectric device based on vertical architecture. Temperature effects on
the thermoelectric properties of Bi2Te3 and Sb2Te3 films are found to be strongly
dependent on the sputtering method and deposition temperature. Deterioration of
thermoelectric properties is observed for the 1µm n-type film deposited at temperatures
above 150°C using the single-target sputtering process due to the evaporation of
tellurium. Room temperature deposition using the two-target co-sputtering process for
the n-type film and single-target sputtering for the p-type film followed by annealing at
93
250°C is chosen to fabricate a novel 10µm device for micro-scale thermoelectric energy
generator (µTEG) geared towards internet-of-things (IoT) and industrial applications
close to room temperature. The 10µm n-type film yielded -102µV/K for the Seebeck
coefficient and 0.7 mW/K2.m for the power factor using the two-target co-sputtering
process. Similarly, prepared p-type Sb2Te3 film but using a single sputtering target
yielded +110µV/K and 1.3 mW/K2.m for their Seebeck coefficient and power factor
respectively. The optimized 10µm films are subsequently fabricated in parallel using
separate n-type and p-type wafers and prepared using die bonding technique to form the
vertical µTEG. Characterization included measurement of the device performance as well
as SEM and EDX analysis. The power output as a function of the true temperature
difference were measured as high as 1 mW for a vertical μTEG with ~13.8 mm2 footprint
and device ΔT of ~7.5 K 6. From manufacturing perspective, the fabrication process flow
of the second-generation chip-scale TEG device is presented. The design of the μTEG is
based on the pyramid architecture, where the thermoelectric elements are deposited and
patterned along a polyimide slope allowing longer effective leg length for higher output
performance. Future work as shown in section 5.4, the TEG devices will be subjected to a
series of stress-related tests to assess reliability performance under field conditions such
as high humidity and high temperatures.
94
5.3.1 Future Work
Post fabrication, the TEG devices will be subjected to a series of aging tests (stress tests)
to evaluate the reliability performance under high humidity and high temperature
conditions. The measurements of the TEG devices will be recorded pre and post each stress
using the following aging test standards: Solder Heat Resistance (SHR), Temperature
Cycling and Unbiased Highly Accelerated Stress Test ( uHAST) and Autoclave. A detailed
description of these aging stress tests is presented below.
5.3.1.1 Solder Heat Resistance
Solder Heat Resistance (SHR) is primarily used to evaluate the ability of a device to
withstand thermal stresses from the soldering process. It is commonly known as a
“preconditioning” step and includes three conditions: 24-hour Bake, Soak and three
passes (3x) of reflow. Based on the moisture sensitivity level (MSL) obtained from spec
J-STD-020 65, the relative MSL3 uses a soak duration is 192 hours at 30°C with 60%
Relative Humidity (RH) to evaluate the thermal stress on the integrity of the device.
5.3.1.2 Temperature Cycling
Temperature cycling test is conducted for the purpose of determining the resistance of
solid-state devices to exposures at extreme high and low temperatures. Changes in
electrical characteristics and even permanent physical damage is likely to occur during
temperature cycling, principally from mechanical stress caused by thermal expansion and
contraction. Figure 5.3 shows a typical profile for the temperature cycle test condition.
95
For this stress, -65°C/+150°C test condition C is used per JEDEC Standard JESD22-
A104E 66. The expectation is to ensure there are no issues with thermal cycling.
Figure 5.4: Representative temperature profile for the thermal cycle condition 66.
5.3.1.3 Unbiased Highly Accelerated Stress Test
uHAST is an unbiased test that utilizes humidity and temperature under non-condensing
conditions to accelerate moisture penetrations through the material. Typical uHAST
conditions applied in such test is 96 hours at 85°C/85% RH.
5.3.1.4 Autoclave
Autoclave (AC) test is performed to evaluate the device’s ability to withstand extreme
temperatures and humidity conditions. Typical AC conditions include 96 hours at +121°C,
100% RH and two atmospheres of pressure. Such conditions accelerate the penetration of
moisture along the interface of the thermoelectric legs.
96
Appendix A. Fabrication and Characterization of
Bi2Te3-Based Chip-Scale Thermoelectric Energy
Harvesting Devices
Authors
Jane Cornett*, Baoxing Chen, Samer Haidar, Helen Berney, Pat McGuinness, Bill Lane,
Yuan Gao, Yifan He, Nian Sun, Marc Dunham, Mehdi Asheghi, Ken Goodson, Yi Yuan,
Khalil Najafi
(* Corresponding Author)
A.1. Introduction
Thermoelectric (TE) energy harvesters make use of the Seebeck effect: the phenomenon
by which materials convert a temperature gradient into an electric potential. In this work,
we report on the fabrication and characterization of chip-scale thermoelectric energy
harvesting devices. The TE energy harvesters presented here are targeted towards
industrial applications close to room temperature—generating enough power from a
temperature drop of ~10°C to power a wireless sensor node. We will present details on
device design and process development, as well as the results of extensive device
characterization. Finally, we will discuss planned process improvements for next
generation devices. While we have explored several different device architectures and
thermoelectric materials, in this work we focus on devices based on n-type and p-type
bismuth telluride (Bi2Te3) with a vertical device architecture. Bismuth telluride-based
thermoelectric materials were chosen for their excellent room-temperature transport
properties.1 The vertical structure, described in detail below, is typical of many devices
97
in the literature 2–5 as well as commercial modules. Optimization of the leg geometry
and device fill factor for these devices was done previously, and is reported in Ref. 6.
A.2. Methods
A cross-sectional schematic of the device architecture is given in Fig. 1. During
application, an external temperature gradient is maintained between two Si wafers with
heat flowing vertically along the thermoelectric elements (labeled N and P). An electric
potential is established in each of the thermoelectric elements in response to an applied
temperature gradient. The total device voltage is a sum of the Seebeck voltages created in
the array of legs, which are thermally in parallel and electrically in series. Highlights
from the process flow for wafer fabrication of the Bi2Te3-based vertical structure devices
are as follows:
1. Electroplate Au interconnect
2. Spin and pattern thick photoresist for lift-off of Bi2Te3
3. Sputter deposit n-type (p-type) Bi2Te3
4. Sputter deposit Bi
5. Lift-off to remove photoresist, patterning n-type (p-type) Bi2Te3 and Bi
After the wafer fabrication is finished, the wafers are diced and die-bonded using a flip-
chip bonding tool. A set of devices with varied feature sizes and numbers of
thermoelectric elements was built following
98
Figure 1. Cross-sectional schematics of the vertical Bi2Te3-based device architecture
discussed here.
Device performance characterization of the Bi2Te3-based devices was completed by
sandwiching the device between two large copper blocks; a temperature gradient was
generated and controlled by heating one block and cooling the other. The magnitude of
the temperature drop across the device was determined using a QFI infrared microscope,
and confirmed using temperature readings from thermocouples imbedded in the copper
blocks. Current-voltage characteristics were collected throughout temperature cycling by
probing pads on the devices.
In addition to performance characteristics, scanning electron microscopy (SEM) and
energy dispersive x-ray (EDX) analysis was completed on the thermoelectric devices.
This included top-down imaging of uncapped devices (for determining the cross-sectional
area of the active materials post-bond), as well as cross-sectional imaging (performed
after filling the devices with epoxy and mechanically polishing to expose the active
materials).
99
A.3. Results:
An example set of data measured for a single device is shown in Fig. 2. Measurements
were performed for a set of load resistances between 10Ω and 10kΩ, and for a range of
cross-device temperature gradients from_1 to 7.5_C. Current–voltage characteristics are
given in Fig. 2a, while the power out as a function of load resistance is shown in Fig. 2b.
Open circuit voltage and power output increases monotonically with the temperature
drop, or DT, across the device. In addition, maximum power is achieved under essentially
matched load conditions, independent of ΔT; the total device resistance in this case was
close to 260 Ω. The maximum power, which follows the expected quadratic dependence
on ΔT, is plotted in Fig. 2c.
Figure 2. Device performance data collected for a single TEG: (a) Load voltage as a
function of current and (b) power out as a function of load resistance for several
magnitudes of temperature gradient across the device. Maximum power as a function of
temperature gradient is shown in (c).
SEM images of one of the thermoelectric devices are shown in Fig. 3. The image in Fig.
3a was taken of the active area of the device after removing the top die. The n- and p-type
Bi2Te3-based thermoelectric elements as well as the top and bottom interconnects can be
clearly seen, and there is minimal deformation due to the bonding process. The images in
100
Fig. 3b and c are cross-sectional views taken after mechanical polishing. Figure 3b
includes a pair of n- and p-type legs, indicating slight deformation to the n-type leg. The
image in Fig. 3c was taken at the interface of the top Au interconnect and the n-type
Bi2Te3 leg, showing voids in the bond interface. Finally, an EDX map taken at the bond
interface is shown in Fig. 4. In addition to the expected active materials in the device
(bismuth Bi, tellurium Te, gold Au), significant oxygen (O) is found in the interface
layer, indicating a non-optimized bond process.
Figure 3. SEM images of a Bi2Te3-based device fabricated at Northeastern University. (a)
Image is taken at an angle, with the top Si substrate removed to show the TE legs. (b,c)
Images taken in cross-section after mechanical polishing.
Figure 4. EDX map of the bond interface of a Bi2Te3-based device fabricated at
Northeastern University. Individual elemental maps are shown on the left, and
superimposed on the right.
101
Leveraging on what was learned from complete characterization of the devices described
above, process development is currently underway for fabrication of second-generation
thermoelectric energy harvesters. Process improvements include: (1) reduction in contact
resistance between the Au interconnects and the Bi2Te3 through optimized bonding, (2)
improvements to the lift-off photoresist process for better Bi2Te3 leg profile and (3)
increased thickness of the Bi2Te3.
A.4. Conclusion
We have demonstrated fabrication of chip-scale thermoelectric devices through
collaborative work with several universities. The active thermoelectric materials in these
devices were based on Bi2Te3, and the device architecture (shown in Fig. 1) is a standard
vertical structure. Characterization included measurement of device performance as well
as SEM and EDX analysis. Ongoing work focuses on the process improvements
mentioned above, as well as exploration of other device architectures.
A.5. References
1. H.J. Goldsmid, A.R. Sheard, and D.A. Wright, Br. J. Appl. Phys. 9, 365 (1958).
2. M.-Y. Kim and T.-S. Oh, J. Electron. Mater. 42, 2752 (2013).
3. K.-J. Shin and T.-S. Oh, J. Electron. Mater. 44, 2026 (2015).
4. J.-P. Fleurial, G.J. Snyder, J.A. Herman, P.H. Giauque, W.M. Phillips, M.A. Ryan, P.
Shakkottai, E.A. Kolawa, and M.A. Nicolet, in 18th International Conference on
Thermoelectrics(1999).
5. L.W. da Silva, M. Kaviany, A. DeHennis, and J.S. Dyck, in 22nd International Conference on
Thermoelectrics (2003).
6. M.T. Dunham, M.T. Barako, S. LeBlanc, M. Asheghi- Roudheni, B. Chen, and K.E.
Goodson, Energy 93, 2006 (2015).
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Appendix B. Experimental Characterization of
Microfabricated Thermoelectric Energy Harvesters for
Smart Sensor and Wearable Applications
Authors
Marc T. Dunham*, Michael T. Barako, Jane E. Cornett, Yuan Gao, Samer Haidar, Nian
Sun, Mehdi Asheghi, Baoxing Chen, and Kenneth E. Goodson
(* Corresponding Author)
B.1. Introduction
Thermoelectric energy harvesting technology, which uses the Seebeck effect to convert
thermal gradients into electrical potential, is poised to take advantage of the nexus
between advances in microfabrication technology and the widespread demand for small
low-power devices such as autonomous sensors in the Internet of Things (IoT) and
wearable electronics spaces. Thermoelectric generators (TEGs) have been manufactured
on the mm- to cm-scale for thermal energy conversion in the Watts to kilo-Watts-electric
range since the 1950s for niche applications in the aerospace and transportation
industries. [1–4] However, developments in microscale fabrication technologies since the
1990s have enabled a push toward small form factor “micro” thermoelectric generators
(μTEGs) assembled by patterned additive manufacturing such as physical vapor
deposition [5,6] or electrodeposition. [7–10] These approaches allow for a very high
thermocouple density (> 1000 cm-2) and can be optimized [11] to reach voltages on the
order of ~1 V for small temperature gradients (e.g. < 10 K). These voltages enable the
103
efficient use of power management circuitry [12] to buffer transients in the thermoelectric
system from temperature fluctuations or to trickle-charge a battery or capacitor for
periodic high-current discharge bursts (e.g. low duty cycle wireless transmissions). [10]
Microfabricated TEGs produced in a streamlined wafer-scale process offer a cost-
effective, small form-factor, and maintenance-free alternative to battery-powered or hard-
wired devices that may be impractical to re-access after installation.
Significant early efforts in the fabrication of microscale TEGs include the deposition of
Bi2Te3-based materials by magnetron sputtering by Stordeur and Stark onto thin
substrates which were then diced and arranged in a stack to form a large thermopile. [13]
Similar “in-plane deposition, stacked assembly” methods were later used by Stordeur and
Stark, [14] Kim, [15] and by Weber et al. in a coiled assembly. [16] In 1999, Fleurial et al.
demonstrated direct deposition of thermoelectric material to form vertical arrays of
thermoelements using photoresist templates, [9,10] motivating similar efforts in monolithic
vertical fabrication by Glatz et al. [7,8] and Cornett et al. [17] In addition to the use of
system-level analyses by Dunham et al. [11] which demonstrated the impact of a variety of
geometric design parameters on the performance of vertically-assembled μTEGs, this
work aims to improve upon the characterization techniques common in the literature
which are particularly susceptible to uncertainty from thermal contact resistances.
In this work we report the comprehensive design, fabrication, and experimental
characterization of wafer-processed μTEGs for thermal energy harvesting applications.
We use IR microscopy to measure the in situ device temperature gradient with micron-
scale spatial resolution. We simultaneously measure the temperature across the active
region of the device while recording current-voltage sweeps across a variable load
104
resistance to measure the full set of electrical output characteristics from the open circuit
through the optimal matched-load conditions. In addition to measuring load power versus
temperature gradient, we use this technique to determine device thermal resistance,
thermal efficiency, and a device-level thermoelectric figure-of-merit ZT.
B.2. Design of Microfabricated TEGs:
The design of μTEGs in this study is guided by the models and conclusions developed by
Dunham et al. [11] for the optimization of power density. The energy harvesters operate by
forming a thermal pathway from a heat source (e.g. hot water pipe surface, machinery
casing, or human skin) to a heat sink (e.g. ambient air or a cold solid surface). The
thermal resistance of the μTEG establishes a temperature gradient across an array of
thermocouples which are arranged thermally in parallel, such that each thermocouple sees
approximately the same temperature gradient, and electrically in series, such that the
Seebeck voltage generated by each thermocouple adds together for a large electrical
potential. A representative model of the μTEGs in this study, scanning electron
micrograph (SEM) of internal thermocouple array, example packaged assembly for water
pipe thermal harvesting, and illustrations of reduced 3D unit cell and 1D thermal resistor
network models are shown in Figure 1.
105
Figure 1. Illustration of size scales from individual thermoelement (μm) to device-level μTEG
(mm) to example system-level implementation (cm), with insets of SEM showing thermocouples,
thermoelements, and interconnects (center-left), and illustrations of reduced 3D unit cell and 1D
thermal resistance network models.
For a fixed thermal resistance between the heat source and heat sink external to the
generator (e.g. spreading and bond interface resistance on the hot side and heat sink on the
cold side), illustrated by Rt,c and Rt,h in the 1D resistor network in Figure 1, the power
output of an ideal μTEG is optimized when the thermal resistance of the active
thermoelectric region approximately equals the total sum of external thermal resistances.
The concept of “thermal load matching” does not necessarily hold for large temperature
gradients, where temperature-dependent properties, Peltier effects, and Joule heating
introduce significant non-linearities. [18] However, in the domain of small temperature
differences for energy scavenging applications it is a reasonable first-order approximation.
An optimal thermal resistance ratio occurs because the primary mechanism for increasing
thermal resistance (increasing the aspect ratio of the thermoelements, or individual leg of
106
a thermocouple) also increases the electrical resistance. As the ratio of internal to external
thermal resistance goes to infinity, the temperature difference across the μTEG
asymptotically approaches the source-sink temperature difference, while the electrical
resistance increases without bound. This is a one-direction optimization, meaning if the
external thermal resistance is known and fixed, the thermal resistance of the thermoelectric
region should be designed to match it. However, reducing the external thermal resistance
will always lead to an increase in power output as it increases the thermal gradient across
the generator, ΔTTEG, and electrical power generated is proportional to the square of this
temperature difference.
The relation for power delivered to an electrical load resistance matching the electrical
resistance of the generator, Re,TEG, is given in Equation (1), where STEG is the total Seebeck
coefficient including all thermocouples in series. While parasitic losses, primarily Peltier
heating and cooling from electrical current flow, in reality shift the optimal electrical load
resistance to be larger than the generator electrical resistance, the assumption of maximum
load power delivered at matched electrical loading conditions is reasonable for small ΔTTEG
and low device-level figure of merit ZT (discussed in Section 5.4).
( )2
2TEG TEG
load,matched
e,TEG e,TEG4 4
S TVP
R R
= =
(1)
The devices in this study are designed to be coupled to external thermal resistances
totaling approximately 5-10 K W-1. This range is intended to be representative of a solid
bond contact on the hot side and a high-performance natural convection heat sink,
radiation heat sink, or solid contact to a heat pipe on the cold side. The device thermal
resistance is calculated using a 1D resistor model, illustrated in Figure 1, accounting for
107
the series contributions of the silicon substrates, passivation layers, and thermocouple
region including air surrounding the thermocouples. Four different device geometries are
studied, plus one duplicate geometry which is die-bonded under higher pressure. Table 1
provides a summary of the device designs. Thermal resistances are calculated using an
average thermal conductivity of 1.3 W m-1 K-1 for Bi2Te3 and Sb2Te3 thin films formed
by physical vapor deposition (PVD). While stoichiometric single crystal material in
macroscale ingots is typically assumed to have thermal conductivity of ~1.6-2.0 W m-1 K-
1, [19,20] thin films are typically more thermally resistive (e.g. ~1.2-1.4 W m-1 K-1
measured for co-evaporated Bi2Te3 thin films [21]) due to defects and grain disorder. All
devices have a footprint of 4.3 mm x 3.2 mm, corresponding to the area of the larger
substrate in the illustration presented in Figure 1.
Device
#
# of
TCs
Thermoelement
height/width
[μm]
Average nominal
bond pressure on
thermoelements
[MPa]
Nominal
thermoelectric
layer thermal
resistance [K W-1]
Nominal device
thermal
resistance [K W-1]
1 700 10/30 44 5.6 6.9
2 900 10/30 44 4.4 5.6
3 1100 10/30 44 3.7 4.7
4 348 10/40 44 6.2 7.6
5 348 10/40 53 6.2 7.6
Table 4. Nominal design parameters for μTEGs in this study.
B.3. μTEG Fabrication
The μTEGs are fabricated on 3-inch <100> Si wafers coated with a 500 nm thick SiO2
insulation layer deposited via plasma-enhanced chemical vapor deposition. Separate n-
and p-type wafers are fabricated in parallel. Following the blanket SiO2 deposition, ~4
μm of Au (measured by SEM to be 3.2 μm on the n-type wafer and 3.9 μm on the p-type
108
wafer) is electroplated to form the interconnect layer. The wafers are then patterned with
a 15 µm thick lift-off photoresist layer (AZ-9620). The thermoelectric depositions are
done at room temperature in an RF-sputtering physical vapor deposition (PVD) system.
The n-type thermoelectric material is deposited by co-sputtering from Bi2Te3 (60 W) and
Te (10 W) targets, while the p-type film is sputtered from a single Sb2Te3 target (60 W).
The additional Te target for deposition of the n-type material is used to supplement low
Te compositions consistently observed using energy-dispersive x-ray spectroscopy
(EDX) when using a single Bi2Te3 target. The power factor of our test p-type films show
less sensitivity to variations in Te content, and a supplemental target is not required. The
deposited Bi2Te3 and Sb2Te3 films are approximately 8 µm thick. In both cases, 10 nm of
Cr is used to promote adhesion between the thermoelectric material and the Au.
Following the thermoelectric film depositions, 1 μm of Bi is sputtered to form a eutectic
with Au during die bonding. Lift-off of the Cr/Bi2Te3/Bi (Cr/Sb2Te3/Bi) stack is
performed by stripping the AZ-9620 in acetone for several hours. After lift-off, the
wafers are annealed under nitrogen (to prevent oxidation) at 250 °C for 30 minutes,
which brought the films closer to ideal stoichiometry and also reduced the electrical
resistivity. Prior to bonding, the wafers are diced into individual die, with the cap die
slightly smaller to expose electrical contact pads on the device die below.
Bonding is performed using a SETNA FC150 flip-chip bonder. In a typical
thermocompressive bond recipe, the die are ramped up to 350 °C under N2 flow, with
bonding force applied for a total of 150 seconds. The bond process accounts for
approximately 10% of the total thermal budget including annealing, and we do not expect
109
it to significantly alter the material properties. Annealing is performed as a separate
process to enable blanket film characterization after annealing and prior to bonding. A
eutectic bond is formed between the Bi layer on the n-type (p-type) wafer and the Au
interconnect on the p-type (n-type) wafer. The bonding force varies depending on the
particular device fill factor, with the nominal pressure on the thermoelectric legs
relatively close to 44 MPa.
The deposited thermoelectric materials were characterized via X-ray diffraction (XRD)
and scanning electron microscopy (SEM), with the film compositions determined by
EDX. The thermoelectric properties of the films were determined using an Ecopia HMS-
3000 Hall measurement system and a Seebeck measurement system based on a 4-probe
differential measurement technique. Electrical contact resistances between the
thermoelectric materials and Au depositions were measured using patterned Kelvin
structures, and represent an average, effective contact resistance that includes the
adhesion and bonding materials in the interfacial regions (Cr and Bi). A summary of the
results of these measurements in given in Table 2.
Material S [μV K-1] ρ [Ω m] PF [mW m-1 K-2] ρcontact,Au [Ω m2]
Bi2Te3 (n-type) -102 1.56 x 10-5 0.7 9.42 x 10-10
Sb2Te3 (p-type) +110 0.90 x 10-5 1.3 3.42 x 10-8
Au -- 2.6 x 10-8 -- --
Table 5. Measured properties for deposited thermoelectric and interconnect materials.
110
B.4. Device Characterization
The most challenging aspect of system-level characterization for μTEGs is determining
the operating temperature gradient across the generator in the presence of multiple
parasitic resistances and interfaces. The small contact surfaces and impracticality of using
a high-conductance permanent bond in the test fixture lead to large thermal contact
resistances at the boundaries. For example, a representative thermal resistivity for an
aluminum/aluminum interface with Dow Corning 340 grease and ~100 kN m-2 contact
pressure may be approximately 7 x 10-6 m2 K W-1. [22] In this study, the larger contact
face is approximately 4.3 mm x 3.2 mm and the smaller contact face is approximately 3.3
mm x 3.2 mm, leading to total thermal contact resistances above 1 K W-1, which is
around 20% of the design thermal resistance of the μTEGs. Further, the exterior silicon
surfaces of these devices are unpolished, which could easily increase the total contact
resistance to the magnitude of the generator resistance itself. For these reasons, a more
precise thermal measurement technique is needed than the conventional approach of
embedded thermocouples in adjacent source/sink materials, which grossly over-predicts
the temperature gradient experienced by the functional part of the device.
B.4.1. Infrared Microscopy
We use an IR microscope (QFI InfraScope II) to directly measure the through-plane
device temperature gradient with a spatial resolution of ~20 microns per pixel. The
emissivity at the surface of the undoped silicon substrate edges is increased by applying a
thin coating of black liquid electrical tape (Gardner Bender LTB-400), observed under an
111
optical microscope to be ~10-20 μm thick after solidifying. The IR microscope uses a
pixel-by-pixel emissivity calibration feature to accurately convert the emission from
surfaces to temperature without assuming a spatially-homogeneous value of emissivity.
Further details of this technique have been previously published. [23,24] The calibrated
emissivity of the coating is typically observed to be 0.88-0.94. This particular coating is
chosen for the μTEGs and reference layers instead of graphite lubricant spray [25] to avoid
electrical shorting of the device or boron nitride spray [26] because of difficulty masking
the narrow device edges and a concern for possible thermal shunting across the substrate
gap. Boron nitride spray is used to increase the emissivity of the copper block surfaces, as
it can cover a large area with acceptable uniformity and thermal shunting on the copper
blocks is not a concern. Finite element models are used to verify both that the film does
not introduce appreciable thermal shunting and that the apparent surface temperature is
not be compromised by the thin resistive film. A piece of nonporous alumina ceramic
(96-99.8% alumina composition purchased from McMaster-Carr) with known thermal
conductivity of 27 W m-1 K-1 cut to the footprint dimensions of the μTEG is similarly
coated with the black liquid tape on the measurement edge, placed in series with the
device, and used as a heat flux sensor. A custom heating and linear compression
apparatus is used to support the device under the infrared objective lens (see Figure 2a
and 2c). A miniature button load cell is placed in-line with the compression apparatus to
ensure a consistent force of ~18 N during characterization. On the smaller, 3.2 mm x 3.3
mm face, substrate this provides a pressure of approximately 1.7 MPa which is in a
reasonable range for a grease-joined thermal interface. [22] For the smallest measured fill
fraction of 0.18, this translates to ~9.5 MPa at the individual legs, which is well below the
112
minimum 44 MPa applied for bonding. During the experiment, copper blocks are heated
by resistive Joule heaters with water line connections on one side. Thermocouples (K-
type) are embedded into the copper blocks to monitor the reservoir temperatures.
Electrical contact is made to 1 mm2 gold contact pads on the device with beryllium-
copper probe tips to minimize electrical contact resistance. Comparative tests with and
without probe tip contact to the device demonstrate insignificant thermal losses through
the probes.
Figure 2. (a) Schematic of thermal measurement structure, (b) electrical measurement
circuit diagram, (c) photograph close-ups of thermal measurement structure, and (d)
representative plot of temperature vs. position from infrared microscope data. We attribute
the visible temperature fluctuations near interfaces to error induced by large spatial
gradients in calibrated emissivity, for example when the coating has been damaged.
Throughout the experiment, open-circuit device voltage and copper block temperature is
recorded at a frequency of 4 Hz using a NI cDAQ-9174 chassis with modules for voltage
(NI-9207) and thermocouples with cold-junction compensation (NI-9213). Data are
113
visualized and recorded with Labview. The system is brought to steady state at
temperatures intended to give a range of temperature differences across the μTEG from
ΔTTEG = 0 to ~10 K. The steady state criterion used is a total fluctuation of less than 0.2
K in the thermocouple readings of each copper block and their difference over a 5-minute
period. After reaching steady state conditions, an infrared image is acquired averaging
over 20 frames to reduce noise. For IR imaging, the load circuit is left open to prevent
Peltier heating, although this is estimated from measured V-I curves to have a negligible
contribution relative to the heat input (< 7% for minimum load resistance, and ~3% at
maximum power point). After reaching steady state and recording the IR image, the
μTEG is connected to a circuit containing a 10 kΩ potentiometer to sweep a range of load
resistances. Voltage is read across a fixed low-resistance sense resistor (4.8 Ω) to
determine current and potentiometer resistance simultaneously, and the voltage across the
sense resistor in series with the potentiometer is recorded as load voltage. The electrical
resistance of the μTEG at room temperature is measured using a modified Harman
method technique. [25] The sense resistor value must be less than the nominal electrical
resistance of the device to present a peak in the load power vs. load resistance curve, as
we generally expect the maximum power point to occur near matched electrical loading,
but large enough to permit stable measurements for small currents at the higher range of
the resistance sweep. For each load resistance, electrical data are averaged over 20
acquisitions (i.e. 5 seconds).
For analysis, a rectangular region of interest spanning the device and several millimeters
of each copper block is selected, and the temperature averaged in the direction
114
perpendicular to heat flow to reduce noise. By using the extracted heat flux and the
midpoint temperature of each device substrate, we extrapolate to determine the
temperatures at the outer surfaces of the device. Further details and validation of this
approach, as well as discussions of uncertainty, are provided in the Supplemental
Information. A representative set of temperature profiles, best fits, and extrapolation lines
is shown in Figure 2d. The temperature drops due to thermal boundary resistance (TBR)
between adjacent layers are directly observable using IR temperature mapping and
illustrate the difficulty in relying on external thermocouple measurements for
characterization. The measured values for open circuit voltage and maximum load power
as a function of extracted temperature difference across the μTEG are plotted in Figure 3a
and 3b.
115
Figure 3. Measured values for (a) μTEG open circuit voltage and (b) maximum load
power as a function of the μTEG temperature difference extracted using the infrared
microscopy methodology. Solid lines are linear and quadratic best fit lines. Plots of (c)
voltage vs. load current with fit lines and (d) load power vs. load resistance with visual
aid lines. All data are shown at the ΔTCu ≈ 20 K steady state condition. Vertical dashed
lines in (b) show the μTEG electrical resistance as extracted from data in (c).
The trends shown in Figure 3a and 3b are consistent with thermoelectric device models,
exhibiting a highly-linear dependence of open circuit voltage on temperature difference
(the slope defines the effective Seebeck value), and a quadratic dependence of load power
on temperature difference ΔTTEG. For an externally-imposed temperature difference and
all other parameters fixed, an increasing density of thermocouples will increase the open
circuit voltage and the load power from the generator. [11] This is apparent in the sequence
of devices with 700, 900, and 1100 thermocouples (Devices 1-3). For the two identical
devices bonded using different nominal bonding pressure, Device 4 (bonded at 44 MPa)
demonstrates a higher open circuit voltage but lower output power than Device 5 (bonded
at 53 MPa). This was found to be the result of deformation of the internal structure (see
Section 4.2). At the higher bond pressure, the legs were crushed to a lower aspect ratio,
leading to lower thermal and electrical resistances. Since Figure 3 only considers a fixed
temperature difference across the device and not the heat load, the 53 MPa bonded device
116
appears to produce more power despite having a lower device Seebeck value. A summary
of measured and extracted parameters for all five devices is provided in Table 3. Values
of device Seebeck STEG and device Seebeck per thermocouple STEG,TC are extracted from
the data in Figure 3. We note that the parameter STEG,TC is not the net material Seebeck
coefficient SBi2Te3 – SSb2Te3, but rather the Seebeck voltage of the entire device (open
circuit voltage divided by ΔTTEG, divided by number of thermocouples nTC). Therefore, it
is impacted by the relative contributions to thermal resistance in the device of the active
and inactive regions of each μTEG and is always less than the net material Seebeck
coefficient because it includes parasitic temperature drops through the substrates and
other materials not contributing to the Seebeck voltage. The net material Seebeck
coefficient (231 μV K-1) is extracted using the method detailed in Section 5.3.
Device 1 Device 2 Device 3 Device 4 Device 5 # of TCs 700 900 1100 348 348
TE bond pressure [MPa] 44 44 44 44 53
STEG [mV K-1] 94 114 149 59 48
STEG,TC [μV K-1 TC-1] 134 127 135 170 137
Re,RT [Ω] 166 211 255 246 59
Re,UT [Ω] 164 207 252 226 54
Re,TE [Ω] 37 53 71 20 7.5
Re,IC [Ω] 20 23 25 12 10
ρc [Ω m2] 7.9 x 10-11 6.7 x 10-11 7.2 x 10-11 3.7 x 10-10 1.1 x 10-10
Nominal / imaged leg
height [μm]
8.2 / 4.4 8.2 / 4.4 8.2 / 5.3 8.2 / 6.2 8.2 / 3.5
Nominal / imaged leg
width [μm]
30 / (45.2 ±
3.5)
30 / (43.0 ±
1.8)
30 / (45.0 ±
3.2)
40 / (51.5 ±
3.3)
40 / (63.3 ±
6.0)
Nominal / imaged FF 0.12 / 0.28 0.15 / 0.32 0.19 / 0.43 0.11 / 0.18 0.11 / 0.27
Rth,TEG [K W-1] 2.4 ± 0.5 1.7 ± 0.2 1.5 ± 0.2 3.0 ± 0.4 2.2 ± 0.3
ΔT
Cu ≈
20
K
ΔTCu [K] 19.9 19.9 20.1 19.7 19.7
ΔTTEG [K] 4.1 4.2 3.7 5.7 4.2
Q [W] 1.7 2.5 2.6 1.9 1.9
Pload,max [mW] 0.22 0.26 0.29 0.12 0.15
Pa,load,max [mW cm-
2]
1.6 1.9 2.1 0.9 1.1
ηmax 1.29 x 10-4 1.06 x 10-4 1.15 x 10-4 6.21 x 10-5 7.98 x 10-5
ηCarnot 0.012 0.012 0.011 0.016 0.012
ZT 0.044 ± 0.018 0.035 ± 0.008 0.043 ± 0.007 0.015 ± 0.004 0.027 ± 0.006
Table 6. Summary table of measured and extracted device parameters.
117
The thermocouple-normalized Seebeck value STEG,TC is helpful in interpreting the data.
For Devices 1-3 bonded using the same pressure per leg, the value remains relatively
constant. However, there is a significant difference between the values obtained for
Devices 4 and 5 which underwent different bonding pressures. Since the deformation in
Device 5 affected only the active thermoelectric region and not the silicon substrates, the
ratio of thermocouple-to-device thermal resistance is significantly lower. This means that
for a given temperature difference across the entire μTEG (including substrates), the
thermocouples in Device 5 see a smaller fraction of that gradient than do the
thermocouples in Device 4. The result is a larger Seebeck voltage, and consequently
larger STEG,TC, from Device 4 for the same temperature drop from substrate to substrate.
Using the measured load voltage, I-V profiles and load resistance curves are produced for
each μTEG. For comparison, the data for each device under the steady state condition of
ΔTCu ≈ 20 K (temperature difference of the Cu blocks measured by embedded
thermocouples) are shown in Figure 3c. The minimum load resistance (Re,sense plus a
small contribution from the nominally-zeroed potentiometer) can be subtracted from the
slope of the voltage vs. load current data shown in Figure 3c to calculate the electrical
resistance of the μTEG under test, Re,UT. There is no significant deviation in device
electrical resistance between room temperature and test conditions, although the electrical
resistance generally trends downward with increasing temperature.
We measure maximum load power levels on the order of hundreds of μW to single mW
for a device temperature difference ΔTTEG < 10 K. A similar μTEG would typically be
integrated with a power management circuit, in which a capacitor or other energy storage
medium would be trickle-charged by the generator and power could be provided to
118
functional components with regulated voltage. This type of circuitry for μW to mW
power sources is typically reported with approximately 60% end-to-end conversion
efficiency in the literature [27–30]. Tan and Panda performed calculations for operational
lifetime of a fully autonomous wireless sensor node assuming 1 mW average power
consumption. [31] Assuming this is the average power consumption including typical
losses in a power management circuit, the ΔTTEG values required for Devices 1-5 to
produce 1 mW are 8.8 K, 8.1 K, 6.9 K, 16.3 K, and 10.5 K respectively. Depending on
the data rate, RF transmission technology, and operational duty cycle, power
requirements can be significantly reduced. Zhang et al. [32] developed an
electrocardiogram module powered by body heat and a TEG+power management circuit
which wirelessly transmits data in multiple modes. In raw-data transmit mode at 200kbps
and 100% duty cycle operation, the module consumes 397 μW. In “AFib detection
mode,” designed only to transmit a short buffer of recent data on the occurrence of an
unusual atrial fibrillation event, the module consumes just 19 μW. The ΔTTEG required for
Device 3 to run these two extreme modes would be 4.3 K and 1.0 K, respectively.
B.4.2. Thermal Resistance and Structural Imaging
Determining an accurate temperature drop across thermoelectric generators is critical for
a true power versus temperature difference measurement. However, to simulate device
performance accounting for realistic thermal boundary conditions such as contact and
heat sink resistances, we must have knowledge of the μTEG’s thermal resistance.
119
Measurements of the μTEG thermal resistances using the Al2O3 reference layer are
consistently lower than anticipated from available models [11] and assumed parameters.
After repeated tests we hypothesized that the force from die bonding may have reduced
the aspect ratio of the thermoelements, resulting in shorter, wider legs than the nominal
design and lowering both the thermal and electrical resistances. This was confirmed by
optical microscopy after filling the devices with epoxy for mechanical stability and
mechanically polishing to reveal a row of thermoelements. Average and standard
deviation of leg dimensions obtained from cross-sectional imaging of a row of
thermocouples are compared to nominal assumptions for each device in Table 3. Values
for leg widths are obtained by measuring and averaging the widths of a full row of
individual thermoelements, while leg heights were calculated by measuring the spacing
between the substrates and subtracting the measured thicknesses of the Au interconnect
layers (3.2 and 3.9 μm). It is particularly noteworthy that Device 5 (bonded at a
thermoelement pressure of 53 MPa) maintained full electrical integrity across 348
thermocouples despite severe deformation (shown in Figure 4b). This is a positive
observation from the standpoint of device robustness but must serve as a warning that
strong deformation can occur for a relatively small increase in applied pressure without
an obvious indication of device failure.
120
B.5. Determination of material and device properties
B.5.1. Thermoelectric material thermal conductivity
The average thermal conductivity of the p- and n-type thermoelectric materials can be
estimated using the calculated thermal resistances and imaged leg dimensions from Table
3 in a numerical model to fit across the five studied devices. The numerical model used is
a 1D thermal resistor network model. [11] Assuming 1 x 10-7 m2 K W-1 thermal contact
resistance at the Bi2Te3/Au and Sb2Te3/Au interfaces, [20] a least-squares fit of 1.3 W m-1
K-1 is determined for the average thermoelectric material thermal conductivity. This value
compares well with the thin film thermal conductivity range of ~1.2-1.4 W m-1 K-1
previously measured for co-evaporated Bi2Te3. [21] The measured experimental thermal
resistances are plotted with the values calculated using the fit value for thermal
conductivity in Figure 4a and 4b.
Figure 4. Comparison of experimental values with numerical values using fit thermal
conductivity of 1.3 W m-1 K-1 for the average TE material value. Figure (b) shows the impact of
higher bonding force resulting in strong deformation of the thermoelements in Device 5.
121
B.5.2. Thermoelement/interconnect electrical contact resistance
Using the device electrical resistances and imaged leg dimensions, we can estimate the
interconnect resistance contribution and the electrical contact resistance of the Bi2Te3/Au
and Sb2Te3/Au interfaces. We note that this approach yields an effective electrical contact
resistance, which averages the resistance at both ends of the thermoelement and includes
the interfacial regions (Cr on one end and Bi-Au eutectic on the other). With an average
p- and n-type electrical resistivity of 1.2 x 10-5 Ω m, measured Au deposition resistivity
of 2.6 x 10-8 Ω m, we calculate the parasitic electric contribution and resulting electrical
contact resistance as:
TC leg
e,TE TE,avg
leg
2n lR
A=
(2)
e,ICs TC IC
IC
12R n
t FF=
(3)
e e,TE e,ICs
contact leg
TC4
R R RA
n
− −=
(4)
The electrical resistance of the interconnects in Equation (3) is derived assuming a square
grid of thermoelements, and an average travel distance for electrical current through each
interconnect equal to the center-to-center spacing between the elements. The TE/IC
electrical contact resistance is consistently less than 1.0 x 10-10 Ω m2 for Devices 1-3,
while it jumps by approximately a factor of four in Device 4. The exact reason for this
increase is not known, as we initially assumed that the larger (nominally) 40 μm x 40 μm
thermoelement cross-sections would form a better thermocompression bond and possibly
122
reduce electrical contact resistance. However, the opposite seems to be true and could
indicate issues with surface roughness or nonuniformity over larger bond areas. All
calculated electrical contact resistances are at least a factor of two lower than the values
measured on the n- and p-type wafers prior to bonding. We attribute this change to
improved electrical contact due to the high temperature/high pressure bond process. We
also note the significant estimated contribution from the Au interconnects which, despite
high electrical conductivity and relatively thick ~4 μm height, essentially match the
electrical resistance due to the thermoelectric legs. For higher aspect ratio legs, the ratio
of interconnect resistance to TE leg resistance should decrease. Devices 1 and 5 possess
comparable fill fraction after bonding (0.28 and 0.27) and illustrate the conclusion drawn
in [11] that for a given fill fraction it is beneficial to use a larger number of legs with
smaller cross-section, in part because the ratio of TE material resistance to total parasitic
resistance will be higher. Estimated contributions from the TE material, interconnects,
and TE/interconnect contacts are illustrated in Figure 5. The large fraction of total
resistance due to parasitics represents significant potential for device optimization. For
example, if the contact resistance of Device 3 could be improved by a factor of 2, total
electrical resistance would decrease from 252 Ω to 174 Ω, and maximum load power for
ΔTTEG = 5 K would increase from 290 μW to 420 μW.
123
Figure 5. Illustration of the estimated component resistances in each μTEG. The relative
percentage of each contribution to total electrical resistance for each device is listed
alongside the bar graphics.
In this work we have assumed that transport in the PVD Bi2Te3 and Sb2Te3 films is
isotropic, taking values measured in-plane (parallel to the Si substrate) to be
approximately equal to those out-of-plane (along the TE legs). This assumption is
supported by XRD spectra from these materials, which show relatively weak texturing
and no preferential alignment along 00l crystal plane that is often seen in such films.
While the electrical and thermal conductivities of highly-textured Bi2Te3 and Sb2Te3
exhibit strong anisotropy, [3,33] the transport properties of polycrystalline Bi2Te3-based
materials with a low degree of grain orientation are essentially isotropic. [34,35] Should the
properties be anisotropic, the primary impact on the present analysis would be in the
calculation of electrical contact resistance. In the case of highly-ordered Bi2Te3-based
films, the electrical conductivity anisotropy ratio could be as high as four, [33] and the true
contribution of the thermoelements to electrical resistance could differ from what is
124
reported in Table 3. Since the calculated contribution of electrical resistance from the
thermoelements is subtracted from the measured device electrical resistance to determine
the contact resistance, a change in resistivity due to anisotropy could impact these values.
B.5.3. Material Seebeck coefficient and load power modeling
We can calculate the net Seebeck coefficient of an individual thermocouple independent
of the material measurements performed on the deposited wafers by using information
obtained from IR and optical microscopy. Since the interior geometry and material
thermal conductivities are now known, we can calculate the thermal resistance Rt,TE of the
active thermoelectric region (thermocouples in parallel with air filler material). By using
the measured temperature difference across the generator ΔTTEG and the calculated
thermal resistance of the μTEG, Rt,TEG,modeled, the temperature difference across the
thermocouple region is found using a voltage divider analog:
t,TE
TE TEG
t,TEG,modeled
RT T
R =
(5)
The device-level Seebeck coefficient per thermocouple STEG,TC from Table 3 is divided
by the thermal resistance ratio Rt,TE / Rt,TEG,modeled to obtain the net material Seebeck
coefficient, with uncertainty determined by the uncertainties in ΔTTEG. The net Seebeck
values are plotted in Figure 6a. The average value is 231 μV K-1, or 9% higher than the
value of 212 μV K-1 measured from the pre-bonded wafers. The higher value is used with
the other parameters determined in this study to model maximum load power versus
ΔTTEG. We compare measured maximum load power values with model outputs in Figure
6b, which show good agreement (less than 10% deviation from measured values).
125
Figure 6. (a) Comparison of extracted material net Seebeck coefficient with pre-bond
wafer measured value (212 μV K-1) and average of extracted values (231 μV K-1), and (b)
Modeled (lines) and measured (markers) maximum load power vs. ΔTTEG. The model
assumes the average extracted material net Seebeck coefficient value of 231 μV K-1.
B.5.3. Device ZT from thermal efficiency
With the thermal conductivity data extracted from measured device resistances, we can
estimate an average material zT using the following relation:
2
net
avg
avg avg4
SzT T
k = (6)
Using values of Snet = 231 μV K-1, kavg = 1.3 W m-1 K-1, ρavg = 1.23 x 10-5 Ω m, and Tavg =
70°C, we obtain an average material zT of 0.29. Although electrical and Seebeck
measurements were performed in-plane and thermal conductivity is effectively out-of-
plane, we reasonably assume the transport properties to be isotropic as described in
Section 5.2. Material properties Snet and ρavg were measured at room temperature, while
device characteristics were measured in the range of ~60-80 °C for increased IR
126
sensitivity. The μTEG electrical resistance was not observed to change significantly
between room temperature and the elevated characterization temperatures.
While material zT presents interesting information about the active thermoelectric
materials in the μTEG, we know that significant device-level losses motivate an analysis
at the system level. To compare the average material zT with an effective device-level
“ZT” accounting for thermal and electrical losses, we begin with the relationship for
maximum efficiency, [19] assuming that Tc / Th ~ 1 at small temperature differences:
max Carnot
1 1
1 1
ZT
ZT
+ −=
+ +
(7)
where ηCarnot is the Carnot efficiency. We can then solve algebraically for ZT, giving the
relation:
( )Carnot max
2
Carnot max
4ZT
=
− (8)
From use of the reference alumina material for obtaining thermal conductivity and the
measurement of maximum load power, we calculate the device efficiency and the
effective device-level ZT of Equation (8) as given in Table 3. In these calculations it is
assumed that variation of the electrical load resistance does not significantly affect the
heat flow through the device, Q , in which case the point of maximum load power
delivery is also the point of maximum thermal efficiency because η = Pload / Q and Q is
127
constant in this case. This assumption is supported by the relatively small Peltier heat
contribution.
From the data in Table 3, we can see that the higher electrical contact resistances
significantly reduce the device ZT values of all evaluated devices. Furthermore, the
impact of device design and fabrication conditions on the contribution of parasitic losses
make this ZT value geometry- and process-dependent. Devices 4 and 5 show the largest
reduction, with the losses in Device 4 coming primarily from high electrical contact
resistance and the losses in Device 5 coming primarily from the small thermal resistance
of the low aspect ratio thermoelements.
Taking the first term of the Taylor series expansion of Equation (8) about ηmax = 0 gives
the expression:
max
Carnot
4ZT
(9)
Assuming maximum power at matched electrical load, ηmax = Pmax / Q = ΔV2 / (4 × Re,TEG
× Q). The Carnot efficiency, assuming Tavg ≈ Th for small temperature differences, is
given by ηCarnot = ΔTTEG / Tavg. Combining terms we have:
22
e,TEG TEGmax
avg
Carnot TEGe,TEG
t,TEGavg
41
V V
R Q TZT T
T RRT
= =
(10)
Substituting the device-level Seebeck coefficient STEG = ΔV / ΔTTEG and μTEG thermal
conductance KTEG = 1 / Rt,TEG (with STEG and Rt,TEG reported in Table 3), we return to the
128
familiar form of the thermoelectric figure of merit at the device level, with electrical and
thermal losses lumped into the constituent parameters of Z:
( )2
TEG
lumped avg
e,TEG TEG
SZT T
R K=
(11)
It is often reported in the literature [36–38] that power delivery (and efficiency, depending
on the boundary conditions) in thermoelectric generators is maximized for an electrical
load resistance higher than the electrical resistance of the TEG, by a factor related to the
figure of merit as e,load,max e,TEG1R zT R= + . This observation differs from the common
assumption of load power being maximized when load resistance matches the internal
resistance of the power source and is due to the presence of the parasitic Peltier heating
and cooling produced when electrical current flows in the generator. In this study, a
negligible difference was observed between measured load power at Re,load,max using the
material zT of 0.29 compared to loads near the matched resistance Re,UT. This is because
in a real, non-ideal device, the effective device ZT must be used in order to account for
electrical and thermal losses. For Device 3, for example, using the material zT (0.29)
gives an optimal electrical load resistance of 286 Ω while the device ZT (0.043) yields
257 Ω, which is much closer to the measured Re,UT = 252 Ω. Maximum measured load
power was observed for Re,load ~ 251 ± 20 Ω, although measured power did not decrease
by more than 1% from the maximum value until Re,load ~ 320 Ω. In higher-ΔT
applications this effect becomes more significant, and the design of matched electrical
load conditions should be based on the effective device ZT rather than material zT.
129
B.6. Summary and Concluding Remarks
Microfabricated thermoelectric generators, or μTEGs, have the potential to provide
battery-free and wireless power to a growing number of low-power distributed sensor
modules. Use of thin film fabrication techniques make high thermocouple densities
possible, allowing load voltages on the order of 1 V from small temperature differences.
This work demonstrates the successful design and fabrication of a set of functional
μTEGs, and characterization using infrared microscopy for accurate determination of the
generator temperature gradient and thermal resistance independent of large thermal
contact resistances. Information from device cross-sections is used with measured
material properties to estimate the relative contributions to electrical resistance from
active and parasitic components, confirming conclusions from previous theoretical work
and illustrating pathways to significant performance enhancements through reduction of
parasitic electrical losses. A formula for a device-level figure of merit ZT is derived using
measured thermal efficiency, made possible by the use of the infrared microscopy
technique, which includes all thermal and electrical losses. Despite a modest average
material thermoelectric figure of merit zT ~ 0.3, load power levels above 1 mW for μTEG
temperature gradients as low as 7.3 K were produced that would easily satisfy power
requirements for a variety of wireless sensor nodes and other small devices.
B.7. Acknowledgements
This work was supported by Analog Devices, Inc. and the National Defense Science and
Engineering Graduate Fellowship (M.T.D. and M.T.B.)
130
B.8. Nomenclature
A Area (m2)
FF Fill fraction (-)
I Electric current (A)
k Thermal conductivity (W m-1 K-1)
K Thermal conductance (W K-1)
l Length (m)
nTC Number of thermocouple pairs
P Electric power (W)
PF Thermoelectric power factor (mW m-1 K-2)
Q Heat rate (W)
Re Electric resistance (Ω)
S Seebeck coefficient (μV K-1)
t Thickness (μm)
T Temperature (K)
TC Thermocouple
TBR Thermal boundary resistance
V Electric voltage (V)
zT Thermoelectric material figure of merit (-)
ZT Thermoelectric device figure of merit (-)
Greek
η Efficiency
ρ Electrical resistivity (Ω m)
ρcontact Area-specific electric contact resistance (Ω m2)
Subscript
a Area-specific
avg Average of n- and p-type material properties
c Cold side
Carnot Related to Carnot efficiency
e Electric
gen Generated by Seebeck effect
h Hot side
IC Interconnect
Joule Related to Joule heating effects
leg Related to a single thermoelectric leg
load Related to the connected electrical load
max Corresponding to maximum power and/or efficiency condition
meas Measured value
net Difference of n- and p-type material properties
Peltier Related to Peltier heating/cooling effects
RT Related to room temperature conditions
sense Related to sense resistor
TC Quantity normalized by number of thermocouples
TE Related to the thermoelectric material
TEG Related to the thermoelectric generator module
UT Related to conditions of μTEG under test
131
B.9. References
[1] J. Yang, T. Caillat, MRS Bull. 2006, 31, 224.
[2] S. LeBlanc, Sustain. Mater. Technol. 2014, 1, 26.
[3] T. M. Tritt, Annu. Rev. Mater. Res. 2011, 41, 433.
[4] J. Yang, F. R. Stabler, J. Electron. Mater. 2009, 38, 1245.
[5] H. Böttner, J. Nurnus, A. Gavrikov, G. Kühner, M. Jägle, C. Künzel, D. Eberhard, G.
Plescher, A. Schubert, K.-H. Schlereth, J. Microelectromechanical Syst. 2004, 13, 414.
[6] J. Cornett, B. Chen, S. Haidar, H. Berney, P. McGuinness, B. Lane, Y. Gao, Y. He, N.
Sun, M. Dunham, M. Asheghi, K. Goodson, Y. Yuan, K. Najafi, J. Electron. Mater. 2017,
46, 2844.
[7] W. Glatz, E. Schwyter, L. Durrer, C. Hierold, J. Microelectromechanical Syst. 2009, 18,
763.
[8] W. Glatz, S. Muntwyler, C. Hierold, Sensors Actuators A Phys. 2006, 132, 337.
[9] J. P. Fleurial, G. J. Snyder, J. A. Herman, P. H. Giauque, W. M. Phillips, M. A. Ryan, P.
Shakkottai, E. A. Kolawa, M. A. Nicolet, in 18th Int. Conf. Thermoelectr., 1999, pp. 294–
300.
[10] J. P. Fleurial, G. J. Snyder, J. A. Herman, M. Smart, P. Shakkottai, P. H. Giauque, M. A.
Nicolet, in 34th Intersoc. Energy Convers. Eng. Conf. Proc., 1999.
[11] M. T. Dunham, M. T. Barako, S. LeBlanc, M. Asheghi, B. Chen, K. E. Goodson, Energy
2015, 93, 2006.
[12] H. Lhermet, C. Condemine, M. Plissonnier, R. Salot, P. Audebert, M. Rosset, IEEE J.
Solid-State Circuits 2008, 43, 246.
[13] M. Stordeur, I. Stark, Proc. 16th Int. Conf. Thermoelectr. 1997, 575.
[14] I. Stark, M. Stordeur, in Eighteenth Int. Conf. Thermoelectr. Proceedings, ICT’99 (Cat.
No.99TH8407), Ieee, 1999, pp. 465–472.
[15] I. Kim, Mater. Lett. 2000, 43, 221.
[16] J. Weber, K. Potje-Kamloth, F. Haase, P. Detemple, F. Völklein, T. Doll, Sensors
Actuators A Phys. 2006, 132, 325.
[17] M. T. Dunham, M. T. Barako, J. Cornett, Y. Gao, S. Haidar, N. Sun, M. Asheghi, K. E.
Goodson, J. Power Sources 2017.
[18] K. Yazawa, A. Shakouri, T. J. Hendricks, Energy 2017, 118, 1035.
[19] D. M. Rowe, Ed. , Thermoelectrics Handbook: Macro to Nano, CRC Press, Boca Raton,
FL, 2006.
[20] L. W. da Silva, M. Kaviany, Int. J. Heat Mass Transf. 2004, 47, 2417.
[21] L. M. Goncalves, C. Couto, P. Alpuim, a. G. Rolo, F. Völklein, J. H. Correia, Thin Solid
Films 2010, 518, 2816.
[22] T. L. Bergman, A. S. Lavine, F. P. Incropera, D. P. Dewitt, Introduction to Heat Transfer,
John Wiley & Sons, Inc., Hoboken, NJ, 2011.
132
[23] A. M. Marconnet, N. Yamamoto, M. a. Panzer, B. L. Wardle, K. E. Goodson, ACS Nano
2011, 5, 4818.
[24] M. T. Barako, Y. Gao, Y. Won, A. M. Marconnet, M. Asheghi, K. E. Goodson, IEEE
Trans. Components, Packag. Manuf. Technol. 2014, 4, 1906.
[25] M. T. Barako, W. Park, a. M. Marconnet, M. Asheghi, K. E. Goodson, J. Electron. Mater.
2013, 42, 372.
[26] T. E. Salem, D. Ibitayo, B. R. Geil, IEEE Trans. Instrum. Meas. 2007, 56, 1973.
[27] J. Im, S. Wang, K. Lee, Y. Woo, IEEE J. Solid-State Circuits 2012, 47, 3055.
[28] I. Doms, P. Merken, C. Van Hoof, in 2007 Eur. Conf. Power Electron. Appl. EPE, 2007.
[29] I. Doms, P. Merken, R. Mertens, C. Van Hoof, 2008, 44, 2824.
[30] T. Becker, M. Kluge, J. Schalk, K. Tiplady, C. Paget, U. Hilleringmann, T. Otterpohl,
IEEE Sens. J. 2009, 9, 1589.
[31] Y. K. Tan, S. K. Panda, IEEE Trans. Ind. Electron. 2011, 58, 4424.
[32] F. Zhang, Y. Zhang, J. Silver, Y. Shakhsheer, M. Nagaraju, A. Klinefelter, J. Pandey, J.
Boley, E. Carlson, A. Shrivastava, B. Otis, B. Calhoun, in Proc. IEEE Int. Solid-State
Circuits Conf., 2012, pp. 298–300.
[33] J. Fleurial, L. Gailliard, R. Triboulet, J. Phys. … 1988, 49, 1237.
[34] B. Poudel, Q. Hao, Y. Ma, Y. Lan, A. Minnich, B. Yu, X. Yan, D. Wang, A. Muto, D.
Vashaee, X. Chen, J. Liu, M. S. Dresselhaus, G. Chen, Z. Ren, Science 2008, 320, 634.
[35] J. J. Shen, L. P. Hu, T. J. Zhu, X. B. Zhao, Appl. Phys. Lett. 2011, 99, DOI
10.1063/1.3643051.
[36] H. P. J. De Bock, V. Novak, in 2008 11th IEEE Intersoc. Conf. Therm. Thermomechanical
Phenom. Electron. Syst. I-THERM, 2008, pp. 1276–1282.
[37] A. Sahin, B. Yilbas, Int. J. Energy Res. 2012, 111.
[38] M. Zebarjadi, K. Esfarjani, M. S. Dresselhaus, Z. F. Ren, G. Chen, Energy Environ. Sci.
2012, 5, 5147.
133
Bibliography
1. Toberer, E. S., May, A. F. & Snyder, G. J. Zintl Chemistry for Designing High
Efficiency Thermoelectric Materials. Chemistry of Materials 22, 624–634 (2010).
2. Seebeck, T. J. Magnetic polarization of metals by temperature difference. Annalen der
Physik 82, 133–160 (1826).
3. Peltier, J. C. New experiments on the heat effects of electric currents. (1834).
4. Ismail, B. & Ahmed, W. Thermoelectric Power Generation Using Waste-Heat Energy as
an Alternative Green Technology. Recent Patents on Electrical Engineering 2, (2010).
5. Lopera, J. M., Rodríguez, H. d A., Pereira, J. M. P., Castro, A. R. de & Vigil, J. L. R.
Wireless sensors supplied by energy harvesting thermoelectric generators. in 2016 IEEE
Industry Applications Society Annual Meeting 1–8 (2016).
doi:10.1109/IAS.2016.7731916.
6. Dunham, M. T. et al. Experimental Characterization of Microfabricated Thermoelectric
Energy Harvesters for Smart Sensor and Wearable Applications. Advanced Materials
Technologies doi:10.1002/admt.201700383.
7. Neeli, G., Behara, D. K. & Kumar, M. K. State of the Art Review on Thermoelectric
Materials. in (2016).
8. Hummel, R. E. Electronic Properties of Materials | Rolf E. Hummel | Springer.
https://www.springer.com/gp/book/9781441981639.
9. Rowe, D. M. Thermoelectrics Handbook: Macro to Nano. (CRC Press, 2006).
10. Lucke’, W. H. A Brief Survey of Elementary Thermoelectric Therory. 20 (1963).
11. Szczech, J. R., Higgins, J. M. & Jin, S. Enhancement of the thermoelectric properties in
nanoscale and nanostructured materials. J. Mater. Chem. 21, 4037–4055 (2011).
12. Tritt, T. M. & Subramanian, M. A. Thermoelectric Materials, Phenomena, and
Applications: A Bird’s Eye View. MRS Bulletin 31, 188–198 (2006).
13. Yavorsky, B. Y., Hinsche, N. F., Zahn, P. & Mertig, I. Electronic structure and transport
anisotropy of Bi2Te3 and Sb2Te3. arXiv:1109.0186 [cond-mat] (2011)
doi:10.1103/PhysRevB.84.165208.
14. Rajput, I., Rana, S., Jena, R. P. & Lakhani, A. Crystal growth and x-ray diffraction
characterization of Sb2Te3 single crystal. AIP Conference Proceedings 2100, (2019)
15. Rowe, D. M. CRC Handbook of Thermoelectrics. CRC Press
https://www.crcpress.com/CRC-Handbook-of-
hermoelectrics/Rowe/p/book/9780849301469.
16. Ghafouri, N. Bismuth Telluride and Antimony Telluride Based Co-evaporated
Thermoelectric Thin Films: Technology, Characterization, and Optimization.
https://deepblue.lib.umich.edu/handle/2027.42/94061.
17. Bashir, M. B. A., Mohd Said, S., Sabri, M. F. M., Shnawah, D. A. & Elsheikh, M. H.
Recent advances on Mg2Si1−xSnx materials for thermoelectric generation. Renewable
and Sustainable Energy Reviews 37, 569–584 (2014).
134
18. Cutler, M. & Mott, N. F. Observation of Anderson Localization in an Electron Gas.
Physical Review 181, 1336–1340 (1969).
19. Jonson, M. & Mahan, G. D. Mott’s formula for the thermopower and the Wiedemann-
Franz law. Phys. Rev. B 21, 4223–4229 (1980).
20. Snyder, G. J. & Toberer, E. S. Complex thermoelectric materials. Nature Materials 7,
105–114 (2008).
21. Rull-Bravo, M., Moure, A., Fernández, J. F. & Martín-González, M. Skutterudites as
thermoelectric materials: revisited. RSC Adv. 5, 41653–41667 (2015).
22. Xie, J., Lee, C. & Feng, H. Design, Fabrication, and Characterization of CMOS MEMS-
Based Thermoelectric Power Generators. Journal of Microelectromechanical Systems 19,
317–324 (2010).
23. Remeli, M. F. et al. Power Generation from Waste Heat Using Heat Pipe and
Thermoelectric Generator. Energy Procedia 75, 645–650 (2015).
24. Cornett, J. et al. Chip-scale thermal energy harvester using Bi2Te3. in IECON 2015 -
41st Annual Conference of the IEEE Industrial Electronics Society 003326–003329
(2015). doi:10.1109/IECON.2015.7392612.
25. Micropelt: TGP. http://www.micropelt.com/en/energy-harvesting/tgp.html.
26. Martin, P. Handbook of Deposition Technologies for Films and Coatings - 3rd Edition.
https://www.elsevier.com/books/handbook-of-deposition-technologies-for-films-and-
coatings/martin/978-0-8155-2031-3.
27. Zou, H., Rowe, D. M. & Min, G. Growth of p- and n-type bismuth telluride thin films by
co-evaporation. Journal of Crystal Growth 222, 82–87 (2001).
28. Goncalves, L. M. et al. Optimization of thermoelectric properties on Bi2Te3 thin films
deposited by thermal co-evaporation. Thin Solid Films 518, 2816–2821 (2010).
29. Kim, D.-H., Byon, E., Lee, G.-H. & Cho, S. Effect of deposition temperature on the
structural and thermoelectric properties of bismuth telluride thin films grown by co-
sputtering. Thin Solid Films 510, 148–153 (2006).
30. Lee, H.-J., Park, H. S., Han, S. & Kim, J. Y. Thermoelectric properties of n-type Bi–Te
thin films with deposition conditions using RF magnetron co-sputtering. Thermochimica
Acta 542, 57–61 (2012).
31. Chen, T. et al. Influence of Substrate Temperature on Structural and Thermoelectric
Properties of Antimony Telluride Thin Films Fabricated by RF and DC Cosputtering.
Journal of Electronic Materials 41, (2012).
32. Makala, R. S., Jagannadham, K. & Sales, B. C. Pulsed laser deposition of Bi2Te3-based
thermoelectric thin films. Journal of Applied Physics 94, 3907–3918 (2003).
33. Cho, S. et al. Antisite defects of Bi2Te3 thin films. APPL. PHYS. LETT., Applied Physics
Letters Applied Physics Letters, Applied Physics Lettrs 75, 1401–1403 (1999).
34. Kim, Y. et al. Structural and thermoelectric transport properties of Sb2Te3 thin films
grown by molecular beam epitaxy. Journal of Applied Physics 91, 715–718 (2001).
35. Harrison, S. E. et al. Two-step growth of high quality Bi2Te3 thin films on Al2O3
(0001) by molecular beam epitaxy. Appl. Phys. Lett. 102, 171906 (2013).
135
36. Giani, A. et al. Growth of Bi2Te3 and Sb2Te3 thin films by MOCVD. Materials Science
and Engineering: B 64, 19–24 (1999).
37. Li, S. et al. Fabrication of Nanostructured Thermoelectric Bismuth Telluride Thick Films
by Electrochemical Deposition. Chem. Mater. 18, 3627–3633 (2006).
38. Handbook of Sputtering Technology. (Elsevier, 2012). doi:10.1016/C2010-0-67037-4.
39. What Is Sputtering? Magnetron Sputtering? http://www.semicore.com/what-is-
sputtering.
40. Lakhtakia, A. & Martín-Palma, R. J. Engineered Biomimicry. (Elsevier, 2013).
doi:10.1016/C2011-0-06814-X.
41. Cho, A. Y. & Arthur, J. R. Molecular beam epitaxy. Progress in Solid State Chemistry
10, 157–191 (1975).
42. Cho, S., Kim, Y. & Ketterson, J. B. Structural and thermoelectric properties in (Sb1-
xBix)2Te3 thin films. Appl Phys A 79, 1729–1731 (2004).
43. Wang, X., He, H., Wang, N. & Miao, L. Effects of annealing temperature on
thermoelectric properties of Bi2Te3 films prepared by co-sputtering. Applied Surface
Science 276, 539–542 (2013).
44. Jeon, S., Oh, M., Jeon, H., Hyun, S. & Lee, H. Effects of post-annealing on
thermoelectric properties of bismuth–tellurium thin films deposited by co-sputtering.
Microelectronic Engineering 88, 541–544 (2011).
45. Srivastava, G. P. The Physics of Phonons. (CRC Press, 1990).
46. Tian, Z., Lee, S. & Chen, G. Heat Transfer in Thermoelectric Materials and Devices.
Zhiting Tian (2013).
47. Thermoelectrics at Northwestern.
http://thermoelectrics.matsci.northwestern.edu/thermoelectrics/nanomaterials.html.
48. Heinz, N. A., Ikeda, T., Pei, Y. & Snyder, G. J. Applying quantitative microstructure
control in advanced functional composites. Advanced Funtional Materials 24, 2135–
2153 (2014).
49. Lan, Y., Minnich, A. J., Chen, G. & Ren, Z. Enhancement of Thermoelectric Figure-of-
Merit by a Bulk Nanostructuring Approach. Adv. Funct. Mater. 20, 357–376 (2010).
50. Media, R. What Is Annealing? Metal Supermarkets - Steel, Aluminum, Stainless, Hot-
Rolled, Cold-Rolled, Alloy, Carbon, Galvanized, Brass, Bronze, Copper
https://www.metalsupermarkets.com/what-is-annealing/ (2018).
51. Verhoeven, J. Fundamentals of Physical Metallurgy | Wiley. Wiley.com
https://www.wiley.com/en-us/Fundamentals+of+Physical+Metallurgy-p-
9780471906162.
52. Fan, P. et al. The high performance of a thin film thermoelectric generator with heat flow
running parallel to film surface. Appl. Phys. Lett. 102, 033904 (2013).
53. Stark, I. & Stordeur, M. New micro thermoelectric devices based on bismuth telluride-
type thin solid films. in Eighteenth International Conference on Thermoelectrics.
Proceedings, ICT’99 (Cat. No.99TH8407) 465–472 (1999).
doi:10.1109/ICT.1999.843432.
136
54. Wang, W. et al. A high packing density micro-thermoelectric power generator based on
film thermoelectric materials fabricated by electrodeposition technology. Surface and
Coatings Technology 231, 583–589 (2013).
55. Kim, D.-H. & Lee, G.-H. Effect of rapid thermal annealing on thermoelectric properties
of bismuth telluride films grown by co-sputtering. Materials Science and Engineering: B
131, 106–110 (2006).
56. Bourgault, D., Garampon, C. G., Caillault, N., Carbone, L. & Aymami, J. A.
Thermoelectric properties of n-type Bi2Te2.7Se0.3 and p-type Bi0.5Sb1.5Te3 thin films
deposited by direct current magnetron sputtering. Thin Solid Films 516, 8579–8583
(2008).
57. Huang, H., Luan, W. & Tu, S. Influence of annealing on thermoelectric properties of
bismuth telluride films grown via radio frequency magnetron sputtering. Thin Solid Films
517, 3731–3734 (2009).
58. Zeng, Z., Yang, P. & Hu, Z. Temperature and size effects on electrical properties and
thermoelectric power of Bismuth Telluride thin films deposited by co-sputtering. Applied
Surface Science 268, 472–476 (2013).
59. PANalytical X’Pert PRO MRD XRD | For Sale | Labx Ad 10257831.
https://www.labx.com/item/panalytical-x-pert-pro-mrd-xrd/10257831.
60. Furiouslettuce. Bragg Diffraction Planes. (2009).
61. Skakle, J. Applications of X-ray powder diffraction in materials chemistry. Chem Rec 5,
252–262 (2005).
62. Bos, J. W. G., Zandbergen, H. W., Lee, M.-H., Ong, N. P. & Cava, R. J. Structures and
thermoelectric properties of the infinitely adaptive series (Bi2)m(BiTe3)n. Phys. Rev. B
75, 195203 (2007).
63. Cornett, J. et al. Fabrication and Characterization of Bi2Te3-Based Chip-Scale
Thermoelectric Energy Harvesting Devices. Journal of Elec Materi 46, 2844–2846
(2017).
64. Wafer scale thermoelectric energy harvester having interleaved, opposing thermoelectric
legs and manufacturing techniques therefor - US 10,224,474 B2 - PatentSwarm.
https://patentswarm.com/patents/US10224474B2.
65. IPC-JEDEC J-STD-020E table of contents. 4 (2015).
66. TEMPERATURE CYCLING | JEDEC. https://www.jedec.org/standards-
documents/docs/jesd-22-a104e.