cic annual report 2012 developed a bio/environmental sensing chip technology platform for ......

National Chip Implementation CenterNational Applied Research Laboratories

CIC Annual Report 2012

2

Preface 4

Meet CIC 6

Our Team 8

Milestones 2002-2011 10

Highlights of 2012 16

Research and Development 22

CMOS Application Integration 24

CMOS Integrated Circuits and Biosystem Platform 26

ENFET Sensor Verification 26

Development of Advanced Application-Oriented Embedded Systems 27

3D System Integration and Platform Development 28

Development of Advanced Application-orientated Miniature Systems 31

Contents

Contents

3CIC Annua l Repor t 2012

Design and Fabrication Services 34

Design Environment Service 36

Verification Environments for IC and System Design 36

Embedded System and Software Development Environment 36

Fabrication and Design Service for RF SiP 39

Chip Implementation Service 40

Advanced Processes 40

Chip Prototyping Service 41

Measurement Services 42

Development and Testing Facilities for High-Frequency 44

Testing of Heterogeneous System Chips 46

Education 50

IC Design/Test Courses 52

e-Learning Courses 53

Publication 54

Patents and Papers 56

Patents 58

Papers 61

2012 International Journal Papers 61

2012 International Conference Papers 62

Imprint 64

4 Pre face

Make Taiwan aLeading Player in the Global Semiconductor Market.


PrefaceIn the era of the knowledge-based economy, high-quality human resources are the

keys to enhancing the competitiveness of a country. To make Taiwan a leading player in the global semiconductor market, National Chip Implementation Center (CIC), for the past two decades, has endeavored to provide academia in Taiwan services in the following three major areas: IC/System design environments; chip fabrication, heterogeneous packaging and measurement services; promotion of technology for IC/system design and international collaboration.

In 2012, CIC provided twelve advanced processes for academic users. They include five CMOS processes, one BiCMOS process, one tMt GIPD process, two CMOS MEMS processes, one CMOS BioMEMS process, one PHEMT/MHEMT process, and one high-voltage process. During this period, CIC helped to conduct 1,905 IC design projects and produce 1,713 chips. In addition, the center also helped to complete testing/measurement of 1,271 chips. On the total, 267 professors have benefited from the design and fabrication environments provided by CIC. In 2012, the center offered 205 training classes to 8,655 students in seven categories, including full-custom IC design, cell-based IC design, MEMS/embedded system, FPGA design, IC testing, RF/MMIC design and SoC/IP. In the future, CIC will continue to collaborate with the academia, industries, and research institutes in Taiwan to cultivate more high-quality designers, and to enhance the IC/system design technology so as to strengthen the core competence of Taiwan in the SoC area.

Last but not least, I wish to express my deep gratitude to National Science Council, CIC advisory committee members, and all CIC staff. I am truly honored to work with such a dedicated group of CIC staff in the endeavor to support top talents of Taiwan academia.

Director General

6

Meet CIC

During the past few decades, the focus of Taiwan economy has shifted from traditional industries to high-tech industries. In 1992, the National Science Council initiated the Chip Implementation Center Project, which aimed to establish a national research and service center for IC designers. CIC was established to cultivate professionals and improve IC technology and system design. Its primary mission includes the following:

(1) Establishing an IC/system design environment; (2) Providing chip fabrication and measurement services; (3) Promoting IC/system design technology and international collaboration (4) Improving IC/design service in southern Taiwan.

In the future, CIC will continue to provide training and develop advanced IC and system design technology. CIC will also collaborate with various sectors to improve the related technology for meeting the demands of academia in Taiwan.

Meet CIC


CIC Hsinchu Office

CIC Tainan Office

National Chip Implementation Center

8

Our TeamIn 2012, CIC had 117 employees, including 76 researchers and 19

technicians. Among the employees, 15 (12.8%) hold PhD degrees and 68 (58.1%) have MS degrees.

Chin-Fong ChiuPrincipal Investigator

Jiann-Jenn WangDeputy Director General

Chen-Hao ChangDeputy Director General, Division Director of Advance Technology Division

Tzi-Dar ChiuenDirector General

Chun-Ming HuangPrincipal Investigator

Our Team


Yi-Chia FanchiangDivision Director,Administration Division

Jen-Chieh WangDivision Director,Technology Promotion Division

Chun-Ming HuangPrincipal Investigator

Chien-Ming WuDeputy Division Director,Advanced Technology Division

Ying-Zong JuangPrincipal Investigator

Da-Chiang ChangDivision Director,Chip Implementation Service Division

Chi-Shi ChenDeputy Division Director,Design Service Division

Xun-Chen ChengDeputy Division Director,Chip Implementation Service Division

Wei-Chang TsaiDivision Director,Design Service Division

N A R L a b s

Milestones2002-2011

12

Milestones 2003-2007

Two-time Recipient of the Distinguished Project Award for the National Science & Technology Program—National Science and Technology Program for System-on-Chip (SoC)

Current 3C products, in particular smartphones, always feature a variety of functions. This was made possible by SoC, which integrates different chips with various functions into a single chip that allows a single device to perform multiple functions.

CIC has participated in implementing the “National Science and Technology Program for System-on-Chip” since 2003. During the project execution period of eight years, CIC has built a comprehensive SoC design environment, provided over 10 types of chip fabrication services, established a cutting-edge environment for SoC testing, and nurtured excellent talents in design for the academia. Such great efforts enormously enhance Taiwan’s competitiveness internationally. The first and second phases of this program were awarded the National Science and Technology Program for System-on-Chip Distinguished Project Award.

2003

Mi les tones 2002-2011


0.35μm CMOS MEMS—The world 's leading IC integration platform

CIC took the lead in the world by launching a 0.35μm CMOS MEMS integration platform in 2005. Its development was directed toward the MEMS sensor and IC integrated development. In terms of process technology, it combined a mature mixed-mode process to establish reliable analysis and verification and integrated the developed material parameters into 0.35um CMOS MEMS PDK. Since this technique is low cost and can be produced in miniature size, it can assist the academic community to develop a wide range of innovative chips.

2005

A global leader providing academia an environment for implementing low-cost SoC—Developed multi project SoC design technology

Due to higher costs, the SoC R&D teams in Taiwan’s academia in the past seldom had chances to verify completed SoC chips. The technology of Multi-Project SoC (MP-SoC) proved that a single vehicle can accommodate several SoC designs. This dramatically lowered SoC chip prototyping costs. This excellent achievement enabled the MP-SoC design technology to acquire a total of 7 U.S. and R.O.C. (Taiwan) patents. The experimental results were published in the IEEE Transactions on Industrial Electronics, nine international conference papers and a book in English. In 2007, CIC was awarded the 2nd place in the category of technology service of the 1st NARL Outstanding Technology Contribution Award.

2007

Agilent93000—An SoC debugging platform that functions with mixed-signal SoC testing

By integrating all functions, SoC gives us a new approach for system implementation, which is totally different from the traditional methods. In 2004, NARL-CIC established an Agilent 93000 SOC Series Test System and an automated platform for mixed-signal chip testing and debugging, including 320 signal pins with a maximum speed of up to 660Mbps. Each signal pin can have 28M Vectors of scan memory and eight sets of up to 7V and 6A power supply. Also, it has two sets of arbitrary waveform generators (AWG) and two sets of analog sampler digitizers compatible with many chip packaging types and load boards. The purposes of this service are to provide a measurement environment for digital and mixed-signal IC and SoC; strengthen individual chip testing services; and to support skill development and technical advice.

2004

Milestones 2008-2012

14

Developed a modularized FPGA development platform (MorFPGA) with three innovative advantages

Integrating peripheral interfaces commonly used in student contests, teaching and research, CIC developed a modularized FPGA development platform (MorFPGA). The advantage of this platform includes: (1) lowering the costs for the user purchasing this platform so as to replace the functions of traditional multiple monolithic FPGA platforms; (2) enhancing the circuit functions in contest, teaching and research; and (3) connecting the development of embedded system technology. CIC had applied for 2 patents and published 10 papers for this technology, which won the Excellence Award in the category of technology service of the 6th NARL Outstanding Technology Contribution Award.

2008

Smart home care work— A bio-sensing platform

CIC developed a bio/environmental sensing chip technology platform for smart home care. This platform comprised six techniques, including MEMS, CMOS MEMS integration, heterogeneous chip system packaging, CMOS Bio-MEMS platform, heterogeneous chip measurement and wireless transmission. Chips fabricated by this platform have two advantages. First, multi functions can be integrated on the same chip, which can be applied to biomedical analysis, communications, and so on. Second, chips can be produced in miniature size, which was easily integrated into personal belongings. In 2010, this technology was awarded the Excellence Award in the category of technology service of the 4th NARL Outstanding Technology Contribution Award.

2009

Mi les tones 2002-2011


Developed an intelligent electronic system platform with powerful performance

Through die-level modularization and 3D stack modules with the "MG +4C" application, CIC used the concept of sharing and reusing to develop an intelligent electronic system platform—MorPACK ™ (Morphing + Packaging). It featured the characteristics of diversified, time-effective, low-cost, and miniaturized system integration. As an effective tool in developing MG +4C products, it can be applied in various areas, such as safety, action, health, life, communication, entertainment, and so on. This technology has acquired a total of 5 U.S. and R.O.C. (Taiwan) patents and won the Excellence Award in the category of technology service of the 5th NARL Outstanding Technology Contribution Award.

2011

Promoted Taiwan's dominating production of technology in single-chip smart sensor products

In 2012, CIC made a breakthrough on sensor chip technology by promoting Taiwan’s dominating technology in commercializing smart sensor single chip, which successfully integrated the vibrating micromechanical structure inside CMOS chips. Four crucial keys to this technology include: (1) circuit protection, (2) structural control, (3) safe dicing, and (4) IP system verification.

This technique is low cost, and can be produced in miniature size and used to overcome the difficulty of integrating sensors and data readout and processing from chips into a single substrate. It can assist the industry, academia and research organizations in developing various innovative IP sensors, developing key components of sensor chips. This technology so far has acquired a total of 5 U.S. and R.O.C. (Taiwan) patents and 12 patents are pending. In 2012, it was awarded the Excellence Award in the category of technology service of the 6th NARL Outstanding Technology Contribution Award and the Outstanding Microsystems & Nanotechnology Industry Contribution Award from the R.O.C. (Taiwan) Nanotechnology and Micro System Association (NMA).

2012

Highlights of2012

N A R L a b s

18

April 18, 2012

High-Frequency Device, Circuit and System Application Workshop

CIC and National Nano Device Laboratories (NDL) co-hosted the 2012 High-Frequency Device, Circuit & System Application and MorPACK’s Platform Design Workshop. Prominent scholars and experts were invited to deliver speeches about technology developments and future innovations. By increasing the interaction between professionals, CIC hopes to advance the development of high-frequency devices, circuits, system applications, and technology nationwide.

April 23, 2012

The 18th World Micromachine Summit (MMS 2012)

The Micromachine Summit (first organized in 1995) provides a micro-nano technology snapshot of worldwide industrial, academic and government initiatives. Delegations from the most important regions and countries in this arena participated in the summit. Delegates gather in a roundtable environment to address topics of special interest and discuss the progress and policies in each country and region.

High l ights of 2012

Highlights of 2012


April 25-27, 2012

MorPACK Intelligent Electronic System Development Platform Conference

Using the concept of sharing and reusing, CIC applied the patented technology of die-level modularization and 3D stack modules to develop an intelligent electronic system platform. This platform can be applied in various applications, such as biomedical, 3C, car electronics, safety, and entertainment.

20

Highlights of2012

June 8, 2012

The 6th NARL Outstanding Technology Contribution Award

NARL organized the 6th NARL Outstanding Technology Contribution Award in order to enhance the NARL's R&D technology and reward those research staffs with outstanding contributions. CIC won a total of three big awards, including the Excellent Award by the project on “Environmental, Biomedical and Inertial Sensor Single Chip Technology” in the category of technology development, the Excellent Award by the project on “MorFPGA: A Modular FPGA System Development Platform” in the category of technology service, and an Honorable Mention by the project on “Building A Service Platform for CMOS/IPD Integrated Process & Production" in the category of technology service. Among the 11 NARL centers, CIC is the center with the most number of awards!

High l ights of 2012


October 29-31, 2012

IEEE Sensor-2012

Taiwan hosts the " IEEE Sensor 2012", an internationally famous and important conference for the sensor technology. The main exhibit from CIC in this event is the MorSensor-modulized wireless sensor fusion system. It provided a removable modular, which can be applied to various sensors. In addition, it had a variety of different power modules for use. Meanwhile, it also offered application software, with which the user can take advantage of Tablet PC or Windows PC to receive and analyze the signal. During the exhibition, a lot of vendors and researchers from different countries around the world showed their high degree of interest in the development platform as well as other products showcased by CIC. Through this exhibition, CIC hopes to let all walks of life better understand CIC for the purpose of improving its publicity and visibility in the international community.

August 7-10, 2012

The 23th VLSI Design/CAD Symposium & CIC Achievement Presentation

At this event, CIC showcased achievements in services and research, including MorPack, hybrid process, chip implementation service, the CMOS IPD process service, CMOS BioMEMS platform, CMOS MEMS platform, system measurement service, and the heterogeneous system chip testing. CIC also used this opportunity to explain the new practices of co-payment, application, and reservation of our services, including MorFPGA + Modularized FPGA platform, MorPACK 3D heterogeneous system integration platform, MorSensor wireless sensor fusion platform, 60V HV and 800V UHV process services.

Research and Development

N A R L a b s

0

5

10

15

20

25

30

4 4.1 4.2 4.3 4.4 4.5 4.6 4.7

In 2012, CIC collaborated with UMC and completes a 8" 0.18μm DRIE CMOS-MEMS process. In addition, CIC also designed an accelerometer SoC chip (Fig. 1) to verify the stability of this process.

Compared to the current CIC 0.18μm CMOS MEMS fabrication platform, the minimum space of released structures is reduced by 30%. It will increase the sensitivity of the CMOS MEMS sensor and extend the CMOS MEMS sensor applications.

Fig. 2 shows that the uniformity of resonant frequency of the accelerometer in 8-inch wafers is good. The characteristics of this accelerometer SoC chip, including the operating range, sensitivity, linearity, and so on, are similar to those of several commercial products (Table 1). The results have already been published in the renowned international Journal of Micromechanics and Microengineering. The above results show that the UMC 0.18μm DRIE CMOS MEMS process has reached the performance requirements for commercialization.

Fig.2 Distribution of resonant frequency of the accelerometer in 8-inch wafers

4.4 4.3 4.4 4.3 4.4 4.3 4.3 4.5 4.5 4.4 4.3 4.2

4.6 4.4 4.5 4.4 4.3 4.4 4.4 4.3 4.4 4.4 4.3 4.4 4.4 4.3 4.2 4.3

4.4 4.5 4.5 4.3 4.2 4.3 4.2 4.3 4.3 4.3 4.3 4.3 4.3 4.3 4.2 4.2

4.5 4.5 4.3 4.4 4.3 4.4 4.3 4.2 4.3 4.4 4.2 4.6 4 4.4 4.4 4.4

4.4 4.4 4.5 4.4 4.5 4.6 4.4 4.4 4.3 4.7 4.4 4.3

4.1 4.6 unit: KHz

X Y

35 36 3732 33 34

31 30 29 28 27 26 25 24

20 21 22 2316 17 18 19

15 14 13 12 11 10 9 8

5 6 72 3 4

1

CMOS Application Integration

Fig.1 An accelerometer SoC chip

resonant frequency (KHz)

die

coun

t

Histogram for resonant frequency

24 Research and Deve lopment

ST(LIS334AI)

ADI(ADXL335)

Freescale(MMA6361L)

CIC(JMM 2012)

ProcessThick Epi-

Poly+CMOS(hybrid)

Poly silicon+ASIC (hybrid)

Poly silicon+ASIC

(hybrid)

0.18um CMOS MEMS

Type capacitive capacitive capacitive capacitive

Range ±3.6 ±3.6 ±6 ±6

Sensitivity (V/g) 0.3 0.3 0.2 0.36

Power cons. (mW) 2.1 1 1.3 1

Nonlinearity (%) 0.6 0.3 1 1

Cross-axis sensitivity (%) <2 <1 <5 <5.8

Noise floor (mG/rtHz) 0.275 0.15 0.35 0.35

Table1. A comparison of characteristics between an accelerometer SoC chip and commercial products from world leading international companies

CIC had invited academia to try this process on September 20, 2012. In addition to demonstrating the U18 DRIE CMOS MEMS process, relevant specification and modeling files were also provided to the designers. A total of 8 academic design projects completed the tape-out at the end of November 2012.


ENFET Sensor Verification

A complementary metal-oxide-semiconductor (CMOS) compatible urea enzyme field effect transistor (FET) without enzyme immobilization is realized by CMOS BioMEMS technology. The natural formed aluminum oxide (Al2O3) above the top metal is used as the hydrogen sensing membrane. All the devices were fabricated by TSMC 0.35μm 2P4M CMOS process. In order to realize the micro sensing biological sensing system, the traditional Ag/AgCl reference electrode is replaced by the pseudo Ag/AgCl reference electrode in this study. First, the pH-FET is measured with the pseudo Ag/AgCl reference electrode. The sensitivity is 54.8mV/pH. The chip is fully isolated with epoxy except the sensing area. Figure 3 is picture photograph of this setup. The 50μl droplet contains urease and Tris buffer solution was applied onto the sensing area first, then urea and Tris buffer solution were added sequentially. The sensitivity of urea is around 88.7mV/mM which is shown in Figure 4. The detection range is 1~11mM. It covers the standard urea concentration range (3~6mM) in the human blood. In this report, we realize a simple CMOS urea sensor by using the urease in the Tris buffer solution and native Al2O3. Without the immobilization process and additional sensing membrane, it shows

great potential for use as a bio-analytical tool in point-of-care diagnoses.

Fig.4 Detection range and the sensitivity of urea

1.4

Urea concentration(mM)

CMOS Integrated Circuits and Biosystem Platform

Fig.3 Photograph of CMOS urea micro sensing system

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Development of Advanced Application-Oriented Embedded Systems

CIC focused on developing application-oriented embedded systems to assist professors to elevate their research results. One of application-oriented embedded systems, CONCORD platform was developed and demonstrated in collaboration with National Chung Cheng University (NCCU), National Chiao Tung University (NCTU) and National Cheng Kung University (NCKU) research teams. Besides, CIC and National Yunlin University of Science and Technology (YunTech) research team collaborated to develop another embedded system for monitoring bridge structural heath. Furthermore, we also cooperated with NCTU research team to develop the customized biomedical embedded system for measuring biomedical sensors. In 2012, CIC had derivative income, ca. NTD 830,000, contributed from two authorization cases from academia. One of authorization cases, CONCORD verifying system for the NCCU and NCTU teams was shown in Fig. 5. The other authorization cases, CONCORD verifying system for NCKU is shown in Fig. 6.

Fig.5 Photograph of the verification system for the NCCU and NCTU teams

Fig6. Photograph of the verification system for the NCKU team


In 2012, CIC integrated the processor (code N12) from Andes Technology Corp. (Andes) into the MorPACK platform (MorPACK-Indigenous Processor Sub-Module). CIC has completed the design and fabrication of the processor chip from Andes and the measured results were confirmed to meet the specifications. Currently, CIC has been conducting the sub-module hardware/software integration and development of this processor. Furthermore, CIC is also planning the sub-module development of the open source processor, such as OpenRISC and LEON processor, so as to enable the MorPACK platform with various core abilities for selection. The processor core chip architecture and layout of domestic Andes processor applied to the MorPACK platform are shown respectively in Fig. 7 and Fig. 8. This chip, which contains an Andes N1213 (16K instruction cache and 16K data cache) and two dedicated processor memory (32KB SRAM), would be integrated through the Tri-state AHB bus and the MorPACK system.

Fig.7 Andes N1213 processor core chip architecture Fig.8 Andes N1213 processor core chip layout

Die Area (um2) 2959x2167Core Area (um2) 2420x1630Signal Pads 107Power Pads 118

Macro CellAndes N1213_3OT2G

ILM(32KB)

DLM(32KB)

JTAG

AHB Bus

Tri Bus

Tri-Bus Port

3D System Integration and Platform Development


3D System Integration and Platform Development

Furthermore, for better promotion, CIC in 2012 developed a low-cost, detachable version of MorPACK platform. Due to its low-cost and easy-to-stack features, CIC has manufactured 100 sets of this product. CIC planned to provide the technical service to academia during the first quarter of 2013. Introductions to each module substrate of this MorPACK platform are described in the following.

Fig.9 CPU module substrate

Fig. 9 is a picture of a CPU module substrate with the size of 6cm x 6 cm. The middle area of this CPU is its core part, and FX8 connectors with a total of 360 signal transmission pins. The upper and lower pin signals are passed through including AHB signals, power supplies, and other peripheral control-related signals. Internal CPU includes an ARM926EJ processor and two 32KB SRAM dedicated processor memory as shown in Fig. 9. The CPU chip is directly picked and placed on the CPU module substrate for data transfer through the Tri-state AHB bus.

Fig. 10 is a picture of the north-bridge module substrate with the size of 6 cm x 6 cm and three chips included: a north-bridgechip, a SDRAM chip and a NOR Flash chip. In this picture, the upper left corner is where the NOR Flash die is positioned, the upper right corner is where the SDRAM die is positioned, and the middle part is where the Northbridge die is positioned. This north-bridge chip includes some of higher-speed system modules, such as SDRAM controller, NOR Flash controller, bus infrsatructure, SRAM, ROM, and CLCD controller. Among these, the bus infrsatructure includes an arbiter and a decoder. Because the arbitor and the decoder are positioed inside the north-bridge chip, the number of master/slave devices of the entire MorPACK system is therefore determined by the north-bridge chip. For north-bridge chip, the internal part conducts data transfer through the AHB bus, and the external part transforms the AHB signals into the tri-state AHB signals via the tri-state I/O modules for saving the input and output pins.

Fig.10 North-bridge module substrate


Fig.13 MorPACK 3D embedded system integration platform

In 2012, CIC also took advantage of the MorPACK platform to complete the designing and fabrication for a 3D platform for mobile devices. This platform has wireless and portable features; the hardware platform and its designing example will be given for future academic research for rapidly pushing the system design and verification process to a better level. Fig. 13 is a picture showing the use of MorPACK 3D platform for mobile devices.

Fig. 11 is a picture of a south-bridge module substrate. A south-bridge chip contains a number of low-speed peripheral circuits, such as APB bridge, interrupt controller, timers, pause/remap, WDT, UART and GPIO. A south-bridge chip is directly picked and placed on its module substrate. The external part transforms the AHB signals into Tri-state AHB signals through the Tri-state I/O modules for saving the input and output pins.

Fig. 12 is a picture of stacking low-cost, detachable MorPACK platforms

Fig.12 Stacking MorPACK platformsFig.11 South-bridge module substrate

Mor PACK modules

Socket Layer

FPGA, Power Layer

Wirless Layer


The MorPACK platform is adopted by nine research teams from six universities to accomplish developments of application system. In order to spread the MorPACK platform to researchers and academics, the CIC held a workshop for the exhibit and experience sharing of MorPACK platform, and the workshop title is “MorPACK heterogeneous system integration platform with exhibit and experience sharing” on May 31, 2013. Seven research teams are invited to exhibit their research results by utilizing the MorPACK platform in this conference. The research results include “Application of Ultrasonic System,” which was proposed by A. Y. Wu (National Taiwan University), “Application of Mobile Healthcare Cardiogram System,” which was proposed by C. Y. Lee (National Chiao Tung University), “Application of Image Processing System,” which was proposed by Y. T. Hwang (National Chiao Tung University), “Application of Multimedia System,” which was proposed by J. I. Guo (National Chiao Tung University), “Application of Object Detection System,” which was proposed by M. H. Shu (National Yun-lin University of Science and Technology), “Application of Debugging System,” which is proposed by K. J. Lee(National Cheng Kung University), and “Applications of Debugging and Surveillance Systems,” which is proposed by I. J. Huang (National Sun Yat-Sen University).” The MorPACK platform covered many areas that include security, mobility, healthcare, communications, entertainment etc.

For MorPACK platform, we have accomplished two authorization cases from academia. The revenue of authorization cases is gained NTD 2,650,000. CIC helped National Chung Cheng University to develop a MorPACK miniature systematic platform featuring with MorPACK module and load board of MorPACK (Fig. 14).

Fig.14 MorPACK miniature systematic platform authorized by National Chung Cheng University

Development of Advanced Application-orientated Miniature Systems


Fig.16 Illustration of the boards authorized by NCCU

In Fig. 15, the MorPACK module includes ARM processor module, north bridge module, south bridge module, FPGA module, dual-port SRAM module, and NCCU proposed H.264 module. Each module is equipped with stackable socket for assembling, and power and signal were also transferred through stackable socket. The load board of MorPACK platform included Socket Layer, FPGA/Power layer and Peripheral Layer. Each load board was stacked by DIP connector on both sides, and its size is 9 cm x 9cm. Finally, MorPACK module is fixed on the load board of MorPACK, as shown in Fig. 15. CIC released the MorPACK platform to NCCU, and also transplant a Linux OS to MorPACK platform. The MorPACK platform with Linux OS will help them to easily verify and show their research.

Fig.15 The illustration of Integrated Module authorized by NCCU

CCU H.264 IP

StackableSocket

上蓋

Socket Layer

Dual-Port SRAM

Sppartan-6 FPGA

NB

SB

ARM CPU


Figure 17 is shown the multi-view decoder architecture design from authorization case by NCTU. In order to integrate decoder chips of multi-view decoder architecture (DEC Chip 1 and DEC Chip 2) to MorPACK system platform, DEC Chpi1 and DEC Chip2 were package to submodule. The arbiter of the both decoder chips was used by a FPGA (Xilinx, Spartan6 XC6SLX75) module. Other circuits, such as processer, LCD control circuit are built in MorPACK module. The SD card controller was be burnt into a FPGA (Xilinx, Spartan3 XC3S5000) on the load board of MorPACK. MorPACK modules were assembled through FX8 connector, as shown in Figure 18. The load board of MorPACK platform provided power, debug interface, peripheral interface and etc. to MorPACK platform, as shown in Figure 19.

Fig.17 Multi-view decoder architecture design integrated by MorPACK

RISC LCD MEMSD card

orPC

Arbiter

MorPACK Wrapper

S M

3D-ICLayer 3

3D-ICLayer 2

3D-ICLayer 1

Decoder1S M

DEC Chip1

Decoder2S M

DEC Chip2

BUS

Fig.18 MorPACK fabricated platform Fig.19 The boards authorized by NCTU


Design and Fabrication Services

N A R L a b s

Verification Environments for IC and System Design

The verification environment for IC and system design includes software, hardware, design libraries, silicon IPs, and design verification flows which integrate tools and data. CIC currently offers verification flows for full-custom or cell-based IC design, FPGA design, mixed-signal design and ESL to meet the verification requirements for IC and system designs with various characteristics.

In 2012, CIC acquired two C language-based high-level synthesis tools, Synphony C Compiler and C-to-Silicon Compiler, from Synopsys and Cadence, respectively. Other software packages from ARM, Altera, Cadence, Mentor Graphics, Synopsys, and Xilinx, were also upgraded to the latest versions.

Embedded System and Software Development Environment

In response to the growing demands for the MorFPGA platform and to lower the production costs, CIC in 2012 upgraded the original MorFPGA platform and authorized Microtime Computer Inc. for production and after-sales service. The new version was named "MorFPGA+ Teaching & Contest common Platform" (hereinafter referred to as MorFPGA+ platform). In addition to maintaining the basic functions in original version, the main differences between the old and new version platforms are as follows:

1. Xilinx FPGA chips were upgraded from Spartan-3 to new generation Spartan-6; Altera FPGA chips were upgraded from Cyclone II to new generation Cyclone IV;

2. The board connector was switched to the Hirose connector;

3. New price was only 60% of the original price; and

4. Instruction materials for the entire semester

To confirm its functions, MorFPGA+ platform has completed the verification testing through the automatic test program developed by CIC. An entity display of the automatic test program (taking Xilinx version as an example) is shown in Fig. 20, The sale content is shown in Fig. 21, including a packing case, MorFPGA+ platform (including core FPGA, memory and peripheral modules), a data CDROM, a transformer and an easy instructions manual.

Design Environment Service

36 Des ign and Fabr ica t ion Serv ices

Fig.20 An entity display of the automatic test program (Taking the Xilinx version as an example)

Fig.21 The MorFPGA+ platform sale contents

In order to promote the MorFPGA+ platform successfully, CIC has completed its implementation materials for the entire semester and planned the E-learning courses already. The experimental teaching materials are free of charge for the purpose of sharing teaching resources.

Moreover, to further enhance the usability and lower the MorFPGA+ costs for academic promotions, CIC planned and developed peripheral virtualization technologies, based on the software simulation to replace actual hardware peripherals. A diagram of the virtualized peripheral hardware platform system architecture is shown in Fig. 22. Currently, CIC has already completed the technical developments for basic peripheral GPIO, buttons, switches, LED and UART of the MorFPGA+ platform. Fig. 23 depicts a software user interface on the PC screen, which was used to simulate the development of the peripheral board status. Fig. 24 is the Linux booting procedure on an evaluation board, where the booting procedure and applications were demonstrated individually on the PC virtual terminal and the LCD screen.


Fig.24 Booting procedure of Linux

Fig.23 Basic peripheral virtualization display

Fig.22 A diagram of virtualized peripheral hardware platform system architecture

GPIOUARTGDBLCD

Moues

USB Cable

Virtual peripheral

Physical peripheral

USBDriver

PC HostVirtual Platform

Target board

TerminalDebuggerMonitor

SD Card Camera Speaker MIC ETH

USBInterface(FPGA)

USBPHY

SOC(FPGA)

FLASH

SDRAM

CLKPWR


Fabrication and Design Service for RF SiP

In 2012, CIC has integrated the four processes of CMOS, IPD, bumping, and assembly, and will continue to provide the CMOS-PID integrated fabrication service to academia. In 2012, two CMOS-PID process services and 29 IPD design cases were completed, and we also evaluated how to integrate Glass IPD with advanced CMOS processes by completing an IPD wafer bumping process. The relevant technology will be verified through integration with CMOS chips of advanced processes. Some implementation examples of IPD RF front-end integration circuits had been verified, including 60GHz RF front-end passive circuits (antenna and filter, Fig. 25).

Figure 25. Photo and simulation of antenna band-pass filter

The microphotograph of the fabricated integrated quasi-Yagi chip antenna-filter

Configuration of the proposed integrated quasi-Yagi chip antenna-filter

Simulated and measure S-parameters of the bandpass filter

Simulated and measured S-parameters of the quasi-Yagi chip antenna

Simulated and measured S-parameters of the the integrated antenna-filter

Simulated and measured antenna gains of the integrated antenna-filter and

quasi-Yagi antenna


Advanced Processes

In order to satisfy the demand for advanced research in Taiwan’s academia, CIC has continued providing the TSMC 40-nm advanced fabrication process, and completed the following tasks:

• Approved 39 applications and 14 chips that had been fabricated in the two runs of processes.(Fig. 26, and Fig. 27)

Fig.26 TSMC 40-nm chip layout in TN40G-101A tape out Fig.27 TSMC 40-nm chip layout in TN40G-101B tape out

Fig.28 One case of VCMP hot spots in a TSMC 40-nm chip layout

• Maintained and updated the PDK platform for TSMC 40-nm process.

• Provided a training course and technical consultation service for applicants who use the TSMC 40-nm process.

• Updated the Design for Manufacture (DFM) technical kits and provided a training course for DFM verification flow of the TSMC 40-nm process. One real case study of VCMP hot spots is shown as Fig. 28.

Chip Implementation Service


Chip Prototyping Service

A. Planning 2012 IC fabrication and tape-out

• Collected and analyzed domestic and foreign IC design data in 2011.

• Evaluated the use of fabrication processes developed in 2011 and analyzed the implementation rate.

• Evaluated the new processes that matured in 2011 and completed the evaluation report.

• Evaluated the new educational process and integrated advanced design to simplify the process and customize the design.

B. Providing implementation services for 12 types of processes

• Services of advanced processes include: TSMC 90-nm 1P9M RF low-power CMOS process, the new TSMC 40-nm 1P9M CMOS process, and the new TSMC 90-nm 1P9M MS general-purpose process.

• General application process include: TSMC 0.18-μm 1P6M CMOS process, TSMC 0.35-μm 2P4M CMOS process, TSMC 0.35-μm 2P4M CMOS MEMS post-process, TSMC 0.35-μm 2P4M CMOS BioMEMS post-process, and TSMC 0.18-μm 1P6M CMOS MEMS post- process.

• Special application process include: TSMC 0.18-μm SiGe BiCMOS process, WIN 0.15-μm PHEMT/MHEMT process, TSMC 0.25-μm 60V high-voltage process, and tMt GIPD process.

• Implementation environment for integrating the tMt GIPD process and TSMC 0.18-μm 1P6M CMOS process.

• Prototyping services for 1,713 chips.


Measurement Services

N A R L a b s

• Deve loped the sys tem measurement technology for the 60GHz transmitter. The measurement system includes the down-converter, vector signal analyzer and vector signal analyzer software.

• Provided the modulation signal measurement service up to 20GHz. We provided the WLAN modulation signal and fundamental modulation signals, like QPSK, 16QAM, ASK and etc. We can measure the system parameters, like ACPR, CCDF, EVM and etc.

Fig.30 20GHz modulation signal measurement system

Fig.29 Demodulation results for 60GHz QPSK modulation signal

RF Analog In

AnalogI In

AnalogQ In

AnalogI+AnalogI-AnalogQ+AnalogQ-

Vector signal generator

RF/Analog Out(250KHz~20GHz)

orAnalog l & Q Out

(DC~40MHz)or

Analog l+,l- & Q+,Q-out(DC~40MHz)

DUTor

or

or or

Analo

g l+

,l-, &

Q+,Q

-out

Analo

g l &

Q o

ut

RF/A

nalo

g o

utp

ut

Vector signal analyzer

RF/Analog in(3Hz~26GHz)

orAnalog l & Q in

(-40MHz~40MHz)or

Analog l+,l- & Q+,Q-in(-40MHz~40MHz)

DC Input1

DC Input2

DC Input3

DC Input4 Power supplyVector signal generator

Vector signal analyzer and vector signal analyzer software

Development and Testing Facilities for High-Frequency Measurement

44 Measurement Serv ices

• Upgraded the testing facility for signal source parameter evaluation: the new system uses dual cross-correlated channels to reduce the influence of external circuits and LO on the phase noise from the 60-GHz signal source. In addition, the new system does not require an external divider to avoid frequency drift, which prevents the system from identifying the phase noise.

Fig.31 Use of dual cross-correlated channels to improve the measurement of 60-GHz phase noise

DUT

1.85-mm CableMatch Tee

Signal Source Analyzer


A.Upgraded the testing facility for CMOS RF power components and evaluated test systems and technologies for 60-GHz nonlinear parametric power components.

CIC acquired a 67-GHz X-Parameter measurement module to establish environment and develop technology for nonlinear parametric power components. This facility enables the measurement of nonlinear characteristics for RF circuits under 50 Ω resistances, such as P1dB, IIP3, and OIP3. In addition, X-Parameter On-Wafer measurement will be developed. The measurement data and ADS software will be employed to simulate the active component equivalent model to establish a library for circuit designers.

Fig.32 X-Parameter measurement system

Testing of Heterogeneous System Chips


B.Maintained current testing facilities to provide environment of power measurement, analog measurement, and regular measurement services.

To continue providing the RF power measurement service, CIC acquired a testing system for 0.8-GHz to 18-GHz 3D antennas, as shown in Fig. 33. The major function of this facility is to measure parameters for 1D, 2D, and 3D electromagnetic radiation waves, such as antenna gain, radiation directivity, radiation beam-width, and efficiency. CIC will provide measurement services to research institutes and cultivate human resources in antenna design. We also support system antenna development for application communication bands, such as WiMAX, WLAN, and GSM.

Figu.33 A testing system for 0.8-GHz to 18-GHz 3D antennas


The heterogeneous chip measurement services in CIC include:

A. Measurement environments for the load-pull, 0.8~18GHz, antenna, analog (10bits ADC, 12bits DAC) measurement services. Measurement services for general measuring instruments and technical support were also provided.

B. CIC opened the HV(60V) CMOS measurement environment services to the public since June 2012 These services include completing the relevant machine procurement (Fig. 34) and establishing relevant measurement techniques in switching regulator, buck/boost converter and charge pump converter.

C. Environment for automated constant temperature measurement.

D. Measurement environments for OPAMP and 12bits ADC, and opened the OPAMP’s for continually providing the south area both the general chip and advanced analog (ADC, DAC) measurement services and technical advice.

Fig.34 HV (60V) CMOS measurement environment


Signal Source Analyzer


EducationN A R L a b s

In recent years, heterogeneous integration system design, high-frequency circuit design, and systematic design have become increasingly important. Therefore, we organized additional training courses for these fields. In 2012, CIC provided 43 course categories in 205 training sessions, in which 8,655 engineers and students participated (Fig. 35).

Fig35. Course category, No. of courses, and No. of students

171 163 168 166

146 162

183

164 149

175 175

205

36 47 47 46

37 45 44 44 44 44 43 43

0

50

100

150

200

250

2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012

Number of Courses Course Category

1000

8000

6000

4000

2000

7166

2001 2002 2003 2004 2005 2006 2007 20092008 2010 2011 2012

8227 80977667

4012

6835

8419 84237369

6046

8020 8655

0

Number of Students

IC Design/Test Courses

52 Educat ion

To fosten more IC design professionals, CIC provided e-learning courses which are accessible anywhere at any time to achieve the 3E principle of economical, effective, and efficient learning. In 2012, we offered 16 e-learning courses (Table 2) for 5,304 attendees.

Table2 e-Learning Courses

Items e-Learning Courses

E001 HSPICE

E002 Full-Custom IC Design Concept

E003 Design of CMOS RF IC

E004 Novas Fundamental Training

E005 LakerADP+LakerL3 SDL flow training

E006 Advanced Design System – Fundamentals

E007 CMOS BioMEMS Sensing Technology

E008 Sensor Readout Circuit Technology

E009 RF System in Package (SiP) technology

E010 Advanced Design System – Momentum

E011 Digital IC Testing Step-by-Step with Verigy 93000

E012 Step Into ESL Design

E013 FPGA Design Fundamentals for Altera

E014 Logic Synthesis (Synopsys)

E015 Cell-Based IC Physical Design and Verification with IC Compiler

E016 Brief Introduction of Cell-based Design

e-Learning Courses


To effectively communicate information with different sectors, CIC issues monthly e-News (Fig. 36) newsletters to report news and activities, publish advanced technical articles, and announce important information to the public. Additionally, we also release an annual report in English (Fig. 37). The content of the annual report includes general information about the CIC organization and presents significant annual events and achievements in research, services, educational training, and technology promotion. In 2012, 813 people in academia, research institutes and industry received the CIC annual report in English.

Publication

Publication

54 Educat ion

Fig.36 CIC e-News

Fig.37 CIC Annual Report

Publication

CIC eNews

Annual Report


Patents and PapersN A R L a b s

Patent Approved and Application List

Title of Approved Patents Country Type Approval Date

biosensor package structure with a micro-fluidic channel

Taiwan Invention 2012/4/1

biosensor package structure with a micro-fluidic channel

U.S. Invention 2012/5/17

Multi-layer system chip module architectures


Method for arranging memories of low-complexity LDPC decoder and low-complexity LDPC decoder using the same


Three-dimensional SoC structure stacking by multiple chip modules


Socket structure stack and socket structure thereof


Patents

58 Patents and Papers

Title of Pending Patents Country Type Date of Application

Structure for MOSFET sensor U.S. Invention 2012/3/13

Low noise amplifier with back-to-back connected diodes and back-to-back connected diode with high impedance thereof


Cmos sensor with image sensing unit integrated therein


Miniature Sieve Apparatus and Manufacturing Method Thereof


Miniature Sieve Apparatus and Manufacturing Method Thereof


Microparticle detecting apparatus Taiwan Invention 2012/5/7

Microparticle detecting apparatus U.S. Invention 2012/7/12

3D pointing device Taiwan Invention 2012/8/6

3D pointing device U.S. Invention 2012/9/12

Circuit sharing time delay integrator Taiwan Invention 2012/6/13

Circuit sharing time delay integrator U.S. Invention 2012/8/24

Vehicle idle-speed warning system and idle-speed detection method


Vehicle idle-speed warning system and idle-speed detection method


LED driver circuit structure with over-current suppression


LED driver circuit structure with over-current suppression


Table2. Patents Approved and Applied Table


Year 2006 2007 2008 2009 2010 2011 2012

Cases Approved

0 1 4 2 4 3 6

Cases Applied

5 5 6 10 14 13 15

Table3. Number of patents approved and applied


2012 International Journal Papers

1. Chih-Min Hu, C.-Y. H.-H.-C.-Z.-F.-M. (2012/02). A 60-GHz Three-Stages Low Noise Amplifier using 0.15-μm GaAs pHEMT technology. Microwave and Optical Technology Letters, (p. 329-332).

2. Ting Lee, C.-H. W.-L.-Z.-I. (2012/03). A 3.6 mW 125.7–131.9 GHz Divide-by-4 Injection-Locked Frequency Divider in 90 nm CMOS. IEEE Microwave and Wireless Components Letters, p. 132-134.

3. R.-L. Wang, C.-W. Y.-H.-M.-F.-H.-Z. (2012/04). Temperature Sensor Using BJT-MOSFET Pair. Electronics

Letters, (p. 503-504).

4. S.-H. Tseng, M. S.-C. (2012/04). Implementation of a monolithic capacitive accelerometer in a wafer-level 0.18-μm CMOS MEMS process. Journal of Micromechanics and Microengineering, (p. NA).

5. H. C. Li, S.-H. T.-C. (2012/04). Study of CMOS micromachined self-oscillating loop utilizing a phase-locked loop driving circuit. Journal of Micromechanics and Microengineering, (p. NA).

6. Hwann-Kaeo Chiou, K.-C. L.-H.-Z. (2012/06). 1 V 5 GHz Self-Bias Folded-Switch Mixer in 90-nm CMOS for WLAN Receiver. IEEE Transactions on Circuits and System I, (p. 1215-1227).

7. J.S. Yuan, H. Y. (2012/06). Experimental Verification of RF Stress Effect on Cascode Class-E PA Performance and Reliability. IEEE Trans. on Device and Material Reliability, (p. 369-375).

8. Ibrahim Haroun, C. P.-C.-C. (2012/07). Compact 60-GHz IPD-Based Branch-Line Coupler for System-on-Package V-Band Radios. IEEE Trans. on Components, Packaging and Manufacturing Technology, (p. 1070-1074).

9. I-Ting Lee, C.-H. W.-R.-Z.-I. (2012/08). A D-band Divide-by-3 Injection-Locked Frequency Divider in 65nm CMOS. IET Electronics Letters, (p. 1041-1042).

10. Ying-Zong Juang, C.-F. L.-H.-H.-L. (2012/11). CMOS Biomedical Sensor with In Situ Gold Reference Electrode for Urine Detection Application. Procedia Engineering, (p. 1005 – 1008).

11. Yuan-Ta Hsieh, B.-D. L.-F.-L.-H.-Z. (2012/11). A High-Dimming-Ratio LED Driver for LCD Backlights. IEEE Transactions on Power Electronics, (p. 4562-4570).

12. Ruey-Lue Wanga, Y.-K. H.-H.-C.-F.-H.-Z. (2012/12). A concurrent dual-band folded-cascode mixer using a LC-tank biasing circuit. Microelectronics Journal (ELSEVIER), (p. 1010-1015).

Papers


2012 International Conference Papers

1. Gang-Neng Sung, C.-M. H.-C. (2012/01). A PLC Transceiver Design of In-Vehicle Power Line in FlexRay-based Automotive Communication Systems. ICCE. Las Vegas, U.S.A.

2. Chien-Lin Huang, N.-S. C.-S.-P.-M.-M. (2012/04). A Novel Design Methodology for Hybrid Process 3D-IC. VLSI DAT. Hsinchu, Taiwan.

3. Jin-Ju Chue, C.-C. Y.-C.-C.-M.-M. (2012/04). Investigation of Chip Temperature Related to Various Copper Thickness on Glass-Fabric-Based Substrate. EuroSimE. Lisbon, Portugal.

4. Yi-Jun Liu, C.-C. Y.-L.-C.-C.-M.-M. (2012/04). An Efficient Memory Controller for 3D Heterogeneous Integration Platform. VLSI-DAT. Hsin-chu, Taiwan.

5. Hsu-Feng Hsiao, S.-G. L.-H.-H.-C.-Z. (2012/05). Bit Error Rate Measurement System for Radio Frequency Integrated Circuits. 2012 IEEE International Instrumentation and Measurement Technology Conference. Graz, Austria.

6. Hsu-Feng Hsiao, S.-G. L.-H.-H.-C.-Z. (2012/05). Digital Modulation/Demodulation Measured System within Connected Solution. Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW), 2012 IEEE 18th

International. Taipei, Taiwan.

7. Chen-Fu Lin, H.-H. L.-H.-Z.-L.-M.-W. (2012/06). CMOS Biomedical Chip Integrated with Microfluidic System. The 4th International Symposium on Microchemistry and Microsystems (ISMM). Zhubei, Taiwan(R.O.C.).

8. Chun-Chieh Chu, H.-H. L.-C.-D.-P.-M.-M. (2012/06). CONCORD II: A Configurable SoC Prototyping Platform. IS3C. Taichung, Taiwan.

9. Chun-Ming Huang, C.-C. Y.-J.-C.-C.-D.-C.-L.-P.-M. (2012/06). A New Embedded System Prototyping Service for Taiwan Academia. ICEE. Turku, Finland.

10. Hsi-Tse Wu, K.-C. Y.-T.-M.-M. (2012/06). MiniTester: A Low-Cost Verification Platform for Integrated Circuits. IS3C. Taichung, Taiwan.

11. Hua-Yen Chung, Y.-C. H.-K.-C.-Z. (2012/06). Broadband and Low-loss Ruthroff-type Transmission Line Transformer in Integrated Passive Devices Technology. 2012 International Microwave Symposium. Montreal, Canada.

12. Chih-Yuan Yeh, F.-S. H.-C.-H.-Z. (2012/07). A High-Sensitivity Current Detection Readout Circuit for Silicon-Nano-Wires Field Effect Transistor. APCOT. Nanjing, China.

13. Chun-Lin Ko, C.-P. C.-N.-C.-Z. (2012/07). A 1-V 60 GHz CMOS Low Noise Amplifier with Low Loss Microstrip Lines. 2012 International Symposium on VLSI Design, Automation and Test. Hsin-Chu, Taiwan.


14. Kuei-Cheng Lin, H.-K. C.-C.-C.-Z. (2012/07). "Variable Gain Active Predistorter with Linearity Enhancement for a 2.4 GHz SiGe HBT Power Amplifier Design. VLSI-DAT. Hsin-Chu, Taiwan.

15. Lieh-Chuan Lin, C.-H. T.-C.-Z. (2012/07). Radiation Pattern Estimation of Bond Wire Antennas. 2012 IEEE

International Symposium on Antennas and Propagation and USNC-URSI National Radio Science Meeting.

Chicago, U.S.A.

16. Chih-Ting Kuo, C.-Y. C.-T.-P.-M.-M. (2012/08). CIC Signal Processing Embedded System, A Modulizable Platform for Multi-Domain Signal Processing. The 34th Annual International Conference of the

Engineering in Medicine and Biology Society(IEEE EMBC-2012). San Diego, U.S.A.

17. Yuan-Ta Hsieh, C.-L. F.-F.-H.-Z.-D. (2012/08). Monolithic Fan Speed Control IC for Monitoring Temperature and Improving Power Efficiency. The SICE Annual Conference 2012. Akita, Japan.

18. Y.-J. Hung, S.-H. T.-J.-H.-Z. (2012/09). A physical measurement for modeling a CMOS MEMS resonator. 38th Micro and Nano Engineering Conference (MNE). Toulouse, France.

19. Ying-Zong Juang, C.-F. L.-H.-H.-L. (2012/09). CMOS Biomedical Sensor with In Situ Gold Reference Electrode for Urine Detection Application. The 26th European Conference on Solid-State Transducers. Kraków, Poland.

20. Chun-Ming HuangYang, Chien-Ming Wu, Chun-Chieh Chiu, Yi-Jun Liu,Chun-Chieh Chu, Nien-Hsiang, Chang, Wen-Ching Chen, Chih-Hsing Lin, Hua-Hsin LuoChih-Chyau. (2012/09). A NOVEL DESIGN FlOW FOR A 3D. 25th Internaltional System-on-Chip Conference (SoCC 2012). Niagara Falls, U.S.A.

21. Chen-Chia Chen, S.-H. H.-C.-M.-M. (2012/10). Effect of Surface Morphology on Performance of Micro-coil for Concentrated Magnetic Beads. 25th International Microprocesses and Nanotechnology Conference

(MNC 2012). Kobe, Japan.

22. Chen-Fu Lin, Y.-Z. J.-H.-J.-H.-H.-L. (2012/10). A High Sensitivity CMOS Compatible Urea Enzyme Field Effect Transistor without Enzyme Immobilization. IEEE SENSORS 2012. Taipei, Taiwan.

23. S.-H. Tseng, Y.-J. H.-H.-Z. (2012/10). Implementation of a DETF resonator in a wafer-level 0.18-um CMOS MEMS process. 25th International Microprocesses and Nanotechnology Conference. Kobe, Japan.

24. Yuan-Ta Hsieh, J.-F. W.-L.-H.-Z.-D. (2012/10). A Dimmable LED Driver with an Ambient Light Sensor Based on a Constant Off-Time Control Technique. The 15th International Conference on Electrical

Machines and Systems. Sapporo, Japan.

25. Chen-Chia Chen, S.-H. H.-H.-C.-M.-M.-T. (2012/11). Multilayer Planar Micro-Coils Chip As Actuators and Heaters for Biological Applications. 2012 IEEE Biomedical Circuits & Systems Conference (BIOCAS

2012) . Hsinchu, Taiwan.


Publisher/

Chiueh, Tzi-Dar

Vice Publishers/

Chang, Chen-Hao

Wang, Jiann-Jenn

Editorial Committee/

Chang, Da-Chiang

Chen, Chi-Shi

Cheng, Xun-Chen

Chiu, Chin-Fong

Fanchiang, Yi-Chia

Huang, Chun-Ming

Juang, Ying-Zong

Tsai, Wei-Chang

Wang, Jen-Chieh

Wu, Chien-Ming

Imprint

Editor-in-Chief/

Wang, Jen-Chieh

Editorial Team/

Chen, Jen-Jia

Chen, Peng-Chun

Chien , Wei-De

Hsieh, Bing-Jang

Wang, Jiann-Jong

Art Editorial Team/

Chang, Meng-Chan

Liu, Hsin-Yu

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Copyright © 2013 by National Chip Implementation CenterPublished by National Chip Implementation CenterNational Applied Research Laboratories

7F, No. 26, Prosperity Rd. 1, Hsinchu Science Park, Hsinchu 300, Taiwan, R.O.C.TEL / 886-3-5773693FAX / 886-3-5774064http://www.cic.org.tw ISBN / 978-986-82443-7-5Printed in TaiwanPublishing Date / September 2013

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