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CITY UNIVERSITY OF HONG KONG DEPARTMENT OF

PHYSICS AND MATERIALS SCIENCE

BACHELOR OF ENGINEERING (HONS) IN MATERIALS ENGINEERING

2006-2007

DISSERTATION

SYNTHESIS AND CHARACTERIZATION OF SILICON

NANOWIRES AND SILICON NANOWIRE BASED FIELD

EFFECT TRANSISTOR

by

XIANG Jing Lei

March 2007

SYNTHESIS AND CHARACTERIZATION OF SILICON

NANOWIRES AND SILICON NANOWIRE BASED FIELD

EFFECT TRANSISTOR

by

XIANG Jing Lei

Submitted in partial fulfilment of the

Requirements for the degree of

BACHELOR OF ENGINEERING (HONS)

IN

MATERIALS ENGINEERING

from

City University of Hong Kong

March 2007

Project Supervisor : Prof. S. T. Lee

A. Content

A. Content I

B. List of graphs III

C. List of figures IV

D. Acknowledgment V

E. Abstract VI

1. Introduction

1.1 Silicon Nanowires 1

1.2 Silicon based semiconductors and technology 2-3

1.3 Silicon Nanowire-based nanoelectronics devices 4

2. Literature Review

2.1. Various methods in the synthesis of silicon nanowires

2.1.1 Template-Directed Synthesis 5-6

2.1.2 Vapor-Liquid-Solid growth 6-7

2.1.3 Oxide-Assisted Growth 7-9

2.1.4 Metal-Nanoparticle-Catalyzed Chemical Etching 9-11

3. Experimental Procedures 12

3.1 Synthesis of silicon nanowires by MNCCE 12

3.1.1 Characterization of SiNW 12

3.1.1.1 SEM 12

3.1.1.2 TEM 13

3.1.1.3 EDX 13

3.2 Simple Device Construction 13

3.2.1 Wafer preparation 13

3.2.2 Nanowire dispersion 14

3.2.3 Electrode deposition 14

I

3.2.3.1. Mechanical Mask Route (MMR) 14

3.2.3.2 .Photolithography Route (PR) 14

3.2.4. Positioning of SiNW 15

3.3 Field Effect Transistor Construction 15

3.3.1 Performance of SiNW in the ambient condition 15

3.3.2 Surface passivation by coating an oxide layer 16

3.4. Process of photolithography and experimental flow chart 17-18

4. Results and discussions

4.1 Properties of SiNW synthesized by MNCCE 19-20

4.2. I-V of SiNW prepared by mechanical mask 21

4.2.1. Effects of work function of the electrode material 21

4.2.2 Exchange electrodes measurements for contact check 22-23

4.3. I-V of SiNW prepared by photolithography 24-25

4.4. Effect of contact resistance 26-27

4.5. Gate construction for FET 28-32

4.5.1 SiNW in the ambient atmosphere 28-32

4.5.2 SiNW coated with a layer of SiO2 32-35

4.6. Possible errors involved in calculation 35

5. Conclusion 36-37

6. Future Work 37

7. List of Reference 38-41

II

B List of graphs:

Fig.2.1. Shadow sputtering against an array of V-grooves to form 1D nanomaterial

Fig.2.2 Vapor-phase deposition of 1D nanomaterials into V-grooves

Fig.2.3. Porous membrane used in the 1D structure synthesis

Fig.2.4 Nanomaterial synthesized by VLS mechanism

Fig.2.5 Phase diagram of Si-Au alloy

Fig.2.6 Schematic graph showing the Ag particle is pinned

Fig.2.7 Schematic graph showing the sinking track of Ag

Fig.2.8 Cross-section of SiNW synthesized

Fig.3.1. Electrode pattern on the wafer prepared by photolithography

Fig.3.2 Magnified electrode with marks

Fig.3.3. Schematic illustration of a two point probe station

Fig.3.4 The configuration of the SiNW device

Fig.3.5 Photolithography Technique

Fig.3.6 Experimental flow chart

Fig.4.1 SEM micrograph of SiNW synthesized by MNCCE

Fig.4.2 EDX pattern showing the composition of the SiNW

Fig.4.3 Band diagram for Schottky barrier

Fig.4.4 I-V curve of a Schottky barrier

Fig.4.5. Exchange electrode measurement of I-V

Fig.4.6 SEM of Sample A prepared by shadow mask

Fig.4.7.SEM of Sample B prepared by shadow mask

Fig.4.8 I-V characteristics of 3 samples prepared by shadow mask

Fig.4.9 Electrode pattern fabricated by photolithography without metal coating

Fig.4.10 Electrode pattern fabricated by photolithography with metal coating

Fig.4.11 SEM image of NW on electrode prepared by photolithography (Sp A)

Fig.4.12 SEM image of NW on electrode prepared by photolithography (Sp B)

Fig.4.13 Schematic illustration of contact area

Fig.4.14 I-V characteristics of the FET device

Fig.4.15 Explanation of linear region in the curve

III

Fig.4.16 Explanation of saturation region in the curve

Fig.4.17 Ids vs. Vg plotted in the linear scale and log scale. Inset is the SEM image of

the measured sample

Fig.4.18 Transconductance measured at every gate voltage in air

Fig.4.19 I-V characteristics of the FET device modified by SiO2

Fig.4.20 Ids vs. Vg plotted in the linear scale and log scale with threshold voltage

about 2 V. Inset is the SEM image of the measured sample

Fig.4.21 Transconductance measured at every gate voltage with oxide coated

C. List of Tables:

Table.4.1 Resistivity of SiNW measured from the photolithographic samples and

shadow mask samples

Table 4.2 Mobility obtained in the ambient condition and in SiO2 treated condition

IV

D. Acknowledgement

I would like to take this opportunity to express my gratitude and appreciation to my

supervisor, Professor S.T. Lee for his constant encouragement and support. The

enlightening discussion between Professor Lee and me has aroused great passion in

me to explore the beauty of science and technology.

I would also like to thank Dr.Jie for helping me get familiar with research

environment in the lab while demonstrating to me so many experiments that kept me

gravitated to the field of nanotechnology. The valuable advice he shared with me

inspired me a lot throughout the project.

I wish to thank all the Mphil students and PhD students in the Center of

Super-Diamond and Advanced Films for giving me so many help during the

experiment and sharing their research experience with me. Hereby, I would like to

thank Mr. Tang Hao, Mr. Chen Zhenhua, Mr Jack Chung and Mr. Ye Qing and etc.

particularly for their invaluable discussion with me on my project.

Also, I would like to thank my parents and my friends for their encouragement and

support without which the project will never be so successful. I treasure the kindness

of all the people who have helped me in the project and I believe I will live up to your

expectations.

V

E. Abstract:

Microelectronic technology has made a big difference in almost every corner of our

lives thanks to the progressive development of semiconductor industry. Nowadays,

people are making all those electronic devices smaller in size, and better in

performance. Yet, challenges also come along since further miniaturization of devices

require even better precision technology and the traditional planar fabrication

technology will soon feel its confinement. 1D nanostructured materials have brought

possibilities to overcome the difficulties and their potential to be applied in the

electronic industry has created excitement in a lot of research labs all over the world.

In this project, the SiNWs are used for all the experiments. They are synthesized by

the Metal-Nanoparticle-Catalyzed-Chemical-Etching method which provides a better

alignment of nanowires and easier controllability of its doping concentration as

compared to the chemical vapor deposition, laser ablation and thermal evaporation.

In order to measure the conductivity of the as-synthesized SiNWs, they were

dispersed onto the silicon wafer randomly. Different masks for lithography were used

to fabricate the electrodes. Shadow masking and photolithography defined the size and

the pattern of electrode layout. The electrode material to be deposited was also

carefully selected since either Schottky contact or ohmic contact would influence the

charge flow in the SiNW due to the difference between the work function of the metal

and that of the semiconductor. In order to achieve ohmic contact that allows the

current flow in either direction, metals with work function higher than the

semiconductor was used such as Au.

Once the I-V characteristic of the SiNW was measured, gate voltage applied to the

silicon substrate was also examined and the SiNW based field effect transistor was

thus constructed (similar to a metal-oxide-semiconductor structure). The transport

property of SiNW was manipulated by the application of different gate voltages. Since

the SiNW is of p-type, positive gate voltage tends to expel the holes in the nanowire to

the negative electrode, thus forming a depletion region with high resistance and a

VI

shallow conducting channel. The response of the SiNW FET shows an increase in the

conductivity of the SiNW and higher saturation voltage with the negative increase of

the gate voltage. Instead of scanning the source-drain voltage, the gate voltage was

scanned while keeping the source-drain voltage fixed. The current flow in the source

and drain and the corresponding gate voltage applied plotted in either linear or

logarithmic scale shed light on the threshold voltage and the depletion threshold

voltage of the device.

To improve the performance of SiNW FET, silicon dioxide layer was used to cover the

SiNW exposed in ambient environment. The surface was said to be isolated from

external environment and the transport properties were observed to change quite a lot.

The main mechanism accounting for the increase in hole mobility is the suppression

of reaction between the surface and molecular species and reduction of scattering by

the surface defects.

VII

Final Year Project by Xiang Jing Lei

1. Introduction:

1.1 Silicon Nanowires

A nanowire is a wire of dimension of the order of a nanometer (10−9 meters).

Alternatively, nanowires can be defined as structures that have a lateral size

constrained to tens of nanometers or less and an unconstrained longitudinal size. At

these scales, quantum mechanical effects are important — hence such wires are also

known as "quantum wires". Many different types of nanowires exist, including

metallic (e.g., Ni, Pt, Au), semiconducting (e.g., InP, Si, GaN, etc.), and insulating

(e.g., SiO2, TiO2). Nanowires usually exhibit an aspect ratio of 1000 and more. As

such they are often referred to as 1-Dimensional materials. Nanowires have many

interesting properties that are not seen in bulk or 3-D materials. This is because

electrons in nanowires are quantum confined laterally and thus occupy energy levels

that are different from the traditional continuum of energy levels or bands found in

bulk materials.

As for the synthesis of SiNW, much effort has been made to prepare them by different

methods, such as chemical vapor deposition,[1] laser ablation,[2,3] thermal

evaporation decomposition,[4,5] supercritical fluid liquid solid (SFLS) synthesis,[6-7]

and other methods. These methods are quite accessible and will be briefed in the

second chapter.

As the building blocks for future nanoelectronics, the 1D nanowire can be employed

as active devices or interconnects that have great potential in improving the

performance of the electronic devices prevailing in the market now because of their

small size and reduced power consumption. Yet, everything has a trade off and the

same for semiconducting nanowires. The conductivity of a nanowire is expected to be

much less than the bulk material. The primary reason is that the scattering from the

wire boundary will severely hinder the effective transport of carriers when the width

of the nanowires is less than the mean free path of charge carriers. The so-called edge

1


effects come from atoms that lay at the nanowire surface and are not fully bonded to

neighboring atoms like the atoms within the bulk of the nanowire. The unbonded

atoms are often a source of defects within the nanowire, and may cause the nanowire

to conduct electricity more poorly than the bulk material.

1.2 Silicon based semiconductors and technology

Silicon based semiconductor devices have been studied for more than 125 years. [8]

The building blocks for semiconductor devices are showing better performance and

adaptability to advance integrated circuits. The very primary components of

semiconductor devices in chronological order in terms of its invention are the

metal-semiconductor contact, the p-n junction, the heterojunction and the

metal-oxide-semiconductor (MOS) structure. The development of semiconductor

technology has made it possible for humans to fabricate more advanced integrated

circuits with the combination of all these basic semiconductor devices and their

derivatives.

Semiconductor technology

Crystal growth: From the starting material sand (silicon dioxide) to a silicon wafer,

several chemical processes are involved to form a high-purity polycrystalline

semiconductor from which single crystals are grown. The polycrystalline silicon is

placed in the crucible with the furnace heated above the melting temperature of silicon.

A suitably oriented seed crystal is suspended over the crucible in a seed holder and

inserted into the melt. Part of it melts, but the tip of the remaining seed crystal still

touches the liquid surface. It is then withdrawn. The progressive freezing at the

solid-liquid interface yields a large, single crystal. This method is called Czochralski

technique and virtually all the silicon used for fabricating integrated circuits is

prepared by this technique. Then, the ingots are shaped to define the diameter of the

material and sawed into wafers.

Film formation: To fabricate discrete devices and integrated circuits, we may use

2


different kinds of thin films, namely, thermal oxides, dielectric layers, polycrystalline

silicon, and metal films. Semiconductors can be oxidized by various methods; thermal

oxidation is by far the most important for silicon devices. Thermal oxidation of silicon

contains a reactor [9] consisting of a resistance-heated furnace, a cylindrical

fused-quartz tube containing the silicon wafers held vertically in a slotted quartz boat,

and a source of either pure dry oxygen or pure water vapor. The oxidation temperature

is generally in the range of 900-1200C and the typical gas flow rate is about

1liter/min.

Lithography and etching: lithography is the process of transferring patterns of

geometric shapes on a mask to a thin layer of radiation-sensitive material (called resist)

covering the surface of a semiconductor wafer. These patterns define the various

regions in an integrated circuit such as the implantation regions, the contact windows,

and the bonding-pad areas. The resist patterns defined by the lithographic process are

not permanent elements of the final device but only replicas of circuit features. To

produce circuit features, these resist patterns must be transferred once more into the

underlying layers comprising the device. The pattern transfer is accomplished by an

etching process that selectively removes unmasked portions of a layer.

Impurity doping: Diffusion and ion implantation are the two key methods of impurity

doping. Until the early 1970s, impurity doping was done mainly by diffusion at

elevated temperatures. In this method the dopant atoms are placed on or near the

surface of the wafer by deposition from the gas phase of the dopant or by using

doped-oxide sources. The doping concentration decreases monotonically from the

surface, and the profile of the dopant distribution is determined mainly by the

temperature and diffusion time. Since the early 1970s, many doping operation have

been performed by ion implantation. The doping concentration has a peak distribution

inside the semiconductor and the profile of the dopant distribution is determined by

the ion mass and implanted-ion energy. Both diffusion and ion implantation are used

for fabricating discrete devices because these processes complement each other.[10]

3


1.3 Silicon nanowire based nanoelectronic devices

Since the composition and dimension of SiNWs can be controlled during the synthesis

process, we can obtain a single SiNW with diameter less than 100nm for measuring

the electrical properties of the wire by placing under two electrodes being source and

drain respectively. The conductivity can be readily measured by 2 probe or 4 probe

station. The poor conductance of SiNW can be attributed to a list of factors, such as

the scattering effects of the boundary wire, the large contact resistance between the

metal and semiconductor interface, and also the presence of surface defects along the

wire. Furthermore, field effect transistor can be constructed by applying a back gate

voltage to measure the response of the SiNW in terms of its change in conductivity.

SiNW based field effect transistor can be turned on or off by the applied voltage

making it possible to be used as a potential switching device in advanced circuits. The

on/off ratio representing the performance of the FET device can be improved by

proper surface modification of the SiNW so that the defects on the surface of the wire

can be saturated; reducing the scattering sites of the charge carriers.

SiNWs can also be used to construct p-n diode thanks to the better alignment

technology including the Langmuir-Blodgett technique [11] and fluidic-directed

assembly [12], p-type SiNW and n-type SiNW can be crossed to form a junction, the

potential application also extends to other disciplines, revolutionizing the daily life of

human beings.

4


2. Literature Review

2.1. Various methods in the synthesis of silicon nanowires

2.1.1 Template-Directed Synthesis

Template-directed synthesis represents a straightforward route to 1D nanostructure.

The template simply serves as a scaffold within (or around) which a different material

is generated in situ and shaped into a nanostructure with its morphology

complementary to that of the template. When the template is only involved physically,

it is often necessary to selectively remove the template using post-synthesis treatment

(such as chemical etching and calcination) in order to harvest the resultant

nanostructures. In a chemical process, the template is usually consumed as the

reaction proceeds and it is possible to directly obtain the nanostructures as a pure

product.

As shown by Jorritsma and co-workers [13], metal nanowires as thin as 15nm could

be prepared by shadow sputtering a metal source against an array of V-grooves etched

on the surface of a Si(100) wafer. Fig.2.1. In another procedure, metal or

semiconductor was applied at normal incidence using techniques based on

vapor-phase deposition or solution-phase electrochemical plating, and then allowed to

reconstruct into 1D nanostructure at the bottom of each V-groove Fig.2.2.[14] Using

these approaches, continuous thin nanowires with lengths up to hundreds of

micrometers could be routinely prepared as parallel arrays on the surfaces of solid

supports that could be subsequently released into the free-standing form or be

transferred onto the surfaces of other substrates.

Channels in porous membranes provide another class of templates for use in the

synthesis of 1D nanostructure pioneered by Martin and several others. [15] Two types

of porous membranes Fig.2.3 are commonly used in such synthesis: polymer films

containing track-etched channels and alumina films containing anodically etched

pores. For track-etching, a polymer film (6-20 microns) is irradiated with heavy ions

5


to generate damage spots in the surface of this film. The spots are amplified by

chemical etching which facilitates the penetration of cylindrical pores into the films.

[16] A variety of materials have been examined for use with this class of templates.

The requirement for this method is that the material can be loaded into the pores using

liquid phase injection, or solution-phase chemical or electrochemical deposition.

Although the nanowires synthesized by this method are usually polycrystalline, the

major advantage associated with membrane-based templates is that both the

dimension and composition of nanowires can be easily controlled by varying

experimental conditions.

Fig. 2.1 Fig. 2.2

Fig. 2.3

Fig.2.1. Shadow sputtering against an array of V-grooves. Fig.2.2 Vapor-phase

deposition of 1D nanomaterials into V-grooves. Fig.2.3. Porous membrane used in the

1D structure synthesis.

2.1.2 VLS growth of silicon nanowires

The vapor-liquid-solid mechanism Fig.2.4 described in detail by Wagner and his

co-workers [17-19] is one of the many common ways to synthesize the silicon

nanowires catalyzed by gold nanoparticles. The name arises from the fact that the

silane [20] semiconductor vapor phase reactants usually taken as the source of silicon

6


will alloy with gold nanoparticles which are in a melted state when heated. As long as

the temperature is higher than the eutectic temperature of the binary system Fig.2.5,

the silane will decompose at the surface of the gold nanoparticle and the silicon will

dissolve into the liquid gold nanoparticle. As silicon continues to dissolve in the gold,

saturation will eventually occur as predicted by the phase diagram of the binary alloy

system. After that, the silicon will precipitate out from the liquid phase to form the

solid nanowire as we require. Since the eutectic temperature of Si-Au binary alloy

system is around 363C [21], theoretically the temperature of synthesizing the silicon

nanowire can be around 400 degrees which is not that high. The size of the as-grown

silicon nanowires is controlled by the dimensions of gold nanoparticles and the growth

rate is dependant on the partial pressure and temperature of the growing environment.

Growth defects such as kinking and bending are observed from the experiment due to

the different conditions used to grow the nanowires. The growth direction, as can be

predicted by thermodynamic principles, is along <111> family.[22-23]

Fig. 2.4 Fig.2.5

Fig.2.4 Nanomaterial synthesized by Fig.2.5 Phase diagram Si-Au alloy

VLS mechanism

2.1.3 Oxide Assisted Growth

Another way to synthesize silicon nanowires in the absence of metal catalyst was

proposed by Lee and co-workers [5] several years ago by laser ablating a mixture of

7


Si and SiO2. The vapor phase SixO generated by laser ablation seemed to be the key

intermediate in this oxide assisted process. The formation of silicon was believed to

occur through the following two steps:

SixO Six-1 + SiO (x>1)

2SiO Si + SiO2

The TEM observations suggested that these decomposition reactions first led to the

precipitation of Si nanoparticles encapsulated in shells of silicon oxide. Some of these

particles might be piled up on the surface of the silicon oxide matrix, and served as

seeds for the growth of nanowires in the following steps. SixO (x >1) layer at the tip of

each nanowire seemed to have a catalytic effect. This layer might be in or near a

molten state and thus capable of enhancing atomic absorption, diffusion, and

deposition. The SiO2 component in the shell might help to retard the lateral growth of

each nanowire. The precipitation, nucleation and growth of Si nanowires always

occurred in the region closest to the cold finger suggesting that the temperature

gradient was the driving force for the nanowire growth.[24-30]

OAG growth with Au catalysts

The diameter of the SiNWs grown by OAG method is determined by the ambient

environment such as He, H2+Ar or N2 that controls the cluster migration and phase

transformation of the tip of the SiNW. Lee and co-workers [31] proposed OAG with

gold catalyst to grow SiNW with better dimensional control.

The mechanism is just the combination of the VLS and OAG methods. The reduced

growth temperature relative to that of metal-free OAG may be attributed to the Au

catalytic effect in lowering SiO decomposition temperature. During growth, the

arriving silicon atoms have to diffuse through the thin oxide layer to reach the Au

particle. Thus, the growth temperature should be sufficiently high to allow silicon

penetrating through the oxide layer to form the eutectic alloy so as to sustain the

growth of SiNWs. The Au-SiO approach offered certain advantages over VLS growth

8


and OAG, such as the absence of toxic and flammable gases and the control of size

and epitaxial growth of SiNW. The nanowires primarily grew along the <1 1 2> and

<1 1 0> directions, similar to SiNWs grown by the OAG method without any catalysts.

The side surfaces of the SiNW are made of the {1 1 1} and {1 1 0} facets for the

nanowire grown along [1 1 2] direction. The presence of those crystal facets could

minimize the total energy of the nanowire because the surface energy of the {1 1 1}

facets is the lowest and the energy of the side surfaces dictates the total surface energy

of a SiNW [32]

2.1.4 Metal-nanoparticle catalyzed chemical etching

Besides all the methods that I have introduced above in the synthesis of SiNWs, there

is still one important mechanism which involves the electrochemical reaction in

synthesizing nanomaterials. Since Si shows novel electrochemical properties in

solutions containing hydrofluoric acid, Peng and co-workers [33] proposed electroless

metal deposition (EMD) [34-37] and electroless etching in the synthesis of SiNW.

The electroless metal deposition describes a galvanic displacement process that

involves the spontaneous oxidation of Si and reduction of metal ions to metal particles

without external electrical power source. In the case of electroless deposition of Ag in

AgNO3/HF solution, the energy level of the system Ag+/Ag lies well below the Si

valence band, simultaneous electrochemical processes including the reduction of Ag

ions and the oxidation of silicon atoms occurs, silver ions are able to capture the

electrons in the VB of silicon atoms and being reduced while the silicon atoms are

being oxidized in the solution. As soon as the silicon oxide form below the Ag

nanoparticle, the HF solution will etch it away and the Ag particle sinks into the hole

which is kept immobile in the horizontal direction. Since the Ag nanoparticle is more

electronegative to silicon, it continues to capture electrons from the silicon atoms and

the Ag- ions formed will attract more Ag+ from the solution, silicon beneath the Ag

particle continues to supply the electrons needed for reduction of metal ions and the

nanoparticle is becoming larger in size along with the deposition process. With longer

9


immersion time in the solution, the Ag particles that do not enter the pits will grow

into the branched silver dendrites.

In another system involving Fe (NO3)3/HF solution with Ag nanoparticles dispersed

on the silicon substrate, the temperature is as low as 50 degrees, the redox reaction

between the silicon atoms and Fe ions is very slow. Yet, the whole process can be

speed up by covering the silicon substrate with a layer of Ag nanoparticle film. Metal

contamination has a strong catalytic activity for the cathodic reaction. The Ag

nanoparticle can act as local micro-cathodes which are for the reduction of Fe ions,

owing to the more positive redox potential of Ag+/Ag system compared to Fe3+/Fe2+

couple, the general reaction equation is presented below:

Fe3+ + e- Fe2+;

Si (s) + H2O SiO2 + 4H+ + 4e-;

SiO2 + 6HF H2SiF6 + 2H2O;

Therefore, in the Ag/Si/HF/Fe(NO3)3 system, the Fe3+ ions have a strong tendency to

obtain electrons preferentially from Ag particles and be reduced to Fe2+ ions, while the

silicon underneath the Ag nanoparticles is locally oxidized into SiO2. The reaction

proceeds as long as the Si atoms are able to dissolve into the solution, or until thick

SiO2 forms, thereby halting electron transfer. In the present HF/ Fe (NO3)3 solution,

the dissolution rate of SiO2 by HF is higher than the Si oxidation rate by Fe (NO3)3.

Therefore, the Si surface is always exposed to the solution.

Since the Ag nanoparticle is pinned Fig.2.6 in the hole there is confinement in the

horizontal movement. All Ag nanoparticles will just sink Fig.2.7 in the holes and their

sinking tracks will interconnect with each other and the silicon substrate looks porous

in this sense. The walls of the pores Fig.2.8 that are left by the Ag nanoparticle

constitute the 1D SiNWs as observed in the SEM. The galvanic displacement process

will not come to a halt until the Fe3+ ions are exhausted in the reaction solution. By

utilizing this method, single-crystalline SiNWs with desirable crystallographic

10


orientations can be readily and controllably created by the selection of Si wafers with

the corresponding crystallographic orientations. [38]

Fig.2.6 Fig.2.7

SiNW synthesized

Fig.2.8

Fig.2.6 schematic graph showing the Ag particle is pinned. Fig.2.7 schematic graph

showing the sinking track of Ag. Fig.2.8 cross-section of SiNW synthesized

11


3. Experimental

3.1 Synthesis of silicon nanowires by metal-nanoparticle catalyzed chemical

etching

The synthesis of large-area oriented 1D silicon nanostructure arrays was conducted in

a Teflon-lined stainless steel autoclave. The production process comprises 3 steps: 1)

the silicon wafers were cleaned with acetone (5 min), ethanol (5 min), deionized water

(2-3 times) and H2SO4/H2O2 (3:1 H2SO4 (97%)/H2O2 (30%),10 min), then the wafers

were thoroughly rinsed with deionized water (10 min) and dipped into a solution of

HF (1 min); 2) electroplating the metal-nanoparticle films onto the cleaned silicon

surface; and 3) immersion of the metal-nanoparticle-covered silicon wafers into

HF-based aqueous chemical etching solutions contained in a sealed vessel and treated

for the desired time (20–60 degrees).

All the experiments described here were performed at 50 degrees. The thickness of

films (or the length of 1D silicon nanostructures) could be effectively controlled

through adjusting the etching time, and film sizes could be readily made as large as

needed and are ultimately limited only by the vessel dimensions. The concentrations

of HF and AgNO3 for the deposition of Ag nanoparticle films were 4.6 and 0.01m,

respectively.

3.1.1 Characterization of SiNW

3.1.1.1 SEM

The morphology of the SiNWs were examined with a Philips XL30 scanning electron

microscope (SEM) equipped with a field emission gun (FEG) which emits electrons to

bombard the sample surface and the secondary electrons on the surface will recoil.

Thornley-Everhard secondary electron detector is used to collect the recoiled

secondary electrons and form the images of the sample through computer processing.

12


3.1.1.2 TEM

Transmission electron microscope (TEM) was used to examine the crystal structure of

SiNWs. TEM working principle is like a slide projector. The electron gun in the TEM

projects a beam of electron through the sample. While the electron beam passes

through the sample, the beam is deflected by the lattice structures and the materials of

the sample. The transmitted beam is then projected onto the viewing screen, forming

an enlarged image of the sample. The diffraction mode in TEM could clearly show the

electron diffraction pattern of the SiNW showing the crystal structure of the material.

3.1.1.3 EDX

EDX is used in conjunction with SEM. An electron beam strikes the surface of a

conducting sample. The energy of the beam is typically in the range of 10-20keV.

This causes X-rays to be emitted from the point of the material. The energy of the

X-rays emitted depends on the particular material. Therefore, EDX was used to

characterize the composition of SiNWs.

3.2 Simple Device Construction

3.2.1. Wafer Preparation:

After the silicon nanowires were successfully prepared by metal-nanoparticle

catalyzed chemical etching method. They were carefully scratched off from the silicon

substrate surface and dissolved into the ethanol. In order to have a better dispersion of

the SiNW in the ethanol, the sample was ultra-sonicated for 15 minutes. At the same

time, the Si/SiO2 substrate with the oxide thickness of about 300nm was sterilized first

by ethanol because the application of ethanol would kill organisms by denaturing their

proteins and dissolving their lipids. Then the wafer was again sterilized by acetone

which was used to remove the organic substances on the wafer. Deionized water was

used so as to remove the possible remains of ethanol and acetone.

13


3.2.2. Nanowire dispersion:

After the SiNWs have been immersed in the ethanol for a certain amount of time, it

was ready for dispersion onto the silicon substrate which has already been placed on

the heater for a better dispersive property. A sucker was used to suck a little bit of

SiNW solution to drop on the substrate. The droplet, once it has contacted the surface

of the wafer, would soon diffuse out and gradually covered the entire surface. This

suck and drop process was repeated for 10 to 20 times to ensure that the SiNWs could

be uniformly distributed onto the wafer surface having a concentration as expected.

3.2.3. Electrode fabrication:

3.2.3.1. Mechanical Mask Route (MMR)

The first method was shadow mask: a shadow mask with through slots aligned

properly on the mask was used and it was tightly pinned on the wafer. The slots were

places where metal vapor could be successfully deposited on while leaving the

covered area unexposed to the metal vapor. Gold electrodes were deposited on the

silicon substrate by electron beam evaporation and gapped for further inspection of the

electrical properties of SiNWs. In the last step, the shadow mask was removed.

3.2.3.2 .Photolithography Route (PR)

In stead of using the shadow mask, we used a Cr mask with electrode patterns. The

wafer was initially heated to drive off the excessive moisture that might be present in

it. Photoresist (AJ5206E) was then applied in its liquid form onto the substrate as it

underwent rotation. The speed of rotation (3500 rev/min) determined the thickness of

the photoresist dispersed on it. The photoresist-coated wafer was then transferred to a

hot plate where a soft bake would be applied to drive off excessive solvent before the

wafer was introduced into the exposure system. Light from a mercury arc lamp was

focused through a complex system of lenses onto a "mask" (also called a reticle),

containing the desired image. The light passed through the mask and was then focused

to produce the desired image on the wafer through a reduction lens system.

14


Polymeric Developers were applied to remove the exposed photoresist. Gold was then

deposited onto the windows etched away by the developer and lift-off technique was

used to remove the unexposed photoresist.

3.2.4. Positioning of SiNW for inspection

After the SiNWs were successfully dispersed onto the wafer, in order to measure the

conductivity of a single SiNW or a bunch of nanowires contacting the electrodes,

microscopic examination was needed to ensure that the nanowires were electrically

contacted. Proper reference was made that we could record the exact position of the

qualified nanowires for further analysis. The electrode pattern Fig.3.1-2 on the silicon

wafer was shown below and the electrodes were marked with numbers. If nanowires

were found to be lied across two, three or four electrodes, then probe could be placed

on the appropriate electrodes for measurement of current through the nanowires.

Fig.3.1 Fig.3.2

1 3

2 4

Fig.3.1. Electrode pattern on the wafer Fig.3.2 Magnified electrode with marks

3.3. Field Effect Transistor and two-point measurement

3.3.1 Performance of SiNW in the ambient condition:

Since the substrate was composed of a layer of silicon and a layer of silicon oxide, we

could apply a voltage to the silicon substrate as the back gate. Due to the small size of

15


the substrate, it was rather difficult to apply the voltage directly. A piece of copper was

attached to the conducting glue which directly contacted the bottom of the silicon

substrate. A MOS structure was formed and the electrostatic potential could be altered

by changing the gate voltage.

A two point probe station Fig.3.3 was used to measure the I-V characteristics of the

device and data could be collected automatically by the computer to calculate the

mobility of the charge carriers in the SiNW.

Fig.3.3. Schematic illustration of a two point probe station

3.3.2. Surface passivation by coating a layer of SiO2 onto the SiNW:

A layer of silicon oxide (200nm) was evaporated onto the SiNWs to cover all the

surface of the substrate. Although the electrode material gold was also covered with a

layer of oxide, it would not affect the measurement since the adhesion between the

silicon oxide and gold was poor and could be scratched off easily by the probe tip. The

FET characteristics were measured. Schematically, the graph is shown as in Fig.3.4

Glass

Conducting glue Silicon Wafer

2 point probe

Copper plate

16


Gold SiNWSilicon oxide

Substrate

Fig.3.4 the configuration of the SiNW device

3.4.Process of photolithography and experimental flow chart:

The following two graphs Fig.3.5 and Fig.3.6 show the process of photolithography

and the experimental flow chart:

Fig.3.5 Photolithography Technique

17


Fig.3.6 Expe al flow chart

riment

18


4. Results and discussion:

4.1. Properties of silicon nanowires synthesized by MNCCE

For the SiNWs synthesized by the VLS method, there are several problems that we

have to address; firstly, the reactive gas used in this case is toxic and flammable,

secondly, it is difficult for us to remove the metal particle on top of the nanowires and

thirdly, doping of the SiNW involves a series of processes not that easily controlled.

The same problem also exists in the OAG + VLS method although both methods

involve the gold metal particle to help manipulate the size of the SiNW as synthesized.

Yet the biggest advantage of using the silver particle catalyzed chemical etching

method to synthesize the SiNW is the controllability of its doping density because the

silicon wafer is pre-doped to be n-type or p-type with a certain doping concentration.

The silver particles deposited on the silicon substrate will sink into the pits and the

substrate is said to be etched. Actually, the SiNWs formed are the walls of the silver

nanoparticle sinking tracks. So the morphology of the nanowires is of irregular shape

and the interconnectedness of the sinking tracks has made the silicon substrate appear

porous. Among other things, as long as the etching process continues, there will be a

layer of silver dendrites deposited on the silicon substrate. The superfluous silver ions

are reduced and grow on the dendrite to form a layer, which can effectively prevent

the deposition of silver atoms on the small silver particles trapped in the pits.

Schematically the synthesis process is illustrated as below and the morphology of the

p-type SiNW is also shown in the SEM micrograph shown in Fig.4.1, element

composition of the SiNW is examined by EDX shown in Fig.4.2 and we found that

the SiNW is composed of Si mainly. Since the material is prepared in the copper

meshwork, the high intensity of copper signal is reasonable.

19


Fig.4.1 SEM micrograph of SiNW synthesized by MNCCE

Fig.4.2 EDX pattern showing the composition of the SiNW

20


4.2. I-V characteristics of SiNW prepared by mechanical mask:

4.2.1. Effects of work function of the electrode material:

In order to measure the electrical conductivity of the SiNW, voltage was applied

across the nanowire. The voltage was scanned from -2 volts to 2 volts and the

corresponding current level was measured. The choices for different electrode

materials will have a large impact on the current-voltage characteristics because of the

different work functions. Whenever the work function of the electrode material is

smaller than that of the p-type semiconductor, the Fermi level of the metal and

semiconductor should line up and ensure that the vacuum level across the two

materials is continuous. In the first case, the electrode material chosen is Ag and the

work function is 4.63eV comparing to the p-type SiNW which is 4.99eV, so the

semiconductor will bend downwards creating a potential barrier for holes to cross

from semiconductor to the metal. The Schottky barrier serves to restrict the flow of

charge carrier in one direction. The I-V characteristic has shown very clearly that the

current will increase exponentially in the positive voltage range while maintaining a

very small value in the negative range value. To explain this phenomenon by band

diagram Fig.4.3, positive voltage will reduce the potential barrier, making it easy for

holes to move, while potential barrier will be increased if a negative voltage is applied,

restricting further the flow of holes. The I-V curve is shown in Fig.4.4

Fig.4.3 Band diagram for Schottky barrier

On the other hand, if the electrode material used is Au whose work function is larger

21


than that of p-type SiNW, since there are more energetic holes in the metal side, they

will tunnel to the semiconductor in search of lower energy until the equilibrium is

reached, i.e. the alignment of Fermi energy in both sides. The holes will accumulate at

the contact region and the conducting holes in either side have about the same energy

level and there is no barrier in between when they cross the junction in either direction

under the influence of an applied field. In the case of ohmic contact, the linear region

is used to calculate the resistance of the SiNW together with its contact resistance

once the slope of the curve is obtained by OriginPro 7.5.

Fig.4.4 I-V curve of a Schottky barrier

4.2.2 Exchange electrodes measurements for contact check:

In order to check whether the contact between the electrode and the semiconductor

has constrained the flow of the charge carriers, I-V curve was measured twice while

the electrodes were exchanged in the second time. One thing to be noted is that if the

two I-V curves appear the same in the two cases, it is solid evidence that the contact is

ohmic and the contact is not imposing a restriction on the direction of the charge flow.

On the other hand, if the two curves appear symmetric with respect to the origin (0,0),

the contact is not ohmic and a rectifying effect may take place. This technique is

usually applied when the current is rather small and we can not simply decide whether

the small current is caused by the contact effect or the pinch-off effect. Fig.4.5

22


Fig.4.5. Exchange electrode measurement of I-V

SEM images Fig.4.6-7 show the configuration of the SiNW lying on the gap of the

electrodes. Since the conductivity of the etched SiNW is the same as that of the silicon

wafer, I can compare the values of the calculated results with the reference parameter

of the silicon wafer given by the manufacturer. Three samples are measured and their

I-V characteristics are shown in Fig.4.8

The slope of the linear region estimated by linear fit is B=VI

ΔΔ . The resistance R of the

p-type SiNW is calculated according to Ohm’s Law by R=IVΔΔ , the reciprocal of the

slope. Also, intrinsically, the resistance R=ALρ , where ρ is the resistivity of SiNW

and L is the length of the SiNW; A is the cross-section area of the SiNW, respectively.

23


Fig.4.8 I-V characteristics of 3 samples prepared by shadow mask

Fig.4.6 SEM of Sp A Fig.4.7.SEM of Sp B

4.3. I-V characteristics of SiNW prepared by photolithography

The process of photolithography was briefly introduced previously, and the major

advantage is that the electrical property of single nanowire can be possibly measured

due to the shorter length of the electrode in the central and the gap distance is also

reduced to 2 micros. Such design has effectively increased the possibility of capturing

a single nanowire crossing the electrode and it is far better than the mechanical mask

24


in which the gap length is long and the electrical property that we have measured may

consist of a bundle of SiNWs instead of a single one. SEM images Fig.4.11-12 show

the sample A and B prepared by photolithography.

SiNW found lying on the central

Fig.4.9 Electrode pattern fabricated by Fig.4.10.Electrode pattern fabricated by

PL without metal coating PL with metal coating

Fig.4.11 SEM of nanowire lying on the Fig.4.12 SEM of nanowire lying

electrode prepared by PL (Sp A) on the electrode prepared by PL (Sp B)

25


The table presents the results of the calculated resistivity of the SiNWs either through

photolithography technique or shadow mask technique.

Shadow Mask Length(cm) SectionalArea(cm2) B(slope) R(B-1) ρ (Ωcm)

Sample A 3.0E-4 1.26E-9 3.80E-7 2.6E6 10.92

Sample B 2.0E-4 1.14E-9 2.151E-7 4.65E6 26.5

Sample C 5.3E-4 1.26E-9 5.031E-8 2.0E7 47.4

Photolithography Length(cm) SectionalArea(cm2) B(slope) R(B-1) ρ (Ωcm)

Sample A 2.0E-4 3.14E-10 9.86E-8 10E7 15.7

Sample B 2.0E-4 2.15E-10 1.06E-7 9.4E6 10.11

Table.4.1 Resistivity of SiNW measured from the photolithographic samples and

shadow mask samples.

The reference value of the silicon substrate is 9-13Ωcm as compared with the results

presented by the table, the photolithographic route yields better accuracy.

4.4. Effect of contact resistance between the semiconductor and metal

From the Table 4.1 shown above, the calculated resistivity of the SiNW deviates a lot

from the reference value. The reason is that it is difficult to tell how many nanowires

are lying across the electrode gap, yet the I-V curve is a reflection of the general

profile of the nanowires successfully dispersed on the gap and may not be useful in

calculating the resistance of a single nanowire as we have expected.

The result shown by the photolithography improved due to the shorter strips of

electrodes and the electrical property of single nanowires could be manageably

obtained. Yet another important issue we could not afford to ignore is the large contact

resistance of the metal-semiconductor interface. The contact resistance is inversely

proportional to the contact area. In the case concerned, the SiNWs are surrounded by a

layer of very thin Ti about 1nm. The reason why the Ti layer is deposited is that once

26


the developer etches the photoresist, the underlying oxide is exposed to the air. Gold

can not be directed evaporated onto the silicon substrate because of its poor tackiness

to the oxide. The layer of Ti acts as a buffer layer so that gold can contact well with

the SiNW as well as the substrate. Due to the extreme thinness of Ti layer, the contact

between the Au and the SiNW is still ohmic. The quality of metal evaporation and the

coverage of gold film onto the nanowires are of great importance in calculating the

resistance of the bulk SiNW. The surface of the interface might be very rough all the

way along the contact, making the actual contact area much smaller than the apparent

contact area illustrated in Fig.4.13. When the SiNW is synthesized by MNCCE and

prior to electrode deposition, the surface of silicon oxide might be oxidized to a

certain extent in the atmosphere. This layer of oxide film might be gapped between

the metal and the semiconductor restricting the flow of charge carriers. The surface

defects such as voids and pores and impurities could serve as scattering sites reducing

the MFP of the charge carriers and the contact resistance could be very high in this

case. Possible solution to reduce the contact resistance is to anneal the

metal-semiconductor in high temperature for a while, the stress and strains could be

annealed out with time and gold film could flow to cover the SiNW well in order to

increase the contact area.

Fig..4.13 schematic illustration of contact area

27


4.5. Gate construction for Field Effect Transistor

4.5.1. SiNW in the ambient environment

Measuring the I-V curve of a single SiNW under the source drain voltage gives us

information about the intrinsic conductivity of the nanowire. Yet, the conductivity of

the semiconductor wire can also be altered by applying a gate voltage on the silicon

substrate. The effect of the gate voltage on the conductivity of the SiNW can be

interpreted from the corresponding I-V measurements

The original curve actually locates at the third quadrant and I convert the graph into

the first quadrant for better observation. Among the I-V characteristics shown in

Fig.4.14 of the SiNW under different gate voltages marked by different colors, there is

one thing in common, current increases with the negative increase of source-drain

voltage, a linear relationship between I-V is observed. Yet, the current will not

increase infinitely with voltage until saturation occurs which means that beyond

certain voltage, the current remains almost the same. The principle of the existence of

linear region in Fig.4.15 and the saturation region in Fig.4.16 can be explained by the

expansion or shrinkage of conducting channel in the SiNW. As shown schematically

in the draft, the drain is connected to the ground with zero potential, and the voltage is

input from the source. The gate voltage is input from the silicon substrate. e.g. if the

source input is -2 volts, then the potential along the SiNW should be from -2 volts to 0

volt and assume no voltage is applied to the silicon substrate, then the potential

difference at the source is the difference between the gate voltage and the source

voltage, (in this case, the voltage will be 0-(-2) =2 volts) similar principle will apply to

all the points along the SiNW. Since the majority of charge carrier in the p-type SiNW

is hole, positive voltage will expel holes and a depletion region will form. The positive

voltage along the SiNW is decreasing, so is the depletion region. Once the voltage at

the source is large enough to deplete all the holes, pinch-off occurs and the current

remains almost the same. Increase of the saturation voltage will enable the pinch-off

point to move towards the drain, flatness of the I-V curve at higher voltage is

28


attributed to the fact that the pinch-off voltage remains the same, so do the number of

holes that are attracted to the pinch-off point P.

Conducting channel of SiNW (shaded)

SiO2

Si

Fig.4.15 Explanation of linear region in the curve

Depletion Region

Fig.4.16 Explanation of saturation region in the curve

When the gate voltage is applied on the silicon substrate, the potential along the

SiNWs is changed, the negative voltage of the gate will attract more holes in the

SiNW and the pinch-off (corresponding to saturation) occurs at a higher negative

voltage given the fact that pinch-off voltage remains the same. The conductivity of the

SiNW under the linear region increases with negative gate voltage as evidenced by the

steeper slope of the linear region.

29


Fig.4.14 I-V characteristics of the FET device

In order to inspect deeper into the device response to the gate voltage, the source-drain

voltage is maintained while the gate voltage is scanned so as to examine the Ids versus

the Vg, both linear scale and logarithmic scale is used to inspect the relationship

between the current and the voltage. The source-drain voltage is fixed at -0.2 volts.

From the Fig.4.17 the threshold voltage defined as the voltage to turn on or off the

device is approximated as an intersecting point on the x-axis by the tangential line

where the curve assumes best linearity. The on/off current ratio observed from the

logarithmic plot is estimated to be about 103. The transconductance defined as the

dIds/dVg is plotted against the gate voltage for every single Vg shown in Fig.4.18 and

the largest value of transconductance is found which later will be used in the

calculation of the hole mobility.

30


Fig.4.17 Ids vs Vg plotted in the linear scale and log scale. Inset is the SEM image of

the measured sample

Fig.4.18 Transconductance measured at every gate voltage

31


The capacitance of the SiNW is calculated from the following equation assuming the

metal cylinder on an infinite metal plate model [39]:

C= )/4ln(/2 0 dhLπεε

ε is the dielectric constant of SiO2 and ε 0 is the dielectric constant of vacuum. L is

the source-drain nanowire length, h is the SiO2 thickness and d is the diameter of

SiNW.

The hole mobility of SiNW is obtained with the equation described below:

VVsdgVsdLC

m 2.012 −=－）＝（μ ,

C is capacitance of nanowire, L is the source-drain nanowire length, Vsd is source

drain voltage kept constant, gm is the transconductance of SiNW.

Due to the limited time, I have only measured two samples. The results of the samples

are presented in the Table 4.2 below:

4.5.2. SiNW coated with a layer of oxide

Since the transport property can be affected by the ambient environment, the

deposition of a layer of SiO2 can effectively passivate the surface and the molecular

species in the atmosphere will have the least effect on the SiNW.

As observed from the response of I-V under different gate voltages Fig.4.19, the

current was obviously larger than the sample in the air. I shrank the range of Vds to

-0.2V so that the device still remained in the linear region. The increase of

conductivity could be easily interpreted from the slope of the I-V curve. Compared

with the result of the experiment done in atmosphere without the shielding of the

coating layer, the current is observed to increase phenomenally by almost two orders

of magnitude in this case. In this case, the threshold voltage is about 2 volts and the

on/off current ratio reaches 104 as observed in the Fig.4.20. The maximum

32


transconductance is obtained from Fig.4.21 corresponding to the gate voltage of -2V.

The major mechanism accounting for the increase in conductance and mobility is that

charge carriers will be protected from its external environment unlike the presence of

oxygen in the ambient condition that will trap the holes compromises the conducting

channel in the surface by forming a depletion region. Also, other species in the air will

not have the direct route to contact the surface of the SiNW, maintaining the surface to

be intact and free of external disturbance.

Fig.4.19 I-V characteristics of the FET device modified by SiO2

33


Fig.4.20 Ids vs Vg plotted in the linear scale and log scale with threshold voltage about

2 V. Inset is the SEM image of the measured sample

Fig.4.21 Transconductance measured at every gate voltage

34


The results of the samples in the ambient condition and the result from the sample

coated by a layer of oxide are presented in this table with key parameters highlighted:

Table 4.2 mobility obtained in the ambient condition and SiO2 treated condition

Air Diameter(m) Length(m) h (m) Vsd(V) gm C μ

Sp A 1.5E-7 2.5E-6 3E-7 0.2 3.34E-8 2.61E-16 40.03

Sp B 1.5E-7 4E-6 3E-7 0.2 8E-9 4.17E-16 15.34

SiO2 Diameter(m) Length(m) h (m) Vsd(V) gm C(F) μ

Sp A 1.5E-7 2.5E-6 3E-7 0.06 6.8E-8 2.61E-16 271.68

4.6. Possible errors involved in calculation:

The threshold voltage as determined from the Vg intersected by the tangential line in

the maximum slope of the Ids vs. Vg may not be very accurate since certain mobile

charges or fixed charges are already present in the interface of the silicon oxide and

the silicon substrate. The positive charge they carry may contribute to the threshold

voltage and Vth as found may be underestimated in the real case.

Also, since the expression used for all calculation of nanowire capacity is based on the

assumption that the nanowire is an equipotential surface like in metals. However, the

SiNW as synthesized with a doping concentration (lower than a certain concentration)

may not qualify it to assume a metallic nature. So the expression used may not be very

accurate. Another error resulting from the calculation of nanowire capacitance is its

irregular geometry. The expression only accounts for the calculation in the case of a

cylindrical nanowire. The SiNWs produced by metal particle catalyzed chemical

etching do not have proper shape that facilitates the calculation.

35


5. Conclusion

In this project, p-type SiNWs are synthesized by metal-nanoparticle-catalyzed

chemical etching method. The as-synthesized SiNWs have exhibited good alignment

and easier control of doping concentration within the SiNW. It provides us a very

convenient way to cast the SiNW with the desired doping concentration for practical

application without going through the complicated process of doping the SiNW during

its synthesis. The cross section of the as-synthesized SiNW is irregular due to the

mechanism of etching and this may affect the charge transport in the SiNW devices

and their overall performances.

Simple devices can be constructed with the 1D nanowire through several processes,

namely, preparation of silicon wafer, dispersion of nanowires randomly onto the wafer,

lithography technique to transfer a pattern of a mask onto the silicon substrate,

deposition of electrode contact material followed by measurement of transport

properties of the particular nanowires. Among all these processes, deposition of

electrode material into the open windows can be critical in device construction.

Electrode materials with an appropriate work function should also be carefully

selected to form ohmic contact with the semiconductor nanowire instead of a contact

barrier. In addition, the contact resistance between the semiconductor and the metal

also affect the behavior of devices due to the defects in the interface of the two

materials serving the scattering sites for charge carrier and the real contact area is

much less than the apparent one.

To measure the transport characteristic of SiNW such as the conductance of SiNW and

mobility of charge carriers, a gate voltage is applied to the silicon substrate to

construct a SiNW-based FET. The response of SiNW in terms of its Ids vs. Vds curve

will show the effects of the gate. For p-type devices, negative gate voltage attracts

more holes to the conducting channel so as to increase the carrier density while

positive voltage expels the holes and form a depletion region. Current saturation will

36


occur when pinch-off point is reached meaning the depletion region is so wide as to

cut off the conducting channel in the SiNW.

Improvement is observed when the surface of SiNW is covered with a layer of

insulating silicon oxide which has effectively eliminated the influence of external

environment. The conductance and mobility increases quite compared with the result

obtained in the ambient environment. This is a clear indication of the effect of

molecular species on the surface property of SiNW. It is predicted that certain

molecules in the atmosphere can trap the holes in the surface of the nanomaterials

although the details of the mechanism is not clear yet.

6. Future work

Since the performance of SiNW FET, namely the conductance, the mobility is affected

by the surface property a lot due to the large surface to volume ratio. Passivation of

the surface defects seem to be very important. Once the defect in the surface region is

saturated, its dangling bonds which may carry certain charge will be neutralized and

form a stable chemical species, reducing the possibility of attracting charge carriers in

the conducting channel. Certain chemicals can be used to react with the surface of

SiNW, altering the nature of its property. In addition, the quality of contact area should

further be improved so that resistance in the contact can be further reduced.

37


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