cmos digital circuits - book

8/4/2019 Cmos Digital Circuits - Book

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ding block for digital circuit design. As Fig. 11.1the inverter paforms the logic operation of A toA. When the input to theis connected toground, he output, in accordwith the digital models in the lastpchannel transistor. When the input terminal isthrough the n-channel MOSPET. Thecharacteristics that am addressed in this chapter:to ground unlike other logic families that neveratic power dissipation of the CMOS inverter isbe sized to give equal sourcing and sinkingId can be set by changing he size of the

s chapter coneentram on the DC switching characteristicsof the inverter andon times associatedwith driving capacitive loads and RC transmission lines,addnsses other types of inverters availablein theCMOSprocess.

-re 11.1 IheCMOS invcrta, schtmatie, and logic symbol.

Chapter


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204 Part Il CMOSDigitalC i-1INMH= VOH-VIH

and the noise margin forthe low logic levels isgiven byNML= Vn.-VOL

ForVDD =5V he ideal noise margins are 2.5 V; hat is,NM, =NM, = VDDf2..Example11.2For the minimum-size invertw in Ex. 11.1 detennine the noiseComment on making the noise. margins closer to ideal.UsingEqs. (11.1) and(lI.Z),NM,=S-2A=2.6andNML= 1.7-O= 1.7high noise margin is almost a whole volt greater than the lower noise nThis is mainly because the inverter switching point, V,, is approximatelinstead of the ideal case of 2.5 V orVDDn. This isdiscussed further ind o n .

1110 nverterSwltchlngPointConsider the tmn

Flpre 11A Transfer chara*cristicsof the inverter showing the s ~ i

Solving for V , give3

ximately unity. lbat s,WI w2B.=$P=KP,, -=KP -LI PL2

KP, =3KP,, he width of the pchannel transistor must be three times theof the n-chanael, assuming equal-lengthMOSPETs. For V, =2.5 V , hiswz=3w,

a channel length of 2 pm for the ratio of 3 W, W, 3 pm (onefor the ratio of 1,setW, 3 pm and W, 9p; or the ratio of In.

tchingCharacteristicsinverter can be genecdized by examining the parasiticsociated with the inverter. Consider the invertw. shown1tP equivalent digital model. Although themodel is shown with bothin practice one of the switches isclosed, lieepinp the output conoectsd toNotice that theeffective input capacitance of the inverter is

3cfa= +cod= chn +cnp (1 1.5)output capacitance of the inverter is simply


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11 The Inverter 207

c propagationdelays of the inverter are

and simulate the inttinsic propagation delays of the minimum-size

Inputhe gtbdninulse rsedinga ~ ahrough

Ftgarr 11.7 Inhinsic inverter delay.

I ..,I, ' 3-

t p g~ R ~ IC a R n l . (Cow +Clod r I (11.10)- _ I .


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Part I1 CMOS DigitalCil208

Example11.6Estimate and simulate the propagation delay of a minimum-size inverter dria 100fF capacitor. 4The schematic of the minimum-size inverter driving a 100fF load and theldsymbol of the inverter are shown in Rg. 11.8. The sizesadjacent to the in1correspond to the ratio of the pchannel width to the n-channel width, assuthe lengths of the MOSFETs are the.same size. Usually, the lengths mminimum size available, which for CN20 is 2 pun. The total capacitance,on the output of the inverter is the sum of C the load capacitance aminterconnecting capacitance. In this case C = 109.6 fF, assumininterconnecting capacitance. The propagation delay time8arc then tPHL Band tp M= 2.63 ns. This can be compared to the simulationresults of fig. 1111

Figure11.8 Inverterdriving a 100tT load capacitsllce n Ex.11.6.6.OV.

4.0V.

2.0v.

0v.-

-2.ov.ens 1on 1ms 14- 16na 1811s. (voutf.(2) TimeFigure 11.9 Sirnulatianresults ofminimum -silr nv&CY drivitl8 100

11 The Inverterce that in the simulations, a zero risetime input results in delays somewhatthan hand calculations indicate. Wered. If R,, =R,, , he delay time8 areequal. This is equivalenttomaking W =ch was the same requirementused in the previous section for making V, =TheRingO~ollfatornumber of inverters of the circuit shown in Fig. 11.10 fams a closed loop withfeedback and is calleda ring oscillator. The willat ion fnquency is given by

fm 1 (11.11)n . (tm ~PLH)the inveTters are identical and n is the number (odd) of inverters in the ring. Since the ring oscillator is self-starting, it is often added to a test portion of agive an indication of the spedof aparticular run.

cw c,A -Cm = 2C, + 3C, = 5Cm=2pn.3pm.C&,sothat

2PHL+~PLH Rnl +Rpz)Cm=(12k+36k)-. SCm= lMlk .Car (11.13)3nsider the case when the inverters are sized to give equal propagationdelays to be identical, W must equal 3W,, which leads to a larger oxide

Ca.2=3C,1 (11.14)

cam c.A AC = 4C, + 6c, = lOC,agationdelaysaregiven by

10C, = 160k. Csame as that given in Eq. (11.13). Although the e M v e esistanceofthed u c a l by a factor of three, the capacitanceof M,was increased by aIn general, the ring oscillator fkquency is dependent on W, lthoughone would expect Also note that only five invertem were used. In

ta keep theoscillation frequency n the ens ofMHz ange. the numberis31 (for-.


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Part II CMOSDigitalC

rimCMOS inverter driving a capacitive load shown inFig. 11.11,chaages states, it must either supply a charge to C,, or sin!to the nput of the inll, fa , he averageamount of current that the inv-current is king supplied from VD D only when the

.--dynamic power dissipated by the inverter is

dissipation is a function of the clock ffquency. Acing the power dissipation in CMOS circuits. Onenarmc logic (Ch.15) is its lower power dissipation.

11 The Inverter 211haracterize the speed of a digital process, a tenn called the power delayP) is oftenused ThePDP, measured in joules, isdetinedby

PDP= P, . tm+ m ) (11.19)terms canbe detamined from the ring oscillator circuit of the previous section.frequently used to compare different tectechogica or device sizss, for

have a lower propagation delay,thepow= dissipation maybe larger

the PDP of CN20, using hand analysis of a five-stage ring oscillator= W,= 10pm. Simulate the oscillator with SPICE and compare thetive resistances of the n-andp-channelMOSPETs are

R.1= 12k .--1un - 2 . 4M10 CIrnRpz=361(.--CIrn -7 .2kn

10 CLmt capacitance of any inverter is

Cow=Corn+Cow=CI,(W"Ln+WpLp)=32 fPcapacitance on the output of any inverter is the sum of its own outputce and the input capacitance ofthenext (Identical) stage. This is given

C,=C. ,+C*=80E

frequency, romJ3q. (11.11),is then


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size(11,

i devices,18), s

-are specified. me

Part 11 CMOS Digital (

I average power dissipated per inverter, using

(512. 260 MHz)=520 pWThe power delay product, using hand calculations, is 400 fJ (femto-joulSPICE simulation gives a PDPof 330 fJ.

-2.0~10s 5ns 1Ons 15ns 2011s 25v(2) Time

Figure11.12 SPICE imulation of the five-stagering oscillator of Ex. 11.7.

es).

11.3 Layout of the InverterIf care is not taken when laying out CMOS circuits, the parasitic devices pcause a condition known as latch-up. Once latch-up occurs, the inverter outpchange with the input; that is, the output may be stuck in a logic state. Toproblem, the power must be removed. Latch-up is especially troublingcircuits. Manufacturers of integrated circuits often use NMOS invertersin this chapter) for output drivers, thus eliminating the possibility of latch-up.11.3.1 Latch-upFigure 11.13 illustrates two methods of laying out a minimum-size invcross-sectional view in Fig. 11.14 shows both the n-channel and thMOSFETs that make up an inverter. Notice first that in Fig. 11.7, thefeeds through the gate-drain capacitance. This causes the output to change indirection as the input before the inverter starts to switch. This feedthrouparasitic bipolar transistors cause the latch-up.

11 The nverter 213

Figure 11.13 Two inverter layout styles.

1 and RW2 represent the effects of the resistance of the n-well, and1 and RS2 represent the resistance of the substrate. The capacitors C1 andt the drain implant depletion capacitance, that is, the capacitance between

of the transistors and the source and substrate. The parasitic circuit resultinginverter layout is shown in Fig. 11.15.

output of the inverter switches fast enough, the pulse fed through C2 (forg inputs) can cause the base-ernitter junction of 4 2 to become forward

s then causes the current through RW2 and RW1 to increase, causing Q1 toen Q1 is turned on, the current through RS1 and RS2 increases, causing

n harder. This positive feedback will eventually cause Q2 and Q1 to turnand remain that way until the power is removed and reapplied. A similarcan be made for negativegoing inputs feeding through C1.

a1 techniques reduce the latch-up problem. The first technique is to slowfalltimes of the logic gates, reducing the amount of signal fed through C1=@educing the areas of M1 find M2's drains lowers the size of the depletiond the amount of signal fed through. Probably the best meiod ofup effects is to reduce the parasitic resistances RW1 and RS2. If thesezero, Q1 and 42 never turn on. The value of these resistances, as seen


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216 Part II CMOS Digital C

11.4 Sizing for LargeCapciUveLoadsDesigning a circuit to drive large capacitive loads with minimum delaywhen driving off-chip loads. Consider the inverter string driving a loadlabeled C,, and shown in Fig. 11.17. Ifa single inverter were to drive Cw ,times would be

~ P H L+ p w = Rn +Rp) . Cmr+C r d )If, moving toward the load, cascading N inverters areused, each inverterprevious by a factor A (that is, the width of each MOSFET is multipminimum delay can be obtained as long as A and N are pickedinverter's input capacitance is also larger than the previous inverter'sby a factor of A. If the load capacitance is q u d to the input capacitance ofinverter multiplied' byA, then

Input C of final in- = C,, .AN=CZWwhere C,,, is the input capacitance of the fmtinverter. RearrangingEq. 11.20

The total delay of the inverter string is given byR p t ) . A C w I + A ZacuaMwdd.y

where R,, and R,, are the effective resistances of the first inverter andcapacitance of the first inverter. As the inverters are increased in 8capacitances, both input and output, increase by A while their resistancesfactorA. The equation ( 11.23)can be written as

N( t p ~ ~~PLH)~ , , , ,= (Rnl +RP ~)(Cw rlA c i d )EN(R-I +Rpt)(Coutl+ A C db l

Figure 11.17 Cascade ofinvcItem used todrive a Large load capaciuln

' Consider this as if the load capacitance were simulating the input capacitance ofinverter (if there was another invertn).

e help of Eq. 11.22):

term in this equation is the intrinsic delay of the fust inverter in our cascade ofIf we assume that this delay is small, solving thjs equation for NgivesclodN=ln-chl ( 1 1.27)

and (11.22) are used to design a cascade of invertem in order to drive a


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Designing a buffer begins with determining C,,. For the present case28.8 fE Thenumber of inverter6 using Bq. (1 1.27) is

seven inverters is negligible. If we did not want a logic inversion,we wasix stages. The areafa& is then

The total&lay, usingBq. (1 1.2.5), is then(tpm+ p ~ ) ~7(16k)(19.2 F+2.55 .28.8F) 10

or over 30 ti- faster. SSincc the pchannel width is thne times thatn-channel width, the pmpagation May times, and t areequal, ortpm= pui=5.2 ns

A schematic of the design is shown in Fig. 11.18. The actual siecchanged toa number close to that given using thevalue of A calculated amake the layout easier. N&CCthat the first invatsr is the same inVer(8above. m e SPICE simulation results are shown in Fig. 11.19. Note 1unbuffered inverter does not fully charge the capacitor since the inparinverter changes back to zerovolts 15 ns after it changes to VDD.

Figure11.18 Buffsrdesigned n Ex. 11.8.

It should be clear that, although this technique &ts indriving the2.0pF load, theMOSPBTsneeded are v w arge. Inmanyminimum delay througha buffer is not requind. A specificationthatthan some value is given. Consider thefollowing example.

Figme11.19 Simulaticmresults fromEx. 11.8.ple 11.9kn the buffer of Ex . 11.8 so that the delay, tP8 + t,m, is less than 15ns.wumdelay was 10.4ns nEx. 113.)

maintain the logic invasion, either three or five stages should be's begin by trying threestages. ' be ereaEactorfor thne tagesisgiven

b e nd efib t l y

A=[-Im=8.868.8 Fis calculated usingEq. (1 1.25) and is given by

tm+ m =3(16k)(19.2 81+8.86.28.8 tT) 13.2 ns

tpm =~PLH 6.6 nsis shown in Fig. 11.20. The layout size of this buffer iser than the buffer designed iqEx.11.8, while the increase in

it takes to lay out the large MOSFETsused in an output buffer canusing cell hienuthy. As a simple example, let's lay out a 25Qn


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77n PartIt CMOSDigitalCipq

n OutputInput++-hzopp

- 1lwn 11.U) Buffer design of Ex. 11.9.n-channel MOSFET.by 2), with a rank of 1We begin by creating a cell, called NAA25X2 (n-activand shown in Fig. 11.21.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .t. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . .

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Flpn 11.21 Layout of an n-channelMOSFETmeasuriag25p width) by 2W

cell. The "trick" when placing the NAA25X2cells is to overlap

The

MOSRrank of

Inverter

F'lacing basic cellsto f a m a largeMOSFBT.is afml ayout em.) Since the standard-cellframe,SPRAME (with atheCN20 etupsprovidedwithLASI,pmvides these connections, we could

to our basic layout. The result isshown n Fig. 11.23b.

ver circuit shown in Fig. 11,24a containing 11 inverters. If all of theinthefigureare the same size, thedelay from the input to theoutput is~ P R L ~PuI=(&Rp)(Co*r+10Cd (1 1.28)

the circuitshown in Fig. 11.24b with 13 invuters. Again, assumingallsame size, thedelay from the input to the output is(Rn+Rp)[(Car+2Ch) +(Car +5Ch) l= (Rn +Rp)[2Cwr +7 Cd (1 1.29)

8 delay than the circuit with 11 inverters. Often, distributing the signal intoU canreduce the pmpagation delay. At this point we can ask hequestion,ILethe Ent inverter in the circuits of Fig. 11.24 really large so that it has

tances fordriving the ten invertem quickly?" The answer is simplythe size of an inverter, we also increase its input capacitance. Ine ust idral voltagesources to drive the firstgate in our circuit. Inis driven fm m another gate somewhere on the chip. Increasingpropagationdelay-time of thegatedrivingthis inverter.


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CMOS-J U U L LCi

Figure11.23 (3Layout of I usinga


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224 Part II CMOS Digital

Plgmc 11.25 hiving an RC aansmisaian line.11.5 Other Inverter ConfigurationsThreeother inverter conf1gurati0118are shown in Fig. 11 6.11.26a s anNMOS-only invntcr, useful in avoiding latchFig. 11.26b and c use a p-channel load, which is, inwith a large number of inputs (more on this inse1ection of the MOSFET sizes follows the 4 o 1of the oad is made four times larger than the resistance of MI .will never reach 0V for these inverters, and thusbasic CMOS i n v e f Fig. 1 1.1. Also. DC ower will belogic level is a low since a drain cumnt will flhigh level of the invntcr of Fig. 11.26c Will reachthat thepower dissipation of the invextern sCMOS inverter. However, sincethe input capacitancebasic CMOS inverter and the output voltage swing is reduced, thegreatest power dissipation is determinedbyrhe opcratiag fresuewy.frequencies,the basicCMOS nverter dissipatesthemost pow=.-

(*) @)Plgure 11.26 Other inverter c a n f i ~ ~ .

11 The Invmer 225k N-ChanntrlOnly OutputD r km

put driverssic "NMOSmdM3arethe h~rffer

I t=. --,,MInd M 4 o turn on pulling the &put to VDD- V,,,,,, ssuming the inp~.b a l amolihlde is VDD.

Fimm 11.27 NMOS aumx buffer.

-.. -- -- -- -- -.- --". a PDC oltageof nominally VDD+ 2 V . This allows the out~utienal to reach

- out

I= FbPre 11.28 Alternative output buffer.


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VDD

*S

Figure 11.29 Circuits and lc@csymbolfa the the-stateinwter.11.5.3 The BootstrappedNMOS InverterConsider the modified version of he NMOS nvatw of fig . 1126 shownThis inverter configuration is calle d the bootsttapp~d MOS inverter. Itthe output voltage must swi ng up to VDD. To understandthe operation,the case when input to the inverter is a logic high. 'Ihe MOSFET M1output is pulled down to appmximately

-

W o n n su lt s are shown n fig . 11.32. Notice how the output doesn't goay to ground ot VDD. We candecrease the size (WIL)fM2 (increase


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partn CMOS Digital9 229

R.L. Geiger,P. E. Allen and N. R. Strader, VLSI-Desrgn Techniques orAnalogand Digital Circuits, McGraw-HiU Publishing Co.. 1990. ISBNN. H E. Weste. and K. Eshraghian, Principles of CMOS VLSI Design,Addison- Wesley, 2nded, 993. ISBN 0-201-533766.

CN20process for the followingproblemsunless otherwise stated.

eatEx. 11.6 for MOSFETs with W = 0pn and a load capacitance of 1pF.nimum-size inverters.

out the standard-cell frame of Fig. 11.16. Explain how the added implantsHowever, since this capacitor is charged throughM3, t h ~ sign and simulate the operation of a buffer to drive a 50 pF capacitive loadcharging timewill cause themaximumpracticaloperatingfrequency m an inverter with size of 1U)IM. Ihe ,, + t,, shouldbe less than 10 ns.to decrease. . t Ex . 11.9, using a minimum delay of 20 ns, where the first inverter in theis minimum size, that is, 312 @channel) and 3/2(n-channel).ign and simulate the &lay of a minimum-size inverter driving a 1mm polyterminated with a 1pF capacitor.

out an inverter with a size of 4501150 using the standard-cell frame of Ch.ate the operation and explain the results for the NMOS super buffer shownEx. 11.10 if M4's size is inmmed to 20/20.Ex. 11.5 using minimum-size (0.910.6) MOSFBTs in the CMOS14TBh. 1.6 using minimum-size MOSFETs in CMOS14TB.

h the cross-sectional views, at the positions indicated, fo r the ayout shown


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Chapter

LogicGateser we discuss the DC characteristics, dynamic behavior, and layout oflogic gates. Static logic means that the output of the gate is always a

tion of thc inputsand always available on the outputs of the gate regardlesse begin with the NAND and NOR gates.

BCharacteristicsof the NAND and NOR Gatesic input NAND and NOR gates are shown in Rg. 12.1. Before we get intoon, notice that each input into the gate is connected to both a p- and antransistor similar to the inverter of the last chapter. We will make use of the:h. 11to exvlain the operation of thesegates.- .Characteristics ol the NANDGate

D gate of Fig. 12.1 requires both inputs to be high before the output will. Let's begin our analysis by determining the voltage transfer curve of a gateMOSFETs that have. W=W,, L = L,, nd n-channel MOSFETs with W. If both inputs of the gate are tied together, the gate behaves l i e an

'determine the gate switching point voltage, V, ,we must remember that twoin parallel behave like a single MOSFET with a width equal to the sum ofwidths. For the two parallel pchannel MOSFETs in Kg. 12.1, we can

w3+w,=2wp (12.1)ng that all p-channel transistors are of the same size. The

eters can also be combined into the transconductance parameter

83+84=2pp (12.2)


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partn CMOS DigitJ 233B.ranseonductancc ratio of NAND gate =- (12.5)4 8 ~switching point voltage, with the help of 4. 11.4). of the wo-input NAND gate is

g m d or an winputNAND gate (pee Rg. 2.2).we get

it should be rememberedthatwe have neglected the body effect (an increase inhold voltage with increasing V A . Voltage transfer curves using one input,oth as tied to VDD,will give slightly diffa cnt resultsbecauseof this effect.

NAND nd NORgatedrademdlosicrymhok.

hand calculations and compare to a SPICE simulation for ausingminimum-site devices.

FLgnre123 Schematic of an n-inputNAND ate.


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The switching point voltage is determined by calculating the transconduratio of the gate, or

and then using Eq. 12.7). 0.572 (0.83)+ 5- .92) =2.9VS P= 1.572The SPICE simulation results are shown in Fig. 12.3. The simulatioVspof approximately 3.1 V. W

-v Y i n

.O 0.5 1.0 1.S 2.0 2.5 3.0 3.8 4.0ug

Pllpvc123 Voltage trans& charoctaistiics of he tberrpat12.18 D C C h a r a c t s r l ~ d t h . N O R ~

11 8 *Figure 12.4 Schematicof ann-input NOR gate.

switching point voltage of a three-input NOR gate made fromMOSFETs to that of the three-input NAND gate of Ex. 12.1.

which gate is closer to ideal, that is, V, = VDDl2.the minimum-size three-input NOR gate is 1.35 V, while the Vspof

-size three-input NAND gate was calculated to be 2.9 V. For an= 2.5 V, so that the NAND gate is closer to ideal than the NORses because the transconductance (actually the mobility) of thelarger than that of the p-channel. In CMOS digital design, the

is used most often. This is due partly to the DC characteristics,ns, and the dynamic characteristics. We will also see shortly

has better transient characteristics than the NOR gate. WofheNOR andNANDGates

1 three-input minimum-size NOR and NAND gates is shown in Fig. 12.5I1 frame. MOSFETs in series, for example, the n-channelate are laid out using a single-drain and a single-sourcen the gate poly is shared between two devices. This has

arasitic drainlsource implant capacitances. MOSFETs inn-channel MOSFETs in the NOR gate, can share a drain areainputs and outputs of the gates are on poly.


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Static Logic Gates 237

mn in this equation represents fht intrinsic swirchtng time of the sdmrlOSFBTs,while the rcolld tam eprrscnts Re de&y eard by R*C Forthecasewbm N = I, ttds implynbca toa$-. W~th nexternalstance, the high to low &ray-time becomes

t ~ r n = N . R . . ( + + C w + 0 . 3 5 . R . C h ( N - 1 ) 2 ( 1 2 1 3 )me1MOSFETs n serieb, asimilaranalysis vields


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238 partn ~ O Sigital

In

F lpm 12.7 Serbd m f MOSPEl's and equivalmtdigital

Thtsequations are approximatim for the propagation delaysgivingwithin a factor of hvo of themtasunmcnts.123.1 NAND ObtrConsider the n-input NAND gate of Rg. 12.8 driving a capacitivelow-&hi& propagation time, usin$ Eq. 12.10),is

where.h e represents the capacitaace externaltoCM rYm ented the capacitance exUmal to the@

itance is much greater han the output capacitance of the gate, he ow to highn timecan be estimated byRP?~LH ' -. cldN (12.16)

to lowpropagation time. usingEq. (12.13). isgiven by

ismuch larga than theoutputcapacitance of the gate

e intrinsic propagation delays, t , + t , of a thre ~inputNAND gatehg minimum-site lransistors. Estimate and simulate the delay whenis driving a load capacitance of 100 fP. Assume that inputs are tied

input NAND gate, the thne p-channel MOSFPTs in parallel aretheoutputhigh. Since they are minimum-size

Rp=24LnaodCow=4.8 Fa low-to-high propagation time. usingEq. (12.15).with C, =0,of

of 100 fP, he propagation delays become, t,, = 928 ps and t,,, =PICE simulation results are shown in Fig. 12.9 followed by theHelpingwith convergmce. the .OFTIONS statement was used,

at0.1ns nsteadof the lllCaliStic conditionsof 1 ps.


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240 m n CMOSDigital

60

50

10

$0

20

10

0 0

-1 0I""

Flgure129 Output of the minimum-sizeNAND gars driving a LOOtP

m T a p L s v e l ~ ~ ~ 1 2 S * *C1 501001MI 5 1 2 0CMOSNBGh lW . SumPSJdpPWP8Q (UM2 2 1 4 0 CMOSNB M u w-3~AD=sBpAk36p P W U S-24M3 4 1 O O C M W B I B u W ~ A S P 9 B p P L ) S a 4 u P ~M4 ~ ~ V W V ~ ~ ~ B L = ~ U W ~ U A D J B P ~ P W C ~ ~M5 5 1 V d d V d d C M O S P B G 2 u W * A D J B P A & 3 8 p m f iMB 5 1 V d d V d d C M O S P B L b U W 9 u ~ ~ ~v1 vddo DC 5V2 1 0 DCO PULSE(O55n .In .In Ion)mnSpioemodeloandmaeromdels"'"MO DEL CMOSNB NMOS LEV-+VFBPB.T91)20EOl, LVFBc3.6745BEOl,WVF&4.7234aE-02s e 8 m m i I i x A f w a ~ ~

&lay equations derived in Ibis section are useful in understanding theon the nutnba of M O S m s used in a NAND gate for high-speed d d g a

tpm. N R a . C w (12.19)when the output of the NAND gate changes from a low to a igh isnt then the high-to-low case. Refening to Fig. 12.6, we see that if ones turns on, it can pull the output to VDD ndependent of the number ofin parallel. Under these circumstarres,Eq. (12.16) can be used with N = 1

the low-to-high delay-time, or for a parallel connection of N p-channelt m - R . . C w (1 2.20)

$10 Ruther simpliflcDtimof digitalmodelsnot showing input capacitsna.I

oaing Eqs. (12.19) and (12.20). the propagation delays for theR minimum-size AND gate, with only m e input switchingdriving aitancc. Compareyour results toSPICE.

delay-timesarc given by~PHL=3.8k 1 0 W .4ns

tm=24k lOOff i 2.4 nssimulption reaults gave tw- pm 9 2.3as with one input

had used Eqs. 12.19 and 12.20 in Ex. 12.3 where all inputsU tho rpme h e , the calculated t, would have given an


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underestimate (but not by much), while the calculated t,, wouldoverestimated the &lay. Also note that since the effective resistancep-channel Is three times greater than that of the n-channel, the seriof three NMOS devices gives approximately the same resistancePMOS. The m u lt is equal switching times and the reason the Ngenerally prefe md over the NOR gate in CMOS circuitdesign.12.3.2 Numberof InputsAs the number of inputs. N, o a static NAND (or NOR) gate increases,shown in F4g. 12.2 (Fig. 12.4) becomes difficult to realize. Consider a NO100 inputs. This gate requires 100 p-chrnncl MOSFETs in series and aMOSFETs (2N MOSFETs). The delay associated with the series pch an aecharging of a load capacitance is too long for most p a c ti d situations.

Assuming that the maximum V , allowed (themore inputs at VDD th500 mV and that the n-channels have W = 3 pm and L = 2 pm resultsand an L of 3 prn for the p-channel. In practice, the length of the p-cincreased beyond this size to lower VOLurther. Th e tatic power diswhen the output is high, neg lecting leakage currents, is zero. Whenstatic power is dissipated due to both a- and p-channels conducting.flows under this condition with the above sizes is 150pA. Decreasinp-channel lowers power draw at the price of increased tpm.

Figure12.11 NOR ccdlgurationbed or a ntrmbm&

242 PartI1 CMOS Digitalmplex CMOS Logic Gates

on of compIex logic functions in CMOS uses thc basic building blocks

VDD

VDD

FIpre 12.12 Logic implementationin CMOS.

%h ~ g i c ,mplement the following logic functions:Z = ~ + B C and Z=A+&+CDr . .


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The implem entation of the first function is shown in Fig. 12.13a. Notice thatp-channel configuration is the dual of the n-channel circuit. The functionobtain is the complement of the desired function, and therefore an inverteused to obtain Z . Using an inverter is, in general, undesirable if both truecomplements of the input variables are available. Applying Boolean algebrthe logic function, we obtain =_.z = ; ~ + B c * Z = A + B C = A . ( E + Q * Z = A . ( E + GThe A 01 implementation of the result is shown in Fig. 12.13b. Logically.circuits of Figs. 12.13a and b are equivalent. However, the circuit of Fig. 12is simpler and thus more desirable. Note that to reduce the output capacit;

thewe:r isanda to

the 1.13bmce IVDD

Figure 12.13 First lo& gate of Ex . 12.5.

Chapter 1 2 Static Logic Gates 245/The second logic function is given by

Z = A + B C + C D = A + C ( B + D ) ~ Z = A + C ( E + D ) = A . ( ~ + B ~ )or

z = ~ . ( ? + E @The logic implementation is given in Fig. 12.14.

VD D

Fimre 12.14 Second logic gate of Ex. 12.5.-xample 12.6UcV01 logic, implement an exclusive OR gate (XOR).- lopic symbol and truth table for an XOR gate are shown in Fig, 12.15Frnrn th e truth table. the l p i c function for the XOR gate is given by


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and finallyz (12.23)

The CMOS A0 1 implementation of an XOR gate is shown in Fig. 12.16..Figure 12.15 Exclusive OR pate

VDD

Figure 12.16 CMOS A0 1 XOR gatC.

Example 12.7Desipn aCM OS full adder using CMOS A0 1 logic.The lopic symbol and t ruth table for a full adder circuit are shown in Fig. 1 2 ' 7 'The lopic functions for the sum and carry outputs can he written as

Cllnpter 12 Static Logi c Gates 24 7

0 0 1 1 0carry-in.;"j.Cany-out 0 1 0 1 0Full adder 0 1 1 0 I1 0 0 1 01 0 1 0 I

s n 1 1 0 0 1S u m a t I 1 1 1 1

Figure 12.17 Full adderThe logic expression for the sum can be rewritten as a sum of products

s. =A.B,c. +Z.B,?, +A.B,F.+A,B.c,nr since

the sum of products can be rewritten asThe A01 im plementation of the full adder is shown in Fig. 12.18..

12.4.1 C a s c o d e V o l t a g e S w i t c h L o g i cCxcode voltage switch logic (CVSL) or differential cascode voltage switch logicIDVSL) is a differential output logic that uses positive feedback to speed up the'";itching tim es (in some cases ). Figure 12.19 shows the basic idea. A gateCrW-connected load is used instead of using p-channel switches, as in the A01 logic, toPllll the output high. Consider the implementation of z = ~ + B c . (This logic function"as "plemented in A 01 in Fig. 12.13.) N-channel MOSFETs are used to implement Z

as shown in Fig. 12.20. Figure 12.21a shows the implementation of a two-inputX o R m ~ ~ ~ate using CSVL, while Fig. 12.21b shows a CSVL three-inputX O R I X ~ ~ ~ate useful in adder design.

Dif feren t la! S pl i t -Level Loq ic-split-level logic (DSL logic) is a sch eme wherein the load is used to reduce''"'pllt swing and thus lower gate delays (at the cost of smaller noise margins).

'llc hasic idea is shown in Fig. 12.22. The reference v oltage V,,,is set to VDD12 + V , ,T h l r ha < the effect of limiting the output voltage swing to a maximum of VDD and aof VDDI2. The main drawback of this logic implementation is the increased

P[I!v,-~ dj c lpation resulting from the continuous power draw through the output leg at a' f LDD12. The output leg at VDD draws no DC power.

part 11 CMOS Digital Circuits Chapter 12 Static Logic Gates


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248 -

VD DI

*VD D

Figure 12.18 A01 mplementation of a ful l adder

249

Output Output0InputsQlock &lock

Figure 12.19 CSVL block diagram.

Figure 12.20 CSVL logic gate.

PIWn CMOS Digital


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250 C 12 StaticLogic Gats 251.

FWn?1255 Tri-amte buffer.


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252 Part 11 CMOS Digital Circuits

12.4.3 Tri-State OutputsA final example of a static logic gate, a tri-state buffer, is shown in Fig. 12.23. Whenthe Enable input is high, the NAND and NOR gates invert and pass A (VDD or ground)to the gates of MI and M2. Under these circumstances, M1 and M2 behave as aninverter. The combination of M1 and M2 with the inversion NANDMOR gate causesthe output to he the same polarity as A. When Enable is low, the gate of M I is held atground and the gate of M2 is held at VDD. This turns both M1 and M2 off. Underthese circumstances, the output is said to be in the high-impedance or Hi-Z state. Thiscircuit is preferable to the inverter circuits of Fig. 11.29 because only one switch is inseries with the output to VD D or ground. An inverting buffer configuration is shown inFig. 12.24.

VD DI

Enable - hg i c symbol *Figure 12.24 Tri-state inverting buffer.

REFERENCES[ I ] M. I Elmasry, Digital MOS Integrated Circuits 11, IEEE Press, 1992- rSBN0-87942-275-0, IEEE order number: PC0269-1.[21 1. P. Uyemura, Circuit Design for Digital CMOS V a l , Kluw~r cadenuCPublishers, 1992.[3] M Qhnii P M O S ni~i ta lCircuit Technology, Prentice-Hall, I

Chapter 12 Static Logic Gates 253/PROBLEMSLTSC the CN20 process unless otherwise specified.

12.2 Desta

12.6 SkcEstcap

:sign, lay out, and simulate the operation of a CMOS AND gate with a V, ofproximately 1.5 V. Use the standard-cell frame discussed in Ch. 4 for the'Out.:sign and simulate the operation of a CMOS A01 half adder circuit usingtic logic gates.peat Ex. 12.3 for a three-input NOR gate.peat Ex. 12.4 for a three-input NOR gate.:tch the schematic of an OR gate with 20 inputs. Comment on your design.:tch the schematic of a static logic gate that implements ( A+B .? ] . .imate the worst-case delay through the gate when driving a 50 fF loadlacitance.~ i g nnd simulate the operation of a CSVLOR gate made with minimum-sizelices.


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Design a tri-state buffer that has propagation delays under 20 ns91 pF load. Assume that the maximum input capacitance of the bufferSketch the schematic of a threeinputXOR gate implemented inA01What ogic functiondm he circuit of Fig. P12.10 implement?Calculate the switching point voltage of the gate shown in Fig. ~d

logic function does this circuit implement? .dEstimate the minimum and maximum output voltages for tlP12.11.The circuit shown in Fig. P12.13 is an edge-triggered one-shot4output pulse, with width td,whenever the input makes a linverters for delay elements, design and simulate the opetr3whose output pulse width is 10 ns. Comment on the resultingof the input pulse is less than td .

Chapter

e TG and Flip-Flopsssion gate (TC3) is used in digital CMOS circuit design topass or not pass aschematic and logic symbol of the transmission gate(TG)re shown in Fig.up of the parallel connection of a p and an nchannel MOSFET.when S(for select) is high we observe that the transmission gateinput to the output. The resistance between the input and theestimated as RJIR, . We begin this chapter with a description of the n-ass transistor.PassTransistorsingle nchannel MOSFET shown in Fig. 13.2a. Assume that the voltageitor (the output of the pass transistor) is initially 5 V. When the

f the MOSFET is taken to VDD, he MOSFET turns on. In thisassume that the drain of the MOSFET is connected to the loadat the source (the input of the pass transistor) is connected to ground,the drain and source are interchangeable. The delay-time of theis simply

13.1 Thetransmissiongate.

256


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Figure 133 An n-channel pass transistor showing transmission of 0V and

Now consider Fig. 13.2b where the capacitor is initially at0V. In this case,connected to VDD and the source is connected to the load capacitance.substrate, assumed at VSS=ground, is not at the same potential as thebody effect present causing the threshold voltage to increase. What b qMOSFET is raised to VDD,the oad capacitor charges to VDD- V , wbmAppendix A, is in the neighborhoodof 1.5V. llIaef~re,he low-to-hlO$!can be estimated by. '>,tp m =RnClwdor a high voltage of VDD- V , i b

In this derivation, we have neglected the parasitic capacitances of thefollowing example illustrates the switching behavior of the n-channel pass tF(

and

~&tima% e and simulate the delay through minitransistors using the test setups of Fig. 13.2 driving aWe know that for the minimum size (W 3 pmand L =2p)effective resistance is 8 kR. Therefore, the propagation delays t ,ps, remembering that the maximum high voltage is VDDapproximately 3.5V. The simulation results are shown in Fig. 13.3.

A similar analysis of the p-channel MOSFET used as a pass~ P H L=Rp c~wd

~ P U I=lip C w or alowThe p-channeI pass transistor can pass alow results in a minimum low voltagetransistor can pass a logic low withoutmaximumhigh voltage of VDD- V,. One advan*is that it can be laid out, in an a-well process, with theeliminating body effect.

SET. Themistor.-' 7aSS

me1800 ,or

tor turning on must discharge the charge stored on the outputMOSFET through its own effective resistance.

passes logic lows well and the pchannel passes logic highs well,lementary MOSFETs in parallel, as was shown in Fig. 13.1,es both logic levels well. lXe CMOS TO equires two control.13.4). ll Ie propagation delay-times of the CMOSTG re

t of the TG s the inputof the MOSFl3Ts

ng. Using a voltage source in

258 I Part I1 CMOSDigitalCq


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1

SPICE for the select lines, which can supply infinite current to charge thecapacitance of the TG, ives the designer a false sense that the delay through thelimited by R, andR, . Often, when simulating logic of any kind, the SPICE-gcontrol signals are sent through a chain of inverters so that the control sign;,closely match what will actually control the logic ondie. I

Figure 13.4 The transmissiongate with control signals shown.


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13.2.2 Series Connection of Transmission GatesConsider the series connection of CMOS transmission gates shown in Fig. 1equivalent digital model is also depicted in this figure. The output caindividual MOSFETs is not shown in this figure and will be neglectedanalysis. The delay through the series connection can be estimated by

t p ~ ~p ~N. Rn IIRp)(Cload)+0.35 Rn IIRp)(Ctm C@)(N)The first term in this equation is simply the sum of the TG effective resisthe second tern in the equation describes the RC transmission line effects.

- - -A1 A2 A3A A AI.PU~- . . .

7 - 1 7 -A1 A2 A3

Figure 13.7 Series connection of transmission gateswith digital model.

13.3 Applications of the Transmission GateIn this section, we present some of the applications of then? I. 21.Path SelectorThe circuit shown in Fig. 13.8 is a two-input path selector. Logically, thtcircuit can be written as

Z=AS+BSWhen the selector signal S is high. A is passed to the output while a lowto the output.

This same idea can be used to implement multiplexetsl$j(MUXIDEMUX). Consider the block diagrams of a MUX and DEMUX 813.9. The number of control lines is related to the number of input lines&

SFigure 13.8 Path selector.

the number of inputs (outputs) to the MUX (DEMUX) and m is the numberlines. A 4 to 1MUXiDEMUX I8 shown in Fig.13.10. Note Uu heMUX isnal; that is, it can be used as a MUX a a DEMUX. Thc logic quarjonthe operation of theMUX is given by

Out

Figwe W.9 BImk diagramofMUXlDBMUX,


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Figure 13.12 TG-based OR gate. Truth abk~ R Q Z ~0 0 1 11 0 1 00 1 0 11 l Q G

Truth tableS R Q ~O O Q G1 0 1 00 1 0 11 1 0 0

I268 Part I1 CMOS Dig itakii


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FF, onsider the data or DFF hown in Fig. 13.18 with associated logic symbol.the clock signal is high, the D input can pass directly to the SR FF. f D iCLK is high, the output, Q,s a 1, while ifD is low the output is a low.any time while the CLK input is high, the output will follow. Whengoes low, the current logic level of D is latched into the SR FF.an edge-sensitiveFF because the output changes at other timestime.Edge-Triggered Flip-FlopsThe JK master-slaveFF, hown in Fig. 13.19, is an example of an edge-a31When the CLK signal goes high, the master JK FF is enabled. Since ms'cannot change states when CLK is high. the clock pulse width does not havethan the propagation delay of the FF. When CLK goes low, the mu*transferred to the slave. If both J and K are low, the output of the mumunchanged, and therefon so does the output of the slave. If J = 1 and K=CLK pulse goes low, the master output, Q, oes high. When the CLK goolhigh output of the master is transfemd to the slave. The master-slave JK Ajust like the JK FF of the previous section except for the fact that the diavailable until CLK goes low and then is no restriction on the pulse width(ic., the FF s falling edge triggered). Addingreset or set capability to the1accomplished by adding logic gates between the NAND and the SR FF ofThe logic gates simply enswe that the SR FF are placed into a certain Iapplication of a reset or set signal.

implementation of the positive edge-triggered D FF s shown in Fig. 13.20a.made using NAND gates. When the CLK input is low, the outputs of theare both high, keeping the SR FF in the "no change mode." When CLK

, he logic value on the D input of the FF s transferred to the S nput and the-transferred to the R input of the SR FF. The CLK input of the NANDthree inverter delays after CLK goes high. This forces both R and S-the flip-flop in the no change mode. The only time that CLK and CLK

the condition required to transfer D to the input of the FF, s the time-K going high and CLK going low. This time is determined by thedelay of the inverters. In practice a single inverter, in place of the three,ide a sufficient delay to allow the inputs of the SR FF o fully charge to D, here are minimum rise- and falltimes requirements for the clock.

implementation of the positive edge-triggered D FF using transmissionin Fig. 13.20b. When the CLK input is low, the logic value at D isA and is on node B. Transmission gates T2 and T3 are off. TheC is available on the output of the FF and is the result of the previousnsition of the CLK input pulse. When CLK goes high, T1 and T4 turn

and T3 turn on and the datum on node is C is transferred, with theinversion to the outputs. A D FFwith set and clear inputs is shown in Fig.

st be set up or present on the D input of the FF (see Fig. 13.20~) certainapply the clock signal. This time is defined as the setup time of the FF.the origin of this time, consider the time it takes the signal at D to

important comment regarding the clock input of a FF s in order. Ifslow, the FFwill not function properly. There will not be anthe sets of transmission gates turning on and off. The result

13 TheTG and Flip-Flops 271


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Figure 1331 IllustratingD F etup time.is to buffer the clock input through several inverters. This has the effect ofup the leading and trailing edges of a slow input pulse and presenting a lower

ance on the clock input to whatever is driving the FF. The mainis the increase in delay times, tpmand tpw(defined by clock to output), ofnerd, the FFs of Fig 13.20b and c should not be laid out without buffering

imum pulse width of the clock, set, or clear inputs is labeled t, . Theis determined by the delay through (refemng to Fig. 13.20) twoNANDThe last timing definition we will consider here is the recovery time,

time between removing the set or clear inputs and a valid clock input. This

D nputs eithaa high w bw

Figure13.22 Illustrating D FF old time.

using inverters andTGs isshown in Fig. 13.23. The crosstoupleds o ~ seferzed to as a latch and is the basis for the staticsad furthcr in Ch. 17. To understand the operation of this

case when CLK s low. The TGs are off, and the outputs do notCLK is high, provided the invertersare sizedinput is connected to Q and the 5 input isback low, the value of D is remembered and

d be made regarding this flip-flop: (1) the outputsCLK is high, that is, it is not an edge-triggered

inputsmust supply a currtnt during switching.

I

Part I1 CMOS Digital


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CLK / \Figure 13.23 Clocktd D flip-flop using the basic latch and TCis.

The input DCconnected to eachTG. n- - -of whatever ga te is driving theTG.) nbe lame. The length of the &vim used in the inverters can

effective digital resistances of the invcrters sh o dTG esistance and the driver mistan ce.

minimum length to reduce the input CUTTCU~.REFERENCES[I] 1. P. Uyemura, Circuit Design for Digiml CMOS V . luPublishers, 1992.[2] M. I. Elmasry, Digital MOS Integrated C i ~ u i t s1, IEEE Pnss,0-87942-275-0, IEEE order number: PC0269-1.[3] M. Shoji, CMOS Digital Circuit Technology, Rentice-Hall, 10-13-138850-9.PROBLEMSUnless otherw ise stated, use the CNU)process.13.1 Verify the simulation nsu lts shown in Fig. 13.3. If we in-channel pass transistor, what happens to thedelay-timestransistor is driven from som e other logic on the chip.capacitan ce seen by this logic when wi?lcresse hewidth of

133 Estimate and simulate the &lay through 10 TG8 (aconnected to a 100 fF load capacitance.13.4 Sketch the schematic of an 8 to 1 DEMUX usiEstimate the delaythrough heDEMUX whenload capacitance.

-Vefi, using SPICE, that thecircuit of Fig. 13.13 operates as an XOR gate.Simulate the operation of an SR lT made with NAND gates usingminimum-size MOSFETs. Show all four logic transitions possible for the FF.Simulate the operation of the clocked D FP of Rg. 13.23b using minimum-sizeMOSFJ~TS.Comment on.any glitches you encounter. Show the IT clocking ina logic 1and 0. What are the setup and hold times for your design?Design and simulate the operation of the FF hown in Fig. P13.8.

shown in Fig. P13.8 has several practical problems. including nota purely cap acitive load at the D-input and large layout size. The FF.9 is a d ifferent implementation of an inverter-based latch which doesurely capacitive load to the D-input and a (possibly) smaller layoutate the operation of this FF using the device sizes shown.

fi. 3.1 using minimum-size (0.910.6) M OS FB h using the CMOS 14113. 3.2 using the CMOS14TB process.

274 Part 11CMOS Digital


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13-12Estimate and simulate the delay through 10 TOI (assume miconnected to a 100fF load capacitance using the CMOS14TB process.13.13 Using a SPICEDC weep, plot the output voltage against the input vq(lthe circuit of Fig. P13.13 with the input varying from 0 o 5 V and-.V to 0. cornmeit on the difference in the plots.

In Out

Chapter

or clocked logic gates are used to decreape complexity, increase speed, andwer dissipation. The basic idea behind dynamic logic is to use the capacitiveMOSFET to store a charge and thus remember a logic level for use later.tart looking into the design of dynamic logic gates, let's discuss leakagethe design of clock circuits.

pdamentals ofDynamk Logic* -channel pass transistor shown in Fig. 14.1 driving an inverter. If wee pass transistor high, the logic level on the input, point A, will beof the inverter, point B. If this logic level is a "0," the input of thele a logic "1 will force the input of the inverter togoes low, the pass transistor shuts off and the inputic level. In other words, when the pass transistorInput capacitance of the inverter is charged to VDD - V ,or ground,pass transistor. As long as this charge is present, the logic value isWhat we are concerned with at this point is the leakage mechanisms

I can leak the stored charge off the node. A node, such as the one labeledis called a dynamic node or a storage node. Note that this node is anode and is easily susceptibletonoise (seeEx. 3.4).

ample of a dynamic circuit and associated stotage capacitance.fk. I ,*.I : *

276


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14.1.1 Charge LeakapConsider the expanded view of the charge storage node shown in Fig. 14.2.the only leakage path on this node is through the MOSmTs drain (ordrain and source are interchangeable) n+ Ipsubstratc diode. If we consi&the drain of the MOSFET, the current is given by- s(e-VdnVr-1)I D =11-e -where V,, s the voltage on the storage node to ground, assuming theground potential. From heBSIM model parameters, the scale current is,

I s =A D . JSIn order to simplify hand calculations we will assume that the leakage c

tratehv

to the scale current, orI m r = I s = A D . JS

The rate at which the storage node discharges is given bydV I * a k y l d AD -J S-=-=dt Cno k Cn~d.

The node capacitance is the sum of the input capasitarm of the inve-,to ground of the metal m p ly line connecting the inverterto the p l scapacitance of the drain implant to substrate (the depletion capaciuasc).applications, we assume thatC d , =Ch of he inverter

discharge rate of the 50 fF capacitor shown below. Assume that then and source areasmeasure 6pmby 6pn.

BSIM model parameters, JS = lo-" Nm2; hcrcfm, the leakage currentI r* =AD * JS=36 p 1 0 4 = 3 6 0 ~ OW 2'A

harge rate is estimated by

slow discharge rate. In practice, the MOSPET can have a nonzerooltage causing a subthreshold current to flow, incmshq the#rate. Also, the value of umnt denslty given in the BSlM modal inA and used above, that is,JS = 10dNma, s the SPICE default value.that the leakage current was not measured whem generating theindicating another possible source of error. .ngDynamlc Clrculta

mely small lealcege currents involved, simulating dynamic circuitst, when SPICE simulates any circuit, it puts a resistor with aven by the parameter GMIN across every pn junction and

to source. The default value of GMIN s mhos or a 1M esistor.node at a potential of 5 V has a leakage current, due toGMIN, f 5the node voltage starts to decrease, the leakage current decmscsascurrent calculated in Ex. 14.1 was 360 x 1P ' A, or over a millionthe 5 pA flowing through the &fault value of GMIN. The value ofsing the .OPTIONS command, at the cost of a longer or moretime, to a smaller value, say 10-Is.

t accuracy), RELTOL (relative accuracy). or VNTOLparameters can limit the accuracy of the simulation andt value of the current accuracy, ABSTOL, is 1 PA. Since

to determine if convergence has been reachedWOUM nstd to be t~ get sma

278 Part I1 CMOS Digital Cil Chapter 14 Dynamic Logic Gates 2794


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results closer to hand calculations. In addition, CHGTOL, the capacitance cltolerance that defaults at 10 fC (1 V on a 10fF apacitor), would need reduction.

In practice, we use the default values of SPICE, which give a pessirestimate for the discharge time of storage nodes in dynamic circuits. The le;current, for VD D = 5 V , s given by

I I , ~ ~ , , , 5 pA = VDD .GMIN ( 1and

dV - 5PA - VDD .GMIN-dt Cno& Cno& (1 ,

For C = 50 fF, it takes approximately 10 ms for the voltage on the charge st(node to fall 1 V , If 1 V is the most we will allow the node to fall before we :another clock signal, then the minimum clock frequency is 100 Hz. The folloexample illustrates the dominance of GMM in the simulation of a dynamic circuit.

)rage~ P P ~ Ywing

Example 14.2Simulate the circuit of Ex. 14.1. Estimate the discharge rate of the capacitor dueto the default value of GMIN.The discharge rate from Eq. (14.7) is 1 V per 10 ms for a GMIN of 10-12 mhos.The SPICE simulation results are shown in Fig. 14.3. Notice how the leakagedrain current is jagged. This is the result of the numerical iteration scheme usedby SPICE. The simulation currents will vary by an amount less than ABSTOL,or 1 PA. In most simulations, we do not see the small current variations. .

. . TimeFigure 14.3 Simulation results showing discharge of a capacitor

14.1.3 Nonoverlapping Clock Generationconsider the string of pass transistor shverters shown in Fig. 14.4. This circuit is

a dynamic shift register. When @, goes high, the first and third stages of the,@er are enabled. Data are passed from the input to point A0 and from point A1 to,A>. If Q, is low while $, is high, the data cannot pass from A0 to A1 and from A2 to, p ~ . f Q, oes low and @ goes high, data are passed from A0 to A1 and from A2 to A3.~f both 4, and@,re high at the same time, the input of the shift register and the outputare connected together, which is not desirable in a shift register application. Thep q o s e of the inverter between pass transistors is to restore logic levels, since then-channel pass transistor passes a high with a threshold voltage drop. Two inverterswould be used to eliminate the logic inversion between stages. The clocks used in thisdynamic circuit must be nonoverlapping, or logically

There should be a period of dead time between transitions of the clock signals, labeled Ain Fig. 14.4. The rise- and falltimes of the clock signals should not occur at the sametime.

Since the design and layout of the dynamic shift register is straightforward let'sconcentrate on the generation of clock signals, @, and @, Note that a simple logicinversion will not generate nonoverlapping clock signals.

t ime

F i ~ u r e4.4 Dynamic shif t register with associated nonover lapping clock s ignals .


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MOSTO InDynamkClreulta

e IeaLage of charge off of or onto the nput capacitance of the n v e n Fig.be attributed to the drain-well diode of the p-chaanel MOSFET and thethe n-chmwl MOSFET wed in the TO. If these leakage

nding on the size of thedrain anas nd the leaLage cmnts.

used in the clocking scheme. Additional MOSFETs can be used forhelping thegateappearmore static in operation.

nehanaddrainhubs d i o d s 4Subsmtc cauKcaon

piw 1 4 ~MOS TOused in dynlmic losic

Part 11 CMOS Digitalad 4 DynamicLogicGates 283


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output is in the Hi-Z tate, or in other words a high-impedance nodesignal feedthrough. The layout of the CMOS gate is thus more crigate. Because of this node, running signal lines above this noddefinite problem. The output of the gate is not static. When the latch is enablis high, the capacitance on the o u G node is charged. The same leakagemepresent in the CMOS TG atch are present here. This limits the minim1frequency to about 100 Hz. Implementing a shift register requires nonovclocks for adjacent stages. The total number of clock signals needed for a C%register is four. The nonoverlapping clocks@,nd42and their complements. 3PE LogicThis section discusses precharge-evaluate logic, or PE ogic. Consider thNAND gate shown in Fig. 14.8. The operation of this gate relies on ainput. When 4, is low, the output node capacitance is charged to VDDDuring the evaluate phase, 0, is high. MI is on, and if AO Al , and A2output is pulled low. The logic output is available only when 4, is high.logic one when 4, is low. One disadvantage of PE logic is that the gate loavailable part of the time and not all of the time as in the static gates.

Several important characteristics of the PE gate should be pointedinput capacitance of the PE gate is less than that of the static gate.connected to a single MOSFET where the static gate inputs are tied toPotentially the PE gate is then faster and dissipates less power.

VDD

Precharge+A1 -A2+A3 A4

4'1 -Ngore 14.9 A complex PE gate.

The size of the MOSFETs used in a PE gate does not need d o i ng fora1 switching point voltage. The absence of complementarydevices and thethe output is pulled hiah during each half cycle makes the gate V,ess. ~owevcr,wemay need to size the devices to attain a certain speed fofi

d capacitance. If the sizes of allNMOS transistors used in Fig. 14.8 are equal,t,,, is approximately 3R& and the t,, is R,C,, where C,, is the totaln the output node. ?his may include the interconnecting capacitanceandacitance of the next stage. Hae we have neglected both the transmission

a series connection of MOSFETs and the intrinsic switching speeds.gic function, F=AO+ A1 A2 +A3 A4, implemented in PE logic is

a& of PE gates shown in Fig. 14.10. During the precharge phase ofoutput of each PE gate is a logic high. T%s high-level output ise input of the next PE gate, Suppose the logic out of the first PE gateuate phase is a low. This output will turn off any MOSFETs in them. owever, during the ph a r g e phase, those same MOSFETs in the-tewill be turned on. The elay between the clock pulse going high and thed he first gate will cause the second gates output to glitch or show anautput. If we can hold the output voltage of fhe PE gate low, instead ofthisracecondition. Upon adding an inverter to the PE gate (Fig.glitch-ftse operation is met. The PEgate with the addition oflogic. The name Domino coxlles fnnn he fact that a gategates cannot change output states until the previous gatein output of the gates occurs similar to a series of fallingin theDomino gateha s the added advantagethat it can beloads.

ter 14 Dynamic Logic Gates 285


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Figure 14.10 Problems with a cascadeofPE@tee. ,1 l

Figure 14.11 Domino logicgate.

14.12 Kce rMOSPETused o hold node A inat when FBprts atput ishigh.

One problem does exist with this scheme, however, referring to Fig. 14.11, noteduring the precharge phase, node A is charged to VDD. If theNMOS logic resultslogic high on node A during the evaluate phase, then that node is at a highce with no direct path to VDD or ground. The result is charge leakage off ofA when the PE output is a logic high. The circuit of Fig. 14.12 eliminates thisem. A "keeper" p-channel MOSFET is added to help keep node A at VDD whenOS logic is off. The WIL of this MOSFET is small, so that it provides enoughto compensate for the leakage but not so much that the NMOS logic can't drive

behind implementing a logic function using NP ogic is shown in Fig. 14.13.r used in Domino logic, making higher speed operation possible. A circuiteasily be implemented in IW ogic is the full adder circuit of Fig. 12.18. Thection of the carry circuit is implemented in the first section of the IW ogic,PMOS section of the sum circuit is implemented in the PMOS section of the

c adder just described performs one two-bit addition with carry during eache. Adding two-four bit words requires the use of pipelining [4]; see Fig.e bits of the word are delayed, both on the input and output of the adder, soof the sum reach the output of the adder at the same time. Note, however,words can be input to the adder at the beginning of each clock

where two numbers are not added continuously can result in longer

Figure14.13 NP ogic.z . A u - * 21


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Aca

Part 11 CMOS Digital Circuits288 -


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14.9 sketch the implementation of an NP logic half adder cell .14-10 Design (sketch the schematic of ) a full adder circuit using PE logic.14.11 Simulate the operatio n of the circuit designed in Problem 14.10.

-

14.12 Figure P14.12 shows one bit of a shift register implemented in the so-calledra t io less NMO S logic . W e te rm ratioless results from the fact that theMO SFE T sizes do not affect the switching point voltages. Also, this gate can belaid out in a very small area and the outputs can swing down to gm un d Discussand simulate the operation of this circuit. Keep in mind that Q, an d b , arenOno verlapping clock signals. Wh at is the maximum outp ut voltage of thiscircuit?

All MOSFETs are minimum size. Figure P14.12

14.13 Show that the dynamic circuit shown in Fig. P14.13 is an edge-triggeredflip-flop 151. Note that a sing le-phase clock signal is used.

Chapter

VLSI LayoutThe past chapters have concentrated on basic logic-gate design and layout. In thischapter we discuss the implementation of logic functions on a chip where the size andor~m izatio n f the layouts are of importance. The number of MOSFFTs on a chip,tiepending on the application, can range from tens (an op-amp) to hundreds of millions(a 2 0 ME G DRAM ). Designs where thousands of MOSFET s or more are integratedo n n single die are termed very-large-scale-integrationVLSI) designs.

To help us understand w hy chip size is important, examine Fig. 15.1. T he dark(k in di ca te a defect that will lead to a chip which doesn't function properly. FigureI( .lr shows a wafer with nine full die. The partial die around the edge of the wafer are\ v s t d Five of the nine die do not contain a defect and thus can be packaged and sold.Next 'conrider a reduction in the die size (Fig. 1 5.lb ). We are assuming each die.

point, we may ask the question, "How do we determine the size of the blocks in


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whether discussing the die of Fig. 15.la or b, performs the same fureduction can be the result of having better layout (resulting in a smallerfabricating the chips in a process with smallerdevicedimensions (e.g.,pm process to a 0.5 pnprocess). The total number of die lost (see Fig.defectsis five; however,thenumber of good die issignificantly larger thandie of Fig. 15.la. The yield (number of good didtotal number of die on.increased with smaller die size. The result is more dietwafer av&Another benefit of reducing die size comes from the realizationwafer are constant and increasing the number of die on a waferdie.15.1 ChipLayoutVLSI designs can be implemented using many different tecMgate-arrays, standard-cells, and fullcustom design[l]. Sincegatearrays are, in general, used where low volume and fastrequired and the chip designer need ho w little to nothingimplementation of the CMOS circuits, we wi l l concentrate on fullc,&sign using standard cells.RegularityAn important consideration when implementing aVLSI chipdesilayout should be an orderly mangement of cells. Toward thisdesigning a chip is drawing up a chip (or section of the chip) flowshows a simple floor plan for an adderdata-path. This f l m planfloor plan of an overall chip, which includes output buffers, control

Fun-aMa cellsoutpUtlrrtchc8

I I>

'lack Figme 15.2 Floorplan fa n adder.

' At many universities, progtammablc-logic-arraysm)mDigital Logic Design, while design using a herdw~vcfield-programmablegatearrays (FPGAs) s discussed inDesign.

,2?" The answer to this question leads us into the design and layout of the cellsimplement each of the logic blocks in Fig. 15.2.

cells are layouts of logic elements including gates, flip-flops, and ALUt are available in a cell library for use in the design of a chip. Customto the design of cells or standard cells using MOSFETs at the lowest level.

cell design refers to design using standard cells; that is, the designer comectsn standard cells to create a circuit or system. The difference between thedesign can be illustrated using a printed circuit board-level analogy. A11 design is analogous to designing with packaged parts. The design ished by connecting wires between the pins of the packaged parts. Customanalogous todesigning the "insides" of the packaged parts themselves.e 15.3 shows an example of an inverter [2]. In addition to keeping the

as small as possible, an important consideration, when laying out a standardrouting of signals. Keeping this in mind, we can state the following generalfor standard-cell design:inputs and outputs should be available, at the same relative horizontalce. on the top and bottom of the cell.

ntal runs of metal are used to supply power and ground to the cell, a.k.a.r and ground busses. Also, well and substrate tie downs should be underheight of the cells should be a constant, so that when the standard cells areend to end the power and ground busses line up. The width of the cellbe as narrow as the layout will allow. However, the absolute width is nott and can be increased as needed.layout should be labeled to indicate power, ground, input, and outputons. Also, an outline of the cell, useful in alignment, should be added to

15.4 illustrates the connection of standard cells to a bus. Note that mlv.. rvertically, can cross the metall lines, which run horizontally withoutt. This fact is used to route signals and interconnect standard cells in aAlso, in this figure, note how the two inverter standard cells areplacede result is that power and ground are automatically routed to each cell.les of static standard cells are shown in Fig. 15.5. A doubleis shown in Fig. 15.5a while NAND, NOR, and transmission gatewn n Figs. 15.5b, c, and d.

.6 shows the layout of a NAND-based SR flip-flop. This layout differswe have discussed. All layouts discussed so far have metal1 and


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,, 7;.p+ aubsmtctie down!

GN I

I N OUT

Figure 15.3 Standardall layoutof an inverter. d Control 6 IN WT

IN WT

294 Part I1 CMOSDigitalis longer than the adjacent MOSFET. This additional width is of little


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S O Q ' R

Figure15.6 SR lip-flop using NAND gates.contacts adjacent to the gate pl y. Also, the gate pl y has been 1bends. The expanded view of a pchannel MOSFET used in theSRin Fig. 15.7. Keeping in mind that whenever p l y crosses active (n+oris formed, we see that the .murceof the MOSFET s connected tocontacts, while the p+ implant forms a resistive connection toremainder of the device. The layout size, in this casethe width of the

ce and has little effect on theDC nd transient properties of the gate. Figurews theNOR mplementation of an SR lip-flop.

Figure 15.8 SR lip-flopusingNOR gates.

blems encountered when designing a chipcan be related to distributionund. When power and ground annot distributed properly, noise canone circuit onto the power and ground conductors and injected intopadframe shown in Fig. 15.9a

power and ground shown. Approximately 600 tandard cells are. The space between the rows of standard cells is used for thes. A line drawing of a possible powerandground bussing architecture. 15.9b. Coasidcr the section of bus shown n Fig. 15.9~.Wire A iswhile wire B is used for(VDD)s returned on B

onductors B and C, which givesconductor. This coupling canbe reduced byand C. This reduces the inductive and capacitive. Another solution is to increase the capacitance&coupling capacitor(Fig. 15.10) can be used toward, A 4 - 2

296 Part I1 CMOS Digitalal. The capacitor is placed in the middle of a standard-cell row. Also, the AC


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Fe drop effects discussed in Ch. 3 are greatly reduced by inclusion of thisor.

VDD

GND

Figure 15.10 Decoupling capacitor.pupling is a problem on signal busses as well. Figure 15.11 shows a simpleUsed to reduce coupling. The length of a section, where two wires are adjacent,Dd by routing the wire to other locations at varying distances along the bus. Theor capacitive coupling between two conductors is directlv related to the length

298 Part II CMOSDig 5 VLSILayoutthe FF s shown in Fig. 15.12b. The layout size and the size of the


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An Adder ExampleAs another example, let's consider the implementation of a four-bit afloorplan for this adder was shown in Fig. 15.2.) The first components 1designed are the nput and output latches. Figure 15.12. shows the schemflip-flop used in the latches. This FF s the level-triggered type d i l auvchapter. When CLK is high, the output, Q.changes states with the iqinverter, 14, is used m provide positive feedback and is sized with a smallthat 11 does not need m supply a large aamunt of DC urrent to force the lal

Figare 15.12 Schematic and ayoutofaD F'.

these examples are larger than what would be used in practice toand viewing the ayouts easier. , .e layout of the static adder is shown in Fig. 15.13. This is theon, using near miniplum-size MOSFETs, of the AOI' static adder of Fig.e carry-out and sum-out logic functionsare mp1emcnted in this cell.

IFigure 15.13 Layout of the static addaof Fig. 12.18.lete layout of the adder is shown in Fig. 15.14. The two four-bitd Word-B, are input to the adder on the input bus. These data areinput latch when CLK is high, while the results of the addition areoutput latch when CLK is low. The inverter standard cell of Fig. 15.3-end of the output latches and is used to generateCLK for use in the

The inputs and outputs of the adder cells arerun on p l y because of theinvolved. The carry-in of the adders is co~ectedo ground, as shown in

4 to 1 MUX/DEMUX is shown in Fig. 15.15 (based on the circuit.11). This layout is different from the layouts discussed so far sincerequirepower and ground connections and the input/output signalsbe connected to the output, the signals S1 and S2 should bethe prapagation delay throughthe n+ should be considered.

LayoutStep8 by Dean Moriarty, CrystalSemiconductor


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Inputbus 1

Figure 15.14 Layoutof thecompleteadder.

S 1 S l n o t S 2 S2no t

mps involved in rendering a schematic diagram into its physical layout are: plan,h connect, polish, and verify. Let's illustrate each of these steps in some detailrgh the use of examples.&g andStick Diagrams

ng steps start with paper and pencil. Colored pencils are useful forng one object from another. You can use gridded paper to help achieve aroportion in the cell plan but don't get too bogged down in the details ofl i e widths at this point; we just want to come p with a general plan. A" is a paper and pencil tool that you can use to plan the layou t of a cell.agram resembles the actual layout but uses "sticks" or lines to represent theWhen used thoughtfully, it can reveal any special hook-uput, and you can then resolve them without wasting any time.e 15.16a shows the schematic of an inverter. In order to realize the layout, t is first necessary to define the direction and metalization of the powerand output. Since the standard-cell template "sframe" in thefor us, we'll use it. Power and ground runhorizontally inmetal17 microns wide. The input and output are accessible from the top orcell and will be in metal2 running vertically. Figure 15.16b shows thek diagram. Note the use of "X" and "0" o denote contacts and vim,ly. The stick diagram should be compared to the resulting layout of Fig.


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Figure15.17 Layout of the inverter shown inPig. 15.16. ,I,Suppose the device sizes of the inverter circuit in Figure 15.16awere

@ = 3612, n = 12/2). Furthemore, let's assume that themaximum recgate width is 20 pn (due to the sheet resistance of the poly) and thmaximum could introduce significant unwanted RC &lays. Let's also suare to optimize the layout for size and speed (as most digital circuits are).criteria, it will be necessary to split transistorsM1 and M2 in half and lay VDDtwo parallel "stripes" of 18/2 for the p-channel and two parallel "stripes"n-channel. Figures 15.18a-d show the schematics, stick diagram, and 1scenario. The output node (drain of M1 and M2) is shared between theminimize the output capacitance. Taking the output inmetal2also hNotice that the stick diagram for this circuit looks like the previousmimw image along the output node. Also observe that the layout omirrored as shown n the stick diagram. This is a common layout t

Incidentally, LASICKT will need a schematic similar to Fig. 15.1connectivity of the layout. More sophisticated (and much more esoftware could use the schematic of Fig. 5.18a

Figure 15.19 shows stick diagrams and layouts for two morethe two-input NAND and the two-input NOR. Compare the stick15.19a and c to the layouts of Figs. 15.19b and d. Observe that thethe active area just as in the previous example. Also note that the spaclaggates of the series-connected &vices is minimum (for the CN20 rocess). W.18 (a) blwmr*@) t i d diagram used for layout, (c)ayout, and(d l Equivalentschematic.

PartII CMOS ~ g i t adTake another look at the two circuits from a geom etrical rather than

15 VLSI Layout 305


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viewpoint. Compare the NAND gate layout to the NOR gate layout. Doeach can be created from the other by simply "flipping" the metal and p l yabout the x-axis?

Figwe 15-19 (a) NAND tick diagram, (b) l a m c) NOR stick&&

CLK

VDD

k 7-CLK-

Figure 1520 Schematicof a dynamic register cell.

s the schematic of a dynamic register cell, while Figs. 15.21 a-c showand layout for a dynamic register. Compare the schematic of Fig.of Fig. 15.21a We have labeled this stick diagramwill soon become apparent. Notice that there is a breakch will form our n-channel devices. Also note that the"cnws o ~ c c t e d "rom ne side of the layout tothis through very far to notice that, with thisclock signals is going fo be very difficult. Nowin Fig 15.21b. Notice that we have rearranged thecontinuous unbroken line. Normally. this "unbrokenp r e f d . It usually results in the most workableWe say "usually" because at timesyour layout has to fi t in an areaocks around it and you have no control over it. Also observe from

clock signal hook-up is more straightforw ard Compare this stickthe layout ofFig. 15. 22~ . Obviously, the device sizes used for this circuite is merely to il lu st rk a layout concept. We can also se e1s a useful tool throughout the layout process.

t i s basically finished, it is time to step back and take a look at it from aof view. Is it pleasing to the eye? Is the hook-up asble, or is it "busy" and hard to follow? Are the spaces between

7 What about the spac e between diffusions? Are there

Part I1 CMOSDigitalM 307

Cells Versus Full-Cumom Layout


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TK CLK

Figun 15.21 Laywt of a dynamicregister cell.enough contacts? Did you share all of the so me and drainshared? Are there sufficient well and substrate ties? Iffollowed the plan described here, you shouldn't run into too

dard-cell approech to physical design usually dictates that cell height be fixedwidth be variable when implementing the circuit. Furthermore, standard cellsed to abut on two sides, usually left andtight, and that abutment scheme mustregular so that any cell can residc next to any other cell without creating ae violation. The tandarden appronch to layoutis very usefuland is alwaysplace to start. However, n the nal world, area on a wafer translatesas tinhtly pwkedwith circuitry aspossible. Therefore,it follows that we want- -t that is as d l s possible so that there can be as many die per wafer as. These re the economics of the situation. 'Ihere ar e also technical advantagesfrom having as small a layout aspossible: intercomtingwires can be asible, thereby reducing parasitic loadingandd k ffects.gure 15.22 shows a typical standardcell block that has been placed and routedc tool. M a t of the individual cells have been omitted for clarity. Noticeect channels between the rows of standard cells. Power, ground, and clockrun vertically to both sides of the block by means of a special cell called anell rows areconnected to power and ground through horizontal busses thatcells thunselvcs. All remaining Connections aremade via thestandard-cdl l a m re designed to acconnnadate metal2

run vertically througheach cell. The autoroutermakes use of thisghs aswedadinoEdato~~nmctorpassignalsfromonemuting channels and their associated intercomectingforboththe~tysladcircuitperf~ofthistypeofcontinue our.discussionof relative layoutdensiq,we need Eo define ah to quantify the matter. It is customray to use the number ofaremillimeter of area for this purpose. Because it 4s a raw numberof all circuit layouts, we can use it even when comparingven unlikepwxsses.

of the standard41 route shown in Fig. 15.22 h appmximatelymillhem. Tbis is faitly represantative of the possibleapproach and the process used (0.8 pm). Figurea digital filta. Thecircuit area is approximately.The density is approximately 17,500 traasistars per squarea 3.5-fold inmase. This circuit, too, s fairrlyrepnsentative offull-custwm layout using this particular 0.8 pmproWs. Bothprocess, and in fact they are from the samewould probably average out to minimum oraffecting density is the interconnect wiring.

with intercoane!ct wiring is commonly referred to as the"J'he designer must bcar this burden in terms of both physical

Part 11CMOS 5 VLSILayoutand electrical parameters (parasitic loading). Let us examine one methodhigh-density custom layout that will minimize interconnect burden and


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res 15.24a-c show a small section of the interpolation filter fromFig. 15.23..24a, we see an explodeQ view of four cells that form part of a data-path: anregister, a t-gate, a full adder, and an output data register. These are(placed as a cell) twice, creating a view of eight cells. The two adder cellsdifferent: the carry inputs and outputs are on opposite sides, so that the

ade to the carry-in of the next adder by abutting (placing next to one. Unlike standard cells, the height and width constraints placed onare contextual. In other words, a cell's aspectratio depends on that of itsthis case, the width of each cell depended on the maximum allowableidest cell in the group: the data register. Notice the top, bottom, left, ands of each cell in Fig. 15.24a Data enter the register cell from the topt the bottom. Clocks,power, ground, and control signals route acrosse adder receives its A andB inputs from the top and outputs their SUMAs already mentioned, carry-out and carry-in are available on the leftf the adder, respectively. Figure 15.24b shows a two-bit slice of thisconnections made by cell abutment. Figure 15.24c llustrates how allcell join together to complete the hook-up.

e seen how circuits can be implemented by means of standard cells orThe time needed to produce a standard-cell route is far less than that of

Rmghtmr

310 Part11 CMOS Dia fullcustom implementation. The trade~ffs re area and performance. 4

ter 15 VLSI Layout 311Repeat Problem 15.1 for a hvo-input NAND gate.


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place and route tools based on routing area rather than routing channehcoming into use. These promise a compromise solution between thedensity of their results rivals that of full-custom layout. Perhapsfull-custom layout will someday become a thing of the past. Nevtechnology will continue to advance, circuit &signets will continuethat test the outermost limits of this technology, and the marketplacedemanding ever cheaper, more powerful, and faster products. Itwill all still have the opportunity to "push a polygon" or two forThere remains no doubt that the future will bring us ever more pothat will take over the tedious aspects of placing and connecting layoutsthe more creative aspects of planning and polishing them.REFERENCES[I] N. H. E. Weste and K. Eshraghian, Principles of CMOSAddison-Wesley, 2nd ed., 1993.ISBN0-201-53376-6.[2] D. V. Heinbuch, CMOS3 Cell Library, Addison-Wesley, 10-201-1 257-4.[3] Kerth, Donald A. "Floorphing-LectureNotes"Crystal Semi[4] Kerth, Donald A. "Analog Tricks of the Trade-LectureSemiconductor, Inc.[5] J. Uyemura, Physical Design of CMOS Integrated Circuits UsingPublishing Co., 1995. SBN 0-534-94326-8.PROBLEMS15.1 The standard-cell height can be reduced to make standard-smaller (Fig. P15.1). Using this cell as an approximate heighta double inverter.

Repeat Problem 15.1 or a two-input NOR gate.transmission gate (with the same functionality as Fig.

Repeat Problem 15.1 for &NAND-basedSR flip-flop.Repeat Problem 15.1 for a NOR-based SR flipflop.Design, lay out, and simulate the operation of a D R o replace the onedescribed in Fig. 15.12. Assume that the FF uses mainly minimum-sizeMOSFETs and that a pass transistor is used for the clocking element., h y out the two-inputMUX usingTGs hown in Fig. P15.8.

S- I z

standard-cell frameheight described in Problem 15.1,ay outs of fig. P15.9. Assume thatboth the inputs and outputs toEMUX based on the layout topology given in Fig.to 1MUX/DEMUX in as small an area as possible.

stickdiagram for he layouts of FTg 15.5.thehigh-hpakpce nodes for the schematic of Fig. 15.20. Discuss theone must consider when laying out a circuit with high-impedance

s hree reasons o have small layout size.D FPshown n Fig. P15.14. Show the stick diagram for your layout.

part 11 CMOS Digital Circuits312 -

B EChapter


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1 XNOREFigure P15.9

BiCMOS Logic Gates

Modern BiCMOS technology began in the early 1980s with high expectations [I]. 'Iname BiCMOS comes from the fact that the logic is made using CMOS and bipojunction transistors (BJT). The BJTs are used for their high-current capability, whCMOS is used because of its small layout size and ease of implementing logic. With tbest of both worlds on a single substrate, high-speed, high-current-driving bipotransistors and low-power, high-impedance CMOS devices, every major semiconduc~foundry now possesses some form of BiCMOS process. Strategies for developiBiCMOS have evolved from the bipolar and the CMOS directions, with advantages adisadvantages associated with each. Bipolar device capabilities have been addedsome CMOS processes to improve speed, while CMOS device capabilities have beadded to some bipolar processes to minimize power dissipation. A chart compariCMOS, BiCMOS, and bipolar (with l2L) technologies can be seen in Fig. 16.1 [2,:This chapter focuses on the CMOS process with bipolar capabilities. Although tCN20 process is not a true BiCMOS process, it does contain some BJT options that wallow demonstration of basic digital BiCMOS circuit design. It should be noted that tCMO~14TBrocess contains no provisions for BJT devices.

Microprocessors are particularly well suited for BiCMOS technology. Typicalgeneric categories limit microprocessor performance [I]: (1) Instructions F

task3 (2 ) cycles per instruction, and (3) time per cycle. The third category can be greal'mproved by increasing the speed critical blocks. A PC microprocessor [41using a bipolar-based BiCMOS process. Operating at 533 MHz, tmicro~r~cessorsed high-density CMOS devices that were added to a bipolar proceTh e floor plan can be seen in Fig. 16.2 [S] n which the speed critical blocks such as tIntegerand floating point units utilized BJT transistors, while power-consuming caca r r ays and I/O cells (for system compatibility) were co&uct ed using -CM(rechno~~m.

cmos digital circuits - book

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