cmos logic data book

7/14/2019 Cmos Logic Data Book

1/449


2/449

CMOS L

Rev.

This book presents technical data for the broad line of CMOS logic integrated circuits and demonductors continued commitment to MetalGate CMOS. Complete specifications are provided in theIn addition, a Product Selector Guide and a Handling and Design Guidelines chapter have been incthe user with these circuits.


3/449

ON Semiconductorand are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves thwithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its ppurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically discincluding without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCIspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, inclvalidated for each customer application by customers technical experts. SCILLC does not convey any license under its patent righSCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the bintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation whermay occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indand its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, evenSCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Empl

PUBLICATION ORDERING INFORMATION

CENTRAL/SOUTH AMERICA:Spanish Phone: 3033087143 (MonFri 8:0

Email: [email protected]

ASIA/PACIFIC: LDC for ON Semiconductor APhone: 3036752121 (TueFri 9:00am to 1:0

NORTH AMERICA Literature Fulfillment:Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone: 3036752175 or 8003443860 Toll Free USA/CanadaFax: 3036752176 or 8003443867Toll Free USA/CanadaEmail: ONlit@hibbertco com


4/449

Table of Contents

Chapter 1 Master Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Alphanumeric Listing of All CMOS Part Numbers with Function and Page Number Information Prov

Chapter 2 Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CMOS Selection Guide Sorted by Product Function

Chapter 3 Reliability Audit Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Explanation of On Semiconductors Outgoing Product Performance Audit Program

Chapter 4 B and UB Series Family Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Explanation of Standardized Specifications for the Product Family

Chapter 5 CMOS Handling and Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Handling Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Protection Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Propagation Delay and Rise Time versus Series Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CMOS Latch Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 6 CMOS Logic Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

See the Master Index for Page Numbering Information

Chapter 7 CMOS Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Air Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Optimizing the Long Term Reliability of Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 8 Equivalent Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 9 Packaging Information Including Surface Mounts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ON Semiconductor Major Worldwide Sales Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ON Semiconductor Standard Document Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


5/449

ALExIS, BulletProof, CHIPSCRETES, Designers, DUOWATT, EFET, EASY SWITCHER, ECL300, ECECLinPS Plus, ELite, EpiBase, Epicap, EZFET, FULLPAK, GEMFET, ICePAK, L2TMOS, MCCS, MDTL,

MHTL, MiniMOS, MiniMOSORB, Mosorb, MRTL, MTTL, MultiPak, ONDemand, PowerBase,

SCANSWITCH, SENSEFET, SLEEPMODE, SMALLBLOCK, SMARTDISCRETES, SMARTswitc

SuperLock, Surmetic, SWITCHMODE, Thermopad, Thermowatt, TMOS, TMOS & Design Device, TM

UNIT/PAK, Uniwatt, WaveFET, ZSwitch and ZIP R TRIM are trademarks of Semiconductor Compo

(SCILLC).

HDTMOS and HVTMOS are registered trademarks of Semiconductor Components Industries, LLC (SC

All other brand names and product names appearing in this publication are registered trademarks o

respective holders.


6/449

CH

Mas


7/449


8/449

MASTER INDEX

Device Function

MC14001B Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14001UB Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14007UB Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . .

MC14008B 4Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14011B Quad 2Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14011UB Quad 2Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14013B Dual D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14014B 8Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14015B Dual 4Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14016B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14017B Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14018B Presettable DividebyN Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14020B 14Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14021B 8Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14022B Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14023B Triple 3Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14024B 7Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14025B Triple 3Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14027B Dual JK FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14028B BCDtoDecimal/BinarytoOctal Decoder . . . . . . . . . . . . . . . . . . . . .

MC14029B Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . .

MC14040B 12Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14042B Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14043B Quad NOR RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14044B Quad NAND RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14046B PhaseLocked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14049B Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14049UB Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14050B Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14051B 8Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . .

MC14052B Dual 4Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . .MC14053B Triple 2Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . .

MC14060B 14Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14066B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14067B 16Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . .


9/449

Device Function

MC14081B Quad 2Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14082B Dual 4Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14093B Quad 2Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14094B 8Stage Shift/Store Register with TriState Outputs . . . . . . . . . . . . . . .

MC14099B 8Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14106B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14174B Hex D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14175B Quad D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14490 Hex Contact Bounce Eliminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14503B Hex 3State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14504B TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . MC14511B BCDto7Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . .

MC14512B 8Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14513B BCDto7Segment Latch/Decoder/Driver with Ripple Blanking . . . .

MC14514B 4Bit Transparent Latch/4to16 Line Decoder (High) . . . . . . . . . . . . .

MC14515B 4Bit Transparent Latch/4to16 Line Decoder (Low) . . . . . . . . . . . . .

MC14516B Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14517B Dual 64Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14518B Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14520B Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14521B 24Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14526B Presettable 4Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . .

MC14528B Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14532B 8Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14536B Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14538B Dual Precision Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . MC14541B Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14543B BCDto7Segment Latch/Decoder/Driver for Liquid Crystals . . . . . .

MC14549B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14551B Quad 2Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . .

MC14553B 3Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14555B Dual Binary to 1of4 Decoder (Active High Outputs) . . . . . . . . . . . . .

MC14556B Dual Binary to 1of4 Decoder (Active Low Outputs) . . . . . . . . . . . . . .

MC14557B 1to64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . .

MC14559B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14562B 128Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14569B Programmable Dual 4Bit Binary/BCD Down Counter . . . . . . . . . . . . .

MC14572UB Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


10/449

CH

Product Select


11/449


12/449

CMOS Selection Guide by Function

Device Function

NAND Gates

MC14011B Quad 2Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14011UB Quad 2Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14093B Quad 2Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14023B Triple 3Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOR GatesMC14001B Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14001UB Quad 2Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14025B Triple 3Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AND GatesMC14081B Quad 2Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14073B Triple 3Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14082B Dual 4Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Complex Gates

MC14070B Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14077B Quad Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14572UB Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Inverters/Buffers/Level TranslatorMC14007UB Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . MC14049B Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14049UB Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14050B Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14069UB Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14503B Hex 3State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14504B TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . MC14584B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Decoders/EncodersMC14028B BCDtoDecimal/BinarytoOctal Decoder . . . . . . . . . . . . . . . . . . . . . MC14511B BCDto7Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . MC14513B BCDto7Segment Latch/Decoder/Driver with Ripple Blanking . . . .MC14543B BCDto7Segment Latch/Decoder/Driver for Liquid Crystals . . . . . .MC14514B 4Bit Transparent Latch/4to16 Line Decoder (High) . . . . . . . . . . . . .MC14515B 4Bit Transparent Latch/4to16 Line Decoder (Low) . . . . . . . . . . . . .MC14532B 8Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14555B Dual Binary to 1of4 Decoder (Active High Outputs) . . . . . . . . . . . . .MC14556B Dual Binary to 1of4 Decoder (Active Low Outputs) . . . . . . . . . . . . . .

Multiplexers/Demultiplexers/Bilateral Switches

MC14016B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14066B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14551B Quad 2Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . .MC14053B T i l 2 Ch l A l M lti l /D lti l


13/449

Device Function

OR Gates

MC14071B Quad 2Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FlipFlops/Latches

MC14042B Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14043B Quad NOR RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14044B Quad NAND RS Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14076B Quad DType Register with TriState Outputs . . . . . . . . . . . . . . . . . . . .MC14175B Quad D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14013B Dual D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14027B Dual JK FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14174B Hex D FlipFlop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14099B 8Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14598B 8Bit BusCompatible Addressable Latch . . . . . . . . . . . . . . . . . . . . . . .

Shift Registers

MC14015B Dual 4Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14517B Dual 64Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14562B 128Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14557B 1to64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . . MC14014B 8Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14021B 8Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14094B 8Stage Shift/Store Register with TriState Outputs . . . . . . . . . . . . . . .MC14549B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14559B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Counters

MC14017B Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14018B Presettable DividebyN Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14020B 14Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14022B Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14024B 7Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14029B Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . MC14040B 12Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14060B 14Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14516B Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14518B Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14520B Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14526B Presettable 4Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . MC14553B 3Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14569B Programmable Dual 4Bit Binary/BCD Counter . . . . . . . . . . . . . . . . . .

Oscillators/TimersMC14521B 24Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14536B Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14541B Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Multivibrators


14/449

CH

Reliability Audit


15/449


16/449

Reliability Audit Program

For Logic Integrated Circuits

1.0 INTRODUCTIONThe Reliability Audit Program developed in March 1977

is the ON Semiconductor internal reliability audit which isdesigned to assess outgoing product performance underaccelerated stress conditions. Logic Reliability Engineering

has overall responsibility for RAP, including updating itsrequirements, interpreting its results, administration atoffshore locations, and monthly reporting of results. Thesereports are available at all sales offices. Also available is the

Reliability and Quality Handbook wall ON Semiconductor devices (HBD

RAP is a system of environmentaperformed periodically on randomly

standard products. Each sample receiin section 2.0. Frequency of testing isdocument 12MRM15301A.


17/449

Pull 500* piece sample from lot following Group A

acceptance.

2.0 RAP TEST FLOW

#One sample per month for FAST, LS, 10H, 10K, MG CMOS, and HSL CMOS.

* PTHB or PTH not required for hermetic products: reduce total sample size to 450 pcs.

**Seal (Fine & Gross Leak) required only for hermetic products.

***PTH to be used when sockets for PTHB are not available.

PTHB

48 HRS

45* 340

PTH***

48 HRS

INITIAL

SEAL**

TEMP CYCLES

40 CYCLES

SCRAP

INTERIMTEST

ADD 460 CYCLES

INTERIM

TEST

ADD 500 CYCLES

FINALINTERIM*

TEST

TEMP CYCLES#

1000 CYCLES

(ADDITIONAL)

FINALELECTRICAL

& SEAL**

(2000 CYCLES)

FINAL

ELECTRICAL

(96 HRS)

FINAL

ELECTRICAL

(48 HRS)

PTH

48 HRS

(ADDITIONAL)

INTERIM

ELECTRICAL

SCRAP

3.0 TEST CONDITIONS AND COMMENTS

PTHB 15 psig/121C/100% RH at rated VCCor VEEto be performed on plastic encapsulated devicesonly.

3. Sampling to include all package ty

4. Device types sampled will be by gelogic I/C product family (CMOS


18/449

CH

B and UB Series Fa


19/449


20/449

The CMOS Devices in this volume which have a B or UBsuffix meet the minimum values for the industry

standardized* family specification. These standardizedvalues are shown in the Maximum Ratings and ElectricalCharacteristics Tables. In addition to a standard minimumspecification for characteristics the B/UB devices feature:

318 volt operational limits Capable of driving two lowpower TTL loads or one

lowpower Schottky TTL load over the ratedtemperature range

Direct Interface to HighSpeed CMOS Maximum input current of 1 A at 15 volt power

supply over the temperature range Parameters specified at 5.0, 10, and 15 volt supply Noise margins: B Series

1.0 V min @ 5.0 V supply2.0 V min @ 10 V supply2.5 V min @ 15 V supply

UB Series

0.5 V min @ 5.0 V supply1.0 V min @ 10 V supply1.0 V min @ 15 V supply

The industrystandardized maximum ratings are shown atthe bottom of this page. Limits for the static characteristicsare shown in two formats: Table 1 is in the industry formatand Table 2 is in the equivalent ON Semiconductor format.The ON Semiconductor format is used throughout this databook. Additional specification values are shown on theindividual data sheets.

Switching characteristics for the B and UB series devicesare specified under the following conditions:

Load Capacitance, CL, of 50 pFInput Voltage equal to VSS VDD(RailtoRailswing)Input pulse rise and fall times of 20 nsPropagation Delay times measured from 50% point of

input voltage to 50% point of output voltageThree different supply voltages: 5, 10, and 15 V

Exceptions to the B and UB Series FamilySpecification

There are a number of devices which have a B or UB suffixwhose inputs and/or outputs vary somewhat from the family

Devices with specialized inputs,inputs, have unique input specifi

Input VoltageThe input voltage specification

worstcase input voltage to produce an0. This 1 or 0 output level is dfrom the supply (VDD) and ground (Vsupply, this deviation is 0.5 V; for a 1for 15 V, 1.5 V. As an example, in a deV supply, the device with the input

guaranteed to switch on or before 3.5 to 1.5 V. Switching and not switching0.5 V of the ideal output level for thesupply. The actual switching level rebetween 1.5 V and 3.5 V.

Noise MarginThe values for input voltages an

deviations lead to the calculated n

margin is defined as the difference beVout(output deviation). As an exampbuffer at VDD= 5.0 volts: VIL= 1.5volts. Therefore, Noise Margin equalsThis figure is useful while cascading With the input to the first stage at a wo(VIL= 1.5 V), the output is guarantee0.5 volts with a 5.0 volt supply. allowable logic 0 for the second stag

volt output provides a 1.0 volt margistage.

Output Drive CurrentDevices in the B Series are capable

of 0.36 mA over the temperature rangThis value guarantees that these CMone lowpower Schottky TTL input.

B Series vs UB CMOS

The primary difference between Bdevices is that UB series gates and invwith a single inverting stage betweendecreased gain caused by using a singnoise immunity and a transfer characte

The decreased gain is quite useful w


21/449

MAXIMUM RATINGS* (Voltages Referenced to VSS)

Symbol

Parameters

Value

Unit

VDD

DC Supply Voltage

0.5 to + 18.0

V

Vin, Vout

Input or Output Voltage (DC or Transient)

0.5 to VDD+ 0.5

V

Iin, lout

Input or Output Current (DC or Transient), per Pin

10

mA

PD

Power Dissipation, per Package

500

mW

Tstg

Storage Temperature

65 to + 150

C

TL

Lead Temperature (8Second Soldering)

260

C

* Maximum Ratings are those values values beyond which damage to the device may occur.

Temperature Derating:

Plastic P and D/DW Packages: 7.0 mW/C From 65

C To 125

C

Ceramic L Packages: 12 mW/C From 100

C To 125

C

VIL= 1.5 VVout= 0.5 V Vout

5.0 V

FIRST STAGE

(NONINVERTING BUFFER)

SECOND STAGE

(NONINVERTING BUFFER)VIL= 1.5 V

Figure 1.

Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications

ELECTRICAL CHARACTERISTICS

Limits

Tem

VDD

TLOW*

+ 25C

Parameter

Range

(Vdc)

Conditions

Min

Max

Min

Max

M

IDD

Quiescent

Device Current

Mil

5

10

15

Vin= VSSor VDD

0.25

0.5

1.0

0.25

0.5

1.0

GATES

Comm

5

10

15

All valid input

combinations

1.0

2.0

4.0

1.0

2.0

4.0

Mil

5

10

15

VIN= VSSor VDD

1.0

2.0

4.0

1.0

2.0

4.0

BUFFERS,

FLIPFLOPS

Comm

5

1015

All valid input

combinations

4

816

4.0

8.016.0

Mil

5

10

15

VIN= VSSor VDD

5

10

20

5

10

20

MSI

Comm

5

10

All valid input

combinations

20

40

20

40


22/449

Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications (con


Limits

Conditions

VDD(Vdc)

TempRange

Parameter

+ 25 C

TLOW*

Conditions

VDD(Vdc)

TempRange

Parameter

M

Max

Min

Max

Min

Conditions

VDD(Vdc)

TempRange

Parameter

VIL

Input

Low Voltage#

B Types

All

5

10

15

VO= 0.5V or 4.5V

VO = 1.0V or 9.0V

VO= 1.5V or 13.5V

|IO| < 1 A

1.5

3.0

4.0

1.5

3.0

4.0

VIL

Input

Low Voltage#

UB Types

All

5

10

15

VO= 0.5V or 4.5V

VO = 1.0V or 9.0V

VO= 1.5V or 13.5V

|IO| < 1 A

1.0

2.0

2.5

1.0

2.0

2.5

VIH

InputHigh Voltage#

B Types

All

510

15

VO= 0.5V or 4.5VVO = 1.0V or 9.0V

VO= 1.5V or 13.5V

|IO| < 1 A

3.57.0

11.0

3.57.0

11.0

37

1

VIH

Input

High Voltage#

UB Types

All

5

10

15

VO= 0.5V or 4.5V

VO = 1.0V or 9.0V

VO= 1.5V or 13.5V

|IO| < 1 A

4.0

8.0

12.5

4.0

8.0

12.5

4

8

12

IOL

Output Low

(Sink) Current

Mil

5

10

15

VO= 0.4V,

VIN= 0 or 5V

VO= 0.5V,VIN= 0 or 10V

VO= 1.5V,

VIN= 0 or 15V

0.64

1.6

4.2

0.51

1.3

3.4

0.

0

2

Com

5

10

15

VO= 0.4V,

VIN= 0 or 5V

VO= 0.5V,

VIN= 0 or 10V

VO= 1.5V,

VIN= 0 or 15V

0.52

1.3

3.6

0.44

1.1

3.0

0.

0

2

IOH

Output High(Source) Current

Mil

5

10

15

VO= 4.6V,VIN= 0 or 5V

VO= 9.5V,

VIN= 0 or 10V

VO= 13.5V,

VIN= 0 or 15V

0.25

0.62

1.8

0.2

0.5

1.5

0

0

Com

5

10

15

VO= 4.6V,

VIN= 0 or 5V

VO= 9.5V,

VIN= 0 or 10V

VO= 13.5VVIN= 0 or 15V

0.2

0.5

1.4

0.16

0.4

1.2

0

IIN

Input Current

Mil

Comm

15

15

VIN= 0 or 15V

VIN= 0 or 15V

0.1

0.3

0.1

0.3

Ioz

3State Output

Leakage Current

Mil

Comm

15

15

VIN= 0 or 15V

VIN= 0 or 15V

0.4

1.6

0.4

1.6


23/449

Table 2. ON Semiconductor Format for CMOS Industry B and UB Series Specificat


VDD

55C

25C

Characteristic

Symbol

Vdc

Min

Max

Min

Max

M

Output Voltage 0 LevelVin= VDDor 0

VOL

5.010

15

0.050.05

0.05

0.050.05

0.05

1 Level

Vin= 0 or VDD

VOH

5.0

10

15

4.95

9.95

14.95

4.95

9.95

14.95

4.

9.

14

Input Voltage B Types 0 Level

(VO= 4.5 or 0.5 Vdc)

(VO= 9.0 or 1.0 Vdc)

(VO= 13.5 or 1.5 Vdc)

VIL

5.0

10

15

1.5

3.0

4.0

1.5

3.0

4.0

1 Level(VO= 0.5 or 4.5 Vdc)

(VO= 1.0 or 9.0 Vdc)

(VO= 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

3.5

7.0

11

3

7

1

Input Voltage UB Types 0 Level

(VO= 4.5 or 0.5 Vdc)

(VO= 9.0 or 1.0 Vdc)

(VO= 13.5 or 1.5 Vdc)

VIL

5.0

10

15

1.0

2.0

2.5

1.0

2.0

2.5

1 Level

(VO= 0.5 or 4.5 Vdc)

(VO= 1.0 or 9.0 Vdc)(VO= 1.5 or 13.5 Vdc)

VIH

5.0

1015

4.0

8.012.5

4.0

8.012.5

4

812

Output Drive Current B Gates

(VOH= 2.5 Vdc) Source

(VOH= 4.6 Vdc)

(VOH= 9.5 Vdc)

(VOH= 13.5 Vdc)

IOH

5.0

5.0

10

15

3.0

0.64

1.6

4.2

2.4

0.51

1.3

3.4

0

0

2

(VOL= 0.4 Vdc) Sink

(VOL= 0.5 Vdc)

(VOL= 1.5 Vdc)

IOL

5.0

10

15

0.64

1.6

4.2

0.51

1.3

3.4

0.

0

2

Output Drive Current UB Gates(VOH= 2.5 Vdc) Source

(VOH= 4.6 Vdc)

(VOH= 9.5 Vdc)

(VOH= 13.5 Vdc)

IOH

5.0

5.0

10

15

1.2

0.25

0.62

1.8

1.0

0.2

0.5

1.5

0

0

0

(VOL= 0.4 Vdc) Sink

(VOL= 0.5 Vdc)

(VOL= 1.5 Vdc)

IOL

5.0

10

15

0.64

1.6

4.2

0.51

1.3

3.4

0.

0

2

Output Drive Current Other Devices


(VOH= 9.5 Vdc)(VOH= 13.5 Vdc)

IOH

5.0

1015

0.64

1.6 4.2

0.51

1.3 3.4

0

0 2

(VOL= 0.4 Vdc) Sink

(VOL= 0.5 Vdc)

(VOL= 1.5 Vdc)

IOL

5.0

10

15

0.64

1.6

4.2

0.51

1.3

3.4

0.

0

2

Input Current

Iin

15

0.1

0.1

Input Capacitance (Vin= 0) Cin 7.5


24/449

CH

CMOS Handling and Design G


25/449

HANDLING PRECAUTIONS

All MOS devices have insulated gates that are subject tovoltage breakdown. The gate oxide for ON SemiconductorCMOS devices is about 900 thick and breaks down at agatesource potential of about 100 volts. To guard againstsuch a breakdown from static discharge or other voltagetransients, the protection networks shown in Figures 1A and1B are used on each input to the CMOS device.

Static damaged devices behave in various ways,depending on the severity of the damage. The most severelydamaged inputs are the easiest to detect because the inputhas been completely destroyed and is either shorted to VDD,shorted to VSS, or opencircuited. The effect is that thedevice no longer responds to signals present at the damagedinput. Less severe cases are more difficult to detect becausethey show up as intermittent failures or as degradedperformance. Another effect of static damage is that theinputs generally have increased leakage currents.

Although the input protection network does provide agreat deal of protection, CMOS devices are not immune tolarge static voltage discharges that can be generated duringhandling. For example, static voltages generated by a personwalking across a waxed floor have been measured in the415 kV range (depending on humidity, surface conditions,etc.). Therefore, the following precautions should beobserved:

1. Do not exceed the Maximum Ratings specified by thedata sheet.

2. All unused device inputs should be connected to VDDor VSS.

3. All lowimpedance equipment (pulse generators,etc.) should be connected to CMOS inputs only afterthe device is powered up. Similarly, this type ofequipment should be disconnected before power isturned off.

4. Circuit boards containing CMOS devices are merelyextensions of the devices, and the same handlingprecautions apply. Contacting edge connectors wireddirectly to device inputs can cause damage. Plasticwrapping should be avoided. When externalconnections to a PC board are connected to an input of

a CMOS device, a resistor showith the input. This resistor h

damage if the PC board is remcontact with static generating mfactor for the series resistor is thcaused by the time constant resistor and input capacitance. Ninput rise and fall times shoulFigure 2, two possible networseries resistor to reduce Discharge) damage. For conven

added propagation delay and riseries resistance size is given.

5. All CMOS devices should be smaterials that are antistatic. CMbe inserted into conventiostyrofoam, or plastic trays, butoriginal container until ready f

6. All CMOS devices should be bench surface and operat

themselves prior to handling decan be statically charged withsurface. Wrist straps in contactrecommended. See Figure 3 typical work station.

7. Nylon or other static generatincome in contact with CMOS de

8. If automatic handlers are beinstatic electricity may be genera

of the device, the belts, or the buildup by using ionized ahumidifiers. All parts of machcontact with the top, bottom, omust be grounded to metal material.

9. Cold chambers using CO2 foequipped with baffles, and the Ccontained on or in conductive m

10. When leadstraightening ornecessary, provide ground strused and be sure that soldering


26/449

INPUT PROTECTION NETWORK

Figure 1a. Input Protection Network

Double Diode

Figure 1b. Input Prot

Triple Dio

VDD VDD

CMOS

INPUTTO CIRCUIT


27/449

Figure 2. Networks for Minimizing ESD and Reducing

CMOS Latch Up Susceptibility

TO OFFBOARD

CONNECTION

R1CMOS

INPUT

OR

OUTPUT

TO OFFBOARD

CONNECTION

R2

Advantage:

Disadvantage:

Requires minimal board area

R1 > R2 for the same level of

protection, therefore rise and fall

times, propagation delays, and output

drives are severely affected.

Advantage:

Disadvantage:

R2 < R1 for the same

level of protection.

Impact on ac and dc

characteristics is minimize

More board area, higher i

Note: These networks are useful for protecting the following

A

B

digital inputs and outputs

analog inputs and outputs

C

D

3state outputs

bidirectional (I/O) ports

PROPAGATION DELAY AND RISE TIME

vs. SERIES RESISTANCE

R t

C kwhere:

R

t

C

k

k

= the maximum allowable series resistance in ohms

= the maximum tolerable propagation delay or rise time in seconds

= the board capacitance plus the driven devices

= input capacitance in farads= 0.7 for propagation delay calculations

= 2.3 for rise time calculations


28/449

Figure 3. Typical Manufacturing Work Station

RESISTOR =1 MEGAOHM

1

2

3

4

5

NOTES: 1. 1/16 inch conductive sheet

top work area.

2. Ground strap.

3. Wrist strap in contact with s

4. Static neutralizer. (Ionized

work.) Primarily for use in

grounding is impractical.

5. Room humidifier. Primarily

the relative humidity is les

building heating and coolin

the air causing the relativ

buildings to be less than ou

POWER SUPPLIES

CMOS devices have low power requirements and theability to operate over a wide range of supply voltages.These two characteristics allow CMOS designs to beimplemented using inexpensive, conventional powersupplies, instead of switching power supplies and powersupplies with cooling fans. In addition, batteries may be usedas either a primary power source or for emergency backup.

The absolutemaximum power supply voltage for 14000Series Metalgate CMOS is 18.0 Vdc. Figure 4 offers someinsight as to how this specification was derived. In thefigure, VSis the maximum power supply voltage and ISisthe sustaining current of the latchup mode. The value of VSwas chosen so that the secondary breakdown effect may beavoided.

In an ideal system design, a power supply should bedesigned to deliver only enough current to insure properoperation of all devices. The obvious benefit of this typedesign is cost savings; an added benefit is protection against

the possibility of latchup related protection can be provided by the powvoltage regulator.

CMOS devices can be used with bat

systems. A few precautions should bebatteryoperated systems:1. The recommended power supp

observed. For battery backup syin Figure 5, the battery voltagVolts (3 Volts from the minvoltage and 0.7 Volts to accouacross the series diode).

2. Inputs that might go above the b

should either use a series resicurrent to less than 10 mA or usMC14050B hightolow volta

3. Outputs that are subject to voltor below VSSshould be protecteto limit the current to less tclamping diodes.

IDD

LATCH

UP MODE


29/449

Figure 5. Battery Backup Interface

POWER SUPPLY

LINE POWER ONLY

SYSTEM

CMOS

SYSTEM

MC14049UB

MC14050B

BATTERY BACKUP

SYSTEM

MC14049UB

MC14050B

BATT

R

CMOS

SYSTEM

INPUTS

All inputs, while in the recommended operating range(VSS< Vin< VDD) can be modeled as shown in Figure 6. Forinput voltages in this range, diodes D1 and D2 are modeledas resistors, representing the reverse bias impedance of the

diodes. The maximum input current is worst case, 1 A,when the inputs are at VDDor VSS, and VDD= 15.0 V. Thismodel does not apply to inputs with pullup or pulldownresistors.

Figure 6. Input Model for VSS Vin VDD

VDD

R1

7.5 pF

R1 = R2 = HIGH Z

R2

When left opencircuited, the inputs may selfbias at ornear the typical switchpoint, where both the Pchannel andNchannel transistors are conducting, causing excessivecurrent drain Due to the high gain of the inverters (see

Figure 7. Typical Transfer C

for Buffered Devic

5.0

4.0

3.0

2.0

1.0

00 1.0 2.0 3.0 4.0

Vin, INPUT VOLTAG

Vout,

OUTPUTVO

LTAGE(V)

VDD= 5.0 Vd

SINGLE INPUT N

MULTIPLE INPUT

SINGLE INP

MULTIPLE

For these reasons, all unused inputeither to VDDor VSS. For applicationedge connectors, a 100 kilohm resisused, as well as a series resistor forcurrent limiting (Figure 8). The 100 ki

eliminate any static charges that mprinted circuit board. See Figure protection arrangements.

RSFROM

EDGE

CONNECTOR


30/449

For input voltages outside of the recommended operatingrange, the CMOS input is modeled as in Figure 9. Theresistordiode protection network allows the user greaterfreedom when designing a worst case system. The deviceinputs are guaranteed to withstand voltages from VSS 0.5

V to VDD+ 0.5 V and a maximum current of 10 mA. Withthe above input ratings, most designs will require no specialterminations or design considerations.

Figure 9. Input Model for Vin> VDDor Vin< VSS

1.5 k

D2 7.5 pF

D1

Other specifications that should be noted are themaximum input rise and fall times. Figure 10 shows the

oscillations that may result from exceeding the 15 smaximum rise and fall time at VDD= 5.0 V, 5 s at 10 V, or4 s at 15 V. As the voltage passes through the switchingthreshold region with a slow rise time, any noise that is onthe input is amplified, and passed through to the output,causing oscillations. The oscillation may have a low enoughfrequency to cause succeeding stages to switch, givingunexpected results. If input rise or fall times are expected toexceed 15 s at 5.0 V, 5 s at 10 V, or 4 s at 15 V,

Schmitttrigger devices such as the MC14093B,MC14584B, MC14106B, HC14, or HC132 arerecommended for squaringup these slow transitions.

Vin

Vout

VDD

VSS

VOH

VOL

lout= 0A. The output drives for all buare such that 1 LSTTL load can be temperature range.

CMOS outputs are limited to extvoltages of VSS 0.5 V Vout

voltages are forced outside of this rangrectifier (SCR) formed by parasititriggered, causing the device to information on this, see the explanatioin this section.

The maximum rated output curren10 mA. The output shortcircuit curtypically exceed these limits. Care exceed the maximum ratings found o

For applications that require drivingwhere fast propagation delays are power MOSFETs), two or more outpmay be externally paralleled.

CMOS LATCH UP

Latch up will not be a problem fordesigner should be aware of it, what prevent it.

Figure 11 shows the crosssectioinverter and Figure 12 shows the parThe circuit formed by the parasitic tris the basic configuration of a silicon SCR. In the latch up condition, transturned ON, each providing the base cuother to remain in saturation, thereby the ON state. Unlike a conventional Sis turned ON by applying a voltage ttransistor, the parasitic SCR is turnvoltage to the emitter of either transithat trigger the SCR are the same poiTherefore, to latch up the CMOS devmust be greater than VDD+ 0.5 V orand have sufficient current to trigger tmechanism is similar for the inputs.

Once a CMOS device is latched upis not limited, the device will be destrsuch occurrences are listed below:

1. Insure that inputs and outpumaximum rated values, as follo0.5 V Vinor Vout VDD+VSS) |Iinor Iout| 10 mA (unleon the data sheet)


31/449

series resistors may be used in plugin boardapplications).

4. Voltage regulating or filtering should be used in boarddesign and layout to insure that powersupply linesare free of excessive noise.

5. Limit the available power sdevices that are subject to latccan be accomplished with the pnetwork or with a currentlimi

Figure 11. CMOS Wafer Cross Section

VDD VDD

PCHANNEL NCHANNEL

INPUT

OUTPUTPCHANNEL

OUTPUT

NCHANNEL

OUTPUT

VSS

FIELD OXIDE FIELD OXIDE FIELN+ P+ P+ N+ N+ P+

P WELLN SUBSTRATE

Figure 12. Latch Up Circuit Schematic

VSS

VSS

NCHANNEL OUTPUTNSUBSTRATE RESISTAN

Q1

N+

P

PCHANPWELL RESISTANCE

N

P+

P

N+ N

P+Q2


32/449

CH

CMOS Logic Da


33/449

MC14001B, MC14011B, MC14023B,MC14025B, MC14071B, MC14073B,MC14081B, MC14082B

The B Series logic gates are constructed with P and N channelenhancement mode devices in a single monolithic structure(Complementary MOS). Their primary use is where low power

dissipation and/or high noise immunity is desired. Supply Voltage Range = 3.0 Vdc to 18 Vdc All Outputs Buffered Capable of Driving Two Lowpower TTL Loads or One Lowpower

Schottky TTL Load Over the Rated Temperature Range. Double Diode Protection on All Inputs Except: Triple Diode

Protection on MC14011B and MC14081B PinforPin Replacements for Corresponding CD4000 Series B

Suffix Devices

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range 0.5 to +18.0 V

Vin, Vout Input or Output Voltage Range

(DC or Transient)

0.5 to VDD+ 0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin

10 mA

PD Power Dissipation,

per Package (Note 2.)

500 mW

TA Ambient Temperature Range 55 to +125 C

Tstg Storage Temperature Range 65 to +150 C

TL Lead Temperature

(8Second Soldering)

260 C

1. Maximum Ratings are those values beyond which damage to the device

may occur.2. Temperature Derating:Plastic P and D/DW Packages: 7.0 mW/ C From 65 C To 125 C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

highimpedance circuit. For proper operation, Vinand Voutshould be constrained

http://onsem

Device D

DEVICE INFO

MC14001B Quad 2In

MC14011B Quad 2In

MC14023B Triple 3In

MC14025B Triple 3 In

PDIP14

P SUFFI

CASE 64

SOIC1

D SUFFI

CASE 75

TSSOP

DT SUFF

CASE 948

XX = Specific

A = Assemb

WL or L = Wafer L

YY or Y = Year

WW or W = Work W

SOEIAJ

F SUFFI

CASE 96

MC14001B Series


34/449

LOGIC DIAGRAMS

1

2

5

6

8

9

1213

3

4

10

11

1

2

5

6

8

9

1213

3

4

10

11

1

2

5

6

8

9

1213

3

4

10

11

1

2

5

6

8

9

1213

2INPUT

12 9

3INPUT

8

34 65

1112 1013

12 98

34 65

1112 1013

12 98

34 65

1112 1013

345

2

101112

9

VDD= PIN 14

VSS= PIN 7

FOR ALL DEVICES

NOR

MC14001B

Quad 2Input NOR Gate

MC14025B

Triple 3Input NOR Gate

MC14023B

Triple 3Input NAND Gate

NAND

MC14011B

Quad 2Input NAND Gate

OR

MC14071B

Quad 2Input OR Gate Quad

MC14073B

Triple 3Input AND Gate Dua

PIN ASSIGNMENTS

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

IN 1C

IN 2C

IN 3C

VDD

IN 3A

OUTA

IN 2B

IN 1B

IN 2A

IN 1A

VSS

OUTB

IN 3B

IN 2B

IN 1B

IN 2A

IN 1A

VSS

OUTB

IN 3B

141 VIN 1 141 VIN 1 141 VIN 1 OUT

MC14023BTriple 3Input NAND GateMC14001BQuad 2Input NOR Gate MC14011BQuad 2Input NAND Gate

Dual 4

MC14081B

Quad 2Input AND Gate

Triple

MC14071B

Quad 2Input OR GateMC14073B

Triple 3Input AND Gate

MC14001B Series


35/449

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD

55 C

25 C

Characteristic

Symbol

Vdc

Min

Max

Min

Typ (3.)

Max

M

Output Voltage 0 Level

Vin= VDDor 0

VOL

5.0

1015

0.05

0.050.05

0

00

0.05

0.050.05

1 Level

Vin= 0 or VDD

VOH

5.0

10

15

4.95

9.95

14.95

4.95

9.95

14.95

5.0

10

15

4.

9.

14

Input Voltage 0 Level

(VO= 4.5 or 0.5 Vdc)

(VO= 9.0 or 1.0 Vdc)

(VO= 13.5 or 1.5 Vdc)

VIL

5.0

10

15

1.5

3.0

4.0

2.25

4.50

6.75

1.5

3.0

4.0

1 Level(VO= 0.5 or 4.5 Vdc)

(VO= 1.0 or 9.0 Vdc)

(VO= 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

3.5

7.0

11

2.75

5.50

8.25

3

7

1

Output Drive Current


(VOH= 4.6 Vdc)

(VOH= 9.5 Vdc)

(VOH= 13.5 Vdc)

IOH

5.0

5.0

10

15

3.0

0.64

1.6

4.2

2.4

0.51

1.3

3.4

4.2

0.88

2.25

8.8

0

(VOL= 0.4 Vdc) Sink

(VOL= 0.5 Vdc)(VOL= 1.5 Vdc)

IOL

5.0

1015

0.64

1.64.2

0.51

1.33.4

0.88

2.258.8

0.

02

Input Current

Iin

15

0.1

0.00001

0.1

Input Capacitance

(Vin= 0)

Cin

5.0

7.5

Quiescent Current

(Per Package)

IDD

5.0

10

15

0.25

0.5

1.0

0.0005

0.0010

0.0015

0.25

0.5

1.0

Total Supply Current (4.)(5.)

(Dynamic plus Quiescent,

Per Gate, CL= 50 pF)

IT

5.0

10

15

IT= (0.3 A/kHz) f + I

DD/N

IT= (0.6 A/kHz) f + IDD/N


3. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential pe4. The formulas given are for the typical characteristics only at 25 C.5. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL 50) Vfk

where: ITis in A (per package), CLin pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001 x the nu

per package.

MC14001B Series


36/449

BSERIES GATE SWITCHING TIMES

SWITCHING CHARACTERISTICS (6.)(CL= 50 pF, TA= 25 C)

Characteristic

Symbol

VDDVdc

Min

Typ (7.)

Output Rise Time, All BSeries Gates

tTLH= (1.35 ns/pF) CL+ 33 ns


tTLH= (0.40 ns/PF) CL+ 20 ns

tTLH

5.0

10

15

100

50

40

Output Fall Time, All BSeries Gates

tTHL= (1.35 ns/pF) CL+ 33 ns



tTHL

5.0

10

15

100

50

40

Propagation Delay Time

MC14001B, MC14011B only

tPLH, tPHL= (0.90 ns/pF) CL+ 80 ns



All Other 2, 3, and 4 Input Gates




8Input Gates (MC14068B, MC14078B)


tPLH

, tPHL

= (0.36 ns/pF) CL+ 62 ns


tPLH, tPHL

5.0

10

15

5.0

10

15

5.0

10

15

125

50

40

160

65

50

200

80

60

6. The formulas given are for the typical characteristics only at 25 C.7. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential pe

VDD14

CL

VSS7

PULSEGENERATOR

INPUT

OUTPUT

90%50%

10%

10%50%

90%

20 ns 2

tPHL

tTHL

INPUT

OUTPUT

INVERTING

*All unused inputs of AND, NAND gates must be connected to VDD.

All unused inputs of OR, NOR gates must be connected to VSS.

90%50%10%

OUTPUT

NONINVERTING

tTLH

tPLH

*

Figure 1. Switching Time Test Circuit and Waveforms

MC14001B Series

CIRCUIT SCHEMATIC


37/449

CIRCUIT SCHEMATICNOR, OR GATES

14

*

7VSS

3, 4, 10, 11

VDD

VSS

VDD

*Inverter omitted in MC14001B

1, 6, 8, 13

2, 5, 9, 12

1, 3, 11

2, 4, 12

VSS

VDD

VSS

VDD

8, 5, 13

MC14001B, MC14071B

One of Four Gates Shown

MC14025B

One of Three Gates

*Inverter omitted

CIRCUIT SCHEMATICNAND, AND GATES

*

*Inverter omitted in

14

*

9, 6, 10

VDD2, 5, 9, 12

1, 6, 8, 13

2, 4, 12

1, 3, 11

VDD

VDD

VSS

8, 5, 13

MC14011B, MC14

One of Four Gates

MC14023B, MC14073B

One of Three Gates Shown

MC14001B Series

TYPICAL B SERIES GATE CHARACTERISTICS


38/449

TYPICAL BSERIES GATE CHARACTERISTICS

NCHANNEL DRAIN CURRENT (SINK) PCHANNEL DRAIN CURR

Figure 2. VGS= 5.0 Vdc Figure 3. VGS=

1.0

3.0

5.0

4.0

2.0

01.0 3.0 5.04.02.00

VDS, DRAINTOSOURCE VOLTAGE (Vdc)

1.0

00

TA= 55C

Figure 4. VGS= 10 Vdc Figure 5. VGS=

16

14

12

10

8.0

6.0

4.0

2.0

05.03.01.0 108.06.04.02.00

00

40C

+ 25C+ 85C

+ 125C

1.0 3 2.0

VDS, DRAINTOSOURCE V

TA= 55C

40C

+ 25C+ 85C

+ 125C

VDS, DRAINTOSOURCE VOLTAGE (Vdc) VDS, DRAINTOSOURCE V

18

20

9.07.0 5.0 3.0 1.0 6 4.0 2.0

40

35

30

25

20

15

10

5.0

45

50

TA= 55C

40C

+ 25C+ 85C

80 70

60

50

40

90

100

4035

30

25

20

45

50

TA

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10

I,

D

DRAINCURRENT(mA)

I,

D

DRAINCURRENT(mA)

I,

D

DRAINCURRENT(mA)

I,

D

DRAINCURRENT(mA)

AINCURRENT(mA)

AINCURRENT(mA)

+ 125C

MC14001B Series

TYPICAL B SERIES GATE CHARACTERISTICS (contd)


39/449

TYPICAL BSERIES GATE CHARACTERISTICS (cont d)

VOLTAGE TRANSFER CHARACTERISTICS

Figure 8. VDD= 5.0 Vdc Figure 9. VDD=

1.0

3.0

5.0

4.0

2.0

01.0 3.0 5.04.02.00

00

Vin, INPUT VOLTAGE (Vdc)

SINGLE INPUT NAND, AND

MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR

MULTIPLE INPUT NAND, AND

SINGLE INP

MULTIPLE I

SINGLE

MULTIPL

2.0

6.0

10

8.0

4.0

2.0 6.0 8.04.0

Vin, INPUT VOLTAG

V

,

out

OUTPUTVOLTAGE(Vdc)

V

,

out

OUTPUTVOLTAGE(Vdc)

Figure 10. VDD= 15 Vdc

00

SINGLE INPUT NAND, AND

MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR

MULTIPLE INPUT NAND, AND

2.0

6.0

10

8.0

4.0

2.0 6.0 108.04.0


12

14

16

V

,

out

OUTPUTVOLTAGE(Vd

c)

DC NOISE MARG

The DC noise margin is defined as t

from an ideal 1 or 0 input level woutput state change(s). The typical values of the input values VILand Vbe at a fixed voltage VO are givCharacteristics table. VILand VIHarein Figure 11.

Guaranteed minimum noise margin0 levels =

1.0 V with a 5.0 V supply



Vout

VO

VO

VDD

VDD Vout

VO

VO

VDD

VDD

MC14001B Series

ORDERING & SHIPPING INFORMATION: ORDERING & SHIPPING INFORMA


40/449

ORDERING & SHIPPING INFORMATION:

Device Package Shipping

MC14001BCP PDIP14 2000 Units per Box

MC14001BD SOIC14 2750 Units per Box

MC14001BDR2 SOIC14 2500 Units / Tape & Reel

MC14001BDT TSSOP14 96 Units per Rail

MC14001BDTR2 TSSOP14 96 Units per Rail




MC14011BDT TSSOP14 96 Units per Rail

MC14011BDTEL TSSOP14 2000 Units / Tape & Reel

MC14011BDTR2 TSSOP14 50 Units per Rail







ORDERING & SHIPPING INFORMA

Device Package

MC14071BCP PDIP14

MC14071BD SOIC14

MC14071BDR2 SOIC14 250

MC14071BDT TSSOP14

MC14071BDTR2 TSSOP14

MC14073BCP PDIP14

MC14073BD SOIC14


MC14081BCP PDIP14

MC14081BD SOIC14


MC14081BDT TSSOP14

MC14081BDTR2 TSSOP14 250

MC14082BCP PDIP14

MC14082BD SOIC14


For ordering information on the EIAJ versages, please contact your local ON Semitive.


41/449

The UB Series logic gates are constructed with P and N channelenhancement mode devices in a single monolithic structure(Complementary MOS). Their primary use is where low powerdissipation and/or high noise immunity is desired. The UB set ofCMOS gates are inverting nonbuffered functions.

Supply Voltage Range = 3.0 Vdc to 18 Vdc

Linear and Oscillator Applications Capable of Driving Two Lowpower TTL Loads or One LowpowerSchottky TTL Load Over the Rated Temperature Range

Double Diode Protection on All Inputs PinforPin Replacements for Corresponding CD4000 Series UB

Suffix Devices





(DC or Transient)

0.5 to VDD+ 0.5 V



10 mA

PD

Power Dissipation,


500 mW



TL Lead Temperature

(8Second Soldering)

260 C

1. Maximum Ratings are those values beyond which damage to the devicemay occur.

2. Temperature Derating:

Plastic P and D/DW Packages: 7.0 mW/

C From 65

C To 125

C





to the range VSS (Vinor Vout) VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e g

http://onsem

PDIP14P SUFFI

CASE 64

SOIC1

D SUFFI

CASE 75

XX = Specific

A = Assemb

WL or L = Wafer L

YY or Y = Year

WW or W = Work W

Device Packag

ORDERING INF

MC14001UBCP PDIP1

MC14001UBD SOIC1

MC1400

Quad 2InputMC1401

Quad 2Input

MC14001UB, MC14011UB

LOGIC DIAGRAMS


42/449

MC14001UB

Quad 2Input

NOR Gate

MC14011UB

Quad 2Input

NAND Gate

VDD= PIN 14VSS= PIN 7

FOR ALL DEVICES

13

12

9

8

6

5

21 3

4

10

1113

129

86

521 3

4

10

11

PIN ASSIGNMENTS

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

MC14001UBQuad 2Input NOR Gate

MC14011UBQuad 2Input NAND Gate




43/449

VDD

55 C

25 C

Characteristic

Symbol

Vdc

Min

Max

Min

Typ (3.)

Max

M


Vin

= VDD

or 0

VOL

5.0

10

15

0.05

0.05

0.05

0

0

0

0.05

0.05

0.05

Vin= 0 or VDD 1 Level

VOH

5.0

10

15

4.95

9.95

14.95

4.95

9.95

14.95

5.0

10

15

4

9

14


(VO= 4.5 Vdc)

(VO= 9.0 Vdc)

(VO= 13.5 Vdc)

VIL

5.0

10

15

1.0

2.0

2.5

2.25

4.50

6.75

1.0

2.0

2.5

(VO

= 0.5 Vdc) 1 Level

(VO= 1.0 Vdc)

(VO= 1.5 Vdc)

IIH

5.0

10

15

4.0

8.0

12.5

4.0

8.0

12.5

2.75

5.50

8.25

4

8

1



(VOH= 4.6 Vdc)

(VOH= 9.5 Vdc)

(VOH= 13.5 Vdc)

IOH

5.0

5.0

10

15

1.2

0.25

0.62

1.8

1.0

0.2

0.5

1.5

1.7

0.36

0.9

3.5

0

0

(VOL= 0.4 Vdc) Sink

(VOL= 0.5 Vdc)

(VOL= 1.5 Vdc)

IOL

5.0

10

15

0.64

1.6

4.2

0.51

1.3

3.4

0.88

2.25

8.8

0

0

2

Input Current

Iin

15

0.1

0.00001

0.1

Input Capacitance

(Vin= 0)

Cin

5.0

7.5

Quiescent Current

(Per Package)

IDD

5.0

10

15

0.25

0.5

1.0

0.0005

0.0010

0.0015

0.25

0.5

1.0



Per Gate CL= 50 pF)

IT

5.0

10

15




3. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential pe4. The formulas given are for the typical characteristics only at 25

C.

5. To calculate total supply current at loads other than 50 pF:


where: ITis in H (per package), CLin pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001 x the nu

per package.




44/449

Characteristic

Symbol

VDDVdc

Min

Typ (7.)

Output Rise Time


tTLH= (1.5 ns/pF) CL+ 15 nstTLH= (1.1 ns/pF) CL+ 10 ns

tTLH

5.0

1015

180

9065

Output Fall Time


tTHL= (0.75 ns/pF) CL+ 12.5 ns

tTHL= (0.55 ns/pF) CL+ 9.5 ns

tTHL

5.0

10

15

100

50

40





tPLH, tPHL

5.0

10

15

90

50

40

6. The formulas given are for the typical characteristics only at 25 C.7. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential pe

Figure 1. Switching Time Test Circuit and Waveforms

VDD14

VSS

OUTPUT

CL

INPUT

*

7

PULSEGENERATOR

20 ns

INPUT

OUTPUT

INVERTING

tPHL

90%50%

10%

90%50%

10%

tTHL*All unused inputs of AND, NAND gates must be

connected to VDD.

All unused inputs of OR, NOR gates must be

connected to VSS.


MC14001UB CIRCUIT SCHEMATIC MC14011UB CIRCUIT

(1/4 of Device S


45/449

14 103

VDD

6

5

2

1

VSS

4 7 11

12

13

9

8

(1/4 of Device S

2, 5, 9, 12

1, 6, 8, 13

7 V

14 V

Figure 2. Typical Voltage and

Current Transfer Characteristics

Figure 3. Typical Voltage Transfe

Characteristics versus

Temperature

Vout,

OUTPUTVOLTA

GE(Vdc)

16

14

12

10

8.0

6.0

4.0

2.0

00 2.0 4.0 6.0 8.0 10 12 14 16

8.0

6.0

4.0

2.0

0

ID,

DRAINCURRENT

(mAdc)


Vout,

OUTPUTVOLTA

GE(Vdc)

16

14

12

10

8.0

6.0

4.0

2.0

00 2.0 4.0 6.0 8.0 10 12 14 16


AINCURRENT(mAdc

)

6.0

4.0

2.0

0

AINCURRENT(mAdc

)

4.0

6.0

8.0

10

TA= 55C

TA= +25C

TA= +125C

a

b

c

VGS= 5.0 Vdcb

c

a

c

a

b

c a

b

c

VGS= 1

15 Vdc

VDD= 15 Vdc

TA= +125CTA= 55C

ab

a

b

TA= +25C

Unused input

connected to

VSS.

One input only

Both inputs10 Vdc

5.0 Vdc

b a

b a

b a

15 Vdc

10 Vdc

Unused input

connected to

VSS.

VDD= 15 Vdc

ba

a b

a b

5.0 Vdc

10 Vdc


46/449

The MC14007UB multipurpose device consists of threeNchannel and three Pchannel enhancement mode devices packagedto provide access to each device. These versatile parts are useful ininverter circuits, pulseshapers, linear amplifiers, high inputimpedance amplifiers, threshold detectors, transmission gating, andfunctional gating.

Diode Protection on All Inputs

Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Lowpower TTL Loads or One Lowpower

Schottky TTL Load Over the Rated Temperature Range PinforPin Replacement for CD4007A or CD4007UB This device has 2 outputs without ESD Protection. Antistatic

precautions must be taken.





(DC or Transient)

0.5 to VDD+ 0.5 V



10 mA



500 mW



TL Lead Temperature

(8Second Soldering)

260 C


3. Temperature Derating:Plastic P and D/DW Packages: 7.0 mW/ C From 65 C To 125 C





t th V (V V ) V

http://onsem

A = Assemb

WL or L = Wafer L

YY or Y = Year

WW or W = Work W

Device Packag

ORDERING INF

MC14007UBCP PDIP

MC14007UBD SOIC

MC14007UBDR2 SOIC

PDIP14

P SUFFIX

CASE 64

SOIC14

D SUFFIX

CASE 751

TSSOP1

DT SUFF

CASE 948

SOEIAJ1

F SUFFIX

CASE 96

MC14007UB

PIN ASSIGNMENT


47/449

A

B

C

INPUT

INPUT

A

B

C

12

1

3

5

9

2

4

11

10

14

VDD

6 8

13INPUT OUTPUT CONDITION

11

12

13

14

8

9

105

4

3

2

1

7

6

GATEC

SPC

OUTC

DPA

VDD

DNA

SNC

SNB

GATEB

SPB

DPB

VSS

GATEA

DNB

D = DRAIN

S = SOURCE

SCHEMATIC

14 13 2 1 11

126

7 8 3 4 5 10 9

VDD= PIN 14

VSS= PIN 7

MC14007UB


55 C 25 C


48/449

VDD

55 C

25 C

Characteristic

Symbol

Vdc

Min

Max

Min

Typ (4.)

Max

M


Vin= VDDor 0

VOL

5.0

10

15

0.05

0.05

0.05

0

0

0

0.05

0.05

0.05


VOH

5.0

10

15

4.95

9.95

14.95

4.95

9.95

14.95

5.0

10

15

4.

9.

14


(VO= 4.5 Vdc)

(VO= 9.0 Vdc)

(VO= 13.5 Vdc)

VIL

5.0

10

15

1.0

2.0

2.5

2.25

4.50

6.75

1.0

2.0

2.5

(VO= 0.5 Vdc) 1 Level

(VO= 1.0 Vdc)

(VO= 1.5 Vdc)

VIH

5.0

10

15

4.0

8.0

12.5

4.0

8.0

12.5

2.75

5.50

8.25

4

8

12



(VOH= 4.6 Vdc)

(VOH= 9.5 Vdc)

(VOH= 13.5 Vdc)

IOH

5.0

5.0

10

15

3.0

0.64

1.6

4.2

2.4

0.51

1.3

3.4

5.0

1.0

2.5

10

0

(VOL= 0.4 Vdc) Sink

(VOL= 0.5 Vdc)

(VOL= 1.5 Vdc)

IOL

5.0

10

15

0.64

1.6

4.2

0.51

1.3

3.4

1.0

2.5

10

0.

0

2

Input Current

Iin

15

0.1

0.00001

0.1

Input Capacitance

(Vin= 0)

Cin

5.0

7.5

Quiescent Current

(Per Package)

IDD

5.0

10

15

0.25

0.5

1.0

0.0005

0.0010

0.0015

0.25

0.5

1.0



Per Gate) (CL= 50 pF)

IT

5.0

10

15

IT= (0.7 A/kHz) f + IDD/6



4. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential pe5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:


where: ITis in A (per package), CLin pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.003.

MC14007UB


V


49/449

Characteristic

Symbol

VDDVdc

Min

Typ (8.)

Output Rise Time


tTLH= (0.5 ns/pF) CL+ 20 nstTLH= (0.4 ns/pF) CL+ 15 ns

tTLH

5.0

1015

90

4535

Output Fall Time




tTHL

5.0

10

15

75

40

30

TurnOff Delay Time

tPLH= (1.5 ns/pF) CL+ 35 ns

tPLH= (0.2 ns/pF) CL+ 20 ns

tPLH= (0.15 ns/pF) CL+ 17.5 ns

tPLH

5.0

10

15

60

30

25

TurnOn Delay Time

tPHL= (1.0 ns/pF) CL+ 10 ns



tPHL

5.0

10

15

60

30

25

7. The formulas given are for the typical characteristics only. Switching specifications are for device connected as a8. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential pe

VDD= VGS VDD= VGS

1414VDS= VOH VDD

VSSVSS7

7

IOHIO

IOH,

DRAINCU

RRENT(mAdc)

IOL,

DRAINCU

RRENT(mAdc)

0

4.0

8.0

12

16

20

16

12

8.0

4.0

TA= 55C

TA= +25C

TA= +125C

a

b

c

VGS= 5.0 Vdc b

c

a

10 Vdc 15 Vdc

c

bc

b

a

a

ab

c

a

b c

ab

c5.0

VGS= 15 Vdc

10 Vdc

All unused inputs connected to ground. All unused inputs connect

MC14007UB

VDD20 ns


50/449

Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms

PULSE

GENERATOR

500F0.01 F

CERAMIC

14

CL

Vout

VSS7

Vin

ID Vin

Vout

90%50%10%

90%50%10%

tTHL t

tPHL

APPLICATIONS

The MC14007UB dual pair plus inverter, which hasaccess to all its elements offers a number of unique circuitapplications. Figures 1, 5, and 6 are a few examples of thedevice flexibility.

Figure 5. 3State Buffer

+ VDD

DISABLE 3

INPUT 10

DISABLE 6

12 OUTPUT

11

1

2

9

8

7

INPUT DISABLE OUTPUT

1

0

X

0

0

1

0

1

OPEN

X = Dont Care

Figure 6. AOI Functions Usi

VDD

14

13

11

10

3

6

B

C

A

9

5

4

8

7

O

Substrates of Pchannel devices intern

Substrates of Nchannel devices intern

12


51/449

The MC14008B 4bit full adder is constructed with MOSPchannel and Nchannel enhancement mode devices in a singlemonolithic structure. This device consists of four full adders with fastinternal lookahead carry output. It is useful in binary addition andother arithmetic applications. The fast parallel carry output bit allowshighspeed operation when used with other adders in a system.

LookAhead Carry Output Diode Protection on All Inputs

All Outputs Buffered Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Lowpower TTL Loads or One Lowpower

Schottky TTL Load Over the Rated Temperature Range PinforPin Replacement for CD4008B

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)Symbol Parameter Value Unit



(DC or Transient)

0.5 to VDD+ 0.5 V



10 mA



500 mW



TL Lead Temperature

(8Second Soldering)

260 C


3. Temperature Derating:Plastic P and D/DW Packages: 7.0 mW/

C From 65

C To 125

C





to the range VSS (Vinor Vout) VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14008BCP PDIP

MC14008BDR2 SOIC

MC14008BF SOEIAJ

1 For ordering information

PDIP16

P SUFFI

CASE 64

SOIC1

D SUFFI

CASE 751

SOEIAJ

F SUFFI

CASE 96

MC14008B

TRUTH TABLE

(One Stage)


52/449

BLOCK DIAGRAM

HIGHSPEED

PARALLEL CARRY14 Cout

13 S4

12 S3

11 S2

B4 15

A4 1

B3 2

A3 3

B2 4

A2 5

ADDER

4

ADDER

3

ADDER

2

C4

C3

C2

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

S3

S4

Cout

B4

VDD

Cin

S1

S2

B2

A3

B3

A4

VSS

A1

B1

A2

PIN ASSIGNMENT

Cin B A Cout S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 10 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

MC14008B


VDD

55 C

25 C


53/449

VDD

Characteristic

Symbol

Vdc

Min

Max

Min

Typ (4.)

Max

M


Vin= VDDor 0

VOL

5.0

10

15

0.05

0.05

0.05

0

0

0

0.05

0.05

0.05


VOH

5.0

10

15

4.95

9.95

14.95

4.95

9.95

14.95

5.0

10

15

4.9

9.9

14


(VO= 4.5 or 0.5 Vdc)

(VO= 9.0 or 1.0 Vdc)

(VO= 13.5 or 1.5 Vdc)

VIL

5.0

10

15

1.5

3.0

4.0

2.25

4.50

6.75

1.5

3.0

4.0

(VO= 0.5 or 4.5 Vdc) 1 Level

(VO= 1.0 or 9.0 Vdc)(VO= 1.5 or 13.5 Vdc)

VIH

5.0

1015

3.5

7.011

3.5

7.011

2.75

5.508.25

3

71



(VOH= 4.6 Vdc)

(VOH= 9.5 Vdc)

(VOH= 13.5 Vdc)

IOH

5.0

5.0

10

15

3.0

0.64

1.6

4.2

2.4

0.51

1.3

3.4

4.2

0.88

2.25

8.8

1

0

0

2

(VOL= 0.4 Vdc) Sink

(VOL= 0.5 Vdc)

(VOL= 1.5 Vdc)

IOL

5.0

10

15

0.64

1.6

4.2

0.51

1.3

3.4

0.88

2.25

8.8

0.3

0

2

Input Current

Iin

15

0.1

0.00001

0.1

Input Capacitance

(Vin= 0)

Cin

5.0

7.5

Quiescent Current

(Per Package)

IDD

5.0

10

15

5.0

10

20

0.005

0.010

0.015

5.0

10

20



Per Package)(CL= 50 pF on all outputs, all

buffers switching)

IT

5.0

10

15

IT= (1.7 A/kHz) f + IDDIT= (3.4 A/kHz) f + IDDIT= (5.0 A/kHz) f + IDD

4. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential pe5. The formulas given are for the typical characteristics only at 25

C.

6. To calculate total supply current at loads other than 50 pF:


where: ITis in A (per package), CLin pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.005.

MC14008B


VDDVd

(8 )


54/449

Characteristic

Symbol

Vdc

Min

Typ (8.)

Output Rise and Fall Time

tTLH, tTHL= (1.5 ns/pF) CL+ 25 ns

tTLH, tTHL= (0.75 ns/pF) CL+ 12.5 nstTLH, tTHL= (0.55 ns/pF) CL+ 9.5 ns

tTLH,

tTHL

5.0

1015

100

5040


Sum in to Sum Out




Sum In to Carry Out


tPLH, tPHL= (0.66 ns/pF) CL+ 112 nstPLH, tPHL= (0.5 ns/pF) CL+ 85 ns

Carry In to Sum Out




Carry In to Carry Out

tPLH, tPHL= (1.7 ns/pF)

cmos logic data book

Documents