logic cmos scaling - applied materials

LOGIC CMOS SCALING

IN THE NEXT DECADE & BEYOND

AARON THEAN , Ph.D.

Mar 2014

APPLICATION TECHNOLOGY

TRENDS

3

© IMEC 2014

Sensor / MtM

Networks

Smart Mobile

Devices

Data Centers

& Servers

EMERGING DATA INFRASTRUCTURE

4

© IMEC 2014

1.5EB 2.6EB

+81%

GLOBAL MOBILE DATA FORECAST (CISCO)

• Astounding demand on Data Processing & Exchange

foreseen for the next 5 years and beyond?

15.9EB

6x

5

© IMEC 2014

GLOBAL MOBILE DATA FORECAST (CISCO)

• Continuous demand for devices to support data traffic driven by

growing population & information consumption ?

2014 Global Pop. ~ 7B

2020 Global Pop. ~ 8B

6

© IMEC 2014

PROCESS TECHNOLOGY EXPECTATIONS

Expected Leading CMOS technology

in product

22nm/20nm

28nm

14nm?

20nm?

10nm?

14nm?

• How can advanced CMOS technologies enable increasing

applications?

Mixed-Signal RF, Low-Cost

CMOS (Mixed-Tech)

7

© IMEC 2014

Sensor / MtM

Networks

Smart Mobile

Devices

Data Centers

& Servers

EMERGING DATA INFRASTRUCTURE

8

© IMEC 2014

Sensor / MtM

Networks

Smart Mobile

Devices

Heat

• Performance-centric

• Heat-Dissipation Limited

• User-Experience centric • Battery & Form-Factor

constraints

• Perf-Power Balanced Battery

• Ubiquitous Deployment • Ultra-Low Power

• Ambient Energy Sources?

• Low Cost

SYSTEM-DEVICE-PROCESS SPECIALIZATIONS

Data Centers

& Servers

9

© IMEC 2014

Sensor / MtM

Networks

Smart Mobile

Devices

Data Centers

& Servers

SYSTEM-DEVICE-PROCESS SPECIALIZATIONS

10

© IMEC 2014

PROCESS TECHNOLOGY

TRENDS

11

© IMEC 2014

1 µm 0.8 µm 0.5 µm 0.35 µm 250 180 130 90 65 45 32 22 14 10 7 5

INFLECTIONS: DISRUPTIONS OR ENABLERS?

Copper Interconnect Shallow-Trench Isolation

Embedded SiGe SD pFET

Trench contact + Silicide last

1st Gen RMG High-k

Gate-First MGHK &

SiGe channel 2nd Gen RMG High-k

Local interconnect

FinFET

LELE Metal Interconnect

Ultra-Thin SOI

Spacer-Defined Multiple Patterning

R&D in

Progress

BOTH: THEY ARE INNOVATIONS

Semiconductor Industry Technology nodes

INNOVATION-TO-PRODUCT R&D CYCLES

45nm

2001 2003 2005 2007 1999

32nm/28nm

22nm/20nm

2009 2011

14nm DEV. RESEARCH PROD



1990-1995

High-k Metal Gate Proposed

1998-2000 FinFET Proposed & Demo’d

•High-k Metal Gate in products

14nm/16nm 14nm DEV. RESEARCH PROD

•FinFET/Trigate in products

2013

• Approx. 10 years or more to bring some new game-changing

processes to product ... Research needs to start early.

10nm

7 nm

5 nm

2014 2016 2018 2020 2012

3 nm

2022 2024

• IMEC: Shared-Resources for Precompetitive (& Early) R&D



N+1 FinFET platform

- Power/performance

- Area (193i vs EUV)

- Cost



IMEC

IMEC

IMEC

N+3: device, circuit & physical

design exploration

N+2: process modules/ feature

screening

N+4: New materials, Beyond-

CMOS device concepts, &

System implications

IMEC: PROCESS R&D PIPELINE

14

© IMEC 2014

1 µm 0.8 µm 0.5 µm 0.35 µm 250 180 130 90 65 45 32 22 14 10 7 5

imec founded

What ’s next ?

SOI

FinFET

Bulk FinFET

FUSI MG

HKMG RMG-HK

SiGe Epi rSi Epi

Ge

MOSFET

GaAs on Ge

Si Epi GAA-SOI

PD/FD-SOI TFET

SiGe pFET

SiGe channel

Buried Spacer-defined Fins

Vertical SiGe FET

today

IMEC: INNOVATIVE PROCESS OPTIONS


15

© IMEC 2014

WHAT’S NEXT?

• Logic Devices R&D

• Extending Si

• Beyond Si

• Managing Variability

• Beyond CMOS

• Power, Density, Cost Scalings

• The challenges of the transistor

• Conclusion

16

© IMEC 2014

POWER, DENSITY, & COST SCALINGS “THE CHALLENGES OF THE TRANSISTOR”

17

© IMEC 2014

POWER CRISIS: THE NEED FOR VDD SCALING

Po

wer

(W/C

hip

) S

up

ply

Vo

ltage

,Vd

d (V)

Year

0.5

0.7

Mobile mProc:

Power-source limited

• Higher-Performance & Mobile Processors are power limited

22/20nm 32/28nm

45nm

130nm 90/65nm

CMOS Technologies

• Vdd scaling slowing – What are the process limiters?

14/10nm

5/7nm

?

• How can we overcome them for post-14nm CMOS technologies?

High-Perf mProc:

Thermal Limited

(Adapted from various sources

Includes T.Masuhara, IEEE-SSCM 2013)

18

© IMEC 2014

LIMITERS OF VDD SCALING:

THE ROLE OF LOGIC TRANSISTORS

• Circuit performance loss & variability limits Vdd scaling

• Process & Transistor capability play critical roles

Rin

g O

scilla

tor

Dela

y (

s)

Vdd (V) 1.1 1.0 0.9 0.8 0.7

High Vt

LowVt L

og

(Id

s)

Ioff

High Vt

Vgs (V) 0 Vdd

Low Vt

1. Enhance Drive: High Mobility, Low Raccess Ceff

2. Improve

Electrostatics Sub-Vt swing & DIBL

Rapid performance loss

at low Voltage

Increased variability at

low Voltage

3. Reduce process &

material variations Random & Systematic

19

© IMEC 2014

High-Mobility Materials FinFET Stress Simulations

0

20

40

60

80

100

120

DR14

DR10

DR7

Mo

bilit

y in

cre

ase (

%)

CE

SL TiN

W g

ate

W c

on

tactS

/D s

tre

ss

TO

TA

L

N10

N7

N5

S/D Stressor

Strongest

Looking at scaling

10nm 5nm features sizes

Reducing benefit if

Lg scaling slows

MOBILITY ENHANCEMENT:

STRESSOR VS. ALTERNATE CHANNEL

Ge n/p FETs:

2-6x gains III-V :

10x gains

Narrow Band-

Gap limited

• Different Means = Different Trade-Offs

Dynamic Power

N20 Planar

Vdd=0.9V

N14

Vdd=0.9V

N10 Si FinFET

Vdd=0.8V

N7 Si FinFET

Vdd = 0.7V

N7 IIIV/Ge

Vdd = 0.7V

17%

35%

29%

25%

Leakage Power

N7 IIIV/Ge

Vdd = 0.7V

N7 Si FinFET

Vdd = 0.7V

N10 Si FinFET

Vdd=0.8V

29% 25% 30%

45%

POWER-PERFORMANCE BENCHMARK:

STRESSOR VS. ALTERNATE CHANNEL

Alt. channel offers more

performance – but scalability

needs to be assessed.

Performance gains from

FinFET wrt. planar

Si channel fin can scale to

maximize performance –

Limited by parasitics &

process capability.

• Value in assessing Si & Alternate Channel FinFET scalability

21

© IMEC 2014

N10 M1 DESIGN STYLES AND PATTERNING OPTIONS

2D

Targ

et

layer

• Restricted, 1D; 1.5D Vs unrestricted, 2D designs

• Complex 2D shapes (requiring stitching) are gradually simplified to a fully

unidirectional design style with 1D shapes only to enable scaling

• 1.5/1D have better TDDB performance due to the self-alignment

• 10-15% area penalty is inevitable due to the enforced regularity

48nm pitch

Unrestricted 2D

193 LE3 or EUV

48-45nm pitch

Simplified/Restricted 2D

SADP + block (193 / EUV)

40-45nm pitch

Restricted 1D

SADP + block (193LE2 / EUV)

SADP core

1.5D

block block (LE2)

1D

SADP core

IMEC, B. Vandewalle (SPIE 2014)

Fully-depleted

Channel for Improved

Electrostatics

Multi-gate FETs Ultra-Thin

SOI

Band-Engineered

Channel for

Enhanced Transport

High-Mobility

Channels

Gate-All-

Around,

Nanowires/

Tunnel FETs

(SiGe, Ge IIIV)

Novel Materials/

New Transport/

Extreme

Electrostatics

2D Materials

(Bi-layer

Graphene)

Quantum/

Spin Devices

• Material & Device Architecture Innovations: Enablers of continual scaling

Vdd 1.0-1.1V 0.9-1.0V 0.8-0.9V 0.7-0.8V 0.6-0.7V 0.5-0.6V < 0.5V

Strain &

Advanced Gate Stack

Engineering

SD/stressors Metal Gate

+High-k

MGHigh-k

Si substrate

MGHigh-k

Si substrate

45nm

32/28nm

22/20nm

14nm

10nm

7nm

5nm

Tech Node ...

• Feature Dimension & Voltage Scaling are concurrent drivers

IMEC LOGIC DEVICES R&D ACTIVITIES

23

© IMEC 2014

LOGIC DEVICES R&D

ENABLING PROCESS SPECIALIZATIONS

Fully-depleted


Electrostatics

Multi-gate FETs

Band-Engineered

Channel for

Enhanced Transport

High-Mobility

Channels

(SiGe, Ge IIIV)

Novel Materials/

New Transport/

Extreme

Electrostatics

2D Materials

(Bi-layer

Graphene)

Quantum/

Spin Devices

Vdd 1.0-1.1V 0.9-1.0V 0.8-0.9V 0.7-0.8V 0.6-0.7V 0.5-0.6V < 0.5V

Strain &

Advanced Gate Stack

Engineering


+High-k

MGHigh-k

Si substrate

MGHigh-k

Si substrate

45nm

32/28nm

22/20nm

14nm

10nm

7nm

5nm

Tech Node ...

• Modules to improve Non-planar Si channel performance


• Enhancing &

Extending Si

FinFET Scaling

EXTENDING SILICON

• Investigate solutions to extend the scaling of FinFETs from 14nm 7nm

Implant damage & Advanced doping

Atom Probe

Tomography

Dense FinFET modules & Process Integration

Performance Elements

(SiGe, Si:P. Si:C)

Replacement

Metal Gate stack

& WF Engineering

62nm pitch

FinFET Variability & Reliability

Device Design, Self-Heating etc.

26

© IMEC 2014

FW

FH

1.0 1.5 2.0 2.5 3.0

Fin Height (FH) / Fin Width (FW)

60

65

70

75

80

85

90

Su

b-t

hre

sho

ld S

win

g (

mV

/dec)

LIMITATIONS OF FINFET ELECTROSTATICS

NEW STRUCTURAL ENHANCEMENTS

N10:

Lg=20nm

FW =7nm

Strong

Electrostatics

C. Auth VLSI2012

(22nm FinFET)

• Simple Si FinFET are hitting limits to continual Lg scaling for N7 and below.

N7:

Lg=14nm

FW =7nm

Poor

Electrostatics

• New FinFET “Structural Enhancements” available to extend scaling

QW

QW Fin

Gate-All-

Around Fin

EXTENDING MULTI-GATE STRUCTURES

Fin 2 wires 3 wires

STI

Fin

30n

m

NW

spacing

5nm

SiO2

0.5nm

HfO2

1.5nm Rounding

radius

2.5nm

Fin

10n

m

10n

m

5n

m

5n

m

5n

m

30n

m

30n

m

•New studies in progress to understand the trade-off between electrostatics,

Resistance & current efficiency

1 wire

25n

m

30n

m

Spacing

5nm

STI STI STI

Decrease Sswing & DIBL

Increase Rseries

Fully-depleted


Electrostatics

Multi-gate FETs

Band-Engineered

Channel for

Enhanced Transport

High-Mobility

Channels

(SiGe, Ge IIIV)

Novel Materials/

New Transport/

Extreme

Electrostatics

2D Materials

(Bi-layer

Graphene)

Quantum/

Spin Devices

• Si-Channel Scaling & Beyond-Si Channel Scaling

Vdd 1.0-1.1V 0.9-1.0V 0.8-0.9V 0.7-0.8V 0.6-0.7V 0.5-0.6V < 0.5V

Strain &

Advanced Gate Stack

Engineering


+High-k

MGHigh-k

Si substrate

MGHigh-k

Si substrate

45nm

32/28nm

22/20nm

14nm

10nm

7nm

5nm

Tech Node ...

• 2 Scaling paths for FinFETs down to 7nm


• “Beyond Si”

•New Materials for FinFETs

& other non-planar FETs

BEYOND SI FINFET:

IIIV/GE HETERO-FIN PROCESS @ IMEC

Epitaxial Defect Trapping &

Replacement Fin Process

Si

Ge

IIIV & Ge Gate stack & Channel Passivation

IIIV-IV Heterogeneous Material

Integration

Device integration

(RMG, SD Epi, Contact)

III-V/Ge FinFET Design

• Heterogeneous integration: Activities spanning new materials, integration ,

Device design. Fundamentals to Engineering. ..Lab to Fab.

ADV. METROLOGY : IN-LINE FAB –TO- LAB-SCALE

1E+15

1E+16

1E+17

1E+18

1E+19

1E+20

10 100 1000 10000

Co

nce

ntr

ati

on

(/c

m3

)

Mobility (cm2/Vs)

Scilab fitted spectrum

InGaAs HEMT

In

P

Ge

Si10 nm

10 nm

Thermal wave probe

Defects in Nanostructures

1 2

3 4

Defect detection &

review (Pat.Wafer) Crystal quality Gate stack

Atom Probe

Tomography

(Atomic) SSRM

QMSA( Nano-scale)

InP InGaAs

Second Harmonic Gen.

SiO2

IG

A/

Ga

As

SiO2

36°

IG

A

/G

a

1E+00

1E+03

1E+06

-40 10 60 110 160

Inte

nsi

ty

(Co

un

ts/s

)

Time (min)

Nano-Trench SIMS

• Adv. materials & structures activities drove new metrology R&D

GE OR SIGE PFET BENCHMARK

imec

sSiGe Planar

(2011)

imec

sGe QW FinFET (STI last)

(Unpublished 2013)

imec

sGe QW FinFET (ART)

(2013 To be published)

IBM

sSiGe on Insulator

VLSI 2013

[IEDM’10 INTEL]

sGe/SiGe (75%)

Planar

TSMC

Ge Bulk FinFET (ART)

(IEDM 2012)

• Significant improvement achieved in strained strained-Ge QW FinFET

TSMC Ge Bulk FinFET (ART)

(IEDM 2013)

III-V NFET BENCHMARK

imec (lab) (Unpublished, 2013)

InGaAs planar

Intel IEDM 2009

InGaAs planar

imec (300mm Fab)

InGaAs FinFET

Kim VLSI 2011

InAs channel

Egard IEDM 2011

InGaAs planar

Egard IEDM 2011

InGaAs planar

Ko, Nature2010

InAs-O-I

Lee, VLSI 2013

InAs channel

• We achieved one of the higher performance InGaAs planar devices (IIIV Lab)

Reported strained-

Si ~1300 mS/mm

InAs channel TSMC IEDM 2013

Fully-depleted


Electrostatics


SOI

Band-Engineered

Channel for

Enhanced Transport

Gate-All-

Around,

Nanowires/

Tunnel FETs

Novel Materials/

New Transport/

Extreme

Electrostatics

2D Materials

(Bi-layer

Graphene)

Quantum/

Spin Devices

• Material & Device Architecture Innovations Enablers of continual scaling

Vdd 1.0-1.1V 0.9-1.0V 0.8-0.9V 0.7-0.8V 0.6-0.7V 0.5-0.6V < 0.5V

Strain &

Advanced Gate Stack

Engineering


+High-k

MGHigh-k

Si substrate

MGHigh-k

Si substrate

45nm

32/28nm

22/20nm

14nm

10nm

7nm

5nm

Tech Node ...



• Beyond FinFETs

• New Electrostatics & Transport

34

© IMEC 2014

FinFET GAA

No Room for

Lateral

Contacted Pitch

Vertical?

?

• Eventually disruptive architectures like Vertical NWs can extend density scaling

20 10 7 5 3

10

40

60

90 P

hysi

cal D

imen

sio

n (

nm

)

CMOS Technology Node (nm)

• Continual gate pitch (density) scaling will be limited by space for Contact & Gate

LIMITS TO DENSITY/LGATE SCALING

N-well P-well

P+ junction N+ junction

Gate overlap

Lg

-SiMetal

High-k

c-SiGe(P+)

i-Si

c-III/V (N+)

Si shell Tunnel diode rooting

N-well P-well

P+ junction N+ junction

Gate overlap

Lg

Gate overlap

Lg

-SiMetal

High-k

c-SiGe(P+)

i-Si

c-III/V (N+)

Si shell Tunnel diode rooting

H -Vs.- V Layout Efficiency

Horizontal

Vertical

Channel electrostatics & Device Design

Channel Material – Si

Vs. Ge Vs. III-V

Electrostatics

- Quantum simulations

V-NWFET Circuit Layout & Design

Directed InAs NW on

Si(111)

TFET Physics

Band Engineering for tunneling

NANOWIRE / TUNNEL FET

VERTICAL NANOWIRES PROCESS & CIRCUITS

Parasitic Capacitances Layout & Parasitic

Analysis

Selective

area

growth

{1-10}

(111)

SiO2

InAs

Si (111)

Si (111)

InAs Nanowires

on Silicon

Template Formation D~30-40nm D~100’s nm

PMOS

NMOS

NW pitch

Lateral

Conventional S

RA

M

Vertical

NW

NA

ND

5NM & BELOW VERT-NW

PHYSICAL DESIGN STUDY

0

0.01

0.02

0.03

0.04

0.05

0.06

16.91513.411.9

Are

a (m

m2)

M1 1/2-pitch (nm)

NAND with VFET for N5 SRAM with VFET for N5

NAND(ITRS)

SRAM (ITRS)

NW

7nm 5nm

• Vertical Nanowire Circuits can

promise further logic density

scaling for 5nm & below

(Various collected sources)

DIFFERENT VARIABILITY = DIFFERENT SOLUTIONS

DIE-DIE,

WAFER-

WAFER

ACV,

LAYOUT, CD

OVERLAY

RANDOM

DOPANTS,

LER, LWR

WEAR-OUT

RELIABILITY

TDDB,

NBTI,PBTI

ELECTROMIGRATION Eg. EM ~ 1ns, HCI ~ 10ns,

BTI ~1us

RANDOM TELEGRAPH /

FLICKER NOISE

SUPPLY

VOLTAGE

& PACKAGE

NOISE

TEMPERA-

TURE

VARIATION Self-Heating ~ 1e-4s

THERMAL

NOISE

PLL

JITTER

INTER-

CONNECT

CROSS-TALK

NOISE

Time Scale 100GHz-100MHz 1MHz-100kHz 10kHz-100Hz

Days/Months/Yrs 10ps-10ns Static 100ms-10ms 100ns-10ms

<1

0n

m

100n

m-1m

m

10m

m-1

00m

m

Tra

nsis

tor

Fe

atu

res Inte

rcon

ne

cts

&

Sm

all

Ckts

C

om

ple

x C

kt B

locks

Ch

ip

Featu

re S

cale



DIE-DIE,

WAFER-

WAFER

ACV,

LAYOUT, CD

OVERLAY

RANDOM

DOPANTS,

LER, LWR

WEAR-OUT

RELIABILITY

TDDB,

NBTI,PBTI


BTI ~1us

RANDOM TELEGRAPH /

FLICKER NOISE

SUPPLY

VOLTAGE

& PACKAGE

NOISE

TEMPERA-

TURE


THERMAL

NOISE

PLL

JITTER

INTER-

CONNECT

CROSS-TALK

NOISE

Fast/Transistor-level Variations

Materials & Device Process

Solution

Slow Die/Wafer-Level Variations

Design/Layout Optimizations

&

Smart System Adaptation

<1

0n

m

100n

m-1m

m

10m

m-1

00m

m

Tra

nsis

tor

Fe

atu

res Inte

rcon

ne

cts

&

Sm

all

Ckts

C

om

ple

x C

kt B

locks

Ch

ip

Featu

re S

cale





DIE-DIE,

WAFER-

WAFER

ACV,

LAYOUT, CD

OVERLAY

RANDOM

DOPANTS,

LER, LWR

WEAR-OUT

RELIABILITY

TDDB,

NBTI,PBTI


BTI ~1us

RANDOM TELEGRAPH /

FLICKER NOISE

SUPPLY

VOLTAGE

& PACKAGE

NOISE

TEMPERA-

TURE


THERMAL

NOISE

PLL

JITTER

INTER-

CONNECT

CROSS-TALK

NOISE

<1

0n

m

100n

m-1m

m

10m

m-1

00m

m

Tra

nsis

tor

Fe

atu

res Inte

rcon

ne

cts

&

Sm

all

Ckts

C

om

ple

x C

kt B

locks

Ch

ip

Featu

re S

cale





Solution



&


• Pattern Loading Effect: Layout control (RDRs) & Process Optimization

N10 (10nm) Layout -Dependent

Fin Variation



DIE-DIE,

WAFER-

WAFER

ACV,

LAYOUT, CD

OVERLAY

RANDOM

DOPANTS,

LER, LWR

WEAR-OUT

RELIABILITY

TDDB,

NBTI,PBTI


BTI ~1us

RANDOM TELEGRAPH /

FLICKER NOISE

SUPPLY

VOLTAGE

& PACKAGE

NOISE

TEMPERA-

TURE


THERMAL

NOISE

PLL

JITTER

INTER-

CONNECT

CROSS-TALK

NOISE



Solution



&


<1

0n

m

100n

m-1m

m

10m

m-1

00m

m

Tra

nsis

tor

Fe

atu

res Inte

rcon

ne

cts

&

Sm

all

Ckts

C

om

ple

x C

kt B

locks

Ch

ip

Featu

re S

cale





DIE-DIE,

WAFER-

WAFER

ACV,

LAYOUT, CD

OVERLAY

RANDOM

DOPANTS,

LER, LWR

WEAR-OUT

RELIABILITY

TDDB,

NBTI,PBTI


BTI ~1us

RANDOM TELEGRAPH /

FLICKER NOISE

SUPPLY

VOLTAGE

& PACKAGE

NOISE

TEMPERA-

TURE


THERMAL

NOISE

PLL

JITTER

INTER-

CONNECT

CROSS-TALK

NOISE

<1

0n

m

100n

m-1m

m

10m

m-1

00m

m

Tra

nsis

tor

Fe

atu

res Inte

rcon

ne

cts

&

Sm

all

Ckts

C

om

ple

x C

kt B

locks

Ch

ip

Featu

re S

cale





&


• Device Structure and Materials are important factors



Solution

Bulk FinFET Vs. SOI Vs. Planar

Vt Mismatch sensitive to device

architecture & design

Vt fluctuations due to Traps/defects – Fundamental link to

BTI – Need to engineer Trap-Charge Kinetics

EOT (nm)

Vo

ltage O

verd

rive @

10 Y

ears

(V

)

RELIABILITY BENCHMARK

NBTI

Planar Si

channel

+ HKMG

FinFET NBTI

worsens due

to (110) surface

(110)

40% higher

atomic density

• Fundamental material properties influences reliability

• Quantum Well to engineer the Trap-Charge Kinetics

SiGe QW

planar

SiGe QW

FinFET(N)

SiGe

Si

EMERGING NOISE LIMITERS AT LOW VDD

• RTN Impact is enhanced under linear operation and worsens with

lowering Vdd

• Expects to be major impact on Near-VT operations

• Need to engineer trap-carrier interactions (Eg. QW devices)

1.E-03

1.E-02

1.E-01

1.E+00

0 0.05 0.1

1-C

DF

-DVth (V)

-0.5V -0.2V -0.1V 0V

VG-Vth0 =

Broaden distribution

with decreasing |VG - VT|

Measurement

RTN-influenced VT shift

Fully-depleted


Electrostatics


SOI

Band-Engineered

Channel for

Enhanced Transport

Gate-All-

Around,

Nanowires/

Tunnel FETs

Novel Materials/

New Transport/

Extreme

Electrostatics

2D Materials

(Bi-layer

Graphene)

Quantum/

Spin Devices

• Material & Device Architecture Innovations Enablers of continual scaling

Vdd 1.0-1.1V 0.9-1.0V 0.8-0.9V 0.7-0.8V 0.6-0.7V 0.5-0.6V < 0.5V

Strain &

Advanced Gate Stack

Engineering


+High-k

MGHigh-k

Si substrate

MGHigh-k

Si substrate

45nm

32/28nm

22/20nm

14nm

10nm

7nm

5nm

Tech Node ...



• “Beyond CMOS”

• Charge Vs. Non-Charge Based

• Novel Materials (E.g. Graphene, MX2)

• Fundamental Investigation (Material + Components)

ENERGY EFFICIENCY BENCHMARK

Graphene Logic

Ultimate

Logic

Benchmark: Praveen Raghavan (Logic-Insite)

After Nikonov & Young (Intel 2012)

InAs TFET

• Active investigations on (selected) New competitive devices

All Spin Logic

MTJ Logic

Spin Wave

Piezoelectric Element Transistor

• Non-charge based devices being surveyed

CMOSFET continues to

more efficient with

scaling

2-D MATERIAL DEVICE + INTERCONNECT

Graphene

electrodes

MX2/Multi-layer

Graphene Channels

BLG Tunnel FET Simulations

Lab-Fab

Processing

Gate

Contact

F2030

Contact Resistance Molecular Doping

MX2 MOSFET Experiments

2-D MATERIAL DEVICES

• Demonstrated electrical devices with Molybdenum disulfide (MoS2) nFET &

Tungsten Di-selenide (WSe2) pFET

Si (Back Gate)

SiO2

W(S) W(D)

MX2

WSe2

(Pd)

MoS2

(Ti)

(To be published)

MoS2

Early fundamental work on Flakes

51

© IMEC 2014

1 µm 0.8 µm 0.5 µm 0.35 µm 250 180 130 90 65 45 32 22 14 10 7 5

imec founded

What ’s next ?

SOI

FinFET

Bulk FinFET

FUSI MG

HKMG RMG-HK

SiGe Epi rSi Epi

Ge

MOSFET

GaAs on Ge

Si Epi GAA-SOI

PD/FD-SOI TFET

SiGe pFET

SiGe channel


Vertical SiGe FET

today



52

© IMEC 2014

1 µm 0.8 µm 0.5 µm 0.35 µm 250 180 130 90 65 45 32 22 14 10 7 5

imec founded

SOI

FinFET

Bulk FinFET

FUSI MG

HKMG RMG-HK

SiGe Epi rSi Epi

Ge

MOSFET

GaAs on Ge

Si Epi GAA-SOI

PD/FD-SOI TFET

SiGe pFET

SiGe channel


Vertical SiGe FET

today



Vertical circuit

Arch.

Spin for Logic

Heterogeneous

FinFET

Heterogeneous

Nanowires

53

© IMEC 2014

MESSAGES

• Innovative solutions may be disruptive – early R&D needed to

build the infrastructure

• New drivers & challenges continue to demand Innovative

options at all levels – Material, Tools, Device, Circuits, & Systems

• IMEC continues to Explore the Solutions

• Co-operation across disciplines essential

• System & Process Specializations key for CMOS scaling in

the next decade to meet Power, Performance, Area, Cost needs.

logic cmos scaling - applied materials

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