cmos present and future

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CMOS Technology: Present and FutureBijan DavariSemiconductor and Research Development Center (SRDC)

IBM Microelectronics Division, Hopewell Junction, NY 12533A3STRACT

Presently, we are going through an exciting phase of thesemiconductor industry, as the miniaturization of thedimensions is accelerated and at the same time some of thefundamental limits of device scaling, as well as opticallithography, are rapidly drawing near. h this paper, theimpact of these limits on the future development of CMOStechnology are examined and some of the advanced device,interconnect, and functional integration techniques to furtherextend technology scaling are discussed. Beyond theseadvances, the spectacular success that the semiconductorindustry has had can only continue by increasing the siliconchip fictional integratio~ once the device performance andminiaturization starts to saturate. The success of this phaseof the semiconductor business relies heavily on circuit andarchitectural innovations, aided by embedded technologies.The cost of the integrated system on a chip should remainsignificantly below the price of the system that it intends toreplace in addition to delivering added performance.

INTRODUCTIONTraditional CMOS scaling relies on the miniaturization ofthe device, isolation, interconnect dimensions, andoptimized, reduce& supply-voltage to achieve higherperformance and density and simultaneously contain theescalating power-density and maintain adequate reliabilitymargins [1]. Problems arise when non-scalable parameterssuch as the device threshold voltage (VT) and intercomectRC delay result in performance saturation [1,2], and opticallithography extendibility issues slow down the pace of thedimensional shrink [3]. The mandatory reduction of thesupply-voltage also results in issues such as the reducedeffectiveness of burn-in and screen techniques, andworsening of the soft error rate (SER). It is shown that byexploiting new materials and processes such as copperinterconnects [4] and Silicon On Insulator (S01, [5]) thescaling path can be further extended.However, it will be argued that, even after using the abovetechnologies and before the year 2005, the FET deviceperformance gain saturates as the minimum effective channellength m) approaches 0.03wm (nominal effeixive

channel length of about 0.04pm) @ 1.OV supply voltageand the gate oxide thickness of about 1.5nm [6]. Thiscorresponds to a gate lithography of 0.071.uniandthe 0.1pmtechnology generation. On the DRAM side, the 4X increasein the number of bits per chip every three years will slowdown as the transition from the folded bit line architecture (8lithography squares) to a much less noise immune, open bitline structure (4 lithography squares) becomes necessary.Beyond this point, the performance growth of silicon chipsshould continue by increasing functional integration, madepossible by technologies such as, embedded nonvolatilememory, embedded DRAM [7], mixed signal, etc., withheavy reliance on circuit and architectural inncwations.

CMOS TECHNOLOGY TODAY:NEARING THE LIMITS!Device Scaling: For high-performance, digital CMOSapplications, the supply-voltage transition from 3.3V to 2.5Vtook about 5 years from the early 1990s to 1995 due to thereluctance to depart from standardized voltage levels [1].After this transitio% the pace of supply-voltage (VDD)reduction was accelerated significantly as reflected in therevised National Technology Roadmap for Semiconductors(NTRS) released in 1997 [8]. The primary mason has beento achieve maximum device performance at a givenlithography generation while maintaining aclequate devicereliability, and containing switching power (C VDD2F) [2].The transitions from 2.5V to 1.8V to 1.5V supply-voltagesfor 0,35pnL 0.25~m and O.18ym CMOS generations,respectively, have been taking place at about 2-yearintervals. A device performance gain of about 30/0-400/0and a density enhancement of 2X is delivered betweensuccessive technologies. Therefore, even at this acceleratedpace of voltage reductio% the active power-density has beensteadily rising since the circuit density and performanceenhancements outpace the power reduction achieved via VDDscaling. A low-power scaling scenario with more aggressivesupply voltage reduction can offer relatively constant powerdensity [1].As we prowess along the supply-voltage reduction pat~ theimpact of the non-scalability of the threshold voltage (VT)becomes more severe. Generally, for every 100mV

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reduction in VT, t h e device off current (10$ and the standbycurrent increase by 10X (85C). Low standby current isrequired to allow for functional operation under burn-~ IDNtesting at room temperature, fimctioml dynamic circuits, andadequately low standby power dissipation at worst caseoperating temperature [2]. The exponential dependence ofthe standby current on VT tends to limit the minimumallowable VT to about 0,20V at room temperature.Therefore, as the VDDdecreases without the correspondingreduction in VT, t h e device performance gain slows downdue to the reduced overdrive. This effect is demonstrated inFig. 1, where the performance improvement of successiveCMOS generations down to sub-O.1pm regime is presented[2]. The lower &shed line represents the ideal scalingscenario where the performance improves proportional to thechannel length. We can see that the device performance gaindeparts fkom the ideal case for shorter channel lengths atreduced voltages, mainly due to fact that the VT is scaleddown less than VDDfor the reasons mentioned above.Therefore, the VDDcannot be significantly reduced below1.OVfor performance driven applications, unless new circuittechniques and chip architectures allow decoupling of thedevice off-current from performance which would make itpossible to reduce VT proportional to VDD.The overall chip performance in most designs is calibratedagainst the VTof the nominal or long channel devices, whilethe off current is determined by the minimum channel length.A key element in minimizing the VTof the nominal device isthe reduction of the device short channel effect (V,difference between nominal and minimum channel length ata given technology generation). Excellent short channelbehavior has been demonstrated for nFET and pFET devicesdown to 0.06P and 0.08~ respectively, in a O.18~mgeneration technology, by employing aggressivesource/drain halo, shallow extensions and thin gate dielectric[9]. Further device optimization and thinner gate dielectricswill enable short channel devices down to 0.03pm.A lower limit for the gate dielectric thickness might be onthe order of 1.5nm (SiOz) which is the thickness at which thetunneling gate current approaches the device off-current atVDD of 1.OV [6]. The gate dielectric reliability is anotherkey issue which might dictate the minimum allowablethickness [10].Due to these limitations, it will be diflicult to achieve CMOSdevices with Lm below 0.03~m for room temperatureoperatio~ even if all the manufacturing issues with respectto yielding the very thin gate dielectrics and short channellengths are resolved. Given the current pace of CMOStechnology development (sub-O.1j.un L~ in manufacturingtoday), we should reach 0.031,uuminimum effective channellength before 2005. This corresponds to a nominal effective

channel length of about 0.04~m. One can always improvethe tolerances and reduce the nominal channel len~ andthus gain some level of higher performance, however, thelower limit of the device channel length poses a significantbarrier to future scaling of CMOS technologies.Integration and Copper Interconnect: Presently, the mostadvanced bulk CMOS technology that will be inmanufacturing in 1999 is the O.18pm generation [11,12,13].This technology [11] offers twice the density c~fthe previous0.25wm CMOS generatio~ [14], and about 40% higherdevice performance, in span of two years. An inverter delaybelow 11psec is achieved at supply-voltage of 1.5V (Fig.2).The choice of the supply-voltage is consistent with thehigh-performance scaling scenario [2], delivering the highestdevice performance at dimensions consistent with nominaleffective channel length (L,j-r) under 0.1 ~m. In thistechnology, 7 levels of copper metalizatiorl are offered,delivering low interconnect RC delay as well as low line toline and total capacitances [4, 11]. The application of localinterconnect allows dense SRAM cell size as small as3.84p [11].Fig. 3 shows the effect of the copper in reducing thecapacitances, relative to an optimized aluminum interconnect[12] and for several dielectrics with dielectric constantsranging slom 8=4.1 (Undopped SiOz, US)G) to 8=3.6(Fluorinated SiOz, FSG) to 8=2.9 (hydrogen silsequioxane,HSG). Relative to the Ai/FSG system with the same sheetresistance, the Cu/FSG and Cu/USG deliver 17% and 10%reduction in line to line capacitance, respectively, Fig.3a.This is due to metal height reduction in copper, madepossible by its lower resistivity [4,11]. The total capacitancefor CWFSGis reduced by about IO?40relative to AM?SG,Fig.3b. Overall, the combination of dual damascene copperinterconnect with low e dielectrics will allow continuedscaling of the interconnect lines down to 0.1~m CMOSwithout significant circuit delay impact and insurmountablemanufacturing yield loss and cost. Hierarchical interconnectschemes, dictating thicker and wider lines at upper levelsmust still be employed to contain the long net delays withinan acceptable range, consistent with the several GHzoperating frequencies of the systems which will be built inthese technologies.Lithography: The 1997 NTRS Roadmap [8] of thelithography minimum feature size for the gate level andgeneral lithography (half pitch) is shown in Fig.4 along withthe 1994 NTRSRoadmap. As we can see, there has been asignificant acceleration of the general lithography (about ayear) which is a measure of the density and a very significantacceleration of the gate lithography (about three years)which is a measure of device performance. Thisacceleratio~ in part, can be attributed to the robust 248nm

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DUV lithography system winch not only orrers slgnmcamwavelength reduction (A?J?L =47%0) relative to itspredecessor (I-line @ 365nm), but also offers extendibilitypossibly down to O.13pm generatio~ by employing highnumerical aperture tools and various resolution enhancementtechnologies such as Phase Shift Mask (PSM) and off-axisillumination [15].The discussion of the lithogmphy ecosystem (exposure tools,resist, mask making, RET......) is beyond the scope of thispaper but the key point is that the optical lithography whichhas continued to deliver consistently on all fmna i.e.,resolutio% tolerance, overlay, and throughput is becomingsignificantly more challenging as we move beyond O.13~mgeneration. Shorter wavelength systems with 193nm and157nm are needed for the 0.1m generation and beyond withmany unknowns and at the same time offering lessimprovement (AM) relative to the 2481uu systems. All theother non-optical lithography technologies are significantlybehind in one or more of the key requirements. The net isthat unless there is an overwhelming economic drive, thepace of the lithographic shrink will slow down after theO.lpm generation which is also before year 2005.

FUTURE OF CMOS TECHNOLOGY:PATH TO CONTINUED GROWTH

The two key bottlenecks in the path towards sustainedCMOS growth are: performance saturation and the slowdown of density enhancement. The following are someahernatives to extend further growth.Silicon On Insulator: One of the least disruptivetechnologies that offers additional device level performanceat a given lithography and supply-voltage is (S01) [5]. SOICMOS devices are built on a layer of insulator instead ofbulk silico~ Fig.5, and offer about 20Y0-35Y0performanceenhancement. SOI offers an additional degree of freedom todeliver higher device performance without pushing onchannel length and gate oxide thickness, since the SOIperformance gain over bulk comes from elimination of thearea junction capacitance, higher dynamic drive current, andelimination of the body effect [5]. Higher performance gainis expected if circuits, optimized for SOI devices, areemploye~ e.g., stacked devices, or extensive use of passgates as in CPL. The performance advantage of SOI isdemonstrated in a 64-bit microprocessor, built in 0.22pmCMOS as shown in Table-1 [16]. The key challenges ofemploying SOI technology are the availability of lowcosdlow defect substrate, and minimimtion of floating bodyeffects which complicate device models and circuittechniques. Floating body effects in a partially depleteddesign lead to kink effect, history effect, pass gate leakageand lower device breakdown voltage due to bipolar effect.

Dy proper opmmzauon 01 me uevIw utx+y CUM p WGM,these issues can be contained for 1,8V supply-voltage [5,17].As the supply-voltage drops, the impact of the SOIshortcomings are reduced while the advantages becomemore significant. In addition to higher performance at thesame worst-case off current, SOI offers better SERimmunity, reduced noise coupling through substrate, andpossibly tighter ground rules due to elimination of latch-up.The SOI performance gain can be traded off withsignificantly lower active power dissipation by reducing thesupply-voltage in a given design. A 2-3X active powerreduction can be achieved relative to bulk CMOS at thesame performance, Fig.6 [17].Variations of the SOI device such as Dynamic ThresholdMOS (DTMOS) [18] and double gate [19] may offer fiulheradvantages for operation at lower than 1.OV, or higherdevice currents, respectively. Ano@er possible deviceenhancement can come from increased carrier nobilities byusing strained silicon FET devices [20]. These novelmaterials and structures introduce additional device designand processing challenges which will most likely push theirapplication beyond year 2005.Cooled CMOS: Lowering the operating te~perature of theCMOS circuits improves the device performance and at thesame time reduces the interconnect resistance. Theperformance gain is due steeper sub-threshold slope whichallows a lower VT at a given off-current, and higher carriernobilities. Depending on the device design point, about30% device performance gain can be achieved at -30 C[21].Embedded DRAM: Functional integration, made possibleby embedding analog and dense memories, is a criticaldirection which can lead to significant performanceenhancement of silicon chip even if the device andintercormect performances saturate. One attractivetechnology for such integration is the embedded DRAM intoa high-performance logic base. In a recent worQ a trenchDRAM with a cell size of 0.62~m2 is integrated into ahigh-performance CMOS logic technology [7]. Thisrepresents about a 6X cell density enhancement relative tothe state of the art SR4M in the same technology. Thelogic peri%ormanceof this technology can be 2-3X higherthan a DRAM base embedded technology, Fig,7 [7,9]. Otherdistinguishing features of a logic buse embedded DR4Minclude: flexibility in designing a high-speed DRAM macrowith appropriate (and in some cases more relaxed)application specific specs on retention time ;andcell size,and the migratability of the existing ASIC and variousdesign cores. The exploitation of the trench DRAM is

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particularly usefid, since after the fabrication of the trenchstorage capacitors, the silicon surface is flat and all theprocess heat cycles associated with the storage node arecompleted, Fig.7 [7]. Therefore the high-performance logicdevices can be built undisturbed as they are not subject tothe storage node heat cycle and topography, as would be thecase for stacked storage capacitor. This technology canoffer significant increase in memo~ bus width, bandwidmand lower latency, at reduced power diasipatkm, leading toan overall system performance enhancement and costreduction.We are at the very early stages of exploiting this embeddedtechnology, and innovative circuit and system architecturedesigns are key in realizing its full potential. An importantfactor in the success of the embedded technologies andapplications is that the total system cost should be reduced.Therefore silicon-level embedded technologies where thechip cost exceeds the system price would not be pervasive.However, in those cases, opportunities might exist where apackage-level embedded technology, such as chip staclGcould provide the optimum cost-petiormance system.

SUMMARY and CONCLUSIONSThe semiconductor industry, Iieling and at the same timefunded by the huge Information Technology business, ismoving rapidly through an unprecedented phase ofperformance and productivity boost. The CMOStechnology, which is the workhorse of this industry, has beenrunning at an accelerated pace in the past 5 years, and isbeginning to run out of steam. Todays CMOS technolo~uses bulk devices and aluminum interconnects, Bymigrating to technologies such as copper interconnect andSOI, we will extend the life of CMOS technology.However, before the year 2005, when the FET channellengths approach 0.03~m and supply voltages go down to1.OV, the device performance gain will saturate, even withSOI (we can expect about 2X device performanceenhancement by then). Also, the 4X density boost that wewill enjoy between now and year 2003, will slow downsubsequently, due to significant lithography challenges post0.1pm generation.Fig.8 depicts some of the concepts discussed in this paper.The lower line is the bulk CMOS base line with aluminuminterconnect. In this case, the silicon performance boostmainly comes from the FET devices which deviate horn theideal scaling at the 0.1pm channel length (1.5V) as shown inFig. 1. In addition to the device performance saturatio~ the

interconnect delay degrades the performance as thedimensions shrink. By using copper and low &dielectricinstead of ahnninumRiOz, we can gain back allarge portionof the performance loss due to interconnect RC delay andcapacitances. Employing SOI devices will give us another30% performance boost, and then cooling the chips to-30 C, will yield an additional 30Y0.Other novel materials(such as, strained silicon) and device structures (such as,DTMOS, dual gate) are not included in Fig,,8 as they areunlikely to have a significant impact before the year 2005.Circuit and architecture innovations, along with embeddedtechnologies, will have to carry the load in maintaining thepace of the silicon performance growth as we exhaust thedevice and intercomect gains.

ACKNOWLEDGMENTI would like to express my gratitude to all members of theIBM Semiconductor Research and Development Center(SRDC) who made this work possible. My special thanksgo to Fari Assaderaghi, Tim Brunner, Hi~ Calhoun,Emmanuel Crabbe, Scott Crowder, Subu Iyer, Russ Lange,Tak Ning, Ghavarn Shahidi and Lisa Su for many helpfbldiscussions and their contribution to this work.

REFERENCES1. B.Davan,et al.,Proc. ofIEEE,VO1.83,PP.595,(1995)2. B.Davan,et al., IEDMTech.Digest,pp. 555,(1996)3. T.Bnmner, IEDMTech.Digest,pp. 9, (1997)4. D.Edelstein,et al.,IEDMTech.Digest,pp.773, (1997)5, G. Shahidi,et al.,ISSCCTech.Digest,pp.426, (,1999)6. S.H.Lo, et al.,IEEE, EDL,18,PP.209,(1997)7. S.Crowder,et al.,IEDMTechDigest,pp. 1017,(1998)8. TheNationalTechnologyRoadrnapfor Semiconductors,publishedby the SemiconductorIndustrialAssociation,SanJose,CA (1997)9. M.Hargrove,et al., IEDMTechDigest,pp. 627,(1998)10. J.H.Stathis,etal.,IEDMTechDigest,pp. 167.,(1998)11. S.Crowder,VLSITechnologySymp,(1999)12. S.Yang,et al.,IEDMTech.Digest,pp. 197,(1998)13. M.Redder,et al.,IEDMTech.Digest,pp.623, (1998)14. S, Subbanna,et al., IEDMTech.Digest,pp. 275, (1996)15. M. Levenson,SPIEVO1.3051,p.2, (1997)16. D.H.Allen,ISSCCTech.Digest,pp.438,(1999)17. D.J.Schepis,et al.,IEDMTech.Digest,pp.587, (1997)18, F. Assaderaghi,et al., IEDMTech.Digest,pp. 809,(1994)19. H.S.Wong,et al.,IEDMTech.Digest,pp.427, (1997)20. K.Rim,et al.,IEDMTech.Digest,pp.707, (1!?98)21. Y. Taur,et al.,IEDMTech.Digest,pp.215, (1997)

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22 -1- -- -- -- - -- --- - --- __ .. . . .. . .. .

< lL2/ / - . -H@ perfomme I= 0 .[~ ,/ -A--bw Powes it,,, ! I * $ -i0.06 0.1 0.2 0.4 0.6 1.0Effect ive (Xmrwl Length (Mm)Fig. 1. Delay projections for typicalCMOS loaded NAND.

0.9- ss0.8-

m0.7-CuiHSG CWFSG CWUSG AUFSG

20-

Fig. 3a. Relative lateral line-to-line capacitance formhimum pitch third level metal in a variety ofinterconnect options.

~ 350w.# 250

I

-i.ile 0.07 0.08 0.09 0.1 0.11 0.12Channel Length (urn)

Fig. 2. Unloaded inverter chain delay as a function of channelIe;gth measured at 1.5V, 0.18ym CMOS technology.

. *\ \ . General lith Gatelit.h1994NTRS+ --

----- ----1 Technology for sub-100 run?,1995 !998 2001 2004 2007 2010Fig. 4. Lithography feature size (1997 NTRS).

-

.s. CU/USG+ AUFSG~ CWFSG* CuiHSG

Via Height(urn)-..Fig, 3b. Relative third level metal capacitanceas a function of via height.

Ww4KB Inst+ 128KBkist+ 128KBInst+. . ._64KBDab ! 128KBData I 128KBDataIL2 Directory

supply VoltageTransistors % :EEH.Die Size J162mm2 139mm2 139mm2Power 34 w 22W 24WLefi(NF~ 0.16um 0.121um 0.12umTw 5.Onm 3.5rlm 3.5nm

Metallization 5 layersAl 8 layersCu 6 layersCuContactedM2-M4 pitch 1.26um 0.81urn 0.81um

Table 1. Comparison of 64-bit microprocessordesigns and technologies.

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DG-i I=QsFig. 5. Schematic of NFET on SOI and equivalent devices.

Logic

Fig. 7. DRAM vs. logic performance and logic

7551-

1032.5 sol

25 Bulk1.8 3x 1.8

102 2x1.4

~ ~1 a1.4V

21.2

~~34567EjgAccess Time ( nS )

Fig. 6. Power delay for a 4Mb SRAM on SOI.

Unsilicided Junction

:base embedded DRAM cross section.10 . .

LowTemp,--3OC ,..

:=i$fl:~zz

~ FOnnec s L,,.,..,.. Performance enhancement saturates... due to device non-scalability,and q solinterconnect delay A CU+LOWKA Bulk

11995 2000 2005 2010 2015Year

Fig. 8. CMOS performance roadmap.

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cmos present and future

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